Agilent TechnologiesメーカーFS2100の使用説明書/サービス説明書
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FuturePlus Systems Corporation LOCAL BUS Active Analysis Probe Users Manual- FS2100 / FS2101 For Agilent Technologies Logic Analyzers Revision 1.8 FuturePlus is a trademark of FuturePlus Systems Corpo.
HOW TO REACH US 5 PRODUCT WARRANTY 6 Limitation of w arranty 6 Exclusive Remedies 6 Assistance 6 INTRODUCTION 7 How to Use This Manual 7 ANALYZING THE PCI LOCAL BUS 8 Duplicating the Master Diskette 8.
The Format Menu 17 The STAT variable 18 The ADDR, ADDR_B , ADDR_C, DA TA_B and DATA variables 19 The BUS_UT variable 19 The L_CMD variable 19 Theory of Operation 20 The Input Buffers 20 The Latching B.
The Waveform Display 34 GENERAL INFORMATION 36 Characteristics 36 Analysis Probe Interface Compatibility 36 JTAG Boundary Scan 36 The PCI Present Pins 36 Standards Supported 36 Power Requirements 36 L.
How to reach us For Technical Support: FuturePlus Systems Corporation 36 Olde English Road Bedford NH 03110 TEL: 603-471-2734 FAX: 603-471-2738 On the web http://www.futureplus.com For Sales and Marketing Support: FuturePlus Systems Corporation TEL: 719-278-3540 FAX: 719-278-9586 On the web http://www.
Product Warranty This FuturePlus Systems produc t has a warranty against defects in material and workmanship for a period of 1 year from the date of shipment. During the warranty period, FuturePlus Systems will, at its option, either repl ace or repair products proven to be defective.
Introduction The PCI Active Analysis Probe module provides a complete interface between any PCI add-in slot and Agilent Logic Analyzers. The Analysis Probe interface buffers and in state mode latches and decodes all PCI cycle types and transactions.
Analyzing the PCI Local Bus This chapter introduces you to the PCI Active Analysis Probe and lists the minimum equipment required and accessories supplied for PCI Local Bus analysis. This chapter also contains information that is common to both state and timing analysis.
The PCI Active Analy sis Probe module Minimum Equipment Required The minimum equipment required for analysis of a PCI Local Bus consists of the following equipment: • 1660A/C, 1661A/C, 1662A/C, 1655.
Pod 1 channel 0 can be configured to view any one of the four PCI interrupts. Move the jumper so that it corresponds to the desired interrupt and that interrupt line will be routed to POD 1 channel 0. The jumper and interrupt stake pins are clearly labeled and are located under POD 7.
Parity On No Wait No Idle State ON 1 2 3 4 Parity On No Wait No Idle TD0-TD1 State Timing FuturePlus Systems PCI Active Analy sis Probe front panel Powering the PCI Active Analysis Probe The active circuitry on the PC I Active Analysis Probe module gets its power from the logic analyz er PODs.
Multiplexed versus Demultiplexed The PCI Local Bus specification specifies that the AD lines and the C/BE lines carry different information at different times. This is referred to as multiplexed. Using the extra clocking features and additional pods of the logic analyzer the AD lines can be demultiplexed.
64 bit PCI Multiplexed Logic Analyzer PCI Active Analy sis Probe Comment Master POD 1 Header 1 POD 2 Header 2 POD 3 Header 3 POD 4 Header 4 POD 5 Header 7 16554/5/6/7 expander card POD 1 POD 6 Header .
POD 9 Header 9 16554/5/6/7 expander 2 card POD 1 16550 expander card Pod 3 POD 10 Header 10 16554/5/6/7 expander card POD 2 16550 expander card Pod 4 POD 11 Header 11 16554/5/6/7 expander card POD 3 16550 expander card Pod 5 USER PINS PCI Active Analysis Pr obe Header 4 contains 8 User Defined pins.
The card edge connector of the PCI Active Analysis Probe module can accommodate one 32 or 64 bit 5V OR 3V PCI add in card. The extender card connector is either a 3V or 5V connector depending on how the board was ordered and configured at the factory.
The logic analyzer can be configured for PCI analysis by loading the PCI configuration file. Loading this file will load the PCI Local bus inverse assembler and configure your logic analyzer. To load the configuration and inverse assembler: Setting up the Analyzer from the diskette 1.
1655x,1670/71 P32D_55 5 32 bit Demultiplexed - Analysis Probe PODS 1-6 connect to PODS 1-4 on the Master card and 1-2 on the Slave card 1-2 respectively (PODS 1-6 on the 1670/71) 1655x,1670 P64M_55 5 .
The STAT variable The STAT variable is used by the PCI inverse assembler to decode PCI bus transactions. It should not be changed or deleted from the format menu.
The ADDR, ADDR_B, ADDR_C, DATA_B and DATA variables are defined in the format menu and used to pass the AD line information to the Inverse Assembler during state analysis. They are mapped as shown in the below table. These variables should not be changed or deleted from the format Menu.
RESRVD 0100 RESRVD 0101 MEM_RD 0110 MEM_WR 0111 RESRVD 1000 RESRVD 1001 CON_RD 1010 CON_WR 1011 MEMRDM 1100 DAC_CY 1101 MEMRDL 1110 MEMWRI 1111 I/O_XACTIONS 001X MEM_XACTIONS 011X CONFIG_XACTIONS 101X Theory of Operation The PCI Active Analysis Probe is a universal PCI short card that attaches to Agilent logic analyzers.
The Latching Buffers The latching buffers are used only for state mode. The entire PCI bus (except the clock) is latched in these buffers on the rising edge of the PCI clock. The input to the latching buffers is output port 1 from the input buffers . The latching buffers are IDT 162511 latching buffers with party generation.
PVALID_L - Parity Valid True for the cycles in which parity is being transmitted on the PCI bus. IDLE_L - Idle cycle True when the bus is IDLE. False when the bus is busy.
State Analysis This chapter explains how to c onfigure the PCI Active Analysis Probe to perform state analysis on the PCI Local Bus. The configuration software on the flexib le diskette sets up the format specification menu of the logic anal yzer for compatibility with the PCI Local Bus.
Acquiring Data Touch RUN and, as soon as there is activity on the bus, the logic analyzer will begin to acquire data. The analyzer will continue to acquire data and will display the data when the analyzer memory is full, the trigger specificat ion is TRUE or when you touch STOP.
The following error messages are reported by the PCI inverse assembler. Error Messages ERROR-NO DEVICE SELECTED This error is displayed during a non special cycle data phase when IRDY and TRDY are asserted and DEVSEL is not asserted. ERROR DEVSEL ASSERTED This error is displayed during a special cycle data phase if DEVSEL is asserted.
Captured data is as shown in the following figure. The first figure displays the state listing after disassembly. The PCI PC Mapper is constructed so the mnemonic output closely resembles the actual commands, status c onditions, messages and phases specified in the PCI Local Bus s pecification.
Error Messages The error messages reported by the PCI PC Mapper are the same as those reported with the standard non mapper version of the PCI Inverse Assembler. PCI PC Mapping for memory transactions This section lists the addresses, the commands and the corresponding mapping done by the PCI PC Mapper software.
Address bits 23-0 PC Mapper output 0003C4H INT #F1-FF USER PROGRAMS 000200H INT #80-F0 BASIC 0001E0H INT #78-7F USER PROGRAMS 0001DCH INT #77 IRQ15 0001D8H INT #76 IRQ14 0001D4H INT #75 IRQ13 0001D0H .
000008H INT #02 NMI 000004H INT #01 SINGLE STEP 000000H INT #00 DIVIDE BY ZERO 29.
PCI PC Mapping - I/O Transactions Address bits 23-0 PC Mapper output 0000H MSTR DMA CH 0 0001H MSTR DMA CH 0 0002H MSTR DMA CH 1 0003H MSTR DMA CH 1 0004H MSTR DMA CH 2 0005H MSTR DMA CH 2 0006H MSTR .
00CAH SLV DMA CH6 TRANS COUNT 00CCH SLAVE DMA CH7 MEM ADDR 00CEH SLAVE DMA CH7 TRANS COUNT 00D0H SLV DMA STATUS REG CH 4-7 00D4H SLV DMA MASK REG CH 4-7 00D6H SLAVE DMA MODE REG CH 4-7 00D8H SLAVE DMA.
03CAH VGA FEATURE CONTOL REG 03CCH VGA MISC OUTPUT REG 03CEH VGA GRAPHICS CNTRLR ADDR 03CFH VGA GRAPHICS CNTRLR ADDR 03D4H VGA CRT CNTRLR ADDR REG 03D5H VGA GRAPHICS CNTRLR DATA 03DAH VGA COLOR STAT 1.
Timing Analysis Installation Quick Reference The following procedure describes the major steps required to perform timing analysis measur ements with the PCI Active Analysis Probe module. 1. Set the State/Timing switch to TIMING. The State LED will be doused.
Using the Cycle bits and L_CMD lines Although the Cycle bit and the L_CMD lines were designed for state analysis they can prove to be very useful in Timing analysis. These bits can be effect ively used to trigger the timing analyzer. Note that the cycle bits and L_CMD lines pass through more active logic than the PCI signals directly from the bus.
35.
General Information This chapter provides additional reference information including the characteristics and signal c onnections for the PCI Active Analysis Probe module. Characteristics The following operating characterist ics are not specifications, but are typical operating characteristi cs for the PCI Active Analysis Probe module.
Minimum Clock Period (State) 0 to 33Mhz PCI clock for State mode and 0-100Mhz for Timing Mode. Signal loading The PCI Active Analysis Probe l ogic analyzer interface presents only one electrical load on each PCI bus signal. However, the extender card connector is an additional 4 inches beyond the maximum allowed stub length.
The PCI Active Analysis Probe module monitors signals for both state and timing analysis. The below figure displays how the cable headers are numbered.
Analysis Probe Cable Header and Pin number Logic Analyzer channel number Signal name Header 2 pin 3 CLK/16 GNT_L 5 no connect 7 15 REQ# 9 14 IDSEL# 11 13 WNODEV_L 13 12 ACK64# (DATA64) 15 11 TABORT_L .
Analysis Probe Cable Header and Pin number Logic Analyzer channel number PCI Signal name Header 3 pin 3 CLK/16 M_CLK_H 5 no connect 7 15 AD15 9 14 AD14 11 13 AD13 13 12 AD12 15 11 AD11 17 10 AD10 19 9.
Analysis Probe Cable Header and Pin number Logic Analyzer channel number PCI Signal name Header 4 pin 3 CLK/16 AVALID_L 5 no connect 7 15 AD31 9 14 AD30 11 13 AD29 13 12 AD28 15 11 AD27 17 10 AD26 19 .
Analysis Probe Cable Header and Pin number Logic Analyzer channel number PCI Signal name Header 5 pin 3 CLK/16 5 no connect 7 15 AD15 9 14 AD14 11 13 AD13 13 12 AD12 15 11 AD11 17 10 AD10 19 9 AD09 21.
Analysis Probe Cable Header and Pin number Logic Analyzer channel number PCI Signal name Header 6 pin 3 CLK/16 5 no connect 7 15 AD31 9 14 AD30 11 13 AD29 13 12 AD28 15 11 AD27 17 10 AD26 19 9 AD25 21.
Analysis Probe Cable Header and Pin number Logic Analyzer channel number PCI Signal name Header 7 pin 3 CLK/16 REQ64# 5 no connect 7 15 AD47 9 14 AD46 11 13 AD45 13 12 AD44 15 11 AD43 17 10 AD42 19 9 .
Analysis Probe Cable Header and Pin number Logic Analyzer channel number PCI Signal name Header 8 pin 3 CLK/16 5 no connect 7 15 AD63 9 14 AD62 11 13 AD61 13 12 AD60 15 11 AD59 17 10 AD58 19 9 AD57 21.
Analysis Probe Cable Header and Pin number Logic Analyzer channel number PCI Signal name Header 9 pin 3 CLK/16 5 no connect 7 15 AD47 9 14 AD46 11 13 AD45 13 12 AD44 15 11 AD43 17 10 AD42 19 9 AD41 21.
Analysis Probe Cable Header and Pin number Logic Analyzer channel number PCI Signal name Header 10 pin 3 CLK/16 5 no connect 7 15 AD63 9 14 AD62 11 13 AD61 13 12 AD60 15 11 AD59 17 10 AD58 19 9 AD57 2.
Analysis Probe Cable Header and Pin number Logic Analyzer channel number Signal name Header 11 pin 3 CLK/16 5 no connect 7 15 USER PIN 8 9 14 USER PIN 7 11 13 USER PIN 6 13 12 USER PIN 5 15 11 USER PI.
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