EpsonメーカーS1C33L03の使用説明書/サービス説明書
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T echnical Manual CMOS 32 - BIT SINGLE CHIP MICROCOMPUTER S1C33L03 PRODUCT PART S1C33L03 FUNCTION PART S1C33L03 MF1574 - 01.
NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
S1C33L03 Technic al Manua l Thi s ma nu al de scr ibe s the har dwa r e spe cif icat ion s of the Seik o Eps on orig inal 32-b it mic rocomp uter S1C 33L0 3. S1C 33L0 3 PR ODU CT PART Desc r ibes the ha rdw are sp ec ifi ca tio ns o f th e S 1C33 L03 ex ce pt for d eta ils o f the p eri ph era l ci rcuit s.
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T ABLE OF CO NTENT S S1 C33L03 TECHNICAL MANUAL EPSON i S1C33L03 PRODUCT PART Ta ble of Con tents 1O ut line ..................................................................................................................................... A-1 1. 1F ea tu re s .
T ABLE OF CO NTENT S ii EPSON S1 C33 L03 TECHNICAL M ANUAL Appe ndix A <Refere nce> E xter nal De vic e I nterface T i mings .......................................... A -11 3 A. 1D RA M (7 0ns ) .................................................
T ABLE OF CO NTENT S S1 C33L03 TECHNICAL MANUAL EPSON iii S1C33L03 F UNCTION PART Ta ble of Con tent s IO U TLINE I-1 INT ROD UCT ION ............................................................................................................ B -I - 1-1 I-2 BL OCK DIA GRA M .
T ABLE OF CO NTENT S iv EPSON S1 C33 L03 TECHNICAL M ANUAL Bu s Cl oc k ...................................................................................................................... ............ B -II -4-17 Bu s Sp ee d Mo de ................
T ABLE OF CO NTENT S S1 C33L03 TECHNICAL MANUAL EPSON v III P ERI PH E RA L BL OC K III- 1 INT ROD UCT ION ......................................................................................................... B -I II- 1 -1 III- 2 PRES CA LER .....
T ABLE OF CO NTENT S vi EPSON S1 C33 L03 TECHNICAL M ANUAL III- 7 CL OCK TIM ER ............................................................................................................ B- I II- 7-1 Co nf igu rat ion o f Clo ck T im er ............
T ABLE OF CO NTENT S S1 C33L03 TECHNICAL MANUAL EPSON vii IV AN ALOG BLO CK IV -1 INT ROD UCT ION ......................................................................................................... B-I V- 1- 1 IV -2 A/D C ONVE RTE R ............
T ABLE OF CO NTENT S viii EPSON S1 C33 L03 TECHNICAL M ANUAL VI SDRAM C O NTRO LLER BLO CK VI-1 IN T ROD UCTI ON ......................................................................................................... B-V I- 1- 1 VI-2 SD RA M IN TER FAC E .
T ABLE OF CO NTENT S S1 C33L03 TECHNICAL MANUAL EPSON ix Vi rtual S cr een and Vie w Por t .................................................................................... B-VII -2 -23 Inve rt ing a nd B lank ing th e Disp lay ....................
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S1C33L03 PRODUCT PART.
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1 OU TL I NE S1 C33L03 PRODUCT P ART EPSON A-1 A-1 1 Out line The S1 C3 3L 03 is a Sei ko Epso n ori gin al 32 -bi t micr oco mpu ter with a buil t-i n L CD co ntro lle r.
1 OU TL I NE A-2 EPSON S1 C33 L03 P RODUCT PART Inte rru pt cont ro lle r: Pos sib le to in vo ke D MA Inpu t in te rru pt 10 ty pe s (p ro gr amm able) DMA c ontro ller in te rru pt 5 ty pe s 16- bit.
1 OU TL I NE S1 C33L03 PRODUCT P ART EPSON A-3 A-1 1.2 Block Diagram V DD V SS V DDE A[23:0] D[15:0] #RD #WRL/#WR/#WE #WRH/#BSH #HCAS, #LCAS, #RAS[1:0] #CE10EX, #CE[9:3] #EMEMRD #WAIT(P30) #DRD(P20), .
1 OU TL I NE A-4 EPSON S1 C33 L03 P RODUCT PART 1.3 Pin D escriptio n 1.3.1 Pi n Layou t Diagra m (plast ic packag e) QFP20-1 44pin 73 108 37 72 INDEX 36 1 144 109 No.
1 OU TL I NE S1 C33L03 PRODUCT P ART EPSON A-5 A-1 1.3.2 Pin Func tions Table 1. 3.1 Li st of P in s fo r Pow e r S up ply Sy ste m Pin name P in No. I/O Pull -up Func tion V DD 8,51,78,127 – – Po.
1 OU TL I NE A-6 EPSON S1 C33 L03 P RODUCT PART Pin name P in No. I/O Pull -up Func tion #WRL #WR #WE 43 O – #WRL: Write (low by te) signal when SB USST(D3/0x481 2E) = "0" (defaul t) #WR: .
1 OU TL I NE S1 C33L03 PRODUCT P ART EPSON A-7 A-1 Table 1. 3.3 Li st of P in s fo r HS DMA C on trol S ig nal s Pin name Pin No. I/ O Pull-u p Func tion K50 #DMAREQ0 41 I Pull-up K50: Input port when CF K50(D0/0x4 02C0) = "0" (defaul t) #DMAREQ0: HSDMA Ch.
1 OU TL I NE A-8 EPSON S1 C33 L03 P RODUCT PART Table 1. 3.4 Li st of P in s fo r In ter nal Peri phe ral C irc uits Pin name P in No. I/O Pull -up Func tion K50 #DMAREQ0 41 I Pull-up K50: Input port when CF K50(D0/0x402C 0) = "0" (defaul t) #DMAREQ0: HSDMA Ch.
1 OU TL I NE S1 C33L03 PRODUCT P ART EPSON A-9 A-1 Pin name P in No. I/O Pull -up Func tion P11 EXC L1 T8UF 1 DST1 121 I/O – P11 : I/O port when C FP11(D1/0x4 02D4) = "0" and CF EX1(D1/0x4.
1 OU TL I NE A-10 EPSON S1 C33 L03 P RODUCT PART Pin name P in No. I/O Pull -up Func tion P26 TM4 SOU T2 6 I/O – P26 : I/O port when CF P26(D6/0x4 02D8) = "0" (defaul t) TM 4: 16-bit ti m er 4 output w hen CFP26(D6/0x4 02D8) = "1" SO UT 2: Se ri al I/F Ch.
1 OU TL I NE S1 C33L03 PRODUCT P ART EPSON A-11 A-1 Table 1. 3.5 Li st of P in s fo r LCD Con t roll er Pin name P in No. I/O Pull -up Func tion FP DA T[ 7:4] 13–16 O – 4 high-order bits of data b.
2 POWE R SU PPLY A-12 EPSON S1 C33 L03 P RODUCT PART 2 Power Supply Thi s ch apte r ex pl ain s the o per at ing v olt ag e of th e S 1C 33L0 3. 2.1 Pow er Supp ly Pins The S1 C3 3L 03 has the powe r sup ply pi ns s how n i n Tabl e 2.1 .1. Table 2. 1.
2 POWE R SU PPLY S1 C33L03 PRODUCT P ART EPSON A-13 A-1 A-2 2.3 Po wer Supply fo r I/O In ter fac e (V DDE ) The V DDE voltag e is u sed for in te rfa cin g w ith ex tern al I/ O si gnals . F or th e outp ut in terfa ce o f th e S 1C33 L03, th e V DDE v oltag e is u sed as h igh le ve l an d th e V SS v olt ag e as lo w le vel.
3 IN TE RNAL MEMORY A-14 EPSON S1 C33 L03 P RODUCT PART 3 Inter nal Mem ory Thi s ch apte r ex plain s th e in te rnal m emo ry co nfig ura tio n. Fig ure 3.
3 IN TE RNAL MEMORY S1 C33L03 PRODUCT P ART EPSON A-15 A-1 A-3 3.2 RAM The S1 C3 3L 03 has a bui lt- in 8KB RA M. Th e RAM is a lloca ted t o Are a 0, a ddre ss 0x00 0000 0 to a ddre ss 0x00 01 FFF.
4 PERIPHE RAL CIRCU I TS A-16 EPSON S1 C33 L03 P RODUCT PART 4 Per ip h era l Circuits Thi s ch apte r li sts the b uil t-i n p eri phera l ci rcu it s an d th e I/ O mem ory m ap. F or d eta ils o f th e ci rcu it s, re fer to th e "S1C 33 L 03 F UN CTI ON P AR T " .
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-17 A-1 A-4 4.2 I/O Memo ry Ma p Table 4. 2.1 I/ O Me mo r y Ma p Name Address Register name Bit Function Setting Init. R/W Remarks – P8TPCK5 P8TPCK4 D7–2 D1 D0 reserved 8-bit timer 5 clock selection 8-bit timer 4 clock selection – 0 0 – R/W R/W 0 when being read.
4 PERIPHE RAL CIRCU I TS A-18 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks – – P16TON3 P16TS32 P16TS31 P16TS30 D7–4 D3 D2 D1 D0 reserved 16-bit timer 3 clock control 16-bit timer 3 clock division ratio selection – 0 0 0 0 – R/W R/W 0 when being read.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-19 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks 1 On 0 Off P8TON3 P8TS32 P8TS31 P8TS30 P8TON2 P8TS22 P8TS21 P8TS20.
4 PERIPHE RAL CIRCU I TS A-20 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks – TCHD5 TCHD4 TCHD3 TCHD2 TCHD1 TCHD0 D7–6 D5 D4 D3 D2 D1 D0 reserved Clock timer minute counter data TCHD5 = MSB TCHD0 = LSB – X X X X X X – R/W 0 when being read.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-21 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks – PTOUT0 PSET0 PTRUN0 D7–3 D2 D1 D0 reserved 8-bit timer 0 clock output control 8-bit timer 0 preset 8-bit timer 0 Run/Stop control – 0 – 0 – R/W W R/W 0 when being read.
4 PERIPHE RAL CIRCU I TS A-22 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks – PTOUT3 PSET3 PTRUN3 D7–3 D2 D1 D0 reserved 8-bit timer 3 clock output control 8-bit timer 3 preset 8-bit timer 3 Run/Stop control – 0 – 0 – R/W W R/W 0 when being read.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-23 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks WRWD – D7 D6–0 EWD write protection – 0 – R/W – 0 when being read.
4 PERIPHE RAL CIRCU I TS A-24 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks CLKDT1 CLKDT0 PSCON – CLKCHG SOSC3 SOSC1 D7 D6 D5 D4–3 D2 D1 D0 Syste.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-25 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks 0x0 to 0xFF(0x7F) TXD07 TXD06 TXD05 TXD04 TXD03 TXD02 TXD01 TXD00 D7 D6 D5 D4 D3 D2 D1 D0 Serial I/F Ch.0 transmit data TXD07(06) = MSB TXD00 = LSB X X X X X X X X R/W 7-bit asynchronous mode does not use TXD07.
4 PERIPHE RAL CIRCU I TS A-26 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks 0x0 to 0xFF(0x7F) TXD17 TXD16 TXD15 TXD14 TXD13 TXD12 TXD11 TXD10 D7 D6 D5 D4 D3 D2 D1 D0 Serial I/F Ch.1 transmit data TXD17(16) = MSB TXD10 = LSB X X X X X X X X R/W 7-bit asynchronous mode does not use TXD17.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-27 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks TXEN2 RXEN2 EPR2 PMD2 STPB2 SSCK2 SMD21 SMD20 D7 D6 D5 D4 D3 D2 D1 D0 Ch.2 transmit enable Ch.2 receive enable Ch.2 parity enable Ch.
4 PERIPHE RAL CIRCU I TS A-28 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 D7 D6 D5 D4 D3 D2 D1 D0 A/D conve.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-29 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks – 0 to 7 0 to 7 – – PP1L2 PP1L1 PP1L0 – PP0L2 PP0L1 PP0L0 .
4 PERIPHE RAL CIRCU I TS A-30 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks – 0 to 7 0 to 7 – – PSIO02 PSIO01 PSIO00 – P8TM2 P8TM1 P8TM0 D7 D6 D5 D4 D3 D2 D1 D0 reserved Serial interface Ch.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-31 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks – EK1 EK0 EP3 EP2 EP1 EP0 D7–6 D5 D4 D3 D2 D1 D0 reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 – – 0 0 0 0 0 0 – R/W R/W R/W R/W R/W R/W 0 when being read.
4 PERIPHE RAL CIRCU I TS A-32 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks – FK1 FK0 FP3 FP2 FP1 FP0 D7–6 D5 D4 D3 D2 D1 D0 reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 – – X X X X X X – R/W R/W R/W R/W R/W R/W 0 when being read.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-33 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.
4 PERIPHE RAL CIRCU I TS A-34 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks HSD1S3 HSD1S2 HSD1S1 HSD1S0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 D7 D6 D5 D4 D3 D2 D1 D0 High-speed DMA Ch.1 trigger set-up High-speed DMA Ch.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-35 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks – CFK54 CFK53 CFK52 CFK51 CFK50 D7–5 D4 D3 D2 D1 D0 reserved K.
4 PERIPHE RAL CIRCU I TS A-36 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks T8CH5S0 SIO3TS0 T8CH4S0 SIO3RS0 SIO2TS0 SIO3ES0 SIO2RS0 SIO2ES0 D7 D6 D5 D4 D3 D2 D1 D0 8-bit timer 5 underflow SIO Ch.3 transmit buffer empty 8-bit timer 4 underflow SIO Ch.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-37 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks – SCPK04 SCPK03 SCPK02 SCPK01 SCPK00 D7–5 D4 D3 D2 D1 D0 reser.
4 PERIPHE RAL CIRCU I TS A-38 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks – IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 D7 D6 D5 D4 D3 D2 D1 D0 res.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-39 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks CFEX7 CFEX6 CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 CFEX0 D7 D6 D5 D4 D3 D2 .
4 PERIPHE RAL CIRCU I TS A-40 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks – A12SZ A12DF1 A12DF0 – A12WT2 A12WT1 A12WT0 DF–7 D6 D5 D4 D3 D2 D1.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-41 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks – A6DF1 A6DF0 – A6WT2 A6WT1 A6WT0 – A5SZ A5DF1 A5DF0 – A5W.
4 PERIPHE RAL CIRCU I TS A-42 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks 1 Successive 0 Normal – A3EEN CEFUNC1 CEFUNC0 CRAS RPRC1 RPRC0 – CASC.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-43 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks – 1 Enabled 0 Disabled 1 Enabled 0 Disabled A18AS A16AS A14AS A1.
4 PERIPHE RAL CIRCU I TS A-44 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR0A15 CR0A14 CR0A13 CR0A12 CR0A11 CR0A10 CR0A9 CR0A8 CR0A7 CR.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-45 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR1A15 CR1A14 CR1A13 CR1A12 CR1A11 CR1A10 CR1A9 CR1A8 C.
4 PERIPHE RAL CIRCU I TS A-46 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR2A15 CR2A14 CR2A13 CR2A12 CR2A11 CR2A10 CR2A9 CR2A8 CR2A7 CR.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-47 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR3A15 CR3A14 CR3A13 CR3A12 CR3A11 CR3A10 CR3A9 CR3A8 C.
4 PERIPHE RAL CIRCU I TS A-48 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR4A15 CR4A14 CR4A13 CR4A12 CR4A11 CR4A10 CR4A9 CR4A8 CR4A7 CR.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-49 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR5A15 CR5A14 CR5A13 CR5A12 CR5A11 CR5A10 CR5A9 CR5A8 C.
4 PERIPHE RAL CIRCU I TS A-50 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks DBASEL15 DBASEL14 DBASEL13 DBASEL12 DBASEL11 DBASEL10 DBASEL9 DBASEL8 DBA.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-51 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks TC0_L7 TC0_L6 TC0_L5 TC0_L4 TC0_L3 TC0_L2 TC0_L1 TC0_L0 BLKLEN07 BLKLEN06 BLKLEN05 BLKLEN04 BLKLEN03 BLKLEN02 BLKLEN01 BLKLEN00 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.
4 PERIPHE RAL CIRCU I TS A-52 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks D0ADRL15 D0ADRL14 D0ADRL13 D0ADRL12 D0ADRL11 D0ADRL10 D0ADRL9 D0ADRL8 D0ADRL7 D0ADRL6 D0ADRL5 D0ADRL4 D0ADRL3 D0ADRL2 D0ADRL1 D0ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-53 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks TC1_L7 TC1_L6 TC1_L5 TC1_L4 TC1_L3 TC1_L2 TC1_L1 TC1_L0 BLKLEN17 BLKLEN16 BLKLEN15 BLKLEN14 BLKLEN13 BLKLEN12 BLKLEN11 BLKLEN10 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.
4 PERIPHE RAL CIRCU I TS A-54 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks D1ADRL15 D1ADRL14 D1ADRL13 D1ADRL12 D1ADRL11 D1ADRL10 D1ADRL9 D1ADRL8 D1ADRL7 D1ADRL6 D1ADRL5 D1ADRL4 D1ADRL3 D1ADRL2 D1ADRL1 D1ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-55 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks TC2_L7 TC2_L6 TC2_L5 TC2_L4 TC2_L3 TC2_L2 TC2_L1 TC2_L0 BLKLEN27 BLKLEN26 BLKLEN25 BLKLEN24 BLKLEN23 BLKLEN22 BLKLEN21 BLKLEN20 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.
4 PERIPHE RAL CIRCU I TS A-56 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks D2ADRL15 D2ADRL14 D2ADRL13 D2ADRL12 D2ADRL11 D2ADRL10 D2ADRL9 D2ADRL8 D2ADRL7 D2ADRL6 D2ADRL5 D2ADRL4 D2ADRL3 D2ADRL2 D2ADRL1 D2ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-57 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks TC3_L7 TC3_L6 TC3_L5 TC3_L4 TC3_L3 TC3_L2 TC3_L1 TC3_L0 BLKLEN37 BLKLEN36 BLKLEN35 BLKLEN34 BLKLEN33 BLKLEN32 BLKLEN31 BLKLEN30 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.
4 PERIPHE RAL CIRCU I TS A-58 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks D3ADRL15 D3ADRL14 D3ADRL13 D3ADRL12 D3ADRL11 D3ADRL10 D3ADRL9 D3ADRL8 D3ADRL7 D3ADRL6 D3ADRL5 D3ADRL4 D3ADRL3 D3ADRL2 D3ADRL1 D3ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-59 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks – – SDRAR0 SDRAR1 – SDRPC0 SDRPC1 – D7 D6 D5–4 D3 D2 D1.
4 PERIPHE RAL CIRCU I TS A-60 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks SDRTRCD1 SDRTRCD0 SDRTRSC SDRTRRD1 SDRTRRD0 – D7–6 D5 D4–3 D2–0 SDRAM t RCD spec SDRAM t RSC spec SDRAM t RRD spec reserved 0 0 0 0 0 – R/W R/W R/W – 0 when being read.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-61 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks PCODE5 PCODE4 PCODE3 PCODE2 PCODE1 PCODE0 RCODE1 RCODE0 D7 D6 D5 D.
4 PERIPHE RAL CIRCU I TS A-62 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks VNDPF – VNDP5 VNDP4 VNDP3 VNDP2 VNDP1 VNDP0 D7 D6 D5 D4 D3 D2 D1 D0 Vertical non-display period status reserved Vertical non-display period 0 – 0 0 0 0 0 0 R – R/W 0 when being read.
4 PERIPHE RAL CIRCU I TS S1 C33L03 PRODUCT P ART EPSON A-63 A-1 A-4 Name Address Register name Bit Function Setting Init. R/W Remarks – S1VSIZE9 S1VSIZE8 D7–2 D1 D0 reserved Screen 1 vertical size (high-order 2 bits) – 0 0 – R/W 0 when being read.
4 PERIPHE RAL CIRCU I TS A-64 EPSON S1 C33 L03 P RODUCT PART Name Address Register name Bit Function Setting Init. R/W Remarks VRAMAR VRAMWT2 VRAMWT1 VRAMWT0 EDMAEN BREQEN LCDCST LCDCEC D7 D6 D5 D4 D3.
5 POW ER- DO WN C O NTROL S1 C33L03 PRODUCT P ART EPSON A-65 A-1 A-5 5 Power - Down Co ntrol Thi s ch apte r d esc ribes th e co nt ro ls u sed to re du ce p ower co ns ump tio n o f th e d evi ce .
5 POW ER- DO WN C O NTROL A-66 EPSON S1 C33 L03 P RODUCT PART Func tion Con trol bit "1" "0" Defa ult System cl oc k s wit ch ov er CLK CH G(D2 ) / Power control register(0x40180) .
5 POW ER- DO WN C O NTROL S1 C33L03 PRODUCT P ART EPSON A-67 A-1 A-5 The s ame c loc k sour ce m us t b e us ed fo r th e p res ca ler o per at ing cl oc k an d th e C PU o per at ing cl oc k.
6 BASIC EXTE RNAL WIRING DIAG RAM A-68 EPSON S1 C33 L03 P RODUCT PART 6 Basic Ex ternal Wiring Diag ra m S1C33L03 [The potential of the substrate (back of the chip) is V SS .
7 PR EC AUTIONS ON MOU NTING S1 C33 205 PRODUCT PART EPSON A-69 A-1 A-7 7 Pr ecauti ons o n Mounti ng The f o llow ing show s the p rec au tio ns w he n desi gn ing th e b oar d an d mou nt ing t he IC .
7 PR EC AUTIONS ON MOU NTING A-70 EPSON S1 C33 205 PRODUCT PART (2) Whe n co nn ec ti n g b etw ee n t h e V DD an d V SS p ins w ith a b yp ass ca pa ci tor , th e pi ns sh ou ld b e co nnec te d as sh or t as p oss ible.
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A-71 A-1 A-8 8 Electri cal Char acte risti cs 8.1 Absolute Maxim u m Rat ing (V SS =0V) Item Symbol Condition Rated value Unit ∗ Supply vol tag e V DD -0.3 to +4 .0 V C33 I/O pow er volta ge V DDE -0.
8 ELEC TRI CAL CHARACTE RI STICS A-72 EPSON S1 C33 L03 P RODUCT PART 8.2 Recommen ded Op eratin g Condition s 1) 3. 3 V/5.0 V dual po wer so urce (V SS =0V) Item Symbol Con dit ion Min. Typ. Max. Unit ∗ Supply vol ta ge (hi gh v olta ge) V DDE 4. 50 5.
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A-73 A-1 A-8 8.3 DC Characteristics 1) 3.3 V/5. 0 V dual power so urce (Unless otherw is e spec ifi ed: V DDE =5 V±0.5 V, V DD =2 .7V to 3.6V, V SS =0V , Ta=- 40° C to +8 5°C) Item Symbol Condition Min.
8 ELEC TRI CAL CHARACTE RI STICS A-74 EPSON S1 C33 L03 P RODUCT PART 3) 2. 0 V sin gle po w er sour ce (Unless otherw is e s pecifi ed: V DDE =V DD =2 V±0.
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A-75 A-1 A-8 8.4 Current Co nsump tion 1) 3. 3 V power sour ce (Unless otherw is e spec ifi ed: V DDE =2 .7V to 5. 5V, V DD =2 .7V to 3.6V, V SS =0V , Ta=- 40° C to +8 5°C) Item Symbol Condition Min.
8 ELEC TRI CAL CHARACTE RI STICS A-76 EPSON S1 C33 L03 P RODUCT PART 8.5 A/D Converter Chara c teristics 1) 3. 3 V/5.0 V dual po wer so urce (Unless otherw is e spec ifi ed: V DDE =AV DDE =4 .5V to 5. 5V, V DD =2 .7V to 3. 6V, V SS =0V, Ta =-40° C to +8 5°C, ST[1 :0]=11) Item Symbol Condition Min.
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A-77 A-1 A-8 V'[000]h 3FF 3FE 3FD 003 002 001 000 V SS AV DDE Integral linearity error E L = [LSB] V N ' - V N 1LSB' Digit.
8 ELEC TRI CAL CHARACTE RI STICS A-78 EPSON S1 C33 L03 P RODUCT PART 8.6 AC Characteristics 8.6.1 Sym bol D escrip tion t CYC : Bus- clo ck cy cle tim e • In x1 mode , t CYC = 50 ns (20 MHz ) wh en .
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A-79 A-1 A-8 8.6.3 C33 Block AC Ch arac ter istic Table s Ex te rn al cl ock input characteristics (No te) T he se AC ch ar ac ter ist ics appl y to in pu t si gn als fr om o uts id e the IC .
8 ELEC TRI CAL CHARACTE RI STICS A-80 EPSON S1 C33 L03 P RODUCT PART Comm on chara cterist ics 1) 3. 3 V/5.0 V dual po wer so urce (Unless otherw is e spec ifi ed: V DDE =5 .0V ± 0. 5V, V DD =2 .7V to 3. 6V, V SS =0V, Ta =-40° C to +8 5°C) Item Sym bol Min.
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A-81 A-1 A-8 SRAM r e ad cycle 1) 3. 3 V/5.0 V dual po wer so urce (Unless otherw is e spec ifi ed: V DDE =5 .0V ± 0. 5V, V DD =2 .7V to 3. 6V, V SS =0V, Ta =-40° C to +85°C ) Item Sym bol Min.
8 ELEC TRI CAL CHARACTE RI STICS A-82 EPSON S1 C33 L03 P RODUCT PART DRAM acc ess cyc le common ch ara cterist ics 1) 3. 3 V/5.0 V dual po wer so urce (Unless otherw is e spec ifi ed: V DDE =5 .0V ± 0. 5V, V DD =2 .7V to 3. 6V, V SS =0V, Ta =-40° C to +8 5°C) Item Sym bol Min.
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A-83 A-1 A-8 DRAM random access cyc le and DRAM fast- page cyc le 1) 3. 3 V/5.0 V dual po wer so urce (Unless otherw is e spec ifi ed: V DDE =5 .0V ± 0. 5V, V DD =2 .7V to 3. 6V, V SS =0V, Ta =-40° C to +85°C ) Item Sym bol Min.
8 ELEC TRI CAL CHARACTE RI STICS A-84 EPSON S1 C33 L03 P RODUCT PART SD RA M access cyc le 1) #X 2SP D = "1 " (C P U : SD RAM cl o ck = 1 : 1), 3.3 V sin gle po wer so urce (Unless otherw is e spec ifi ed: V DDE =V DD =3. 0V to 3.6V, V SS =0V , Ta=- 40° C to +8 5°C) Item Sym bol Min.
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A-85 A-1 A-8 Burs t RO M read cyc le 1) 3. 3 V/5.0 V dual po wer so urce (Unless otherw is e spec ifi ed: V DDE =5 .0V ± 0. 5V, V DD =2 .7V to 3. 6V, V SS =0V, Ta =-40° C to +85°C ) Item Sym bol Min.
8 ELEC TRI CAL CHARACTE RI STICS A-86 EPSON S1 C33 L03 P RODUCT PART I nput, Output and I/O port 1) 3. 3 V/5.0 V dual po wer so urce (Unless otherw is e spec ifi ed: V DDE =5 .0V ± 0. 5V, V DD =2 .7V to 3. 6V, V SS =0V, Ta =-40° C to +8 5°C) Item Sym bol Min.
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A-87 A-1 A-8 8.6.4 C33 Block AC Ch aracteri stic Ti ming Ch arts Clo ck OSC3 (High-speed clock) t C3 BCLK (Clock output) t C3 t C3H t C3E.
8 ELEC TRI CAL CHARACTE RI STICS A-88 EPSON S1 C33 L03 P RODUCT PART SRAM re ad c y cle ( b as i c cyc le : 1 cyc le) BCLK A[23:0] #CEx #RD D[15:0] #WAIT t C3 t AD t CE1 t CE2 t RDD2 t RDD1 t RDAC1 t .
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A-89 A-1 A-8 SRAM writ e cycle (ba sic cycle : 2 cycle s) BCLK A[23:0] #CEx #WR D[15:0] #WAIT C1 C2 t AD t CE1 t CE2 t WRD2 t WRD1 t WTS .
8 ELEC TRI CAL CHARACTE RI STICS A-90 EPSON S1 C33 L03 P RODUCT PART DRAM random access cycle (basic cyc le) BCLK A[23:0] #RAS #HCAS/ #LCAS #RD D[15:0] #WE D[15:0] RAS1 Data transfer #1 Next data tran.
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A-91 A-1 A-8 ED O DRAM random access cyc le (basic cycle ) BCLK A[23:0] #RAS #HCAS/ #LCAS #RD D[15:0] #WE D[15:0] RAS1 Data transfer #1 N.
8 ELEC TRI CAL CHARACTE RI STICS A-92 EPSON S1 C33 L03 P RODUCT PART DRAM CAS -b e fo r e -R AS ref resh cyc le BCLK #RAS #HCAS/ #LCAS #WE CBR refresh cycle C CBR1 C CBR2 C CBR3 t RASD2 t RASD1 t CASD.
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A-93 A-1 A-8 SD RA M access cyc le (Bank, Row) (Column) t WED2 t CASD2 BCLK SDCKE A[23:0] SDA10 #SDCEx #SDRAS #SDCAS #SDWE (read) D[15:0].
8 ELEC TRI CAL CHARACTE RI STICS A-94 EPSON S1 C33 L03 P RODUCT PART SDRAM a uto-r efresh cyc le t CASD2 BCLK SDCKE A[23:0] SDA10 #SDCEx #SDRAS #SDCAS #SDWE D[15:0] HDQM/ LDQM Auto refresh nop nop H t CED1 t CED2 t WED1 t WED2 nop nop t RASD1 t RASD2 t CASD1 ∗ A pr echarge cycle is neces sar y before en terin g the au to refr esh mode.
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A-95 A-1 A-8 Burs t RO M read cyc le BCLK A[23:2] A[1:0] #CEx #RD D[15:0] SRAM read cycle Burst cycle Burst cycle Burst cycle t AD t AD t.
8 ELEC TRI CAL CHARACTE RI STICS A-96 EPSON S1 C33 L03 P RODUCT PART 8.6.5 L CD Interface AC Characteristics Cond ition s: V DDE =3.3 V± 10 % or 5. 0V± 10 % , Ta=- 40° C t o +85° C , C L =6 0p F (LCD pane l i nt erf ac e) T rise and T fall for all in pu ts m ust b e less than 5 n s (10% –90 %).
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A-97 A-1 A-8 4- bit single m onochrom e panel t iming FPFRAME FPLINE DRDY (MOD) FPDAT[7:4] VDP VNDP FPLINE DRDY (MOD) FPSHIFT FPDAT7 FPDA.
8 ELEC TRI CAL CHARACTE RI STICS A-98 EPSON S1 C33 L03 P RODUCT PART Frame Pulse Line Pulse DRDY (MOD) Sync Timing 2 1 t 2 t 1 t 5 t 6 t 8 t 9 t 7 t 14 t 11 t 10 t 12 t 13 t 4 t 3 Line Pulse Shift Pulse FPDAT[7:4] Data Timing Note :F o r t h i s timin g diagra m FPSMASK (D 2/0x3 9FFE1) is s et to " 1".
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A-99 A-1 A-8 8- bit single m onochrom e panel t iming FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] VDP VNDP FPLINE DRDY (MOD) FPSHIFT FPDAT7 FPDA.
8 ELEC TRI CAL CHARACTE RI STICS A- 100 EPSON S1 C33 L03 P RODUCT PART Frame Pulse Line Pulse DRDY (MOD) Sync Timing 2 1 t 2 t 1 t 5 t 6 t 8 t 9 t 7 t 14 t 11 t 10 t 12 t 13 t 4 t 3 Line Pulse Shift Pulse FPDAT[7:0] Data Timing Note :F o r t h i s timin g diagra m FPSMASK (D 2/0x3 9FFE1) is s et to " 1".
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A- 101 A-1 A-8 4-b it single colo r panel timing FPFRAME FPLINE DRDY (MOD) FPDAT[7:4] VDP VNDP FPLINE DRDY (MOD) FPSHIFT FPDAT7 FPDAT6 FP.
8 ELEC TRI CAL CHARACTE RI STICS A- 102 EPSON S1 C33 L03 P RODUCT PART Frame Pulse Line Pulse DRDY (MOD) Sync Timing 2 1 t 2 t 1 t 5 t 6 t 8 t 9 t 7 t 14 t 11 t 10 t 12 t 13 t 4 t 3 Line Pulse Shift Pulse FPDAT[7:4] Data Timing 4-b it Si ngl e C o lor Pan el AC Timin g Symb ol Pa r ame ter M in.
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A- 103 A-1 A-8 8-b it single co lor p a nel timing (Format 1) FPFRAME FPLINE FPDAT[7:0] VDP VNDP FPLINE FPSHIFT FPSHIFT2 FPDAT7 FPDAT6 FP.
8 ELEC TRI CAL CHARACTE RI STICS A- 104 EPSON S1 C33 L03 P RODUCT PART Frame Pulse Line Pulse Sync Timing t 2 t 1 t 6b t 6a t 8 t 9 t 7a t 7b t 14 t 11 t 10 t 12 t 13 t 12 t 13 t 4 t 3 Line Pulse Shift Pulse 2 Shift Pulse FPDAT[7:0] Data Timing 1 2 8-b it Si ngl e C o lor Pan el AC Timin g (For m at 1) Symb ol Pa r ame ter M in.
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A- 105 A-1 A-8 8-b it single co lor p a nel timing (Format 2) FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] VDP VNDP FPLINE DRDY (MOD) FPSHIFT FPD.
8 ELEC TRI CAL CHARACTE RI STICS A- 106 EPSON S1 C33 L03 P RODUCT PART Frame Pulse Line Pulse DRDY (MOD) Sync Timing 2 1 t 2 t 1 t 5 t 6 t 8 t 9 t 7 t 14 t 11 t 10 t 12 t 13 t 4 t 3 Line Pulse Shift Pulse FPDAT[7:0] Data Timing 8-b it Si ngl e C o lor Pan el AC Timin g (F orm at 2) Symb ol Pa r ame ter M in.
8 ELEC TRI CAL CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A- 107 A-1 A-8 8.7 Oscillat ion Charac terist ics Osc illatio n char ac ter ist ics ch an ge d epe nd ing o n co ndit ion s (b oard p att ern , com po nent s u sed , et c.) . Use th e follo w ing char ac ter ist ics as re fe ren ce v alu es .
8 ELEC TRI CAL CHARACTE RI STICS A- 108 EPSON S1 C33 L03 P RODUCT PART OSC3 cer amic osci llat ion (Unless otherw is e spec ifi ed: V SS =0V, Ta =25° C) Item Symbol Condition Min.
9 P ACKAGE S1 C33L03 PRODUCT P ART EPSON A- 109 A-1 A-9 9 Pac ka ge 9.1 Pl astic Packa ge QFP20-1 44pin (Unit: mm ) 20 ± 0.1 22 ± 0.4 73 108 20 ± 0.1 22 ± 0.4 37 72 INDEX 0.2 36 1 144 109 1.4 ± 0.1 0.1 1.7 max 1 0.5 ± 0.2 0 ° 10 ° 0.125 0.5 +0.
10 P AD LAYOU T A- 110 EPSON S1 C33 L03 P RODUCT PART 10 Pa d L a yout 10.1 Pad La you t D iag ram X Y (0, 0) 15 1 0 15 20 25 30 35 40 120 115 110 105 100 95 90 85 45 50 55 60 65 70 75 80 160 155 150 145 140 135 130 125 5.
10 P AD LAYOU T S1 C33L03 PRODUCT P ART EPSON A- 111 A-1 A-10 10.2 Pad Co ordi nate (Unit: µm) No. Pad name X Y No. P ad name X Y 1P 22/TM0 -2310.0 -2549.5 51 #RD 2843.5 -1210.0 2N .C. -2200.0 - 2549.5 52 V SS 2843.5 -1100.0 3P 23/TM1 -2090.0 -2549.5 53 D15 2843.
10 P AD LAYOU T A- 112 EPSON S1 C33 L03 P RODUCT PART No. Pad name X Y No. Pad name X Y 101 A4/SDA3 110.0 2549.5 131 V SS - 2843.5 1210.0 102 A5/SDA4 0.0 2549.5 132 DSIO - 2843.5 1100.0 103 V DDE - 110.0 2549.5 133 P14 /FOSC1/DCLK -2843.5 990.0 104 A6/SDA5 -220.
APPENDIX A < REFERENCE> E X T ERNAL DEVICE I NTERFACE TI MINGS S1 C33L03 PRODUCT P ART EPSON A- 113 A-1 A-ap Ap p e nd ix A <R efe r ence> Extern al D evice Interface Ti mi ngs Thi s sect .
APPENDIX A < REFERENCE> E X T ERNAL DEVICE I NTERFACE TI MINGS A- 114 EPSON S1 C33 L03 P RODUCT PART A.1 DRAM (70ns) DRAM i nterface set up exampl es – 70n s Op er ating fre que ncy RAS pr ech.
APPENDIX A < REFERENCE> E X T ERNAL DEVICE I NTERFACE TI MINGS S1 C33L03 PRODUCT P ART EPSON A- 115 A-1 A-ap DRAM : 70n s, CP U: 33M Hz , ra ndom read/write cyc l e 2 RAS cycle CAS cycle RAS pre.
APPENDIX A < REFERENCE> E X T ERNAL DEVICE I NTERFACE TI MINGS A- 116 EPSON S1 C33 L03 P RODUCT PART DRAM : 70n s, CP U: 25/20 MH z, random read/write cycle 1 RAS cycle CAS cycle RAS precharge 2.
APPENDIX A < REFERENCE> E X T ERNAL DEVICE I NTERFACE TI MINGS S1 C33L03 PRODUCT P ART EPSON A- 117 A-1 A-ap A.2 DRAM (60ns) DRAM i nterface set up exampl es – 60n s Op er ating fre que ncy RA.
APPENDIX A < REFERENCE> E X T ERNAL DEVICE I NTERFACE TI MINGS A- 118 EPSON S1 C33 L03 P RODUCT PART DRAM : 60n s, CP U: 33M Hz , ra ndom read/write cyc l e 2 RAS cycle CAS cycle RAS precharge 2.
APPENDIX A < REFERENCE> E X T ERNAL DEVICE I NTERFACE TI MINGS S1 C33L03 PRODUCT P ART EPSON A- 119 A-1 A-ap DRAM : 60n s, CP U: 25M Hz , ra ndom read/write cyc l e 1 RAS cycle CAS cycle RAS pre.
APPENDIX A < REFERENCE> E X T ERNAL DEVICE I NTERFACE TI MINGS A- 120 EPSON S1 C33 L03 P RODUCT PART DRAM : 60n s, CPU: 20M Hz , random read/write cycle 1 RAS cycle CAS cycle RAS precharge 2 t R.
APPENDIX A < REFERENCE> E X T ERNAL DEVICE I NTERFACE TI MINGS S1 C33L03 PRODUCT P ART EPSON A- 121 A-1 A-ap A.3 ROM and Burst ROM Burs t RO M and mask RO M interf ace setup exampl es Op er ating Normal read cycle Burst read cycle Output disable fr equency Wait cycle R ead cycle Wait cycle Read cycle delay cycle 20 MHz 2 3 1 2 1.
APPENDIX A < REFERENCE> E X T ERNAL DEVICE I NTERFACE TI MINGS A- 122 EPSON S1 C33 L03 P RODUCT PART RO M: 100ns , CPU : 25MH z, n o rm al read BCLK A[23:0] #CE9, 10 #RD D[15:0] RD data RO M: 10.
APPENDIX A < REFERENCE> E X T ERNAL DEVICE I NTERFACE TI MINGS S1 C33L03 PRODUCT P ART EPSON A- 123 A-1 A-ap A.4 SRAM (55n s) SR AM in terface set up exampl es – 55n s Op er ating Read cycle Output disab le fr equency Wait cycle R ead cycle Wr ite cycle de lay cycle 20 MHz 1 2 2 1.
APPENDIX A < REFERENCE> E X T ERNAL DEVICE I NTERFACE TI MINGS A- 124 EPSON S1 C33 L03 P RODUCT PART SRAM : 55ns , CPU : 20MHz, rea d cycle BCLK A[23:0] #CEx #RD D[15:0] RD data SRAM : 55ns , CP.
APPENDIX A < REFERENCE> E X T ERNAL DEVICE I NTERFACE TI MINGS S1 C33L03 PRODUCT P ART EPSON A- 125 A-1 A-ap A.5 SRAM (70n s) SR AM in terface set up exampl es – 70n s Op er ating Read cycle Output disab le fr equency Wait cycle R ead cycle Wr ite cycle de lay cycle 20 MHz 2 3 3 1.
APPENDIX A < REFERENCE> E X T ERNAL DEVICE I NTERFACE TI MINGS A- 126 EPSON S1 C33 L03 P RODUCT PART SRAM : 70ns , CPU : 25/20 MHz, rea d cyc le BCLK A[23:0] #CEx #RD D[15:0] RD data SRAM : 70ns.
APPENDIX A < REFERENCE> E X T ERNAL DEVICE I NTERFACE TI MINGS S1 C33L03 PRODUCT P ART EPSON A- 127 A-1 A-ap A.6 82 55A 8255A i nterface set up exampl es Op er ating Read cycle Output disab le fr equency Wait cycle R ead cycle Wr ite cycle de lay cycle 20 MHz 9 ∗ 11 0 1 0 3 .
APPENDIX B P I N CHARACTE RI STICS A- 128 EPSON S1 C33 L03 P RODUCT PART Ap p e nd i x B Pi n Char acteri sti cs Char acteristic Pin No. Si gnal name I/O cell name Input O ut p ut Pu ll- up/ down Powe.
APPENDIX B P I N CHARACTE RI STICS S1 C33L03 PRODUCT P ART EPSON A- 129 A-1 A-ap Char acteristic Pin No. Si gnal name I/O cell name Input O ut p ut Pu ll- up/ down Powe r supply Remarks 51 V DD LVDD 5.
APPENDIX B P I N CHARACTE RI STICS A- 130 EPSON S1 C33 L03 P RODUCT PART Char acteristic Pin No. Si gnal name I/O cell name Input O ut p ut Pu ll- up/ down Powe r supply Remarks 101 A14 /SDBA0 XHB C1T.
S1C33L03 FUNCTION PART.
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S1C33L03 F UNCTION PART I OUTLINE.
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I OUTLIN E: INTRO DUCTION S1C33 L 03 FU NCTI ON P ART EPSON B-I-1-1 A-1 B-I Intro I-1 INTR ODU CTION The Fu nc t ion Pa rt gi v es a detai led des cri pt ion of the va rious fu nc tio n b loc ks b uil t in to th e S eik o E ps on o rig inal 32- bit micr oco mpu ter S1 C33L 03.
I OUTLIN E: INTRO DUCTION B-I-1-2 EPSON S1C3 3 L 03 FUNCTI ON P ART TH IS PAGE I S BLANK..
I OUTLINE: BLOC K DIAGRAM S1C33 L 03 FU NCTI ON P ART EPSON B-I-2-1 A-1 B-I Block I-2 BLOC K DIA GRA M The S1 C3 3L 03 con sists of sev en ma jor blo cks: C3 3 Co re Bloc k, C3 3 Per iphe r al Bl ock , C33 An alo g Bloc k , C33 DMA Bloc k , C33 SD RAM Co nt rol l er Bl oc k, C3 3 LCD Co ntr ol ler Bl ock and C33 I ntern al Me mory Bl oc k.
I OUTLINE: BLOC K DIAGRAM B-I-2-2 EPSON S1C3 3 L 03 FUNCTI ON P ART C3 3 Core Block The C3 3 Core Bloc k consi st s of a fu nc tio na l b loc k C3 3_ CO R E i ncl uding C PU , BCU (B us Con tro l U ni.
I OUTLINE: LIST OF PINS S1C33 L 03 FU NCTI ON P ART EPSON B-I-3-1 A-1 B-I Pin I-3 LIST OF PINS Li st of E xte rnal I/O Pins The f o llow ing li sts th e ex te rnal I/ O p ins of th e C 33 C or e Blo ck, Peri ph era l Blo ck an d LCD C on trolle r B lo ck.
I OUTLINE: LIST OF PINS B-I-3-2 EPSON S1C3 3 L 03 FUNCTI ON P ART Pin name P in No. I/O Pull -up Func tion # HCAS #S DCAS 77 O – #HCAS : DRAM co lumn address st robe ( high byte) signal w hen S DREN.
I OUTLINE: LIST OF PINS S1C33 L 03 FU NCTI ON P ART EPSON B-I-3-3 A-1 B-I Pin Table 3. 2 Li st of Pin s fo r HS DMA C on trol S ig nal s Pin name Pin No. I/O Pull-u p Fu nction K50 #DMAREQ0 41 I Pul l-up K50: Input port when CF K50(D0/0x4 02C0) = "0" (defaul t) #DMAREQ0: HSDMA Ch.
I OUTLINE: LIST OF PINS B-I-3-4 EPSON S1C3 3 L 03 FUNCTI ON P ART Table 3. 3 Li st of Pin s fo r In terna l P eri phe ral C irc uits Pin name P in No. I/O Pull -up Func tion K50 #DMAREQ0 41 I Pull-up K50: Input port when CF K50(D0/0x402C 0) = "0" (defaul t) #DMAREQ0: HSDMA Ch.
I OUTLINE: LIST OF PINS S1C33 L 03 FU NCTI ON P ART EPSON B-I-3-5 A-1 B-I Pin Pin name P in No. I/O Pull -up Func tion P11 EXC L1 T8UF 1 DST1 121 I/O – P11 : I/O port when C FP11(D1/0x4 02D4) = &quo.
I OUTLINE: LIST OF PINS B-I-3-6 EPSON S1C3 3 L 03 FUNCTI ON P ART Pin name P in No. I/O Pull -up Func tion P26 TM4 SOU T2 6 I/O – P26 : I/O port when CF P26(D6/0x4 02D8) = "0" (defaul t) TM 4: 16-bit ti m er 4 output w hen CFP26(D6/0x4 02D8) = "1" SO UT 2: Se ri al I/F Ch.
I OUTLINE: LIST OF PINS S1C33 L 03 FU NCTI ON P ART EPSON B-I-3-7 A-1 B-I Pin Table 3. 4 Li st of Pin s fo r LCD Con tr oll er Pin name P in No. I/O Pull -up Func tion FP DA T[ 7:4] 13–16 O – 4 hi.
I OUTLINE: LIST OF PINS B-I-3-8 EPSON S1C3 3 L 03 FUNCTI ON P ART TH IS PAGE I S BLANK..
S1C33L03 F UNCTION PART II CORE BLOCK.
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II CO RE BLOC K: INTROD UCTION S1C33 L 03 FU NCTI ON P ART EPSON B-II-1-1 A-1 B-II Intro II-1 INTR ODU CTION The c ore bl oc k cons is ts o f a func ti o na l bl oc k C 33 _C O RE in cl ud ing C PU, B.
II CO RE BLOC K: INTROD UCTION B-II-1-2 EPSON S1C 33 L 03 FUNCTI ON P ART TH IS PAGE I S BLANK..
II CO RE BLOC K: CPU AND OPERA T I NG M ODE S1C33 L 03 FU NCTI ON P ART EPSON B-II-2-1 A-1 B-II CPU II-2 CPU AND OPERA TING MODE CPU The C3 3 Co re Bloc k empl oys the S1C3 3000 32-bi t RISC typ e CPU a s the cor e CP U.
II CO RE BLOC K: CPU AND OPERA T I NG M ODE B-II-2-2 EPSON S1C 33 L 03 FUNCTI ON P ART Sta ndb y Mo de The CP U sup p or ts th re e st an db y mod es : tw o H ALT m od es and a S LE EP m od e. By s e tti ng the C PU in th e st an dby m ode, p owe r con s ump t io n ca n g rea t ly be redu ce d.
II CO RE BLOC K: CPU AND OPERA T I NG M ODE S1C33 L 03 FU NCTI ON P ART EPSON B-II-2-3 A-1 B-II CPU Not es on S tandb y Mode Int er r upts The s tand b y mod e can b e ca nc el ed b y an in te rru pt.
II CO RE BLOC K: CPU AND OPERA T I NG M ODE B-II-2-4 EPSON S1C 33 L 03 FUNCTI ON P ART Trap Ta bl e Tabl e 2. 1 s ho ws t he tr ap ta bl e in th e C 33 C or e.
II CO RE BLOC K: CPU AND OPERA T I NG M ODE S1C33 L 03 FU NCTI ON P ART EPSON B-II-2-5 A-1 B-II CPU HEX No. Vec tor numbe r (H ex address) Exc epti o n/ i nt e rr upt name Excep tion /inter rupt fac tor IDMA Ch. Pr ior ity 38 56(Base+E0) Seria l interface C h.
II CO RE BLOC K: CPU AND OPERA T I NG M ODE B-II-2-6 EPSON S1C 33 L 03 FUNCTI ON P ART TH IS PAGE I S BLANK..
II C ORE BLOCK: INITIA L RESET S1C33 L 03 FU NCTI ON P ART EPSON B-II-3-1 A-1 B-II Reset II-3 INIT IAL RES ET Pin s fo r I n itial Reset Tabl e 3.1 s hows t he pi ns us ed f or i nit ial res et. Table 3.1 Pin s fo r In itia l R eset Pin name I/O Func tion #R ESET I Initia l reset in put pi n (Low activ e) Low : Resets the CPU.
II C ORE BLOCK: INITIA L RESET B-II-3-2 EPSON S1C 33 L 03 FUNCTI ON P ART Pow er- on Reset Be s ure to rese t (c ol d start ) th e ch ip af ter tu rning o n the p ow er to st art o per at ing . Sin ce the #R ES ET pin is dir ect ly connec te d to an inpu t g ate , a p ow er- on re se t ci rcu it shou ld b e conf ig ure d o uts id e the ch ip .
II C ORE BLOCK: INITIA L RESET S1C33 L 03 FU NCTI ON P ART EPSON B-II-3-3 A-1 B-II Reset Boot Addr ess When the core C PU is in iti all y rese t, it re ad s th e re se t vect or (p ro gr am st art addr es s) fr om th e boo t ad dr es s (0x0 C 00 000) an d lo ads th e v ect or to th e P C (p ro gr am co un te r).
II C ORE BLOCK: INITIA L RESET B-II-3-4 EPSON S1C 33 L 03 FUNCTI ON P ART TH IS PAGE I S BLANK..
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II-4-1 A-1 B-II BCU II-4 BCU (Bus Co ntrol Unit) The BC U (Bus Cont r ol Un it) pr o vi de s an inte rfa ce fo r ex te rn al devi ce s an d o n-c hi p u ser logi c b loc k.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II-4-2 EPSON S1C 33 L 03 FUNCTI ON P ART User i nterface si gnals Table 4.2 Li st of U ser In terf a ce S ig nal s Si gnal name I/O Function Interna l _a d.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II-4-3 A-1 B-II BCU Combinat io n of S yste m Bus Con trol S ignals The bu s con trol sig nal pin s tha t hav e two or mo re f unc tions h ave thei r fu nc tio nalit y d ete rmin ed whe n an in te rfa ce method i s se le cte d by a p rog ra m.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II-4-4 EPSON S1C 33 L 03 FUNCTI ON P ART Me mo ry A re a Me mo ry Ma p Fig ure 4. 1 sh ows t h e mem o ry map su pp or te d b y th e B CU.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II-4-5 A-1 B-II BCU Ext erna l Memo ry Map a nd Chi p Enabl e The BC U ha s a 24- bi t ex te rnal ad dr es s b us (A[2 3:.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II-4-6 EPSON S1C 33 L 03 FUNCTI ON P ART Area Area 17–18 (#CE17+18) SRAM type 8 or 16 bits Areas 15–16 (#CE15+16) SRAM type 8 or 16 bits Area 14 (#CE14.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II-4-7 A-1 B-II BCU Using In ternal Me mory on Exter nal Me mory Are a The BC U a ll ow s usi ng of an i n terna l m emo ry in th e ex tern al m emo ry ar ea s.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II-4-8 EPSON S1C 33 L 03 FUNCTI ON P ART Area 10 Are a 10 is an ex te rn al mem o ry ar ea th at in cl ud es th e b oot ad dr es s (0 xC 000 00 ). T his ar ea su pp or ts two b oo t mod es . Note : In te rn al RO M is not prov id ed in th e S 1C 3 3L 03 .
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II-4-9 A-1 B-II BCU Area 10 m e mor y m ap Fig ure 4. 4 s how s t he m e mor y map of are a 10. Area 10 External ROM boot mode 0x0C00000 0x0FFFFFF External memory is accessed.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-10 EPSON S1C 33 L 03 FUNCTI ON P ART Set ting Ex terna l Bus Conditions The t ype, siz e , an d wait co nd it ion s of a d evi ce co nn ec te d to th e ex te rn al b us ca n b e in di vid ually se t fo r ea ch ar ea usi ng the co nt ro l re giste r (0 x4 8120 to 0 x481 30).
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-11 A-1 B-II BCU Set ting SRAM T i min g Co ndit ions The a r eas se t fo r th e S RAM al lo w wait cy cl es an d o utp ut di sable d ela y ti me to b e set.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-12 EPSON S1C 33 L 03 FUNCTI ON P ART Output disable delay tim e In ca se s w he n a d evi ce h avi ng a long o utp ut d isa ble ti me is co nn ecte d, if a re ad cy cl e fo r that d evi ce is follo w ed b y th e n ext ac cess , co nt en tio n for th e d ata b us may o ccur.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-13 A-1 B-II BCU Bus Oper ati on Data Arrangement in Me mory The S1 C3 3 Fa mi l y of de vic es ha n dle da ta i n byt es ( 8 b its), half-w ord s (1 6 b its) , and w or ds (3 2 b its) .
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-14 EPSON S1C 33 L 03 FUNCTI ON P ART For in formati on o n mem o ry conn ec tio n, se e F igu re 4.1 8.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-15 A-1 B-II BCU Byte 0 15 Data bus 0 #WRL 1 0 #WRH 0 1 A0 1 0 A1 ∗ ∗ No.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-16 EPSON S1C 33 L 03 FUNCTI ON P ART Data retained 15 Data bus 0 #WRL 0 0 #WRH X X A0 0 1 A1 ∗ ∗ No.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-17 A-1 B-II BCU Bus Clock The bu s clo ck i s gen erate d by t he BC U us i ng t he CP U sy stem cl oc k o utp ut fr om t h e cl oc k gene ra t or . Fig ure 4. 17 sh ows t he cl oc k sy st em .
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-18 EPSON S1C 33 L 03 FUNCTI ON P ART Sin ce t h e b us cl oc k is gene ra ted fr om the C PU sy st em cl oc k (C PU_ C LK), th e fo llo wing se tti ng s af fe ct th e bus cl oc k: 1. Se lec tio n of an os cil lat i on cir cui t ( OSC 3 or OS C1) 2.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-19 A-1 B-II BCU Bus Cycl es in E xte rnal S ystem In terfac e The f o llow ing sh ows a sa m ple SRA M co nn ect io n th e basi c b us cy cl es .
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-20 EPSON S1C 33 L 03 FUNCTI ON P ART The a bo v e exam p le sh ows a re ad cy cl e whe n a w ait mod e is in serte d v ia th e # WAI T si gn al. A wait m ode cons is tin g of 0 to 7 cy cl es can al so b e in serte d u sin g the w ait co ntro l b its.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-21 A-1 B-II BCU SRAM Wr it e Cycle s Basic write cyc le with n o wai t mode BCLK A[23:0] #CExx D[15:0] #WRH/#WRL #WAIT #WR #BSL/#BSH addr data C1 C2 Figur e 4.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-22 EPSON S1C 33 L 03 FUNCTI ON P ART Write cycle wi th wa it mode Exam ple: W h en the BC U has no int ern al w a i t mo de , and 1 wai t cycl e is in se rte d via th e # WAI T p in BCLK A[23:0] #CExx D[15:0] #WRH/#WRL #WAIT #WR #BSL/#BSH C1 CW C2 addr data Figur e 4.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-23 A-1 B-II BCU Burst ROM Read Cycles Burs t rea d cycle Ex am pl e: Wh en 4-c on se cu t iv e- bu r st a nd 2-wa i.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-24 EPSON S1C 33 L 03 FUNCTI ON P ART DRAM Direct Interface Outline of DRAM In terface Th e BC U inc or po r ates a DR AM di r ect in terfac e th at al lo ws D RAM to b e co nn ec te d dire ctl y to ar ea s 8 an d 7 o r ar eas 1 4 an d 1 3.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-25 A-1 B-II BCU DRAM Setting Conditions The DR AM interf ace al low s th e follo w ing cond it ion s to b e se le cted.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-26 EPSON S1C 33 L 03 FUNCTI ON P ART Colu mn add ress size When a c ce ss ing DRA M, ad dr es ses ar e d ivi de d in to a ro w ad dr es s an d a co lu m n addr es s as th ey ar e o utp ut . Choo se t he size o f th is co lum n ad dr es s usin g R CA, as sh ow n b elow.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-27 A-1 B-II BCU Re fresh RPC delay Use RP C0 to set the RP C de lay valu e o f a re fre sh cycl e (a d ela y ti me fr om th e imm ed ia tel y p rec eding pre char g e to th e fa ll o f #CA S).
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-28 EPSON S1C 33 L 03 FUNCTI ON P ART DRAM Read/Wri te Cycles The f o llow ing sh ows th e b asi c b us cycl es o f D RAM . The DR AM interf ace do es n ot ac cept w ait cy cl es in se rted v ia th e # WAIT p in.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-29 A-1 B-II BCU DRAM random wri te cycle Exam ple: RA S: 1 cyc l e; CAS : 2 cycl es ; Prec ha rg e: 1 cycl e BCLK A[11:0] #RASx #HCAS/ #LCAS #WE D[15:0] ROW COL write data RAS cycle CAS cycle Precharge cycle Figur e 4.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-30 EPSON S1C 33 L 03 FUNCTI ON P ART Opera tion i n successi ve RA S mo de Exam ple: RA S: 2 cyc l es ; CAS: 1 cycl e; P rec ha rg e: 2 cycl es BCLK .
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-31 A-1 B-II BCU DRAM Refresh Cy c les The DR AM interf ace sup p orts a C AS-b ef ore -R A S refre sh cycl e and a se lf- re fre sh cycl e.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-32 EPSON S1C 33 L 03 FUNCTI ON P ART Norm ally, DR AM speci f ica tio ns requ ire th at th e co nt ents o f al l ro w addr es ses b e re fre sh ed w ith in a certa in ti me b efore an d af ter a se lf- re fresh .
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-33 A-1 B-II BCU DRAM ref resh when bus owners hip control is re leased In sy st em s whe re D RAM is co nn ec te d d ire ctl y, a refre sh re qu es t co ul d ari se whi le co nt ro l o f th e bus ow ners hip is rel e ased fr om th e C PU.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-34 EPSON S1C 33 L 03 FUNCTI ON P ART I/O Memory of BCU Tabl e 4.2 3 sho ws t h e cont rol b its o f th e B CU. T hese I/ O mem o rie s ar e map pe d into th e ar ea (0 x4 8000 an d follo w ing addr es ses ) u sed fo r th e inte rna l 1 6-b it peri ph era l ci rcu it s.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-35 A-1 B-II BCU Name Address Register name Bit Function Setting Init.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-36 EPSON S1C 33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks – A6DF1 A6DF0 – A6WT2 A6WT1 A6WT0 – A5SZ.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-37 A-1 B-II BCU Name Address Register name Bit Function Setting Init.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-38 EPSON S1C 33 L 03 FUNCTI ON P ART A18SZ :A r e a s 1 8 –17 de vic e siz e se lec tion (DE) / Area s 18 –1 5 se t-u p reg iste r (0x 48120 ) A1.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-39 A-1 B-II BCU A14DR A :A r e a 1 4 D R A M s e l e ct i on (D8) / Area s 14 –1 3 se t-u p reg iste r (0x 48122 .
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-40 EPSON S1C 33 L 03 FUNCTI ON P ART A10DR A :A r e a 1 0 bur st ROM se lec tion (D8) / Area s 10 –9 set -up reg ister (0x 48126 ) A9DRA :A r e a 9 burst ROM sel ection ( D7) / Ar eas 10–9 se t-up reg iste r ( 0x481 26) Set are as 10 and 9 for use of bu rst RO M.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-41 A-1 B-II BCU RCA1– RCA0 : Col umn add ress s ize s elect io n (D[B:A ]) / Bus c ontro l regi st er (0 x4 812 E) Sel ect th e co lu mn ad dr es s si ze o f DRA M.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-42 EPSON S1C 33 L 03 FUNCTI ON P ART RRA1– RRA0 : Refres h RAS pu l se widt h selec tion ( D[6: 5] ) / Bus co nt rol r egis ter (0x 4812E ) Sel ect th e R AS p uls e wid th o f a C AS-b ef ore-R A S refre sh .
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-43 A-1 B-II BCU SWA ITE : #WAI T en able (D0) / Bus cont rol reg ister (0x481 2E ) Enab l e or dis abl e wai t cyc l e co nt ro l vi a the # WA I T pi n.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-44 EPSON S1C 33 L 03 FUNCTI ON P ART CRAS : Succes sive RAS m o de (D8) / DRAM t imi ng set-u p reg ister (0x 48130 ) Set th e su cc essiv e R AS m od e.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-45 A-1 B-II BCU A18I O :A r e a s 18–17 int erna l/e xterna l ac cess se lec tion (DF) / Acce ss cont rol reg ist.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-46 EPSON S1C 33 L 03 FUNCTI ON P ART A18RD :A r e a s 1 8 –17 r ead si gn al (D 7 ) / G /A re ad s i gnal c on tro l r egi st er (0 x4 8 13 8) A16R.
II CO RE BLOC K: BCU (Bus Co n trol Unit ) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 4-47 A-1 B-II BCU SDRENA : Enabl e SDRAM si g n al s (D7 ) / S DR A M control regi st er (0 x3 9F FC 1 ) Enab le the p ins u sed fo r the S DRA M .
II CO RE BLOC K: BCU (Bus Co n trol Unit ) B-II- 4-48 EPSON S1C 33 L 03 FUNCTI ON P ART TH IS PAGE I S BLANK..
II CO RE BLOC K: ITC (In t er rupt Controll er) S1C33 L 03 FU NCTI ON P ART EPSON B-II-5-1 A-1 B-II ITC II-5 ITC (In t err upt Co ntro ller) The C3 3 Core Bloc k conta i ns an i nt err u pt cont ro ll e r, mak i ng i t po ssi b le to co nt ro l al l in terru pts g enera ted b y the in te rna l peri ph era l ci rcu it s.
II CO RE BLOC K: ITC (In t er rupt Controll er) B-II-5-2 EPSON S1C 33 L 03 FUNCTI ON P ART C ontents of table "Hex N o." in di cat es an in terru pt n um ber in h exa de ci mal v alu e. "Vecto r numbe r (Ad dre ss )" in di cat es th e tr ap ta bl e' s v ect or n umbe r.
II CO RE BLOC K: ITC (In t er rupt Controll er) S1C33 L 03 FU NCTI ON P ART EPSON B-II-5-3 A-1 B-II ITC Inter rupt Fa ctors an d Intelli gent DMA Seve ral inte rru pt facto rs ca n b e se t so th at th ey ca n invo ke ID MA st art u p.
II CO RE BLOC K: ITC (In t er rupt Controll er) B-II-5-4 EPSON S1C 33 L 03 FUNCTI ON P ART Trap Ta bl e The C3 3 Core Bloc k allow s the ba se (star tin g) ad dr es s o f th e trap ta bl e to b e set b y th e TTB R re gi ste r.
II CO RE BLOC K: ITC (In t er rupt Controll er) S1C33 L 03 FU NCTI ON P ART EPSON B-II-5-5 A-1 B-II ITC Co nt ro l of Ma skab le Inter rupts Stru c tur e of the In terru pt Contr oller The i n terru pt co nt rolle r is co nf igur ed as s how n i n Fig ure 5.
II CO RE BLOC K: ITC (In t er rupt Controll er) B-II-5-6 EPSON S1C 33 L 03 FUNCTI ON P ART The I L is rewritt en fo r o nly m as kable in te rru pts and n ot fo r an y othe r tr ap s (e xc ep t a rese t). The I L is s e t to le ve l 0 (t hat is , al l in te rru pts ab ov e le vel 1 ar e en ab led) b y an initi al re se t.
II CO RE BLOC K: ITC (In t er rupt Controll er) S1C33 L 03 FU NCTI ON P ART EPSON B-II-5-7 A-1 B-II ITC Int er r upt en able regi ster Thi s reg ist er co ntro ls the o utp ut of an in te rru pt re qu es t to th e C PU.
II CO RE BLOC K: ITC (In t er rupt Controll er) B-II-5-8 EPSON S1C 33 L 03 FUNCTI ON P ART Inter rupt Prio rity Reg ister and In terrupt Le vels The i n terru pt p rio rity re gi ste r is a 3-bi t re gi ste r p rovid ed for ea ch in te rrupt sy st em .
II CO RE BLOC K: ITC (In t er rupt Controll er) S1C33 L 03 FU NCTI ON P ART EPSON B-II-5-9 A-1 B-II ITC IDMA Invoc ation The i n terru pt fa cto rs fo r w hi ch ID MA ch anne l n umbe rs ar e writ ten in T able 5 .1 h ave th e fu nc tion to in voke th e inte llig en t DM A (I DMA ).
II CO RE BLOC K: ITC (In t er rupt Controll er) B-II- 5-10 EPSON S1C 33 L 03 FUNCTI ON P ART Int er r upt after I D MA tr an s f er To ge ne ra te an int e rrupt a fter c omp let ion o f IDM A tr a nsfe r: The i n terru pt re qu est th at h as b een k ept p endin g ca n be g ene ra ted af ter co m pl etion o f th e DM A tr an sfe r.
II CO RE BLOC K: ITC (In t er rupt Controll er) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 5-11 A-1 B-II ITC HSDMA Invocation Som e in terrupt fa cto rs ca n in vo ke high -s pe ed D M As (HS DMA ). HSD M A t r i gger s et-up register The DM A blo c k co nt ains fo ur ch an ne l o f HSD MA ci rcu it .
II CO RE BLOC K: ITC (In t er rupt Controll er) B-II- 5-12 EPSON S1C 33 L 03 FUNCTI ON P ART I/O Memo ry of Interrupt Con trolle r Tabl e 5. 3 s hows the co nt ro l b its of th e in te rru pt co nt ro lle r. Table 5.3 Con tr ol Bit s of In ter ru pt C ont roll er Name Address Register name Bit Function Setting Init.
II CO RE BLOC K: ITC (In t er rupt Controll er) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 5-13 A-1 B-II ITC Name Address Register name Bit Function Setting Init.
II CO RE BLOC K: ITC (In t er rupt Controll er) B-II- 5-14 EPSON S1C 33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks E16TC5 E16TU5 – E16TC4 E16TU4 – D7 D6.
II CO RE BLOC K: ITC (In t er rupt Controll er) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 5-15 A-1 B-II ITC Name Address Register name Bit Function Setting Init.
II CO RE BLOC K: ITC (In t er rupt Controll er) B-II- 5-16 EPSON S1C 33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks HSD1S3 HSD1S2 HSD1S1 HSD1S0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 D7 D6 D5 D4 D3 D2 D1 D0 High-speed DMA Ch.
II CO RE BLOC K: ITC (In t er rupt Controll er) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 5-17 A-1 B-II ITC Name Address Register name Bit Function Setting Init. R/W Remarks T8CH5S0 SIO3TS0 T8CH4S0 SIO3RS0 SIO2TS0 SIO3ES0 SIO2RS0 SIO2ES0 D7 D6 D5 D4 D3 D2 D1 D0 8-bit timer 5 underflow SIO Ch.
II CO RE BLOC K: ITC (In t er rupt Controll er) B-II- 5-18 EPSON S1C 33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks – A10IR2 A10IR1 A10IR0 – A10BW1 A10BW.
II CO RE BLOC K: ITC (In t er rupt Controll er) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 5-19 A-1 B-II ITC Fxxx : In te rrup t fa ctor fl ag Indi ca te th e st atu s o f in te rru pt facto rs g enera ted .
II CO RE BLOC K: ITC (In t er rupt Controll er) B-II- 5-20 EPSON S1C 33 L 03 FUNCTI ON P ART DE xxx : ID MA e nabl e regi st er Enab l e or dis abl e th e IDM A re qu es t.
II CO RE BLOC K: ITC (In t er rupt Controll er) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 5-21 A-1 B-II ITC DENONL Y :I D M A e n able reg i st er s e t met ho d sele ct io n (D2 ) / Flag s et/re set m etho d sele ct re gi st er (0 x40 29 F) Sel ect th e m etho d fo r se tti ng th e ID MA enab le re gi ste rs.
II CO RE BLOC K: ITC (In t er rupt Controll er) B-II- 5-22 EPSON S1C 33 L 03 FUNCTI ON P ART SIO2 TS0 :S I O C h.2 tr ansmit -b uff er e mpty /FP3 inte rru pt fa ct or s witch in g (D3 ) / Inte rru pt fa ct or F P func tion s witch ing re gist er (0x4 0 2C5 ) Sw itch es th e inte rru pt fa ctor.
II CO RE BLOC K: ITC (In t er rupt Controll er) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 5-23 A-1 B-II ITC SIO2 RS1 : S IO Ch. 2 re ceiv e-bu ffer fu ll/ TM1 6 C h.5 c omp are B inte rrupt fa ct or s witch ing (D0 ) / Inte rru pt fa ct or T M16 func tio n s wit chin g re gi ster (0 x40 2CB ) Sw itch es th e inte rru pt fa ctor.
II CO RE BLOC K: ITC (In t er rupt Controll er) B-II- 5-24 EPSON S1C 33 L 03 FUNCTI ON P ART SIO3 ES1 :S I O C h. 3 rece iv e e rro r/TM 16 C h. 3 comp are A in te rrupt fa ct or s wit chin g (D5 ) / Inte rru pt fa ct or T M16 func tio n s witch in g re gi ster (0 x40 2CB ) Sw itch es th e inte rru pt fa ctor.
II CO RE BLOC K: ITC (In t er rupt Controll er) S1C33 L 03 FU NCTI ON P ART EPSON B-II- 5-25 A-1 B-II ITC TTBR0 9– TTBR00 :T r a p t a bl e bas e a d dress [ 9:0 ] (D[9 :0 ]) / T TBR low -or der re .
II CO RE BLOC K: ITC (In t er rupt Controll er) B-II- 5-26 EPSON S1C 33 L 03 FUNCTI ON P ART TH IS PAGE I S BLANK..
II CO RE BLOC K: CLG (Cloc k Generator) S1C33 L 03 FU NCTI ON P ART EPSON B-II-6-1 A-1 B-II CLG II-6 CLG (Clock Gene rator) Th is sect ion d esc ribes th e m et hod fo r co nt rollin g th e syst em cl oc k.
II CO RE BLOC K: CLG (Cloc k Generator) B-II-6-2 EPSON S1 C33 L03 FUNCTION P ART I/O P ins of Cloc k Gener ator Tabl e 6.1 lis ts t he I /O pin s of t he c lock gen erat or.
II CO RE BLOC K: CLG (Cloc k Generator) S1C33 L 03 FU NCTI ON P ART EPSON B-II-6-3 A-1 B-II CLG PLL The PL L inp uts the OSC 3 cl oc k an d m ul tip ly it s fr eq ue ncy. T he mul tip ly mod e shou ld b e set u sin g the P LL S[1: 0] pin s ac cord ing to th e OSC 3 cl oc k fr eq ue nc y.
II CO RE BLOC K: CLG (Cloc k Generator) B-II-6-4 EPSON S1 C33 L03 FUNCTION P ART Set ting a nd S witching Ove r the CP U Op eratin g Clock Set ti ng t he CPU ope rating clock f requency When ope r at ing th e CPU with th e h igh -s pe ed (OS C3 ) cl oc k, th e o per at ing fr eq ue nc y ca n b e sw it ch ed over in four st ep s.
II CO RE BLOC K: CLG (Cloc k Generator) S1C33 L 03 FU NCTI ON P ART EPSON B-II-6-5 A-1 B-II CLG Pow er-Con t ro l Re g ist er P rot ec tion Fl ag The po we r-c ontr ol r egis ter at a ddre ss 0x 4018 .
II CO RE BLOC K: CLG (Cloc k Generator) B-II-6-6 EPSON S1 C33 L03 FUNCTION P ART I/O Memo ry of Clock Generato r Tabl e 6.4 lis ts t h e cont rol bi ts o f cl oc k g ene ra tor . Table 6.4 Con t rol Bit s of C loc k Gene r ato r Name Address Register name Bit Function Setting Init.
II CO RE BLOC K: CLG (Cloc k Generator) S1C33 L 03 FU NCTI ON P ART EPSON B-II-6-7 A-1 B-II CLG CLKCHG : CP U oper ati ng clo ck switc h (D2) / Power co ntr ol r eg iste r (0x401 80 ) Sel ect s the CPU o per at ing cl oc k.
II CO RE BLOC K: CLG (Cloc k Generator) B-II-6-8 EPSON S1 C33 L03 FUNCTION P ART Table 6.6 O pera tin g St at us in S ta ndb y Mo de St an dby mode O perating st atus Reactivating factor HALT mo de Ba sic mo de • The C PU c lock is s topp ed. ( CP U s top s tatu s) •B CU clo ck is s upp lie d.
II CO RE BLOC K: CLG (Cloc k Generator) S1C33 L 03 FU NCTI ON P ART EPSON B-II-6-9 A-1 B-II CLG Pr og ramm ing No tes (1) Im med ia tel y after th e h igh -s peed (O SC 3) osci lla tio n ci rcu it is turn ed o n, a ce rta in p eri od o f ti me is re qu ire d for o sci lla tio n to st ab ili ze (f or a 3.
II CO RE BLOC K: CLG (Cloc k Generator) B-II- 6-10 EPSON S1 C33 L03 FUNCTION P ART (8) If th e IC en te rs th e d ebug mod e th ro ugh th e co nnec t ed S 5U 1C3 30 00 H (I n-Ci r cu it Deb ug ge r fo.
II CO RE BLOC K: DBG (De bug Unit) S1C33 L 03 FU NCTI ON P ART EPSON B-II-7-1 A-1 B-II DBG II-7 DBG (Debug Un it) Debug Ci rcu it The C3 3 Co re Bloc k has a bui lt- in deb ug cir cui t. Thi s fun c tional b loc k is p rov id ed to si mply re ali ze an ad va nc ed soft wa re d eve lo pm en t en vi ro nm en t.
II CO RE BLOC K: DBG (De bug Unit) B-II-7-2 EPSON S1C 33 L 03 FUNCTI ON P ART TH IS PAGE I S BLANK..
S1C33L03 F UNCTION PART III PERI PHERAL BLOCK.
.
III PER IPHERA L BLOC K: INTROD UCTION S1C33 L 03 FU NCTI ON P ART EPSON B-III-1-1 A-1 B-III Intro III-1 INTR ODU CTION The C3 3 pe r iphe ral blo ck con sist s of a pre scal e r, six 8 - bi t p rog r.
III PER IPHERA L BLOC K: INTROD UCTION B-III-1-2 EPSON S1C 33 L 03 FUNCTI ON P ART TH IS PAGE I S BLANK..
III PER IPHERA L BL OCK: P R ESCALER S1C33 L 03 FU NCTI ON P ART EPSON B-III-2-1 A-1 B-III PSC III-2 PRESCALER Co nf ig uratio n of P rescale r The pr es caler d ivi de s th e so ur ce cl oc k (O SC3 /P LL o utp ut cl oc k o r OSC 1 cl oc k) to g ene ra te th e cl oc ks fo r th e inte rna l p eri ph era l ci rcui t s.
III PER IPHERA L BL OCK: P R ESCALER B-III-2-2 EPSON S1C 33 L 03 FUNCTI ON P ART Se lecting Divis ion Rati o and Ou tpu t Con trol fo r Pre scale r The pr es caler has re gi ste rs fo r se le cti ng t.
III PER IPHERA L BL OCK: P R ESCALER S1C33 L 03 FU NCTI ON P ART EPSON B-III-2-3 A-1 B-III PSC I/O Memo ry of Prescale r Tabl e 2.3 sho ws t h e contro l b its o f th e pre sc ale r. Table 2.3 Con t rol Bit s of P res ca ler Name Address Register name Bit Function Setting Init.
III PER IPHERA L BL OCK: P R ESCALER B-III-2-4 EPSON S1C 33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks – – P16TON3 P16TS32 P16TS31 P16TS30 D7–4 D3 D2 D1 D0 reserved 16-bit timer 3 clock control 16-bit timer 3 clock division ratio selection – 0 0 0 0 – R/W R/W 0 when being read.
III PER IPHERA L BL OCK: P R ESCALER S1C33 L 03 FU NCTI ON P ART EPSON B-III-2-5 A-1 B-III PSC Name Address Register name Bit Function Setting Init. R/W Remarks 1 On 0 Off P8TON3 P8TS32 P8TS31 P8TS30 .
III PER IPHERA L BL OCK: P R ESCALER B-III-2-6 EPSON S1C 33 L 03 FUNCTI ON P ART CLGP7 –CLGP0 : Powe r-contr ol re gi st er pr otec tio n fl ag ([ D[ 7:0] ) / Pow e r con tro l p rotec tio n regi ster (0 x40 19 E) Thes e bit s remo ve t he pr ote cti on a gain st wr iti n g to a dd re sse s 0x40 18 0 a nd 0x40 19 0.
III PER IPHERA L BL OCK: P R ESCALER S1C33 L 03 FU NCTI ON P ART EPSON B-III-2-7 A-1 B-III PSC P16T ON0 :1 6 - b i t t i m e r 0 clock contr ol ( D3) / 16- bit t im er 0 clo ck cont rol r eg is ter (0.
III PER IPHERA L BL OCK: P R ESCALER B-III-2-8 EPSON S1C 33 L 03 FUNCTI ON P ART Pr og ramm ing No tes (1) F or th e p res caler cl oc k, th e cl oc k so ur ce sa me as th e C PU o per at ing cl oc k mus t b e se le cte d.
III PER IPHERA L BL OCK: 8 -BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-3-1 A-1 B-III 8TM III-3 8- BIT PR OGRAMMABLE TIMERS Config uratio n of 8- Bit Pro grammab le Ti mer The Pe rip her al Bl ock co nt ain s si x ch an ne ls o f 8 -bi t p rog ra mma ble ti me rs (t im ers 0 to 5 ).
III PER IPHERA L BL OCK: 8 -BIT PROGRAM MABLE TIMERS B-III-3-2 EPSON S1C 33 L 03 FUNCTI ON P ART U ses of 8- Bi t Pro gram mab le Ti mers The do wn -cou nte r of t he 8- bit pro gram mab le t imer cyc lic a lly o utp ut s an und erf low si gn al acco rd ing to the p res et dat a that is set in th e so ft ware.
III PER IPHERA L BL OCK: 8 -BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-3-3 A-1 B-III 8TM 8-bi t pr og ram m ab le t imer 2 • Clo ck sup ply to the C h.
III PER IPHERA L BL OCK: 8 -BIT PROGRAM MABLE TIMERS B-III-3-4 EPSON S1C 33 L 03 FUNCTI ON P ART Control an d Opera tion of 8-Bi t Progr ammab le Timer With the 8-b i t prog ramma ble ti mer, th e fo llo wing se tti ngs m ust fi rst b e m ade b efo re it st art s co un ti ng: 1.
III PER IPHERA L BL OCK: 8 -BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-3-5 A-1 B-III 8TM Se tti ng preset data ( initial counter value) Eac h tim er ha s an 8- bit down -c ou nter and a reloa d dat a reg ist er. The r eloa d dat a reg ist er RL Dx is us ed t o set the in iti al v alu e of th e d own- co un ter of ea ch ti mer.
III PER IPHERA L BL OCK: 8 -BIT PROGRAM MABLE TIMERS B-III-3-6 EPSON S1C 33 L 03 FUNCTI ON P ART When bot h the ti me r RUN /ST OP co nt ro l b it (PTR UNx ) and th e ti mer p res et b it (P SETx ) ar.
III PER IPHERA L BL OCK: 8 -BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-3-7 A-1 B-III 8TM Control of Cloc k Outpu t When out put tin g an u nd erflow si gnal o f th e 8 -bit p rog.
III PER IPHERA L BL OCK: 8 -BIT PROGRAM MABLE TIMERS B-III-3-8 EPSON S1C 33 L 03 FUNCTI ON P ART 8-Bi t P rogr a mma ble T ime r Int e rrup ts a nd DM A The 8- b it pro gram mab le time r has a fu nc tion to g enera te an in te rrupt b ase d o n th e u nderf low st ate o f th e ti mer 0 to 3.
III PER IPHERA L BL OCK: 8 -BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-3-9 A-1 B-III 8TM Hig h -s peed DM A The un de r flo w in terrupt fa cto r o f th e ti mer 0 to 3 ca n al so in vo ke h igh -s peed D MA (H SDM A).
III PER IPHERA L BL OCK: 8 -BIT PROGRAM MABLE TIMERS B-III-3-10 EPSON S1C 33 L 03 FUNCTI ON P ART I/O Me mo ry of 8- Bit P rogram mable Ti mers Tabl e 3.6 sho ws t h e contro l b its o f the 8 -bi t p rogra mma ble ti mers . For det a ils on th e I/ O mem ory o f th e p res ca ler used to se t a cl oc k, re fer to "P res ca ler ".
III PER IPHERA L BL OCK: 8 -BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-3-11 A-1 B-III 8TM Name Address Register name Bit Function Setting Init.
III PER IPHERA L BL OCK: 8 -BIT PROGRAM MABLE TIMERS B-III-3-12 EPSON S1C 33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init.
III PER IPHERA L BL OCK: 8 -BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-3-13 A-1 B-III 8TM CFP13 –CFP1 0 : P1[ 3:0 ] p in func tio n select io n (D[3:0 ]) / P 1 fu nctio n sele ct regist er (0 x4 0 2D4 ) Sel ect s the pin th at is u sed to o utp ut a ti me r u nderf low si gn al to ex tern al d evi ce s.
III PER IPHERA L BL OCK: 8 -BIT PROGRAM MABLE TIMERS B-III-3-14 EPSON S1C 33 L 03 FUNCTI ON P ART PTD07 –PTD0 0 : Tim er 0 count er d ata (D[7 :0 ]) / 8 -bi t timer 0 cou nt er data (0x40 16 2) PTD1.
III PER IPHERA L BL OCK: 8 -BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-3-15 A-1 B-III 8TM PTOUT 0 : Tim er 0 c lock out put cont rol reg ister (D2) / 8-b it tim er 0 cont rol r e.
III PER IPHERA L BL OCK: 8 -BIT PROGRAM MABLE TIMERS B-III-3-16 EPSON S1C 33 L 03 FUNCTI ON P ART F8TU x i s the inte rru pt fa cto r fl ag co rr esp ondi ng to each ti me r. It is se t to "1 " w he n the co un ter u nd erf lows . At t h is ti me, if th e fo llow ing cond it ion s are m et , an inte rru pt to the C PU is g ene rated : 1.
III PER IPHERA L BL OCK: 8 -BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-3-17 A-1 B-III 8TM DE8TU 0 : Ti me r 0 ID M A en ab l e ( D2) / 16- bi t tim er 5, 8- b it tim er , se r ial I/F Ch .
III PER IPHERA L BL OCK: 8 -BIT PROGRAM MABLE TIMERS B-III-3-18 EPSON S1C 33 L 03 FUNCTI ON P ART TH IS PAGE I S BLANK..
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-4-1 A-1 B-III 16TM III-4 16 -BIT PR OG RAMMABLE TIMERS Configur ation of 16-Bit P rogram mable Ti mer The Pe rip her al Bl ock con tai ns six s yste ms of 16 -bi t pro gram m ab le ti me rs (tim ers 0 to 5).
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS B-III-4-2 EPSON S1C 33 L 03 FUNCTI ON P ART I/O P ins of 16 -Bit Pro grammab le Ti mers Tabl e 4.
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-4-3 A-1 B-III 16TM Uses of 16 -Bit Pro grammab le Ti mers The up - co un te rs of the 16- bit pro gram mab le ti me r cy cl ica lly o utp ut a co mpa ris on -mat ch si gn al in ac cord an ce w ith the co m paris on d ata th at ar e se t in th e soft wa re.
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS B-III-4-4 EPSON S1C 33 L 03 FUNCTI ON P ART Control an d Opera tion of 16 -Bit P rogram mable Ti mer The f o llow ing se tti ng s mus t fi rst b e mad e b efore th e 1 6-bit p rog ramma ble ti mer st art s co un ti ng: 1.
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-4-5 A-1 B-III 16TM •E x t er na l c l oc k When using the time r as an ev ent co un te r b y supp ly in g cl oc k p ulses fr om an exte rn al so ur ce , mak e su re th e even t cy cl e is at le as t th e CPU o per at ing cl ock p eri od .
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS B-III-4-6 EPSON S1C 33 L 03 FUNCTI ON P ART Re set ti ng t he counter E ach ti me r in cl udes th e P RESET x b it to rese t th e co unte r.
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-4-7 A-1 B-III 16TM Controllin g Clock Output The t im er s can gen erat e a TM x si gn al u sin g th e co mpa ri son m at ch si gn als fr om th e co un te r.
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS B-III-4-8 EPSON S1C 33 L 03 FUNCTI ON P ART When OUTI NV x = " 0" (a ct iv e h ig h) : The t im er ou tputs a lo w le vel u nti l th e coun te r b ecom es eq ual to th e co mpa ris on d ata A se t in th e CRx A regi ste r.
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-4-9 A-1 B-III 16TM 16-Bit P rogr ammab le Timer Inter rupts an d DMA The 16 - bi t pro gram m ab le ti mer h as a fu nctio n fo r g enera tin g an in te rru pt usin g th e com pa ris on m at ch A an d B st ates.
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS B-III-4-10 EPSON S1C 33 L 03 FUNCTI ON P ART For IDM A to b e in voke d, th e IDM A re qu est an d ID MA enab le b its show n in T ab le 4 .5 mus t be se t to "1 " in adva nc e. T ran sf er co ndit ions, et c.
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-4-11 A-1 B-III 16TM Trap vec tors The t rap v ector ad dr es ses for ea ch d efa ul t in te rrupt fa cto r.
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS B-III-4-12 EPSON S1C 33 L 03 FUNCTI ON P ART I/O Me mo ry of 16 -Bit Progr ammab le Timer s Tabl e 4.7 sho ws t h e contro l b its o f the 1 6-b it p rogra mma ble ti mers . For det a ils on th e I/ O mem ory o f th e p res ca ler used to se t a cl oc k, re fer to "P res ca ler ".
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-4-13 A-1 B-III 16TM Name Address Register name Bit Function Setting Init. R/W Remarks R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS B-III-4-14 EPSON S1C 33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init.
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-4-15 A-1 B-III 16TM Name Address Register name Bit Function Setting Init.
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS B-III-4-16 EPSON S1C 33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init.
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-4-17 A-1 B-III 16TM Name Address Register name Bit Function Setting Init.
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS B-III-4-18 EPSON S1C 33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init.
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-4-19 A-1 B-III 16TM CFP16 –CFP1 0 : P1[ 6:0 ] p in func tio n select io n (D[6:0 ]) / P 1 fu nctio n sele ct regist er (0 x4 0 2D4 ) Sel ect s the pin to b e used fo r in put o f an ex te rnal co un t cl ock to th e ti mer.
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS B-III-4-20 EPSON S1C 33 L 03 FUNCTI ON P ART SELFM 0 : T imer 0 fi ne mode s elect io n ( D 6) / 16-b it time r 0 cont r ol r egis ter (0x 48186 ).
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-4-21 A-1 B-III 16TM CKSL0 : T imer 0 inpu t cloc k s ele ctio n (D3 ) / 16 -b it ti mer 0 con tro l regi s.
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS B-III-4-22 EPSON S1C 33 L 03 FUNCTI ON P ART PRUN0 : T imer 0 RU N/STOP cont rol ( D0) / 16- bit tim er 0 cont rol r egis ter (0x 48186 ) PRUN1 : .
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-4-23 A-1 B-III 16TM TC 015–T C00 : Timer 0 count er data (D[F:0 ]) / 1 6-b it ti mer 0 co unte r da ta r.
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS B-III-4-24 EPSON S1C 33 L 03 FUNCTI ON P ART F16T Ux and F1 6T Cx are th e in te rrupt fa cto r fl ag s co rr espon di ng to the co m par ison B an d com pa ris on A in te rru pts , resp ec tiv ely .
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS S1C33 L 03 FU NCTI ON P ART EPSON B-III-4-25 A-1 B-III 16TM DE16T U0, DE 16T C0 :T i m e r 0 ID MA e n ab le ( D6, D7 ) / Port inp ut 0–3, HSDM .
III PER IPHERA L BL OCK: 1 6-BIT PROGRAM MABLE TIMERS B-III-4-26 EPSON S1C 33 L 03 FUNCTI ON P ART TH IS PAGE I S BLANK..
III PER IP HERAL BLOC K: WATCHDO G TIMER S1C33 L 03 FU NCTI ON P ART EPSON B-III-5-1 A-1 B-III WDT III-5 WA T C H D OG TIM ER Configuratio n of W atc hdo g Ti mer The Pe rip her al Bl ock in corp ora te s a watc hd og ti me r fu nctio n to dete ct th e CPU 's cr as h.
III PER IP HERAL BLOC K: WATCHDO G TIMER B-III-5-2 EPSON S1C 33 L 03 FUNCTI ON P ART Re set ti ng the watchdog tim er When using the watc hd og ti me r, p repar e a ro ut ine to re se t th e 1 6-bit p rog ramma ble ti mer 0 b efo re an N MI is gen erat ed i n a loca tio n whe re it w ill be p eri odica lly p roc essed .
III PER IP HERAL BLOC K: WATCHDO G TIMER S1C33 L 03 FU NCTI ON P ART EPSON B-III-5-3 A-1 B-III WDT I/O Memo ry of Watc hdog Ti mer Tabl e 5.1 sho ws t he cont ro l b its of th e w atchd og ti mer. Table 5.1 Con tr ol Bit s of Wat ch dog Tim er Name Address Register name Bit Function Setting Init.
III PER IP HERAL BLOC K: WATCHDO G TIMER B-III-5-4 EPSON S1C 33 L 03 FUNCTI ON P ART TH IS PAGE I S BLANK..
III PER IPHERA L BLOCK: LOW-SPEED (O SC1) OSC ILLATION C IRCUIT S1C33 L 03 FU NCTI ON P ART EPSON B-III-6-1 A-1 B-III OSC1 III-6 LO W -SPEED ( OSC 1) O SCI LLA TION CI R CU IT Configur ation of Low-Spe ed (OS C1) Osc illati on Circuit The Pe riphe ral Bl ock has a bu ilt -in low-sp ee d (O SC1 ) o sci llatio n ci rcu it .
III PER IPHERA L BLOCK: LOW-SPEED (O SC1) OSC ILLATION C IRCUIT B-III-6-2 EPSON S1C 33 L 03 FUNCTI ON P ART Oscillat or Ty pes In th e lo w -spee d (O S C1) o sci lla tio n ci rcu it , ei th er a cr ystal o sci lla tio n o r an exte rn al cl oc k in p ut ca n b e se le cte d as the ty pe o f osci lla tio n ci rcui t .
III PER IPHERA L BLOCK: LOW-SPEED (O SC1) OSC ILLATION C IRCUIT S1C33 L 03 FU NCTI ON P ART EPSON B-III-6-3 A-1 B-III OSC1 Controlling Osc illat ion The l ow- s peed (OSC 1) os c il lat i on cir cui t can be t urne d on or off usi ng SO SC1 ( D0) / Pow e r con trol reg ist er (0x4 01 80 ).
III PER IPHERA L BLOCK: LOW-SPEED (O SC1) OSC ILLATION C IRCUIT B-III-6-4 EPSON S1C 33 L 03 FUNCTI ON P ART Pow er-Con t ro l Re g ist er P rot ec tion Fl ag The po we r-c ontr o l reg ist er (SO S C1.
III PER IPHERA L BLOCK: LOW-SPEED (O SC1) OSC ILLATION C IRCUIT S1C33 L 03 FU NCTI ON P ART EPSON B-III-6-5 A-1 B-III OSC1 I/O Memo ry of Low-Spe ed (OSC1) Oscillat ion Circuit Tabl e 6.3 lis ts t he cont ro l b its of th e lo w -spee d (O SC1 ) o sci lla tion ci rcu it .
III PER IPHERA L BLOCK: LOW-SPEED (O SC1) OSC ILLATION C IRCUIT B-III-6-6 EPSON S1C 33 L 03 FUNCTI ON P ART SOSC1 : Low -spe ed (O SC 1) o sc illatio n con trol (D 0 ) / P owe r c ontro l regi st er (0 x4 018 0) Tur ns t he lo w-sp ee d (O SC 1) os c ill ati on on or of f.
III PER IPHERA L BLOCK: LOW-SPEED (O SC1) OSC ILLATION C IRCUIT S1C33 L 03 FU NCTI ON P ART EPSON B-III-6-7 A-1 B-III OSC1 The f o llow ing sh ows th e o per at ing st atu s in H ALT m ode (b as ic m ode an d H ALT 2 mod e) an d S LEEP mod e. Ta ble 6.
III PER IPHERA L BLOCK: LOW-SPEED (O SC1) OSC ILLATION C IRCUIT B-III-6-8 EPSON S1C 33 L 03 FUNCTI ON P ART CFP14 : P 14 fu nctio n sele ct ion (D4 ) / P 1 fu nctio n sele ct re gi st er (0 x40 2D4) Sel ect s the pin fu nc tio n o f t h e P1 4 I/O por t.
III PER IPHERA L BLOC K: CLOC K TIMER S1C33 L 03 FU NCTI ON P ART EPSON B-III-7-1 A-1 B-III CTM III-7 CLO CK TIMER Configurat ion of Cloc k Ti mer The c loc k time r cons i s ts o f an 8- bi t b ina r.
III PER IPHERA L BLOC K: CLOC K TIMER B-III-7-2 EPSON S1C 33 L 03 FUNCTI ON P ART Control an d Operatio n of th e C loc k Ti mer Ini t ial set ting At i n itial re se t, the cl oc k ti mer' s co unte r d ata , se tup co nt en ts of al arm s , an d co nt ro l b its incl ud ing RUN /ST OP, ar e no t in iti al iz ed .
III PER IPHERA L BLOC K: CLOC K TIMER S1C33 L 03 FU NCTI ON P ART EPSON B-III-7-3 A-1 B-III CTM RU N/ STOP the clock tim er The c loc k time r st art s co un ti ng whe n "1 " is w rit ten to TCR UN (D0 ) / C lock ti mer R un/S top re giste r (0x4 01 51 ) an d st op s co un ti ng whe n " 0" is w rit ten .
III PER IPHERA L BLOC K: CLOC K TIMER B-III-7-4 EPSON S1C 33 L 03 FUNCTI ON P ART Set ti ng a larm function The c loc k timer h as an al arm fu nc tio n, en ab ling an in ter ru pt to b e g enera ted at a spec ifi ed ti me an d d ay.
III PER IPHERA L BLOC K: CLOC K TIMER S1C33 L 03 FU NCTI ON P ART EPSON B-III-7-5 A-1 B-III CTM An i n te rru pt ca n be g ene ra ted o n a sp ec ifi ed al arm d ay at a sp ec ifi ed ti me as d esc ribed in th e p rec eding sect ion . Inte rru pt s g ene ra ted by a si gn al an d th os e gene ra ted b y an al arm ca n b oth be u sed .
III PER IPHERA L BLOC K: CLOC K TIMER B-III-7-6 EPSON S1C 33 L 03 FUNCTI ON P ART E xample s of Use of Cl oc k Ti mer The f o llow ing sh ows ex am pl es o f u se o f th e cl oc k ti mer an d h ow to co nt ro l th e ti mer in ea ch ca se .
III PER IPHERA L BLOC K: CLOC K TIMER S1C33 L 03 FU NCTI ON P ART EPSON B-III-7-7 A-1 B-III CTM I/O Memo ry of Clock T i mer Tabl e 7.5 sho ws t h e co ntro l b its o f th e cl ock ti me r. Table 7.5 Con t rol Bit s of C loc k Tim er Name Address Register name Bit Function Setting Init.
III PER IPHERA L BLOC K: CLOC K TIMER B-III-7-8 EPSON S1C 33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 59 minutes (Note) Can be set within 0–63.
III PER IPHERA L BLOC K: CLOC K TIMER S1C33 L 03 FU NCTI ON P ART EPSON B-III-7-9 A-1 B-III CTM TC RUN : C lo ck timer RUN/STO P co ntr ol ( D0) / Cl ock tim er Ru n/Stop reg ister (0x 40151 ) Cont rol s the R UN/S T OP o f th e cl oc k ti mer.
III PER IPHERA L BLOC K: CLOC K TIMER B-III-7-10 EPSON S1C 33 L 03 FUNCTI ON P ART TC ASE2–T CASE0 : A larm fact or sele ct regi st er (D [4 :2]) / C lock ti mer in terru pt c ontro l regi st er (0 x4 015 2) Sel ect s the fa ctor fo r w hi ch an al arm is to b e g ene ra ted.
III PER IPHERA L BLOC K: CLOC K TIMER S1C33 L 03 FU NCTI ON P ART EPSON B-III-7-11 A-1 B-III CTM EC TM : Cloc k tim er in terrupt ena ble (D 1) / Port inp ut 4– 7, clock tim er , A/D i nter r upt en abl e r egis ter ( 0x402 77 ) Enab l es or di sab les gen erat ion of a n in terrupt to th e CPU .
III PER IPHERA L BLOC K: CLOC K TIMER B-III-7-12 EPSON S1C 33 L 03 FUNCTI ON P ART Pr og ramm ing No tes (1) T he lo w -spee d (O SC1 ) o sci llatio n ci rcu it , whi ch is th e cl oc k sour ce fo r th e cl oc k ti me r, re qu ire s a mux m um of t hree se cond s for it s o scil lat ion to st ab ili ze af ter it is st art ed u p.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-1 A-1 B-III SIF III-8 SERI AL INTERF A CE Configur ation of Ser ial Inter fac es Featu res of Seri al Inter faces The Pe rip her al Bl ock co nt ain s four ch an nels (C h .
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-2 EPSON S1C 33 L 03 FUNCTI ON P ART I/O Pins of Serial In terfac e Tabl e 8.1 lis ts t he I/O pins us ed b y th e se ria l inter fac e. Table 8.1 Ser i al-In ter fa ce Pin C on figu rati on Pin name I/O Func tion Functi on se l ect bit P0 0/ SI N0 I/O I/O port / Ser ial IF Ch.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-3 A-1 B-III SIF Set tin g T ra n sfer Mode The t rans fer mo de of t he s e ria l inte rfa ce ca n be se t u sin g SM Dx[1 :0] indi vid ua lly fo r ea ch ch anne l as sh own in Tabl e 8.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-4 EPSON S1C 33 L 03 FUNCTI ON P ART Clock-Sy nc hr oni zed In ter face Outlin e of Clock-S ynchronized Inter face In th e cl oc k- syn ch ro nized t.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-5 A-1 B-III SIF Set tin g Cl oc k - Sy nc h r oniz ed Inter face When pe rformi ng cl ock- syn ch ro ni zed tr ansf ers v ia th e se ria l in terfa ce, th e fo llo wi ng se tti ng s m ust b e m ad e befo re dat a tran sfer is ac tu all y b egun: 1.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-6 EPSON S1C 33 L 03 FUNCTI ON P ART RLD = f PS CI N × pd r - 1 (Eq . 1) 2 × bps RLD: Rel oad dat a regis ter setup v alu e of th e 8 -bi t p rogra.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-7 A-1 B-III SIF Control and Operation of Clo ck-Syn chron ized Tr ansfe r Tran smi t c ontrol (1) Ena blin g tran s mit o pera tion Use the tr an smit- en ab le bit T XEN x fo r tr ansm it co nt rol.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-8 EPSON S1C 33 L 03 FUNCTI ON P ART •C l o c k - s yn c hr on i zed ma s t er mod e The t imin g at wh ic h th e devi ce st art s tr an sm itt ing.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-9 A-1 B-III SIF 3. The da ta i n the shif t re gi ste r is shif ted 1 b it by th e n ext fa lli ng ed ge o f th e cl oc k, an d th e bit fo llo w ing th e LSB i s ou tput fr om S OUTx.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-10 EPSON S1C 33 L 03 FUNCTI ON P ART A stat us b it is al so p rov id ed th at in di cat es th e st atu s o f th e re ce ive d ata re gi ste r. Ch. 0 re ce iv e data b uff er full: R DBF 0 (D 0 ) / S eri al I/ F C h.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-11 A-1 B-III SIF 1. Aft er s e tting th e # SRD Yx si gn al to a lo w le vel (r ea dy to rece ive ), th e sl av e wait s fo r cl ock in pu t fr om th e maste r.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-12 EPSON S1C 33 L 03 FUNCTI ON P ART A synch ro nous In ter fac e Outlin e of Asyn chro nous In terface Asyn chron ous t ra nsf ers are per for med by addi ng a st art b it an d a st op b it to th e st art an d en d p oin ts o f ea ch seria l- conv er ted data .
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-13 A-1 B-III SIF Set tin g A synch ronous In terfac e When pe rformi ng asyn ch ro no us tr ansfe r v ia th e se ria l in te rfa ce, the fo llo wing mus t b e do ne be f ore da ta t rans fer can b e start ed : 1.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-14 EPSON S1C 33 L 03 FUNCTI ON P ART Any des ir ed c lock fre q ue nc y ca n b e o bta in ed by se t ti ng th e pres ca ler d ivi sio n ra tio and th e re load d ata o f the 8-b it pr ogr am m abl e ti mer as n ece ss ary .
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-15 A-1 B-III SIF •S a m p l i ng clock In t he as yn ch ro no us m ode, T CL K (t he cl ock o utp ut b y th e 8 .
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-16 EPSON S1C 33 L 03 FUNCTI ON P ART Set ti ng the data format In th e as yn chro no us m od e, the d ata le ngth is 7 o r 8 b its as d eterm in ed by th e tr an sfer mod e se t. T he st art bit is fi xe d at 1 .
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-17 A-1 B-III SIF The t rans fer sta tus ca n b e ch ec ked u sin g the tr an sm it- comp le tio n fl ag (T E NDx ). Ch. 0 tr an smit- co mple tio n fl ag: T END 0 (D5 ) / S eri al I/ F Ch.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-18 EPSON S1C 33 L 03 FUNCTI ON P ART Recei ve cont ro l (1) Ena blin g r ecei ve oper ati ons Use the re ceive -e na ble b it R XEN x fo r re ce ive co nt ro l. Ch. 0 re ce ive -e nable : R XEN 0 (D6 ) / S eri al I/ F Ch.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-19 A-1 B-III SIF Note :T h e r e c e i v e o pe r a tio n is t e rm in at ed w he n th e fi r st s top b i t is s amp led e ven if th e stop bit is conf igu r ed wi th tw o bits .
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-20 EPSON S1C 33 L 03 FUNCTI ON P ART •O v e r r u n e rro r If duri ng su cc es sive re ce ive o per at ion s, a re ce ive o per at ion for th e n.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-21 A-1 B-III SIF IrDA Inter face Outlin e of IrDA In terface E ach ch an ne l o f th e seria l in te rfa ce co nt ain s a P PM m od ul ator ci rcu it , al lo wi ng an in fra re d-r ay co mm unica tio n ci rcuit to b e co nf ig ure d b ase d o n Ir DA 1 .
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-22 EPSON S1C 33 L 03 FUNCTI ON P ART Sel ecting the IrDA interf ace fu ncti on To us e th e IrDA in te rfa ce func tio n, se lect it u sin g the co nt ro l b its show n belo w and th en se t the 8 -bi t (o r 7 - b it) as yn ch ro no us mod e as th e tr ansfe r m od e.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-23 A-1 B-III SIF Control and Operatio n o f IrDA Inter face Th e t rans mi t /re ce iv e pro ce d u res hav e b ee.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-24 EPSON S1C 33 L 03 FUNCTI ON P ART Seri al I nt erf ac e In terru pts and D MA The s eri al i nte rface ca n g ene ra te the fo llo w ing th re e .
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-25 A-1 B-III SIF The i n terru pt p rio rit y regi ste r se ts the in te rru pt prio ri ty le vel o f ea ch in te rrupt so ur ce in a ra ng e b etwee n 0 an d 7.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-26 EPSON S1C 33 L 03 FUNCTI ON P ART If an in te rru pt fa ctor o ccu rs whe n th e IDM A requ es t an d en able b its ar e se t to "1 ", ID MA is invo ke d. N o inte rru pt re ques t is g enera ted at th at poin t.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-27 A-1 B-III SIF •C h . 2 a n d C h . 3 For Ch. 2 a nd Ch .3, ei th er p ort inpu t in terru pts o r 16-b it ti mer in te rru pts ar e se le cte d, and H SDMA is in voke d by m ean s of t hose int err up t fac tor (Se e Tabl e 8.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-28 EPSON S1C 33 L 03 FUNCTI ON P ART I/O Memo ry of Serial Inter fac e Tabl e 8.1 4 sho ws t h e contro l b its o f th e seria l in te rfa ce.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-29 A-1 B-III SIF Name Address Register name Bit Function Setting Init. R/W Remarks – TEND1 FER1 PER1 OER1 TDBE1 RDBF1 D7–6 D5 D4 D3 D2 D1 D0 – Ch.1 transmit-completion flag Ch.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-30 EPSON S1C 33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks 0x0 to 0xFF(0x7F) TXD37 TXD36 TXD35 TXD34 TXD33 TXD32 TXD31 TXD30 D7 D6 D5 D4 D3 D2 D1 D0 Serial I/F Ch.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-31 A-1 B-III SIF Name Address Register name Bit Function Setting Init. R/W Remarks – FSTX1 FSRX1 FSERR1 FSTX0 FSRX0 FSERR0 D7–6 D5 D4 D3 D2 D1 D0 reserved SIF Ch.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-32 EPSON S1C 33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks CFP07 CFP06 CFP05 CFP04 CFP03 CFP02 CFP01 CFP.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-33 A-1 B-III SIF SSOUT3 : S erial I/ F Ch. 3 SO UT s elect ion (D 1) / P ort S IO fu nctio n exte n sion regi st er (0 x4 02D7 ) Sw itch es th e fu nc tio n o f p in P 16 /E XCL 5/# D MAE N D1/S OU T3.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-34 EPSON S1C 33 L 03 FUNCTI ON P ART SSCLK 2 : S eri al I/ F Ch. 2 SCL K s elect io n (D2) / P or t SIO func tion e xten sion re gist er (0x4 02D B) Sw it che s the f unct ion of pi n P25/TM 3/ #S CLK 2.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-35 A-1 B-III SIF RXD07 –RX D00 : C h. 0 receiv e d ata (D[7 :0 ]) / Ser ial I/ F Ch. 0 receiv e d ata re gist er (0x4 0 1E1) RXD17 –RX D10 : C h. 1 receiv e d ata (D[7 :0 ]) / Ser ial I/ F Ch.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-36 EPSON S1C 33 L 03 FUNCTI ON P ART PER0 : Ch. 0 pari ty -er ror fl ag (D3 ) / Ser ial I/ F Ch. 0 stat us re gi st er (0 x4 01E 2) PER1 : Ch. 1 pari ty -er ror fl ag (D3 ) / Ser ial I/ F Ch. 1 stat us re gi st er (0 x4 01E 7) PER2 : Ch.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-37 A-1 B-III SIF RDBF0 : C h. 0 receiv e data b uffer fu ll (D0 ) / Ser ial I/ F Ch.0 s tat us re gist er (0 x40 1E2) RDBF1 : C h. 1 receiv e data b uffer fu ll (D0 ) / Ser ial I/ F Ch.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-38 EPSON S1C 33 L 03 FUNCTI ON P ART EPR0 : Ch. 0 pari ty ena bl e (D5 ) / S er ial I/F C h.0 c ontro l re gist er (0x4 0 1E3) EPR1 : Ch. 1 pari ty ena bl e (D5 ) / S er ial I/F C h.1 c ontro l re gist er (0x4 0 1E8) EPR2 : Ch.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-39 A-1 B-III SIF SSCK0 : C h. 0 input c lock s elect io n (D2 ) / S er ial I/ F C h.0 c ontro l regi st er (0 x40 1E3) SSCK1 : C h. 1 input c lock s elect io n (D2 ) / S er ial I/ F C h.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-40 EPSON S1C 33 L 03 FUNCTI ON P ART IRT L0 : C h.0 Ir DA o utpu t logi c in vers ion (D 3) / S eri al I/ F Ch. 0 Ir DA re gist er (0x4 01E 4) IRT L1 : C h.1 Ir DA o utpu t logi c in vers ion (D 3) / S eri al I/ F Ch.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-41 A-1 B-III SIF ESERR0 , ES RX0, ESTX0 : Ch.0 inte rrupt e nable (D 0,D1 ,D2) / Se rial I / F i nterr upt enab le regis t e r (0x402 76) ESERR1 , ES RX1, ESTX1 : Ch.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-42 EPSON S1C 33 L 03 FUNCTI ON P ART RSRX0 , RSTX0 :C h . 0 ID MA re que st (D 6, D7) / 16- bit t im er 5, 8- b i t ti mer, s erial I/ F Ch. 0 IDM A re qu est re gist er (0x4 0 292) RSRX1 , RSTX1 :C h .
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-43 A-1 B-III SIF SIO2 RS0 :S I O Ch. 2 rece iv e-bu ffer fu ll/ FP1 inte rru pt fa ct or s witch in g (D1 ) / Inte rru pt fa ct or F P func tion s witch ing re gist er (0x4 0 2C5 ) Sw itch es th e inte rru pt fa ctor.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-44 EPSON S1C 33 L 03 FUNCTI ON P ART SIO3 TS0 : SIO Ch .3 tr ansmi t-b uf fer em pt y/FP 6 int e rrupt fa ct or s wit ch in g (D6 ) / Inte rru pt fa ct or F P func tion s witch ing re gist er (0x4 0 2C5 ) Sw itch es th e inte rru pt fa ctor.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE S1C33 L 03 FU NCTI ON P ART EPSON B-III-8-45 A-1 B-III SIF SIO3 TS1 : S IO Ch.3 tr ansmit -b uff er e mpty /TM 16 C h.4 c ompare A in te rrupt fa ctor s witch ing (D3 ) / Inte rru pt fa ct or T M16 func tio n s wit chin g re gi ster (0 x40 2CB ) Sw itch es th e inte rru pt fa ctor.
III PER IPHERA L BLOC K: SERIAL I NT ERFACE B-III-8-46 EPSON S1C 33 L 03 FUNCTI ON P ART Pr ogr a mm i ng Not es (1) B efo re se tti ng v ari ou s se ria l-i nt erf ace p ara m eters, mak e su re th e tr an sm it and re ce ive o per at ions ar e d isa ble d (TX E Nx = RXENx = "0").
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS S1C33 L 03 FU NCTI ON P ART EPSON B-III-9-1 A-1 B-III I/O III-9 INPUT/OU TPUT POR TS The Pe rip her al Bl ock has a tot al of 42 inpu t/o utpu t p orts.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS B-III-9-2 EPSON S1C 33 L 03 FUNCTI ON P ART Inpu t-P or t Pins The i npu t pins co nc ur re ntl y se rv e as the in pu t p ins fo r peri ph era l ci rcu it s, as sh ow n in T ab le 9 .
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS S1C33 L 03 FU NCTI ON P ART EPSON B-III-9-3 A-1 B-III I/O I/O Memo ry of In put Por ts Tabl e 9.2 sho ws t h e contro l b its o f th e inpu t p ort s. Table 9.2 Con tr ol Bit s of In put P ort s Name Address Register name Bit Function Setting Init.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS B-III-9-4 EPSON S1C 33 L 03 FUNCTI ON P ART I/O P orts (P Por ts) St ru cture of I/O P ort The Pe rip her al Bl oc k con tai ns 29 bi t s of I /O por ts (P0 0 to P0 7, P1 0 to P1 6, P2 0 to P2 7, P3 0 to P3 5) tha t can be dir ect ed f or i nput or ou tpu t thr ough the use of a pro gram .
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS S1C33 L 03 FU NCTI ON P ART EPSON B-III-9-5 A-1 B-III I/O Pin name I/O Pull-u p Fu nction Fu nction se lect bit P2 0/ #DRD I/O – I/O port / #DRD output C.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS B-III-9-6 EPSON S1C 33 L 03 FUNCTI ON P ART I/O Memo ry of I/O Por ts Tabl e 9.4 sho ws t h e contro l b its o f th e I/ O p ort s. Table 9.4 Con tr ol Bit s of I/O Port s Name Address Register name Bit Function Setting Init.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS S1C33 L 03 FU NCTI ON P ART EPSON B-III-9-7 A-1 B-III I/O Name Address Register name Bit Function Setting Init. R/W Remarks – SSRDY3 SSCLK3 SSOUT3 SSIN3 D7–4 D3 D2 D1 D0 reserved Serial I/F Ch.3 SRDY selection Serial I/F Ch.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS B-III-9-8 EPSON S1C 33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks CFEX7 CFEX6 CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 CFE.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS S1C33 L 03 FU NCTI ON P ART EPSON B-III-9-9 A-1 B-III I/O IOC 0 7–IO C00 : P0[7:0 ] p ort I/O con tro l (D[7:0 ]) / P 0 p ort I/O con tro l regist er (0 .
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS B-III-9-10 EPSON S1C 33 L 03 FUNCTI ON P ART SSRDY3 : S er ial I/ F Ch. 3 SRDY s elect ion (D 3) / P ort S IO fu nc tion e xten sion regi st er (0 x4 02D7 ) Sw itch es th e fu nc tio n o f p in P 32 /#D MAA C K0/# SR D Y 3.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS S1C33 L 03 FU NCTI ON P ART EPSON B-III-9-11 A-1 B-III I/O CFEX0 : P 12, P 14 fu ncti on ext ensi on (D0) / Port fun ct ion ex tens i on reg iste r (0x 402.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS B-III-9-12 EPSON S1C 33 L 03 FUNCTI ON P ART Input In ter rupt The i npu t ports an d th e I/ O p ort s su ppor t ei gh t sy st em o f p ort inpu t in te rrupts an d two sy st em s o f k ey in put inte rru pts .
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS S1C33 L 03 FU NCTI ON P ART EPSON B-III-9-13 A-1 B-III I/O C onditions for port input-inte rrupt generation E ach p ort in put in te rru pt ca n b e g enera ted by th e ed ge or le ve l o f the in pu t si gnal.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS B-III-9-14 EPSON S1C 33 L 03 FUNCTI ON P ART Key Inpu t Interru pt The ke y in put inte rru pt ci rcu i t has tw o int e rru pt sy st em s (F PK 1 and F PK 0) and a p ort grou p ca n b e sele cte d for gen era ting each inte rru pt fa cto r.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS S1C33 L 03 FU NCTI ON P ART EPSON B-III-9-15 A-1 B-III I/O Sel ecti ng input pins For the FP K1 i n te rru pt sy st em , a four -b it inpu t pi n gr ou p ca n be se l e cte d fr om th e fo ur p red ef ine d g rou ps .
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS B-III-9-16 EPSON S1C 33 L 03 FUNCTI ON P ART Sin ce K50 i s mask ed from in te rrupt b y S MPK00 , n o inte rru pt occu rs at th at p oint (2 ) ab ove.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS S1C33 L 03 FU NCTI ON P ART EPSON B-III-9-17 A-1 B-III I/O Table 9.9 Con tr ol Bit s fo r IDMA Transfe r Sys tem IDM A requ est bit IDMA en able bit FPT7 R.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS B-III-9-18 EPSON S1C 33 L 03 FUNCTI ON P ART I/O Memory for In put Inter rupt s Tabl e 9.1 0 sho ws t h e contro l b its fo r the p ort in put an d k ey in pu t in terru pts . Table 9.10 C ontr ol Bit s fo r In put In terrup ts Name Address Register name Bit Function Setting Init.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS S1C33 L 03 FU NCTI ON P ART EPSON B-III-9-19 A-1 B-III I/O Name Address Register name Bit Function Setting Init.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS B-III-9-20 EPSON S1C 33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks – SPPK11 SPPK10 SPPK01 SPPK00 D7–4 D3 D2 D1 D0 reserved FPK1 i nterrupt input port selection FPK0 i nterrupt input port selection – 0 0 0 0 – R/W R/W 0 when being read.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS S1C33 L 03 FU NCTI ON P ART EPSON B-III-9-21 A-1 B-III I/O SPPT7 –SP PT0 : Input polari ty s ele ct io n (D[7:0 ]) / P o rt interru pt input p ola ri ty s ele ct regist er (0x40 2C8 ) Sel ect s input si gn al p ora rit y for p ort in te rru pt g ene ra tio n.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS B-III-9-22 EPSON S1C 33 L 03 FUNCTI ON P ART SMP K13–S MPK10 : FPK1 input m as k (D[3 :0 ]) / F PK1 input m as k re gi s ter (0x40 2CF ) SMP K04–S MPK0.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS S1C33 L 03 FU NCTI ON P ART EPSON B-III-9-23 A-1 B-III I/O FP 3–FP0 : Por t in put 3 –0 in terru pt fact or fl ag (D [3:0 ]) / Key i nput , p ort in pu.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS B-III-9-24 EPSON S1C 33 L 03 FUNCTI ON P ART RP3–R P0 : P ort in pu t 3 –0 IDM A re que s t (D[3 :0]) / Port inp ut 0–3, hig h-sp eed DMA , 16- bit tim er 0 IDMA r eques t reg ister (0x 40290 ) RP7–R P4 : Port inpu t 7 –4 IDMA reque st (D [7 :4 ]) / Seri al I/F Ch.
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS S1C33 L 03 FU NCTI ON P ART EPSON B-III-9-25 A-1 B-III I/O Pr ogr a mm i ng Not es (1) A fter an in iti al re se t, the in te rru pt fa ctor fl ag s b eco me in deter m ina te .
III PER IPHERA L BLOC K: INPUT/OUT PUT PORTS B-III-9-26 EPSON S1C 33 L 03 FUNCTI ON P ART TH IS PAGE I S BLANK..
S1C33L03 F UNCTION PART IV ANALOG BLOCK.
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IV ANALOG BLOCK: IN T RODUCTI ON S1C33 L 03 FU NCTI ON P ART EPSON B-IV -1-1 A-1 B-IV Intro IV-1 INTR ODU CTION The a n alog b loc k co ns is ts o f an A /D co nver ter w ith 8 in pu t ch anne ls .
IV ANALOG BLOCK: IN T RODUCTI ON B-IV -1-2 EPSON S1C33 L 03 FU NCTI ON P ART TH IS PAGE I S BLANK..
IV ANALO G BLOC K: A/ D CONVERT ER S1C33 L 03 FU NCTI ON P ART EPSON B-IV -2-1 A-1 B-IV A/D IV-2 A/D CON VER TER Fe ature s an d S truct ur e of A/D Con ver ter The A n al o g Bl oc k co ntains an A /.
IV ANALO G BLOC K: A/ D CONVERT ER B-IV -2-2 EPSON S1C33 L 03 FU NCTI ON P ART I/O P ins of A/D Converter Tabl e 2.1 sho ws t he pins us e d by t he A / D c on ve rt er.
IV ANALO G BLOC K: A/ D CONVERT ER S1C33 L 03 FU NCTI ON P ART EPSON B-IV -2-3 A-1 B-IV A/D Setting A/D Converte r When the A/ D c on v er ter is u sed, th e fo llo wi ng se tti ng s m ust be m ad e befo re an A/D co nv er sio n ca n b e p erf orme d: 1.
IV ANALO G BLOC K: A/ D CONVERT ER B-IV -2-4 EPSON S1C33 L 03 FU NCTI ON P ART Table 2.3 Rela tio ns hip be tw een CS/ CE an d In put Cha nne l CS2/CE2 CS1/CE1 CS0/ CE0 Channel selected 11 1 A D 7 11 .
IV ANALO G BLOC K: A/ D CONVERT ER S1C33 L 03 FU NCTI ON P ART EPSON B-IV -2-5 A-1 B-IV A/D Set ti ng t he sampling t ime The A/ D c onve rt e r co n t ains S T[1:0 ] (D [1 :0]) / A /D sam pli ng re g.
IV ANALO G BLOC K: A/ D CONVERT ER B-IV -2-6 EPSON S1C33 L 03 FU NCTI ON P ART When a tr igg er is in put, th e A /D co nv er ter sam ple s and A /D-c on ver ts the an al og in put si gn al, b egi nnin g with the co nv er sio n st art chan ne l se le cte d b y CS[ 2:0 ].
IV ANALO G BLOC K: A/ D CONVERT ER S1C33 L 03 FU NCTI ON P ART EPSON B-IV -2-7 A-1 B-IV A/D A/D Converter Interrupt and DMA Upon comple t ion of A/D c onversi on in ea ch ch anne l, th e A /D co nv er ter g ene ra tes an inte rru pt an d in voke s th e DMA i f n ece ss ary.
IV ANALO G BLOC K: A/ D CONVERT ER B-IV -2-8 EPSON S1C33 L 03 FU NCTI ON P ART Trap vec tor The A/ D c onve rt e r's inte rru p t tr ap-ve ct or d efaul t ad dr es s is se t to 0x 0C00 100. The ba s e a ddr ess o f th e tr ap ta bl e ca n b e ch an ge d u sin g th e TTB R re gi ste r (0 x4 81 34 to 0 x481 37 ).
IV ANALO G BLOC K: A/ D CONVERT ER S1C33 L 03 FU NCTI ON P ART EPSON B-IV -2-9 A-1 B-IV A/D I/O Memo ry of A/D Converter Tabl e 2.6 sho ws t he cont ro l b its o f the A /D co nver ter . For det a ils on th e I/ O memo ry o f th e pres ca ler u sed to se t cl oc ks , refe r to "P res ca ler ".
IV ANALO G BLOC K: A/ D CONVERT ER B-IV-2 -10 EPSON S1C33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks – 0 to 7 0 to 7 – – PAD2 PAD1 PAD0 – PSIO12 PSIO11 PSIO10 D7 D6 D5 D4 D3 D2 D1 D0 reserved A/D converter interrupt level reserved Serial interface Ch.
IV ANALO G BLOC K: A/ D CONVERT ER S1C33 L 03 FU NCTI ON P ART EPSON B-IV-2 -11 A-1 B-IV A/D ADD9– ADD0 : A/D converte d data (D[1 :0 ]) / A/ D con vers i on re su lt ( hi g h- or de r) r egi st er (0 x4 0 24 1) (D[7 :0 ]) / A /D con vers ion re sult (l ow -ord er ) re gist er (0 x4 024 0) Sto res t h e resu lts o f A /D conv er sio n.
IV ANALO G BLOC K: A/ D CONVERT ER B-IV-2 -12 EPSON S1C33 L 03 FUNCTI ON P ART ADF : Conv ersi on- compl ete fla g ( D3) / A/D en able reg iste r (0x 40244 ) Indi ca tes th at A /D conv er sio n h as b een co m pl ete d.
IV ANALO G BLOC K: A/ D CONVERT ER S1C33 L 03 FU NCTI ON P ART EPSON B-IV-2 -13 A-1 B-IV A/D ST1– ST0 : S amp lin g- time setu p (D[1 :0 ]) / A /D samp lin g regist er (0x4 0 24 5) Set s the an al og in pu t sa mpli ng ti me.
IV ANALO G BLOC K: A/ D CONVERT ER B-IV-2 -14 EPSON S1C33 L 03 FUNCTI ON P ART The i n terru pt fa cto r fl ag is se t to "1 " whe ne ver in te rru pt gene ra tio n co nd it ions ar e m et, rega rd les s of h ow the inte rru pt en ab le and in te rru pt p rio rit y regi ste rs ar e set.
IV ANALO G BLOC K: A/ D CONVERT ER S1C33 L 03 FU NCTI ON P ART EPSON B-IV-2 -15 A-1 B-IV A/D Pr og ramm ing No tes (1) B efo re se tti ng th e co nv er sion m od e, st art /en d ch an ne ls , et c. fo r th e A/D co nver ter , be su re to d isa ble the A /D conv er ter (A DE (D 2 ) / A/D en ab le regi ste r (0 x4 02 44 ) = "0 ") .
IV ANALO G BLOC K: A/ D CONVERT ER B-IV-2 -16 EPSON S1C33 L 03 FUNCTI ON P ART TH IS PAGE I S BLANK..
S1C33L03 F UNCTION PART V DMA BLOCK.
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V DM A BLOC K: INTROD UCTION S1C33 L 03 FU NCTI ON P ART EPSON B-V-1-1 A-1 B-V Intro V-1 INTR ODU CTION The D M A Bloc k i s con figu r ed w ith two ty pes o f D MA cont ro lle rs: H SDMA (Hig h- Sp e.
V DM A BLOC K: INTROD UCTION B-V-1-2 EPSON S1C 33 L 03 FUNCTI ON P ART TH IS PAGE I S BLANK..
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) S1C33 L 03 FU NCTI ON P ART EPSON B-V-2-1 A-1 B-V HSDMA V-2 HSDMA (Hig h-Speed DMA) Func ti on al Ou tlin e of H SDM A The DMA Bloc k c o nt ain s fo ur ch an ne ls o f HSD MA (H ig h- Sp ee d DM A) ci rcu it s th at su pp or t d ual -a dd res s tr an sfe r and si ng le- ad dr ess tr an sfe r met ho ds.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) B-V-2-2 EPSON S1C 33 L 03 FUNCTI ON P ART I/O P ins of HSDMA Tabl e 2.1 lis ts t he I/O pins us ed f or H S DMA.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) S1C33 L 03 FU NCTI ON P ART EPSON B-V-2-3 A-1 B-V HSDMA Prog ramm ing Cont rol Inf o rm at ion The HS DMA opera te s ac co rd ing to th e co ntro l in fo rmati on se t in th e re gi ste rs. Note t hat some cont rol b its ch an ge th ei r func tio ns ac co rd ing to th e ad dr es s mod e.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) B-V-2-4 EPSON S1C 33 L 03 FUNCTI ON P ART Block le ngth When using bl o ck tra nsf er mo de (DxM OD = "10 "), t he da ta bl ock l engt h (in uni ts of DA TSI ZE x) sho uld be set u sin g the B LKL ENx [7: 0] b its.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) S1C33 L 03 FU NCTI ON P ART EPSON B-V-2-5 A-1 B-V HSDMA D0ADR L[15 :0]: Ch. 0 des tinati on ad dress [15:0 ] (D[F :0]) / Ch . 0 low- or de r d esti na tio n a dd re ss set- up reg ist e r (0 x4 8228 ) D1ADR L[15 :0]: Ch.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) B-V-2-6 EPSON S1C 33 L 03 FUNCTI ON P ART Set tin g the R egiste rs in Sing le-Ad dress Mode Make sure tha t the HS DMA chan ne l is d isa bled (H S x_EN = "0 ") b efo re se ffi ng th e co nt ro l in fo rmati on .
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) S1C33 L 03 FU NCTI ON P ART EPSON B-V-2-7 A-1 B-V HSDMA In si ng le- ad dress m ode, d ata tr an sfe r is p erf orm ed b etw een th e m emo ry conn ec te d to th e sy st em inte rfa ce an d an ex te rn al I/ O d evi ce .
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) B-V-2-8 EPSON S1C 33 L 03 FUNCTI ON P ART Tr i g g e r Fac t o r A HS DMA tigger factor can be s elect ed fro m a m on g 13 t ypes usi ng t he H S DMA trig ger se t-up re gi ste r fo r ea ch chan ne l. This fu nc tion is su ppor te d b y the in te rru pt co nt ro lle r.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) S1C33 L 03 FU NCTI ON P ART EPSON B-V-2-9 A-1 B-V HSDMA Opera tion of HSDMA An HSDMA c ha nnel s ta r ts data t ra ns f er by th e se lected tr igg er fa cto r.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) B-V- 2-10 EPSON S1 C33 L 03 FU NCTI ON P ART Su ccessiv e transfer mo de The c ha nnel f or which DxMOD i n c ontro l info rmati on is se t to " 0 1" oper at es in su cc essiv e tr an sfe r mod e.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) S1C33 L 03 FU NCTI ON P ART EPSON B-V- 2-11 A-1 B-V HSDMA Block tra nsfer mode The c ha nnel f or which DxMOD i n c ontro l info rmati on is se t to " 10" o per at es in bloc k tr an sfer m od e.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) B-V- 2-12 EPSON S1 C33 L 03 FU NCTI ON P ART Opera tion in Si ngle-Address Mode The op e ra tio n of each tr an sfer m od e is al m ost th e sa me as th at o f dual -a dd res s mod e (s ee th e prev io us se ct ion ).
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) S1C33 L 03 FU NCTI ON P ART EPSON B-V- 2-13 A-1 B-V HSDMA Ti min g Cha rt Dua l-a ddress mode (1) S RAM Exam ple: W h en 2 (R D ) /1 ( WR) wai t c y cles ar e in serte d BCLK A[23:0] #CE(src) #CE(dst) #RD #WRH/#WRL #DMAEND source address destination address Read cycle Write cycle Figur e 2.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) B-V- 2-14 EPSON S1 C33 L 03 FU NCTI ON P ART Si ngl e-addr ess m ode (1) S RAM Exam ple: W h en 2 (R D ) /1 ( WR) wai t c y cles ar e in serte d BCLK A[23:0] #CExx #RD #WRH/#WRL #DMAACK #DMAEND addr Figur e 2.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) S1C33 L 03 FU NCTI ON P ART EPSON B-V- 2-15 A-1 B-V HSDMA Inter ru pt Fu nc ti on of H S DMA The DM A con tr o ller can g ene ra te an inte rru pt w he n the tr an sfe r co un ter in ea ch H SDMA ch an ne l re ache s 0 .
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) B-V- 2-16 EPSON S1 C33 L 03 FU NCTI ON P ART Int e ll ig e nt D M A Inte llig en t DM A (I DMA ) ca n b e in vo ked b y the en d- of -tr ansfe r in te rru pt facto r o f ch anne ls 0 an d 1 o f HSDMA.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) S1C33 L 03 FU NCTI ON P ART EPSON B-V- 2-17 A-1 B-V HSDMA I/O Memo ry of HSD M A Tabl e 2. 5 s hows the co nt ro l b its of H SDM A. Table 2.5 Con tr ol Bit s of H SDMA Name Address Register name Bit Function Setting Init.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) B-V- 2-18 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks HSD1S3 HSD1S2 HSD1S1 HSD1S0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 D7 D6 D5 D4 D3 D2 D1 D0 High-speed DMA Ch.1 trigger set-up High-speed DMA Ch.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) S1C33 L 03 FU NCTI ON P ART EPSON B-V- 2-19 A-1 B-V HSDMA Name Address Register name Bit Function Setting Init.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) B-V- 2-20 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks – – DUALM0 D0DIR – TC0_H7 TC0_H6 TC0_H5 TC0_H4 TC0_H3 TC0_H2 TC0_H1 TC0_H0 DF DE DD–8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) S1C33 L 03 FU NCTI ON P ART EPSON B-V- 2-21 A-1 B-V HSDMA Name Address Register name Bit Function Setting Init. R/W Remarks D0MOD1 D0MOD0 D0IN1 D0IN0 D0ADRH11 D0ADRH10 D0ADRH9 D0ADRH8 D0ADRH7 D0ADRH6 D0ADRH5 D0ADRH4 D0ADRH3 D0ADRH2 D0ADRH1 D0ADRH0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) B-V- 2-22 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks S1ADRL15 S1ADRL14 S1ADRL13 S1ADRL12 S1ADRL11 S1ADRL10 S1ADRL9 S1ADRL8 S1ADRL7 S1ADRL6 S1ADRL5 S1ADRL4 S1ADRL3 S1ADRL2 S1ADRL1 S1ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) S1C33 L 03 FU NCTI ON P ART EPSON B-V- 2-23 A-1 B-V HSDMA Name Address Register name Bit Function Setting Init. R/W Remarks D1MOD1 D1MOD0 D1IN1 D1IN0 D1ADRH11 D1ADRH10 D1ADRH9 D1ADRH8 D1ADRH7 D1ADRH6 D1ADRH5 D1ADRH4 D1ADRH3 D1ADRH2 D1ADRH1 D1ADRH0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) B-V- 2-24 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks S2ADRL15 S2ADRL14 S2ADRL13 S2ADRL12 S2ADRL11 S2ADRL10 S2ADRL9 S2ADRL8 S2ADRL7 S2ADRL6 S2ADRL5 S2ADRL4 S2ADRL3 S2ADRL2 S2ADRL1 S2ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) S1C33 L 03 FU NCTI ON P ART EPSON B-V- 2-25 A-1 B-V HSDMA Name Address Register name Bit Function Setting Init. R/W Remarks D2MOD1 D2MOD0 D2IN1 D2IN0 D2ADRH11 D2ADRH10 D2ADRH9 D2ADRH8 D2ADRH7 D2ADRH6 D2ADRH5 D2ADRH4 D2ADRH3 D2ADRH2 D2ADRH1 D2ADRH0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) B-V- 2-26 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks S3ADRL15 S3ADRL14 S3ADRL13 S3ADRL12 S3ADRL11 S3ADRL10 S3ADRL9 S3ADRL8 S3ADRL7 S3ADRL6 S3ADRL5 S3ADRL4 S3ADRL3 S3ADRL2 S3ADRL1 S3ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) S1C33 L 03 FU NCTI ON P ART EPSON B-V- 2-27 A-1 B-V HSDMA Name Address Register name Bit Function Setting Init. R/W Remarks D3MOD1 D3MOD0 D3IN1 D3IN0 D3ADRH11 D3ADRH10 D3ADRH9 D3ADRH8 D3ADRH7 D3ADRH6 D3ADRH5 D3ADRH4 D3ADRH3 D3ADRH2 D3ADRH1 D3ADRH0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) B-V- 2-28 EPSON S1 C33 L 03 FU NCTI ON P ART IOC 1 6–IO C15 : P1[6:5 ] p ort I/O con tro l (D[6:5 ]) / P 1 I/ O con tro l regi st er (0 x40 2D 6 ) Dir ects P1 5 an d P 16 fo r in pu t o r outp ut an d in di cat es th e I/ O co nt ro l si gn al v alue o f th e p ort .
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) S1C33 L 03 FU NCTI ON P ART EPSON B-V- 2-29 A-1 B-V HSDMA HSD0S 3–H SD0S0 : C h. 0 tr igge r s et-up (D[3 :0]) / H SDMA C h. 0 /1 trigg e r set- up re gi ster (0 x40 298) HSD1S 3–H SD1S0 : C h. 1 tr igge r s et-up (D[7 :4]) / H SDMA C h.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) B-V- 2-30 EPSON S1 C33 L 03 FU NCTI ON P ART HS 0_EN : Ch. 0 en able ( D0) / HS DMA Ch . 0 enab le r eg iste r (0x 4822C) HS 1_EN : Ch. 1 en able ( D0) / HSDMA Ch . 1 enab le reg iste r (0x 4823C) HS 2_EN : Ch.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) S1C33 L 03 FU NCTI ON P ART EPSON B-V- 2-31 A-1 B-V HSDMA D0MOD1 –D0MOD0 : Ch. 0 transf er mode (D[F:E]) / Ch. 0 hi gh- o r der de st i nat ion addr es s s et- up regist er (0x48 22A ) D1MOD1 –D1MOD0 : Ch. 1 transf er mode (D[F:E]) / Ch.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) B-V- 2-32 EPSON S1 C33 L 03 FU NCTI ON P ART D0IN 1–D0I N0 : Ch . 0 destinat ion addres s cont rol (D[D :C]) / Ch. 0 high-or der de stinat ion address s et-up re gist er (0x48 22A) D1IN 1–D1I N0 : Ch . 1 destinat ion addres s cont rol (D[D :C]) / Ch.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) S1C33 L 03 FU NCTI ON P ART EPSON B-V- 2-33 A-1 B-V HSDMA S0ADR L15 –S0ADR L0 :C h . 0 s o urce ad dres s[15 :0] (D[F :0 ]) / C h. 0 low-or der s ou rc e ad dres s set -up r egis ter (0x 48224 ) S0ADR H11 –S0ADR H0 :C h .
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) B-V- 2-34 EPSON S1 C33 L 03 FU NCTI ON P ART EHDM0 : Ch. 0 inte rru pt e nabl e (D0 ) / DM A in te rrupt e nabl e re gi st er (0 x 40271) EHDM1 : Ch. 1 inte rru pt e nabl e (D1 ) / DM A in te rrupt e nabl e re gi st er (0 x 40271) EHDM2 : Ch.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) S1C33 L 03 FU NCTI ON P ART EPSON B-V- 2-35 A-1 B-V HSDMA RHDM0 : Ch.0 IDMA r eq ues t ( D4) / Po rt i np ut 0– 3, H SD MA, 16 - bit t imer 0 ID MA r eques t reg iste r (0x 402 90 ) RHDM1 : Ch.
V DM A BLOC K: HSDMA (Hi g h-Speed DM A) B-V- 2-36 EPSON S1 C33 L 03 FU NCTI ON P ART Pr og ramm ing No tes (1) Whe n se tti ng th e tr an sfe r cond it ion s, al ways mak e su re the D MA co nt rolle r is in ac tiv e (HS x_EN = "0 "). (2) A fter an in iti al re se t, the in te rru pt fa cto r fl ag (F HDMx ) b ecom es inde ter m inate .
V DMA BLO CK: IDMA (Inte lligent DMA) S1C33 L 03 FU NCTI ON P ART EPSON B-V-3-1 A-1 B-V IDMA V-3 IDMA (Intelligent DMA) Func ti on al Ou tlin e of IDMA Th e DM A Bl oc k co nt ain s an in te llig ent D MA (I DMA ), a func tio n that al lo ws cont ro l in fo rmati on to b e pro gram med in RA M.
V DMA BLO CK: IDMA (Inte lligent DMA) B-V-3-2 EPSON S1C 33 L 03 FUNCTI ON P ART The c on t ents of cont ro l in fo rmati on (3 wor ds) in ea ch ch anne l ar e sh ow n in th e ta bl e b elo w.
V DMA BLO CK: IDMA (Inte lligent DMA) S1C33 L 03 FU NCTI ON P ART EPSON B-V-3-3 A-1 B-V IDMA BLK LEN[7 :0 ]: Blo c k si z e/tr an sf e r co unte r (D [7:0]/1 s t Wo rd) In b loc k tr an sfe r mod e, se t th e si ze of a b loc k th at is tr an sfe rred in o ne o perat ion (i n u nit s o f D ATS IZ).
V DMA BLO CK: IDMA (Inte lligent DMA) B-V-3-4 EPSON S1C 33 L 03 FUNCTI ON P ART DS IN C[1: 0] : Dest inat i on addr ess co ntro l (D[ 29:2 8]/3rd Word) Set th e d est inatio n ad dres s u pd ate form at .
V DMA BLO CK: IDMA (Inte lligent DMA) S1C33 L 03 FU NCTI ON P ART EPSON B-V-3-5 A-1 B-V IDMA IDMA Invoc ation The t r igger s by wh ich IDMA is invo ke d h ave th e fo llo w ing th re e ca us es : 1. I nte rrupt fa ctor in an in te rna l peri ph era l ci rcu it 2.
V DMA BLO CK: IDMA (Inte lligent DMA) B-V-3-6 EPSON S1C 33 L 03 FUNCTI ON P ART Thes e i n terru pt fa cto rs ar e used in co mm on fo r in te rru pt re qu es ts an d ID MA in voca tio n re ques ts.
V DMA BLO CK: IDMA (Inte lligent DMA) S1C33 L 03 FU NCTI ON P ART EPSON B-V-3-7 A-1 B-V IDMA IDMA in voc a tio n request during a DMA t ransfer An I DMA i nvoca tion re qu es t to an ot he r chan ne l.
V DMA BLO CK: IDMA (Inte lligent DMA) B-V-3-8 EPSON S1C 33 L 03 FUNCTI ON P ART Opera tion of IDMA IDM A h as th ree tr an sfe r m odes , in ea ch o f whi ch d ata tr an sfe r o per at es d iffere ntl y. F urt he rmor e, an in te rrupt fa cto r is p roc es se d dif fer en t ly dep en di ng on t he t yp e of tri gge r.
V DMA BLO CK: IDMA (Inte lligent DMA) S1C33 L 03 FU NCTI ON P ART EPSON B-V-3-9 A-1 B-V IDMA Su ccessiv e transfer mo de The c h anne ls fo r whi ch DM OD in cont ro l in fo rmati on is se t to " 01" o per at e in su cces siv e tr an sfer mod e.
V DMA BLO CK: IDMA (Inte lligent DMA) B-V- 3-10 EPSON S1 C33 L 03 FU NCTI ON P ART Block tra nsfer mode The c h anne ls for w hi ch DM OD in cont ro l in form ati on is se t to "1 0" o per at e in b loc k tr ansfe r m ode.
V DMA BLO CK: IDMA (Inte lligent DMA) S1C33 L 03 FU NCTI ON P ART EPSON B-V- 3-11 A-1 B-V IDMA Pro cessing of i n terru pt factors by ty pe of trigger •W h e n inv oked by an i nter rupt f acto r The i nte rrup t fac tor fla g by w h ich IDMA ha s bee n invo ke d re m ain s se t even d uri ng a DM A tr an sfe r.
V DMA BLO CK: IDMA (Inte lligent DMA) B-V- 3-12 EPSON S1 C33 L 03 FU NCTI ON P ART Li nkin g If th e ID MA ch anne l n umbe r to be ex ec ut ed next is se t in the ID MA li nk fi eld " LNKC H N&q.
V DMA BLO CK: IDMA (Inte lligent DMA) S1C33 L 03 FU NCTI ON P ART EPSON B-V- 3-13 A-1 B-V IDMA Inter ru pt Fu nc tion of In telli gent DMA IDM A ca n g enera te an in terru pt th at ca uses in vo catio n o f IDM A an d an in terru pt fo r th e com pl eti on o f ID MA tran sfe r it sel f.
V DMA BLO CK: IDMA (Inte lligent DMA) B-V- 3-14 EPSON S1 C33 L 03 FU NCTI ON P ART Trap vec tor The trap ve cto r add ress for a n int err upt upon c om p let ion of IDM A t rans fer by de fau lt i s s et t o 0x0C 00 06 8. The t rap tabl e b ase ad dr es s can b e ch an ge d u sin g the T TBR re gi ste rs (0 x4 81 34 to 0x48 13 7).
V DMA BLO CK: IDMA (Inte lligent DMA) S1C33 L 03 FU NCTI ON P ART EPSON B-V- 3-15 A-1 B-V IDMA DB ASEL[15: 0] : IDMA bas e addre ss [15: 0] (D [F:0]) / IDMA base ad dres s low -o rd er r eg iste r ( 0.
V DMA BLO CK: IDMA (Inte lligent DMA) B-V- 3-16 EPSON S1 C33 L 03 FU NCTI ON P ART FIDM A : ID MA in terru pt fact or fl ag (D 4) / D MA inte rru pt fa ct or fl ag re gist er (0x4 0 281) Indi ca te th e o ccu rr ence st atu s o f an IDM A inte rru pt re qu es t.
V DMA BLO CK: IDMA (Inte lligent DMA) S1C33 L 03 FU NCTI ON P ART EPSON B-V- 3-17 A-1 B-V IDMA Pr og ramm ing No tes (1) B efore se tti ng the ID MA b ase addr es s, b e sure to d isa ble D MA tr an sfe rs (IDM AE N = "0 ").
V DMA BLO CK: IDMA (Inte lligent DMA) B-V- 3-18 EPSON S1 C33 L 03 FU NCTI ON P ART TH IS PAGE I S BLANK..
S1C33L03 F UNCTION PART VI SDRAM CONTR OLL ER BLOCK.
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VI SDRAM CONTROLLER BLOCK: INTRODUCTION S1C33L03 FUNCTION PART EPSON B- V I-1-1 A-1 B-VI Intro VI-1 INTR ODUCTION The SDRAM controller block provides a SDRAM interface that allows direct connection of external SDRAM chips via the BCU.
VI SDRAM CONTROLLER BLOCK: INTRODUCTION B- V I-1-2 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK..
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE S1C33 L 03 FU NCTI ON P ART EPSON B-VI -2-1 A-1 B-VI SDRAM VI-2 S DRAM INTERF A CE The SD RAM c ontr o ller al lows u p to 3 2M B o f S DRA M to b e conn ec te d d ire ctl y to ar ea s 7 an d 8 o r ar eas 1 3 an d 14.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE B-VI -2-2 EPSON S1C33 L 03 FUNCTI ON P ART I/O P ins an d Connec tion I/O Pins Tabl e 2.1 l ist s t he pi ns us ed fo r th e S DRA M in te rface.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE S1C33 L 03 FU NCTI ON P ART EPSON B-VI -2-3 A-1 B-VI SDRAM SDA11(A12) SDA10(P33) SDA[9:0](A[10:1]) SDBA[1:0](A[15:14]) D[15:0] BCLK SDCKE(P20) #SDCE0(#.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE B-VI -2-4 EPSON S1C33 L 03 FUNCTI ON P ART Note s :• B e c a u s e the SDRAM ad dr ess bu s pi ns di f fer in bit num be rs fro m ord inar y ex ter nal ad dr ess pin nam es , car e must be t aken wh en conn ecti n g an SD RAM t o t he S1C33 .
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE S1C33 L 03 FU NCTI ON P ART EPSON B-VI -2-5 A-1 B-VI SDRAM SDR AM Cont ro lle r Configuratio n Set tin g PL L When using the S DRAM co ntro lle r, al wa ys en ab le th e PLL . Refe r to "P LL" in S ect io n II -6, " CLG (Clo ck Gene rato r)", for se tti ng th e P LL.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE B-VI -2-6 EPSON S1C33 L 03 FUNCTI ON P ART B. Whe n us i ng area s 13/ 14 (CEF UNC = "01" ) B-1. A14IO (DD) /Ac ce ss con tro l re gi ste r (0 x4 81 32 ) = "1 " Thi s se ts ar ea s 1 3/14 fo r in te rnal acce ss .
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE S1C33 L 03 FU NCTI ON P ART EPSON B-VI -2-7 A-1 B-VI SDRAM Memory Configuration Use the regis t ers des cri bed bel ow to selec t the area in w hi ch SDR AM s ar e co nn ecte d an d th e ch ip enab le out put pi n to be us ed f or SD RAMs .
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE B-VI -2-8 EPSON S1C33 L 03 FUNCTI ON P ART Ba n k, ro w , a nd column address configuration An SD RAM me mory a rray c onsis ts of two or fou r ban ks, wi th e ach ba nk di vi de d in to p age s.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE S1C33 L 03 FU NCTI ON P ART EPSON B-VI -2-9 A-1 B-VI SDRAM Sele ct ing in i tia liz ati on se quence The SD RAM c ommand s equ ence th at is ru n im m edia tel y af ter S DRAM p ower -up ca n b e se le cte d to su it th e spec ifi ca tio ns o f th e S DRA M u sed.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE B-VI-2 -10 EPSON S1C33 L 03 FUN CTI ON P ART Enab li ng/di sabling bank interleaved access A ban k c a nn ot b e ac cess ed at th e sa m e ti me it is b ein g prec ha rg ed, so an ot he r b ank m ay b e acce ss ed d uri ng that p eri od , w hich re su lts in in cr eas ed ac ce ss sp ee d.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE S1C33 L 03 FU NCTI ON P ART EPSON B-VI-2 -11 A-1 B-VI SDRAM Timing setup The f oll owing parame ters ca n b e set in co nf ormi ty with S DRA M sp ec ifi catio ns b efore u se.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE B-VI-2 -12 EPSON S1C33 L 03 FUN CTI ON P ART SDR A M Op eration Syn c hron ou s Clo ck The SD RAM c ontr o ller uses th e B CLK pin as it o utp uts th e S DRA M cl oc k.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE S1C33 L 03 FU NCTI ON P ART EPSON B-VI-2 -13 A-1 B-VI SDRAM Pow er- up a nd Initializatio n The f oll owin g de s cri bes t he pr oce ssi ng seq uenc e for powe rin g up t he SD RAM.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE B-VI-2 -14 EPSON S1C33 L 03 FUN CTI ON P ART SDRAM power BCLK Command SDCKE #SDCEx #SDRAS #SDCAS #SDWE HDQM/LDQM SDRENA bit SDRIS bit SDRINI bit SDRMRS bit Internal #WAIT SDA10 SDBA[1:0] SDA[12:11, 9:0] PALL NOP H H MRS REF REF CMD Valid Valid Valid Valid Valid Valid 100 µ s min.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE S1C33 L 03 FU NCTI ON P ART EPSON B-VI-2 -15 A-1 B-VI SDRAM Burst Read Cycle Exce pt w h en t he bu rst le ng th is se t to 1 (S D RBL [1:0] ≠ "0 0") , th e SDR AM cont ro lle r al ways re ad s data fr om the SD RAM i n bur sts .
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE B-VI-2 -16 EPSON S1C33 L 03 FUN CTI ON P ART Fig ure 2. 12 s ho ws a n exam pl e of a ti mi ng ch ar t in ca se s w he re the ro w ad dr es s is vari ed d uri ng burs t re ad .
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE S1C33 L 03 FU NCTI ON P ART EPSON B-VI-2 -17 A-1 B-VI SDRAM Refres h Mode The SD RAM c ontr o ller supp or ts tw o SDR AM refre sh m odes : au to re fre sh an d se lf- re fre sh . Aut o ref resh The SD RAM c ontr o ller inco rp ora te s a 1 2-b it au to re fre sh co unte r.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE B-VI-2 -18 EPSON S1C33 L 03 FUN CTI ON P ART Self re fres h Sel f -re fre sh uses th e S DRA M’s se lf- re fre sh func tio n an d d oes not re qu ire cl oc k puls es d uri ng th e refre sh per iod, th us h elp in g to redu ce th e chip ’s p ower co ns ump tio n.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE S1C33 L 03 FU NCTI ON P ART EPSON B-VI-2 -19 A-1 B-VI SDRAM Pow er- do wn Mode The SD RAM c ontr o ller supp or ts thre e p ow er-do w n mod es fo r th e S 1C33 Cor e (H ALT , HAL T2, an d SLE EP). In H ALT mod e, th e b us cl oc k is n ot tu rn ed o ff.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE B-VI-2 -20 EPSON S1C33 L 03 FUN CTI ON P ART 1. The de vic e act i ng as the ex te rn al b us mas ter p romp ts th e S 1C33 to be p rep ar ed to relea se th e b us by m ea ns o f an in te rru pt o r som e o the r mea ns .
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE S1C33 L 03 FU NCTI ON P ART EPSON B-VI-2 -21 A-1 B-VI SDRAM I/O Memo ry of SDRAM Interfac e Tabl e 2.12 sho ws t he con trol bit s of the S DRA M in te rfa ce. The se re gi ste rs ar e m appe d in to ar ea 6 (0 x3 9F FC0 to 0x39 FF CA).
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE B-VI-2 -22 EPSON S1C33 L 03 FUN CTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks SDRTRCD1 SDRTRCD0 SDRTRSC SDRTRRD1 SDRTRRD0 – D7–6 D5 D4–3 D2–0 SDRAM t RCD spec SDRAM t RSC spec SDRAM t RRD spec reserved 0 0 0 0 0 – R/W R/W R/W – 0 when being read.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE S1C33 L 03 FU NCTI ON P ART EPSON B-VI-2 -23 A-1 B-VI SDRAM Name Address Register name Bit Function Setting Init.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE B-VI-2 -24 EPSON S1C33 L 03 FUN CTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks RBCLK – RBST8 REDO RCA1 RCA0 RPC2 RPC1.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE S1C33 L 03 FU NCTI ON P ART EPSON B-VI-2 -25 A-1 B-VI SDRAM A14SZ :A r e a s 1 4 –13 de vic e siz e sel ecti on (D 6) / Area s 14–1 3 set -up r egi.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE B-VI-2 -26 EPSON S1C33 L 03 FUN CTI ON P ART CEFUNC 1– CEFUNC0 : # CE pin fu nctio n sele ctio n (D[A :9 ]) / D RAM ti ming s et- up re gi ster (0 x48 130) Sel ect an ar ea fo r co nnec tio n w ith an S DRA M.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE S1C33 L 03 FU NCTI ON P ART EPSON B-VI-2 -27 A-1 B-VI SDRAM SDRPC1 :# C E 8 / 1 4 pin conf igura tio n ( D2) / SD RAM are a co nfi gur ation re gi st e.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE B-VI-2 -28 EPSON S1C33 L 03 FUN CTI ON P ART SDRI S : Initi al c omm and se quen ce (D4) / SDRAM co ntr ol r eg iste r (0x 39 FF C1) Sel ect th e S DRA M in iti ali za tion se qu en ce . Write "1": 1 .
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE S1C33 L 03 FU NCTI ON P ART EPSON B-VI-2 -29 A-1 B-VI SDRAM SDRBA : Numb er o f S DRAM b a nk s ( D1) / SDRAM ad dres s co nf igu ratio n reg iste r (0x 39 FF C2) Set the num b er of ban ks of t he SD RAM.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE B-VI-2 -30 EPSON S1C33 L 03 FUN CTI ON P ART SD RTRCD1–SD RTRCD0 : SDRAM t RCD spe c (D[7 :6]) / S DRA M ti mi ng s et-up re gist er 2 (0 x3 9FFC5 ) Set th e t RC D S DRA M p ara mete r (AC TI VE to REA D o r WR ITE d ela y ti me).
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE S1C33 L 03 FU NCTI ON P ART EPSON B-VI-2 -31 A-1 B-VI SDRAM SDRSZ : S DRA M d ata p ath b it wid th (D6 ) / S D RAM ad vanc ed co nt rol r egis ter (0x 39FF C9) Sel ect th e S DRA M d ata -path b it wid th.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE B-VI-2 -32 EPSON S1C33 L 03 FUN CTI ON P ART Pr og ramm ing No tes (1) Mak e su re th at two w ait cy cl es ar e in se rte d whe n ac ce ss ing ar ea 6 , w he re th e SDR AM cont ro lle r is al lo cat ed .
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE S1C33 L 03 FU NCTI ON P ART EPSON B-VI-2 -33 A-1 B-VI SDRAM E xample s of SD RAM Contr oller In itial ization Pro gram The f o llow ing show s exam p les of th e in iti ali za tion p rog ra m fo r u sing S DRA M.
VI SDRAM CONTROL L ER BLOC K: S DRA M INTERF ACE B-VI-2 -34 EPSON S1C33 L 03 FUN CTI ON P ART ;;; SD RA M au to re fr esh co un t hi gh -or der re gi ster xld. w %r 0, 0x3 9FF C7 ; xld. w %r 1, 0x0 0 ; ld.b [% r0 ],% r1 ; ;/// /// /// // /// /// // /// /// // /// /// // /// /// // ;;; SD RA M se lf re fr esh co unt re gi ste r ;;; xl d.
S1C33L03 F UNCTION PART VII LCD CONTR OLL ER BLOCK.
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VII LCD CONTROLL ER BLOC K: I NTROD UCT ION S1C33 L 03 FU NCTI ON P ART EPSON B-VII-1- 1 A-1 B-VII Intro VII-1 INTR ODU CTION The LC D Con tro lle r Block pr ovi des LC D con tr ol si gnals fo r a 4 - o r 8 -bi t colo r/m o noch ro me LCD pane l.
VII LCD CONTROLL ER BLOC K: I NTROD UCT ION B-VII-1-2 EPSO N S1C33 L 03 FUNCTI ON P ART TH IS PAGE I S BLANK..
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII-2- 1 A-1 B-VII LCDC VII-2 LCD CON TR OLLER Thi s sec tio n des cri bes t he f u nc tio ns an d co nt ro l p roc ed ur es o f th e L C D con tr o ller.
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII-2-2 EPSO N S1C33 L 03 FUNCTI ON P ART Powe r save • D OZE mod e su ita bl e for E ps on ’s se lf- re fre sh -ty pe L CD p ane ls • T he st atu s of the L CD co nt ro lle r ca n b e chec ke d u sin g th e pow er -sa ve st atus b it.
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII-2- 3 A-1 B-VII LCDC Block Di agra m #BUSREQ #BUSACK #BUSGET #CE7/13(8/14) Address[23:0] Data[15:0] #CE6 FIFO Displa.
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII-2-4 EPSO N S1C33 L 03 FUNCTI ON P ART I/O P ins of the LCD Controlle r Tabl e 2. 1 l ist s t he inpu t/o ut put p ins of th e L CD co nt rolle r. T ab le 2.2 sh ows t he p in co nf i gura t io ns cl as sif ied b y type o f LC D pa nel .
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII-2- 5 A-1 B-VII LCDC S ystem S ett ing s Set tin g the BCU The c on tr ol regi ste rs o f th e LCD cont rolle r ar e m appe d in to ar ea -6 addr es ses 0 x3 9FFE 0 to 0x3 9F FFF.
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII-2-6 EPSO N S1C33 L 03 FUNCTI ON P ART Use t he ED MAEN (D3) / LCD C s yste m contro l re gi ste r (0 x3 9FF FD ) to m as k th e # DMA REQ x si gn als .
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII-2- 7 A-1 B-VII LCDC Clock The LC D c on trol l er us e s the B CU cl ock as th e so ur ce cl oc k fo r it s pix el c l oc k P CLK an d d isp lay m emo ry cl oc k MCLK.
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII-2-8 EPSO N S1C33 L 03 FUNCTI ON P ART Set ting th e L CD Pan el Ty pes of Pan els The LC D c on troll er suppor ts th e fo llo wing ty pes o f si ng le- LCD pane ls .
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII-2- 9 A-1 B-VII LCDC Displ ay Mod es The nu mb er of gra y lev els in gr ays cal e dis pla y and the num b er of col ors in col or di spl ay a re de ter mine d by t he num b er of bit s rep res en tin g eac h pix el ( bpp = bi ts per pix el) .
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII- 2-10 EPSO N S1C33 L 03 FUNCTI ON P ART (3) 4 -b pp (16-gr ay -l ev el /1 6-c o l o r) m o de One pix el is re pr ese nt ed by 4 bi t s, di spl aye d in 16 gra y lev els or 16 col ors .
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII- 2- 11 A-1 B-VII LCDC Look -u p Tables The LC D c on troll er c o nt ain s a lo ok-u p ta bl e co ns is tin g of 1 6 4 -bi t en tr ies , o ne for ea ch o f th e R GB co lo r el emen ts (r ed, g ree n, an d b lue ).
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII- 2-12 EPSO N S1C33 L 03 FUNCTI ON P ART Grayscal e-mode l ook-up ta bles In g ray sc ale mod e, th e L CD co nt rolle r u ses o nly the g ree n lo ok -u p tabl e.
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII- 2- 13 A-1 B-VII LCDC (3) 4 -bpp (1 6-gr ay-l ev el) m ode Use a ll entries o f th e g reen lo ok -up ta bl e. A ll 1 6 g ray leve ls ca n b e assi gn ed to th e lo ok -up ta bl e.
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII- 2-14 EPSO N S1C33 L 03 FUNCTI ON P ART Col or-m ode look- up tables In co lo r m ode, th e L CD co nt ro lle r uses th e re d (R ), g reen (G ), an d b lue (B) lo ok -u p ta bl es. Each co lo r el emen t is re pr ese nted b y 4 -bi t d ata .
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII- 2- 15 A-1 B-VII LCDC (2) 2 -bpp (4 -col or) m o de Use the fi rst four en tr ies o f ea ch lo ok-u p ta bl e. S ele ct 4 -colo r d ata fr om am o ng th e 4 ,09 6 co lo rs, an d w rit e it to th e re sp ec tive en tr ies .
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII- 2-16 EPSO N S1C33 L 03 FUNCTI ON P ART (3) 4 -bpp (1 6-co lor) m ode Use a ll entries o f ea ch look -u p ta ble. S ele ct 1 6-col or d ata fr om amo ng the 4 ,09 6 colo rs, an d writ e it to th e resp ec tiv e en tries .
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII- 2- 17 A-1 B-VII LCDC (4) 8 -bpp (2 56-c olo r) mo de One pix el is re pr ese nt ed by 8 bi t s, di spl aye d in 25 6 col ors . Thi s mode is not ava ila ble f or gra ysca le di spl ay.
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII- 2-18 EPSO N S1C33 L 03 FUNCTI ON P ART Set ti ng data in the l ook- up tables To s et da ta in th e lo ok -up ta bl es, u se the lo ok -u p- table ad dr es s re gi ster (0 x3 9FF F5 ) an d th e lo ok -up- tab le d ata regi ste r (0 x39F F F7 ).
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII- 2- 19 A-1 B-VII LCDC Fram e Rat es The f ram e ra te is ca lc ula te d fr om th e L CD p ane l’ s re so lut io n, n on -di sp lay p eri od , an d p ixe l cl oc k fr eq ue nc y, as show n below .
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII- 2-20 EPSO N S1C33 L 03 FUNCTI ON P ART Other S ettings FPSHIFT mask When a co lo r pass iv e L CD p anel is u sed , F PSHI FT (s hi ft cl oc k) ca n b e tu rn ed o n or of f du rin g the non- dis pla y per iod us i ng FP SMA SK (D 2) /LCD C mo de reg is ter 0 (0x 39 FFE 1) .
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII- 2- 21 A-1 B-VII LCDC Displ ay Con trol Controlling LCD Power Up/Down The LC D c on troll er is ac tiv at ed to st art u p an d g ene ra te LCD si gn als b y setti ng L CDC EN (D 5)/L C DC mod e regi ste r 2 (0 x39F FE 3 ) to "1 ".
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII- 2-22 EPSO N S1C33 L 03 FUNCTI ON P ART The f o llow ing is th e p owe r-d own pr oced ur e. 1. Pla c e th e LCD co nt ro lle r in p ower -sa ve m od e (L P SA VE = "0 b0 0").
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII- 2- 23 A-1 B-VII LCDC Sp lit-Scr een Disp lay The LC D c on troll er s u ppor ts a sp lit -s cre en func tio n, al lowi ng diffe re nt ima ges to be d isp lay ed o n tw o v ert ica lly split sc re en s o n the L CD p ane l.
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII- 2-24 EPSO N S1C33 L 03 FUNCTI ON P ART The s tar ting pos iti on of the vie w po r t is c hang ed by mo di fying th e sc re en 1 st art ad dr es s re gi ste r d esc rib ed ab ov e.
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII- 2- 25 A-1 B-VII LCDC Inver ting and B lankin g the Disp lay The di spl ay c an be bl ank ed ( the e ntir e sc re en tu rned b lac k) with ou t re writi ng th e co nten ts o f th e d isplay m emo ry.
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII- 2-26 EPSO N S1C33 L 03 FUNCTI ON P ART 4. Wr ite a por tra it- mode di spl ay i mag e int o m e mor y, s uch a s A → B .
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII- 2- 27 A-1 B-VII LCDC Alte rnate por tra it m ode A ltern ate p ort rai t mod e does n ot re quire ex tr a d isplay m emo ry as in d efa ul t p ortrai t mo de.
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII- 2-28 EPSO N S1C33 L 03 FUNCTI ON P ART 7. If ne ces sar y, s el ect the pix el c lo ck f requ ency for use in po rtr a it mo de by us ing the PMO DCLK [ 1:0] (D[1 :0 ])/ po rtr ait m od e regi ste r (0 x3 9F FFB ).
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII- 2- 29 A-1 B-VII LCDC Pow er Sa ve The LC D c ontr oll er ha s two typ es of pow e r-s ave m o de s. Us e LP SAV E[ 1: 0 ] (D[1 :0 ])/ LCD C mode re gi ste r 2 (0x3 9FF E3 ) to se t powe r-s av e m ode s.
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII- 2-30 EPSO N S1C33 L 03 FUNCTI ON P ART Controll ing the GP IO Pins The pi n s de scr ibe d bel ow can be use d a s ge ner al- purp os e outpu t (G PO ) pi n s or ge n er al- purp ose input /ou tput (GP IO ) p ins , th ro ug h p anel se le cti on o r o the r se tti ng s.
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII- 2- 31 A-1 B-VII LCDC I/O Memory of LCD Controller Tabl e 2.21 sho ws t he con trol bit s of the L CD co nt ro lle r. The se re gi ste rs ar e map pe d in to ar ea 6 (0 x3 9F FE0 to 0x39 FF FD).
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII- 2-32 EPSO N S1C33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks VNDPF – VNDP5 VNDP4 VNDP3 VNDP2 VNDP1 VNDP0 D7 D6 D5 D4 D3 D2 D1 D0 Vertical non-display period status reserved Vertical non-display period 0 – 0 0 0 0 0 0 R – R/W 0 when being read.
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII- 2- 33 A-1 B-VII LCDC Name Address Register name Bit Function Setting Init. R/W Remarks – S1VSIZE9 S1VSIZE8 D7–2 D1 D0 reserved Screen 1 vertical size (high-order 2 bits) – 0 0 – R/W 0 when being read.
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII- 2-34 EPSO N S1C33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks VRAMAR VRAMWT2 VRAMWT1 VRAMWT0 EDMAEN BREQ.
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII- 2- 35 A-1 B-VII LCDC BP P[1:0] : Bi t-pe r-p ixel s elect (D[7 :6 ]) / LCDC mod e regi st er 1 (0 x39F FE2 ) Sel ect s dis pla y mode (bpp m o de). The c on te nts of s elec t ion, inc ludi n g tha t of LD COL OR, a re l is ted in Ta ble 2.
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII- 2-36 EPSO N S1C33 L 03 FUNCTI ON P ART LPW REN : Enabl e LC DPWR ( D4) / LCDC mo de reg ister 2 (0x 39FF E3) Enab les LCDPW R out put c on t rol b y th e L CD co ntro lle r.
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII- 2- 37 A-1 B-VII LCDC VNDPF : Vertic al no n-dis play sta tus (D7) / Vert ica l no n-dis play per iod reg ister ( 0x39 FFEA) Indi ca tes whe the r th e LCD pane l is in a vert ica l n on -disp lay p eri od.
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII- 2-38 EPSO N S1C33 L 03 FUNCTI ON P ART LC LKSEL[ 2:0] : LCDC c lock s elect (D[2 :0 ]) / FIF O c on trol re gi ster (0 x39F FF4 ) Sel ect s the oper at ing cl oc k fo r th e L CD co nt ro ller.
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII- 2- 39 A-1 B-VII LCDC GPIO2 D : GP IO2 d ata (D 2) / G PIO s tatus /con tro l regi st er (0x3 9FFF9 ) GPIO1 D : GP .
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII- 2-40 EPSO N S1C33 L 03 FUNCTI ON P ART PMO DSEL : Por trait m ode s elect (D 6 ) / P or tra it mod e re gi st er (0x3 9FFF B) Sel ect s a typ e of po rtr ait m o de .
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII- 2- 41 A-1 B-VII LCDC EDMAEN : Enabl e exte rnal D MA (D3 ) / L CD C sys tem c on tro l regi st er (0x3 9FFF D ) Enab les /di sa ble s DMA re ques ts fr om ex te rn al d evi ce s whi le th e L CD co nt ro ller is in u se.
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII- 2-42 EPSO N S1C33 L 03 FUNCTI ON P ART Pr og ramm ing No tes (1) Whe n th e ch ip is set in H ALT 2 or S LEEP mod e af ter th e LCD co nt ro lle r .
VII LCD CONTROLL ER BLOC K: L CD CONTROL LER S1C33 L 03 FU NCTI ON P ART EPSON B-VII- 2- 43 A-1 B-VII LCDC E xamples of LCD Controller Sett ing P rogram (Wa it s ign al = O N ) ;*** *** *** ** *** *** * ;C33 L03 AS M ;*** *** *** ** *** *** * ;=== === === == === === == === === == === === == .
VII LCD CONTROLL ER BLOC K: L CD CONTROL L ER B-VII- 2-44 EPSO N S1C33 L 03 FUNCTI ON P ART ld.b [% r1 ], %r 2 xld. w %r 1, 0x39 ffe a ; se t Ve rt ica l No n- dis pla ye d Peri od xld. w %r 2, 0x 01 ld.b [% r1 ], %r 2 xl d. w %r 1, 0x 39 ffe c ; se t S1 st ar t ad dr ess aa aa xld.
S1C33L03 F UNCTION PART Appe nd i x I/O MAP.
.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-1 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks – P8TPCK5 P8TPCK4 D7–2 D1 D0 reserved 8-bit timer 5 clock selection 8-bit timer 4 clock selection – 0 0 – R/W R/W 0 when being read.
APPENDI X: I/O MAP B-APPENDIX-2 EPSON S1C33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks – – P16TON3 P16TS32 P16TS31 P16TS30 D7–4 D3 D2 D1 D0 reserved 16-bit timer 3 clock control 16-bit timer 3 clock division ratio selection – 0 0 0 0 – R/W R/W 0 when being read.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-3 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks 1 On 0 Off P8TON3 P8TS32 P8TS31 P8TS30 P8TON2 P8TS22 P8TS21.
APPENDI X: I/O MAP B-APPENDIX-4 EPSON S1C33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks – TCHD5 TCHD4 TCHD3 TCHD2 TCHD1 TCHD0 D7–6 D5 D4 D3 D2 D1 D0 reserved Clock timer minute counter data TCHD5 = MSB TCHD0 = LSB – X X X X X X – R/W 0 when being read.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-5 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks – PTOUT0 PSET0 PTRUN0 D7–3 D2 D1 D0 reserved 8-bit timer 0 clock output control 8-bit timer 0 preset 8-bit timer 0 Run/Stop control – 0 – 0 – R/W W R/W 0 when being read.
APPENDI X: I/O MAP B-APPENDIX-6 EPSON S1C33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks – PTOUT3 PSET3 PTRUN3 D7–3 D2 D1 D0 reserved 8-bit timer 3 clock output control 8-bit timer 3 preset 8-bit timer 3 Run/Stop control – 0 – 0 – R/W W R/W 0 when being read.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-7 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks WRWD – D7 D6–0 EWD write protection – 0 – R/W – 0 when being read.
APPENDI X: I/O MAP B-APPENDIX-8 EPSON S1C33 L 03 FUNCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks CLKDT1 CLKDT0 PSCON – CLKCHG SOSC3 SOSC1 D7 D6 D5 D4–3 D2 D1 D0 S.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-9 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks 0x0 to 0xFF(0x7F) TXD07 TXD06 TXD05 TXD04 TXD03 TXD02 TXD01 TXD00 D7 D6 D5 D4 D3 D2 D1 D0 Serial I/F Ch.
APPENDI X: I/O MAP B-APPENDIX-1 0 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks 0x0 to 0xFF(0x7F) TXD17 TXD16 TXD15 TXD14 TXD13 TXD12 TXD11 TXD10 D7 D6 D5 D4 D3 D2 D1 D0 Serial I/F Ch.1 transmit data TXD17(16) = MSB TXD10 = LSB X X X X X X X X R/W 7-bit asynchronous mode does not use TXD17.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-11 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks TXEN2 RXEN2 EPR2 PMD2 STPB2 SSCK2 SMD21 SMD20 D7 D6 D5 D4 D3 D2 D1 D0 Ch.2 transmit enable Ch.2 receive enable Ch.
APPENDI X: I/O MAP B-APPENDIX-1 2 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 D7 D6 D5 D4 D3 D2 D1 D0 A.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-13 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks – 0 to 7 0 to 7 – – PP1L2 PP1L1 PP1L0 – PP0L2 PP0L.
APPENDI X: I/O MAP B-APPENDIX-1 4 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks – 0 to 7 0 to 7 – – PSIO02 PSIO01 PSIO00 – P8TM2 P8TM1 P8TM0 D7 D6 D5 D4 D3 D2 D1 D0 reserved Serial interface Ch.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-15 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks – EK1 EK0 EP3 EP2 EP1 EP0 D7–6 D5 D4 D3 D2 D1 D0 reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 – – 0 0 0 0 0 0 – R/W R/W R/W R/W R/W R/W 0 when being read.
APPENDI X: I/O MAP B-APPENDIX-1 6 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks – FK1 FK0 FP3 FP2 FP1 FP0 D7–6 D5 D4 D3 D2 D1 D0 reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 – – X X X X X X – R/W R/W R/W R/W R/W R/W 0 when being read.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-17 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.
APPENDI X: I/O MAP B-APPENDIX-1 8 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks HSD1S3 HSD1S2 HSD1S1 HSD1S0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 D7 D6 D5 D4 D3 D2 D1 D0 High-speed DMA Ch.1 trigger set-up High-speed DMA Ch.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-19 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks – CFK54 CFK53 CFK52 CFK51 CFK50 D7–5 D4 D3 D2 D1 D0 re.
APPENDI X: I/O MAP B-APPENDIX-2 0 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks T8CH5S0 SIO3TS0 T8CH4S0 SIO3RS0 SIO2TS0 SIO3ES0 SIO2RS0 SIO2ES0 D7 D6 D5 D4 D3 D2 D1 D0 8-bit timer 5 underflow SIO Ch.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-21 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks – SCPK04 SCPK03 SCPK02 SCPK01 SCPK00 D7–5 D4 D3 D2 D1 .
APPENDI X: I/O MAP B-APPENDIX-2 2 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks – IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 D7 D6 D5 D4 D3 D2 D.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-23 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks CFEX7 CFEX6 CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 CFEX0 D7 D6 D5 D.
APPENDI X: I/O MAP B-APPENDIX-2 4 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks – A12SZ A12DF1 A12DF0 – A12WT2 A12WT1 A12WT0 DF–7 D6 D5 D4 .
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-25 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks – A6DF1 A6DF0 – A6WT2 A6WT1 A6WT0 – A5SZ A5DF1 A5DF0.
APPENDI X: I/O MAP B-APPENDIX-2 6 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks 1 Successive 0 Normal – A3EEN CEFUNC1 CEFUNC0 CRAS RPRC1 RPRC0 .
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-27 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks – 1 Enabled 0 Disabled 1 Enabled 0 Disabled A18AS A16AS .
APPENDI X: I/O MAP B-APPENDIX-2 8 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR0A15 CR0A14 CR0A13 CR0A12 CR0A11 CR0A10 CR0A9 CR0A8 .
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-29 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR1A15 CR1A14 CR1A13 CR1A12 CR1A11 CR1A10 CR1A9.
APPENDI X: I/O MAP B-APPENDIX-3 0 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR2A15 CR2A14 CR2A13 CR2A12 CR2A11 CR2A10 CR2A9 CR2A8 .
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-31 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR3A15 CR3A14 CR3A13 CR3A12 CR3A11 CR3A10 CR3A9.
APPENDI X: I/O MAP B-APPENDIX-3 2 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR4A15 CR4A14 CR4A13 CR4A12 CR4A11 CR4A10 CR4A9 CR4A8 .
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-33 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR5A15 CR5A14 CR5A13 CR5A12 CR5A11 CR5A10 CR5A9.
APPENDI X: I/O MAP B-APPENDIX-3 4 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks DBASEL15 DBASEL14 DBASEL13 DBASEL12 DBASEL11 DBASEL10 DBASEL9 DBA.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-35 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks TC0_L7 TC0_L6 TC0_L5 TC0_L4 TC0_L3 TC0_L2 TC0_L1 TC0_L0 BLKLEN07 BLKLEN06 BLKLEN05 BLKLEN04 BLKLEN03 BLKLEN02 BLKLEN01 BLKLEN00 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.
APPENDI X: I/O MAP B-APPENDIX-3 6 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks D0ADRL15 D0ADRL14 D0ADRL13 D0ADRL12 D0ADRL11 D0ADRL10 D0ADRL9 D0ADRL8 D0ADRL7 D0ADRL6 D0ADRL5 D0ADRL4 D0ADRL3 D0ADRL2 D0ADRL1 D0ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-37 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks TC1_L7 TC1_L6 TC1_L5 TC1_L4 TC1_L3 TC1_L2 TC1_L1 TC1_L0 BLKLEN17 BLKLEN16 BLKLEN15 BLKLEN14 BLKLEN13 BLKLEN12 BLKLEN11 BLKLEN10 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.
APPENDI X: I/O MAP B-APPENDIX-3 8 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks D1ADRL15 D1ADRL14 D1ADRL13 D1ADRL12 D1ADRL11 D1ADRL10 D1ADRL9 D1ADRL8 D1ADRL7 D1ADRL6 D1ADRL5 D1ADRL4 D1ADRL3 D1ADRL2 D1ADRL1 D1ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-39 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks TC2_L7 TC2_L6 TC2_L5 TC2_L4 TC2_L3 TC2_L2 TC2_L1 TC2_L0 BLKLEN27 BLKLEN26 BLKLEN25 BLKLEN24 BLKLEN23 BLKLEN22 BLKLEN21 BLKLEN20 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.
APPENDI X: I/O MAP B-APPENDIX-4 0 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks D2ADRL15 D2ADRL14 D2ADRL13 D2ADRL12 D2ADRL11 D2ADRL10 D2ADRL9 D2ADRL8 D2ADRL7 D2ADRL6 D2ADRL5 D2ADRL4 D2ADRL3 D2ADRL2 D2ADRL1 D2ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-41 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks TC3_L7 TC3_L6 TC3_L5 TC3_L4 TC3_L3 TC3_L2 TC3_L1 TC3_L0 BLKLEN37 BLKLEN36 BLKLEN35 BLKLEN34 BLKLEN33 BLKLEN32 BLKLEN31 BLKLEN30 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.
APPENDI X: I/O MAP B-APPENDIX-4 2 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks D3ADRL15 D3ADRL14 D3ADRL13 D3ADRL12 D3ADRL11 D3ADRL10 D3ADRL9 D3ADRL8 D3ADRL7 D3ADRL6 D3ADRL5 D3ADRL4 D3ADRL3 D3ADRL2 D3ADRL1 D3ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-43 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks – – SDRAR0 SDRAR1 – SDRPC0 SDRPC1 – D7 D6 D5–4 D.
APPENDI X: I/O MAP B-APPENDIX-4 4 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks SDRTRCD1 SDRTRCD0 SDRTRSC SDRTRRD1 SDRTRRD0 – D7–6 D5 D4–3 D2–0 SDRAM t RCD spec SDRAM t RSC spec SDRAM t RRD spec reserved 0 0 0 0 0 – R/W R/W R/W – 0 when being read.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-45 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks PCODE5 PCODE4 PCODE3 PCODE2 PCODE1 PCODE0 RCODE1 RCODE0 D7.
APPENDI X: I/O MAP B-APPENDIX-4 6 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks VNDPF – VNDP5 VNDP4 VNDP3 VNDP2 VNDP1 VNDP0 D7 D6 D5 D4 D3 D2 D1 D0 Vertical non-display period status reserved Vertical non-display period 0 – 0 0 0 0 0 0 R – R/W 0 when being read.
APPENDI X: I/O MAP S1C33 L 03 FU NCTI ON P ART EPSON B-APPENDIX-47 A-1 B-ap Name Address Register name Bit Function Setting Init. R/W Remarks – S1VSIZE9 S1VSIZE8 D7–2 D1 D0 reserved Screen 1 vertical size (high-order 2 bits) – 0 0 – R/W 0 when being read.
APPENDI X: I/O MAP B-APPENDIX-4 8 EPSON S1 C33 L 03 FU NCTI ON P ART Name Address Register name Bit Function Setting Init. R/W Remarks VRAMAR VRAMWT2 VRAMWT1 VRAMWT0 EDMAEN BREQEN LCDCST LCDCEC D7 D6 .
AMERICA EPSON ELECTRONICS AMERICA, INC. - HEADQUARTERS - 150 River Oaks Parkway San Jose, CA 95134, U.S.A. Phone: +1-408-922-0200 Fax: +1-408-922-0238 - SALES OFFICES - West 1960 E. Grand Avenue EI Segundo, CA 90245, U.S.A. Phone: +1-310-955-5300 Fax: +1-310-955-5400 Central 101 Virginia Street, Suite 290 Crystal Lake, IL 60014, U.
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http://www.epsondevice.com EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION Issue April, 2003 Printed in Japan B L T echnical Manual S1C33L03.
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