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AMD Geode™ LX Processors Data Book AMD Geode™ LX Processors Data Book February 2009 Publicat ion ID: 33234H.
2 AMD Geode™ LX Processors Data Book © 2009 Advanced Micr o De vices, Inc. All r ights reser ved. The contents of this docu ment are pr o vided in connection with Adv anced Micro Devices , Inc.
AMD Geode™ LX Processors Data Book 3 Contents 33234H Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Tables . . . . . . . . . . . . . . . . . . . .
4 AMD Geode™ LX Processors Data Book Contents 33234H 6.0 Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 6.1 GeodeLink™ Memor y Co ntroller . . . . . . . . . . . . . . . . . . . .
AMD Geode™ LX Processors Data Book 5 List of Figures 33234H List of Figures Figure 1-1. Internal Bloc k Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3-1. Signal Groups .
6 AMD Geode™ LX Processors Data Book List of Figures 33234H Figure 6-42. Ancillary Data Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9 Figure 6-43. M essage Passing Data Packet .
AMD Geode™ LX Processors Data Book 7 List of T ables 33234H List of T ab les Table 2-1. Graphics Pro cessor Feature Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 Table 3-1. Video Signal D efinitions Per M ode .
8 AMD Geode™ LX Processors Data Book - List of T ables 33234H Table 6-11. Data Only Co mmand Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Table 6-12. Bit Descriptio ns . . . . . . . . . . . .
AMD Geode™ LX Processors Data Book 9 List of T ables 33234H Table 6-66. Panel Outpu t Signal Ma pping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 Table 6-67. Register Sett ings for Dither Enable/Disable Fe ature .
10 AMD Geode™ LX Processors Data Book - List of T ables 33234H Table 8-12. sr eg3 Field (FS an d GS Segment Register Selectio n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 24 Table 8-13. ss Field Encodin g . . . . . . . . . . . . . . .
AMD Geode™ LX Processors Data Book 11 1 Overview 33234H 1.0 Ov er vie w 1.1 General Description AMD Geode™ LX processors a re integrated x86 proces- sors specifically designed to power embedded devices f or enter tainment, e ducation, and business.
12 AMD Geode™ LX Processors Data Book Overview 33234H 1.2 Features General Features ■ Functional blocks include: —C P U C o r e — GeodeLink™ Control Processor — GeodeLink Interface Units .
AMD Geode™ LX Processors Data Book 13 Overview 33234H Display Contr olle r ■ Hardware frame buff er compression improves Unified Memory Architecture (U MA) memory efficiency ■ CRT resolutions su.
14 AMD Geode™ LX Processors Data Book Overview 33234H.
AMD Geode™ LX Processors Data Book 15 2 Architecture Overview 33234H 2.0 Architecture Ov er vie w The CPU Core provides maximum compatibility with the vast amount of Internet content availab le w hi.
16 AMD Geode™ LX Processors Data Book Architecture Overview 33234H 2.1.2 Memor y Managemen t Unit The memor y management uni t (MMU) translates the linear address supplied by the integer unit into a ph ysical address to be used by the cache unit and the inter nal bus interface unit.
AMD Geode™ LX Processors Data Book 17 Architecture Overview 33234H 2.5 Graphics Processor The Graphics Processor is based on the graphics proces- sor used in the AMD Ge ode GX processor with several f ea- tures added to enhance performa nce and functionality .
18 AMD Geode™ LX Processors Data Book Architecture Overview 33234H 2.6 Display Contr oller The Display Controller perf or ms the f ollowing functions: 1) Retriev es graphics, video , and cursor data. 2) Serializes the streams. 3) P erforms any necessar y color lookups and output for- matting.
AMD Geode™ LX Processors Data Book 19 Architecture Overview 33234H 2.10 Security Block The AMD Geode LX processor has an on-chip AES 128-bit cr ypto acceleration block capable of 44 Mbps throughput on either encr yption or decr yption at a processor speed of 500 MHz.
20 AMD Geode™ LX Processors Data Book Architecture Overview 33234H.
AMD Geode™ LX Processors Data Book 21 3 Signal Definitions 33234H 3.0 Signal Definitions This chapter defines the sign als and describes th e e xter nal in terface of the AMD Geode™ LX processor . Figure 3-1 shows the pins organized by their functional groupings.
22 AMD Geode™ LX Processors Data Book Signal Definitions 33234H T able 3-1. Video Signal Definitions P er Mode Signal Name CRT w/16-bit VI P RGB w/1 6-bit VIP ARGB (Note 1) w/8-bit VIP TFT w/16-bit .
AMD Geode™ LX Processors Data Book 23 Signal Definitions 33234H 3.1 Buffer T ypes The Ball Assignment tables star ting on page 26 include a column labeled “Buffer T ype”. The details of each buff er type listed in this column are given in T able 3-2.
24 AMD Geode™ LX Processors Data Book Signal Definitions 33234H 3.2 Bootstrap Options The bootstrap options shown in T able 3-3 are suppor ted in the AMD Geode LX processor f or configuring the system. 3.3 Ball Assignments The tables in this chapter use several common abbre via- tions.
AMD Geode™ LX Processors Data Book 25 Signal Definitions 33234H Figure 3-2. BGU481 Ball Assignment Diagr am 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 .
26 AMD Geode™ LX Processors Data Book Signal Definitions 33234H Ball No. Signal Name (Note 1) Ty p e (PD) Buffer Ty p e A1 V SS GND --- A2 V MEM PWR --- A3 V SS GND --- A4 DQ21 I/O DDR A5 V SS GND -.
AMD Geode™ LX Processors Data Book 27 Signal Definitions 33234H H2 V SS GND --- H3 DQS1 I/O DDR H4 SDCLK1N O DDRCLK H28 SDCLK3N O DDRCLK H29 DQM6 I/O DDR H30 V SS GND --- H31 V MEM PWR --- J1 DQ9 I/.
28 AMD Geode™ LX Processors Data Book Signal Definitions 33234H Y2 D A V SS A G ND --- Y3 V IO PWR --- Y4 V SS GND --- Y28 V COR E PWR --- Y29 V SS GND --- Y30 RESET# I PCI Y31 SYSREF I PCI AA1 V A .
AMD Geode™ LX Processors Data Book 29 Signal Definitions 33234H AK4 DRGB14 O (PD) 24/Q5 VOP 9 O AK5 V SS GND --- AK6 DRGB1 O (PD) 24/Q5 VOP 6 O AK7 DRGB4 O (PD) 24/Q5 VOP 3 O AK8 V SS GND --- AK9 DR.
30 AMD Geode™ LX Processors Data Book Signal Definitions 33234H Signal Name Ball No. AD0 AJ19 AD1 AH19 AD2 AL20 AD3 AK20 AD4 AK19 AD5 AH21 AD6 AJ21 AD7 AL19 AD8 AK22 AD9 AL22 AD10 AK23 AD11 AH22 AD1.
AMD Geode™ LX Processors Data Book 31 Signal Definitions 33234H DRGB7 AJ8 DRGB8 AJ2 DRGB9 AK3 DRGB10 AL3 DRGB11 AH5 DRGB12 AJ4 DRGB13 AL4 DRGB14 AK4 DRGB15 AJ5 DRGB16 AF2 DRGB17 AF1 DRGB18 AG3 DRGB1.
32 AMD Geode™ LX Processors Data Book Signal Definitions 33234H VO P 13 A L 3 V OP14 AK3 VO P 15 A J 2 V OP_BLANK AE4 V OPCLK AE1 V OP_HSYNC AE3 V OP_VSYNC AD3 V MEM (T otal of 33) A2, A14, B1, B5, B8, B11, B21.
AMD Geode™ LX Processors Data Book 33 Signal Definitions 33234H 3.4 Signal Descriptions 3.4.1 Sys tem Interfac e Signals Signal Name Ball No. T ype f V Description SYSREF Y31 I 33, 66 MHz 3.3 System Reference . PCI input clock; typical ly 33 or 66 MHz.
34 AMD Geode™ LX Processors Data Book Signal Definitions 33234H TDP AL17 A A nalog N/A Thermal Diode P ositive (TDP). TDP is the positive ter minal of the ther mal diode on the die. The diode is used to do ther mal characteri zation of the device in a system.
AMD Geode™ LX Processors Data Book 35 Signal Definitions 33234H 3.4.3 Memor y Interfa ce Signals (DDR) Signal Name Ball No. Type f V Description SDCLK[5:0]P , SDCLK[5:0]N D20, D21, D23, D24, J28, H28, M28, L28, J4, H4, M4, L4 O up to 200 MHz 2.5 SDRAM Clock Differential P airs.
36 AMD Geode™ LX Processors Data Book Signal Definitions 33234H DQM[7:0] N30, H29, C24, A19, B10, A6, G2, M1 I/O 166-400 Mb/s 2.5 Da ta Mask Control Bits. During memor y read cycles, these outputs control whether the SDRAM output buff e rs are driven on the Mem- or y Data Bus or not.
AMD Geode™ LX Processors Data Book 37 Signal Definitions 33234H 3.4.5 PCI I nterface Signals Signal Name Ball No. Type f V Description AD[31:0] See T able 3-6 on page 30 I/O 33-66 Mb/s 3.3 Multiplexed Address and Data. Addresses and data are multiplex ed together on the same pi ns.
38 AMD Geode™ LX Processors Data Book Signal Definitions 33234H RESET# Y30 I 0-1 Mb/s 3.3 PCI Reset. RESET# abor ts all operations in progress and places the AMD Geode LX proces- sor into a reset state. RESET# f orces the CPU and peripheral functions to begi n e xecuting at a known state .
AMD Geode™ LX Processors Data Book 39 Signal Definitions 33234H DEVSEL# AK25 I/O 33-66 Mb/s 3.3 Device Select. DEVSEL# indicates that the driv- ing device has decoded its addre ss as the target of the current access . As an input, DEVSEL# indicates whether any device on the bus has been selected.
40 AMD Geode™ LX Processors Data Book Signal Definitions 33234H 3.4.6 TF T Display Interf ace Signals Signal Name Ball No. Type f V Description DRGB[31:24] DRGB[23:0] See T able 3-6 on page 30 I/O O (PD) 0-162 Mb/s 3.3 Display Data Bus. DO TCLK AE1 O (PD) 0-162 MHz 3.
AMD Geode™ LX Processors Data Book 41 Signal Definitions 33234H 3.4.7 CRT Display Interface Sign als Signal Name Ball No. Type f V Description HSYNC AE3 I/O 0-350 Mb/s 3.3 (5vt) Horizontal Sync . Horiz ontal Sync es tablishes the line rate and horizontal retrace inter val f or an attached CRT .
42 AMD Geode™ LX Processors Data Book Signal Definitions 33234H F or additional electr ical details on pins, refer to Section 7.0 "Electr ical Specifications" on page 59 7. 3.4.9 P ower a nd Ground Int e rface Signals Signal Name (Note 1) Ball No.
AMD Geode™ LX Processors Data Book 43 Signal Definitions 33234H T able 3-7. Signal Behavior During and Aft er Reset Signal Name T ype Behavior AD[31:0] PCI TRI-ST A TE during RESET# low INT A# PA R .
44 AMD Geode™ LX Processors Data Book Signal Definitions 33234H.
AMD Geode™ LX Processors Data Book 45 4 GeodeLink™ Interface U nit 33234H 4.0 GeodeLink™ Interf ace Unit Many traditional architectures use buses to connect mod- ules together , which usuall y requires unique addressing for each register in ev er y module.
46 AMD Geode™ LX Processors Data Book GeodeLink™ Interface Un it 33234H 4.1.1 P or t Addre ss Each GLIU has sev en channels with Ch annel 0 being the GLIU itself and therefore not considered a p h ysical p or t.
AMD Geode™ LX Processors Data Book 47 GeodeLink™ Interface U nit 33234H 4.1.2 P ort Addressing Exceptions There are some e xceptions to the por t addressing ru les. If a module accesses an MSR fr om within its closest GLIU (e.g., CPU Core accessing a GLIU0 MSR), then, by con- vention, the por t address should be 0.
48 AMD Geode™ LX Processors Data Book GeodeLink™ Interface Un it 33234H Each memor y request is compared against all the P2D descriptors. If the memor y request does not hit in any of the descripto rs, the request is sent to the subtractiv e por t.
AMD Geode™ LX Processors Data Book 49 GeodeLink™ Interface U nit 33234H 4.1.3.2 I/O Routing and T ranslation I/O addresses are routed and are nev er translated . I/O request routing is performed wit h a choice of two descr iptor types. Each GLIU ma y have an y number of each descriptor type.
50 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2 GLIU Regist er Descriptions All GeodeLink™ Interface Unit (GLIU) registers are Model Specific Registers (MSRs) a nd are accessed through the RDMSR and WRMSR instru ctions.
AMD Geode™ LX Processors Data Book 51 GLIU Register Descriptions 33234H GLIU0: 10000089h GLIU1: 40000089h RO SLA VE_O NL Y GLIU0: 00000000_000000 10h GLIU1: 00000000_000001 00h P age 67 GLIU0: 10000.
52 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H GLIU0: 100000C0h GLIU1: 400000C0h R/W Request Compare V alue (RQ_COMP ARE_V AL[0]) 001FFFFF_FFF FFFFFh P age 74 GLIU0: 100000C.
AMD Geode™ LX Processors Data Book 53 GLIU Register Descriptions 33234H GLIU0: 100000DEh GLIU1: 400000DEh R/W Data Compare Mask Low (D A_COMP ARE_MASK_LO[3]) 00000000_0000000 0h P age 78 GLIU0: 100000DFh GLIU1: 400000DFh R/W Data Compare Mask High (D A_COMP ARE_MASK_HI[3]) 00000000_0000000 0h P age 79 T able 4-7 .
54 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H T able 4-10 . GL IU IOD Descript or MSRs Summa ry MSR Address T ype Register Reset V alue Reference GLIU0 100000E0h- 100000E2h.
AMD Geode™ LX Processors Data Book 55 GLIU Register Descriptions 33234H 4.2.1 Standar d GeodeLink™ Device (GLD) MSRs 4.2.1.1 GLD Capabilities MSR (GLD_MSR_CAP) 4.
56 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.1.3 GLD SMI MSR (GLD_MSR_SMI) The flags are set with inter nal condition s. The internal con ditio ns are alwa ys cap abl e of setting the flag, but if the mask is 1, the flagged condition will not trigger the SMI signal.
AMD Geode™ LX Processors Data Book 57 GLIU Register Descriptions 33234H 4.2.1.4 GLD Err or MSR (GLD_MSR_ ERROR) The flags are set with inter nal condition s. The internal con ditio ns are alwa ys cap abl e of setting the flag, but if the mask is 1, the flagged condi tion will not tr igger the ERR signal.
58 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 39 EFLAG7 Request Compar ator Error Flag 0. If high, records that an ERR was generated due to a Request Comparator 0 (RQ_COMP ARE_V AL0, GLIU0 MSR 100000C0h, GLIU1 MSR 400000C0h) e vent.
AMD Geode™ LX Processors Data Book 59 GLIU Register Descriptions 33234H 4.2.1.5 GLD P ower Management MSR (GLD_MSR_PM) 8 EMASK8 Request Comparator Error Mask 1 .
60 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.1.6 GLD Diagnostic MSR (GLD_MSR_DIA G) This register is reser ved for intern al use by AMD and should not be written to . 4.2.2 G LIU Specific Regi sters 4.2.2.1 Coherency (COH) GLD _MSR_PM Bit Descripti ons Bit Name Description 63:4 RSVD Reserved.
AMD Geode™ LX Processors Data Book 61 GLIU Register Descriptions 33234H 4.2.2.2 P or t Active Enable (P AE) P or ts that are not implemente d retur n 00 (RSVD). P or ts that are slav e only retur n 11. Master/Slav e por ts retur n the values as stated.
62 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.2.3 Arbitration (ARB) 4.2.2.4 Asynchr onous SMI (ASMI) ASMI is a condensed version of the por t ASMI signals. The MASK bits can be used to prev ent a device from issuing an ASMI.
AMD Geode™ LX Processors Data Book 63 GLIU Register Descriptions 33234H 4.2.2.5 Asynchron ous ERR (AERR) AERR is a condensed version of the port ERR signal s. The MASK bits can be used to prev ent a de vice from issuing an AERR. If the MASK = 1, the device’ s AERR is disabled.
64 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H AERR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 3 1 3 0.
AMD Geode™ LX Processors Data Book 65 GLIU Register Descriptions 33234H 4.2.2.6 GLIU Ph ysica l Capabilities (PHY_CAP) MSR Address GLIU0: 10000086h GLIU1: 400000 86h Ty p e R / W Reset V alue GL IU0.
66 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.2.7 N Outstanding Response (NOUT_RESP) MSR Address GLIU0: 10000087h GLIU1: 400000 87h Ty p e R O Reset V alue 000 00000_00.
AMD Geode™ LX Processors Data Book 67 GLIU Register Descriptions 33234H 4.2.2.8 N Outstanding Write Data (NOUT_WD A T A) 4.2.2.9 SLA VE_ONL Y MSR Address GLIU0: 10000088h GLIU1: 400000 88h Ty p e R .
68 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.2.10 WHO AM I (WHO AMI) 6 P6_SLA VE_ONL Y P or t 6 Slave Only . (GLIU0 = Not Used; GLIU1 = SB.) If high, indicates that P or t 6 is a slav e por t. If low , P or t 6 is a master/slav e por t.
AMD Geode™ LX Processors Data Book 69 GLIU Register Descriptions 33234H 4.2.2.11 GLIU Slave Disable (GLIU_SL V) The slav e disable registers are av ail able f or the number of por ts on the GLIU .
70 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.2.12 Arbitration2 (ARB2) MSR Address GLIU0: 1000008Dh GLIU1: 400000 8Dh Ty p e R / W Reset V alue 000 00000_00000000h ARB2.
AMD Geode™ LX Processors Data Book 71 GLIU Register Descriptions 33234H 4.2.3 GLIU Statistic and Comparator MSRs 4.2.3.1 Descriptor Statistic Counter (ST A TISTIC_CNT[0:3]) Descript or Statistic Co .
72 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.3.2 Statistic Mask (ST A TISTIC_MASK[0:3] Descriptor Statistic M ask (ST A TISTIC_MASK[0]) Descriptor Statistic Mask (ST A.
AMD Geode™ LX Processors Data Book 73 GLIU Register Descriptions 33234H 4.2.3.3 Statistic Action (ST A TISTIC_A CTION[0:3] Descriptor Statistic A cti on (ST A T ISTIC_A CT ION[0]) Descriptor Statist.
74 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.3.4 Request Compare V a lue (RQ_COMP ARE_V AL[0:3] The RQ Compare V alue and the RQ Compa re Mask enable traps on specific t ransactions . A hit to the RQ Compare i s deter mined by hit = (RQ_IN & RQ_COM P ARE_MASK) == RQ_COMP ARE_V AL).
AMD Geode™ LX Processors Data Book 75 GLIU Register Descriptions 33234H 4.2.3.5 Request Compare Ma sk (RQ_COMP ARE_MASK[0:3] The RQ Compare V alue and the RQ Compa re Mask enable traps on specific t ransactions . A hit to the RQ Compare i s deter mined by hit = (RQ_IN & RQ_COM P ARE_MASK) == RQ_COMP ARE_V AL).
76 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.3.6 D A Compare V alue Lo w (D A_COMP ARE_V AL_LO[0:3 ] The D A Comp are V alue and the D A Compa re Mask enable traps on sp ecific transactions. A hit to the D A Compare is deter- mined by hit = (D A_IN & DA _COMP ARE_MASK) == DA_COM P A RE_V AL).
AMD Geode™ LX Processors Data Book 77 GLIU Register Descriptions 33234H 4.2.3.7 D A Compare V alue High (DA_COMP AR E_V AL_HI[0 :3] The D A Comp are V alue and the D A Compa re Mask enable traps on sp ecific transactions. A hit to the D A Compare is deter- mined by hit = (D A_IN & DA _COMP ARE_MASK) == DA_COM P A RE_V AL).
78 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.3.8 D A Compare Mask Low (DA_COMP ARE_MASK_LO[0:3]) Data Compare Mask Low (D A_COMP ARE_MASK_LO[0]) Data Compare Mask Low .
AMD Geode™ LX Processors Data Book 79 GLIU Register Descriptions 33234H 4.2.3.9 D A Compar e Mask High ( DA_COMP ARE_MASK_HI[0:3]) Data Compare Mask High (D A_COMP ARE_MASK_HI[0]) Data Compare Mask .
80 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.4 P2D Descri ptor Register s P2D descri ptors are ordered P2D_BM, P2D_BMO , P2D_R, P2D_RO , P2D_SC, P2 D_BMK. F or example if NP2D_BM=3 and NP2D_BM0=2, I MSR EO = P2D_BM[0 ], MSR E3 = P2D_SC[0].
AMD Geode™ LX Processors Data Book 81 GLIU Register Descriptions 33234H 4.2.4.2 P2D Base Mask Offset Descriptor (P2D_BMO) See T able 4.1.3.1 "Memor y Routing and T ranslatio n" on page 47 for details on the descrip tor usage.
82 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.4.3 P2D Range Descriptor (P2D_R) See T able 4.1.3.1 "Memor y Routing and T ranslatio n" on page 47 for details on the descrip tor usage.
AMD Geode™ LX Processors Data Book 83 GLIU Register Descriptions 33234H 4.2.4.4 P2D Range Offset Descriptor (P2D_RO) See T able 4.1.3.1 "Memor y Routing and T ranslatio n" on page 47 for details on the descrip tor usage.
84 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.4.5 P2D Swiss Chees e Descriptor (P2D_SC) See T able 4.1.3.1 "Memor y Routing and T ranslatio n" on page 47 for details on the descrip tor usage.
AMD Geode™ LX Processors Data Book 85 GLIU Register Descriptions 33234H 4.2.5 SP ARE MSRs (SP ARE_MSR[0:9], A:F) MSR Address GLIU0: 10000040h-1000004Fh GLIU1: 40000040h-4 000004Fh Ty p e R / W Reset.
86 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.6 I/O Descri ptors I/O descriptors are ordered IOD_BM, IOD_SC. F or exampl e if NIOD_BM = 3 and NIOD_SC = 2, MSR 100000EOh = IOD_BM[0] and MSR 100000E3h = IOD_SC[0]. 4.2.6.1 IOD Base Mask Descriptors (IOD_BM) See T able 4.
AMD Geode™ LX Processors Data Book 87 GLIU Register Descriptions 33234H 4.2.6.2 IOD Swiss Chees e Descriptors (IOD_SC) See T able 4.1.3.1 "Memor y Routing and T ranslatio n" on page 47 for details on the descrip tor usage.
88 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H.
AMD Geode™ LX Processors Data Book 89 5 CPU Core 33234H 5.0 CPU Core This section descr ibes the inter nal o perations of the AMD Geode™ LX processo r’ s CPU Core from a pr ogram- mer’ s point of view . It includes a descr iption of the tradi- tional “core” processing and FPU operations.
90 AMD Geode™ LX Processors Data Book CPU Core 33234H 5.2 Instruction Set Overview The CPU Core instru ction set can be divided into nine types of oper ations: • Arithmetic • Bit Manipulation .
AMD Geode™ LX Processors Data Book 91 CPU Core 33234H 5.3 Application Register Set The Application Register Set c on s i st s of t he r eg i st e r s m os t often used by the applicati ons programmer . Th ese regis- ters are generally accessible, although some bits in th e EFLAGS registers are protected.
92 AMD Geode™ LX Processors Data Book CPU Core 33234H 5.3.1 G eneral Purpose Register s The General Pu rpose registers are divided into f o ur dat a registers, two pointer registers, and two ind e x regi sters as shown in T ab le 5-2 on page 91.
AMD Geode™ LX Processors Data Book 93 CPU Core 33234H 5.3.4 EFLA GS R egister The EFLAGS register contains status information and con- trols cer tain ope rations on the Geode LX processor . Th e lower 16 bits of this register are used when e xecuting 8086 or 80286 code.
94 AMD Geode™ LX Processors Data Book CPU Core 33234H 5.4 System Register Set The Syste m Regist er Se t, sho wn in T able 5-5, consi sts of registers not generally used by application programmers.
AMD Geode™ LX Processors Data Book 95 CPU Core 33234H 5.4.1 Cont rol Regist ers A map of the Control registe rs (CR0, CR1, CR2, CR3, and CR4) is shown in T able 5-6 and the bit descriptions are in the tables th at fo llow . (Thes e registers should not be con- fus ed wi th the C RRn regi sters .
96 AMD Geode™ LX Processors Data Book CPU Core 33234H T able 5-7. CR4 Bit Descriptions Bit Name Description 31:9 RSVD Reserved. Set to 0 (alwa ys retu rns 0 when read). 8P C E Perf or mance Counter Enable. Set PCE = 1 to make RDPMC av ai lable at nonz ero privi- lege lev els.
AMD Geode™ LX Processors Data Book 97 CPU Core 33234H 30 CD Cache Disable/Not Write-Thr ough (Snoop). Cache behavior is based on the CR0 CD and NW bits.
98 AMD Geode™ LX Processors Data Book CPU Core 33234H T able 5-11. Effects of V arious Combi nations of EM, TS, and MP Bi ts CR0[3:1] Instruction T ype TS EM MP W AIT ESC 000 E x e c u t e E x e c u.
AMD Geode™ LX Processors Data Book 99 CPU Core Register Descriptions 33234H 5.5 CPU Core Register Descriptions All CPU Core registe rs are Model Specific Registers (MSRs) and are accessed via the R DMSR and WRMSR instructions. Each module inside the processor is assigned a 256 regis- ter section of the address space.
100 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 00001110h RO IF Sequential Count MRS (IF_SEQCOUNT_MSR) 00000000_000000 00h Page 122 00001140h RO IF Bu ilt-In Self-T est .
AMD Geode™ LX Processors Data Book 101 CPU Core Register Descriptions 33234H 00001335h R/W GS Segment Base/Limit MSR (GS_BASE_MSR) xxxxxxxx_xxxxxxxxh P age 134 00001336h R/W LDT Segment Base/Limit M.
102 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 00001374h R/W Floating P oint Environment Opcode P ointer (FPENV_OP_MSR) 00000000_000000 00h Page 146 00001380h RO Addres.
AMD Geode™ LX Processors Data Book 103 CPU Core Register Descriptions 33234H 00001722h R/W ITB Entry MSR (ITB_ENTR Y_MSR) xxxxxxxx_xxxxxxxxh Page 157 00001723h R/W ITB Entry with Increment MSR (ITB_.
104 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 00001813h R/W Region Configuration Rang e 3 MSR (RCONF3_MSR) 00000000_000000 00h Page 169 W ar m Star t V alue: xxxxx000_.
AMD Geode™ LX Processors Data Book 105 CPU Core Register Descriptions 33234H 00001901h R/W Bus Controller Configuration 1 MSR (BC_CONFIG1_MSR) 00000000_000000 00h Page 184 00001904h RO Reser ved Sta.
106 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 00001A03h R/W FPU Reser ved MSR (FPU_RSVD_MSR) 0000 0000_00000000h P age 202 00001A10h R/W FPU x87 Control Word MSR (FPU_.
AMD Geode™ LX Processors Data Book 107 CPU Core Register Descriptions 33234H 00003000h R/W Standard Lev els and V endor ID String 1 (CPUID0_ MSR) 68747541_000000 01h Page 207 00003001h R/W V endo r .
108 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.1 Standar d GeodeLink™ Device MSRs 5.5.1.1 GLD Capabilities MSR (GLD_MSR_CAP) 5.
AMD Geode™ LX Processors Data Book 109 CPU Core Register Descriptions 33234H 5.5.1.3 GLD SMI MSR (GLD_MSR_SMI) This register is not used in the CPU Core modul e. 5.5.1.4 GLD Err or MSR (GLD_MSR_ ERROR) This register is not used in the CPU Core modul e.
110 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2 CPU Core Specifi c MSRs 5.5.2.1 Time Stamp Counter MSR (TSC_MSR) 5.
AMD Geode™ LX Processors Data Book 111 CPU Core Register Descriptions 33234H 5.5.2.3 P erformance Event Co unter 1 MSR (PERF_CNT1_MSR) MSR Address 000000C2h Ty p e R / W Reset V alue 000 00000_00000.
112 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.4 SYSENTER/SYSEX IT Code Segment Select or MSR (SYS_CS_MSR) SYS_CS_MSR is used by the SYSENTER instruction (fast system call) as the selector of the most pr ivileged code seg- ment.
AMD Geode™ LX Processors Data Book 113 CPU Core Register Descriptions 33234H 5.5.2.5 SYSENTER/SYSEX IT Stack P ointer MSR (SYS_SP_MSR) SYS_SP MSR is used b y the SYSENTER instruction (f ast system call) as the most privileged stack pointer .
114 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.7 P erformance Event Counte r 0 Select MSR (PERF_SEL0_MSR 5.5.2.8 P erformance Event Counte r 1 Select MSR (PERF_SE.
AMD Geode™ LX Processors Data Book 115 CPU Core Register Descriptions 33234H 5.5.2.9 Instruction Fetch Configurati on MSR (IF_CONFIG_MSR) IF_CONFG_MSR controls the operation of the Instr uction Fetch (IF). The Le vel-0 COF cache (Change of Flow (COF) cache), L1 COF cache, return stack, and power saving mode ma y be tur ned on or off.
116 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 28 II_NS Instruction Pipeline (IP) Emp ty Mode . 0: IM Interf ace may m ake requests t o Instruct ion Memor y (IM) when the IP is not empty . (Def ault) 1: IM Interf ac e only makes requests to IM after the IP is empty .
AMD Geode™ LX Processors Data Book 117 CPU Core Register Descriptions 33234H 6S T R O N G Stro ng Prediction. Allow the IF to make strong predictions . 0: Disable. 1: Enable. (Def ault) Note: Enabling strong predictions may improv e perf orm ance. 5 RSVD Reserved.
118 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.10 IF Inv alidate MSR (IF_INV ALID A TE_MSR) IF_INV ALIDA TE MSR ma y be used to inva lidate the contents of the T ag RAMs (L ev el-1 COF cache), Lev el-0 COF cache, and the retur n stack.
AMD Geode™ LX Processors Data Book 119 CPU Core Register Descriptions 33234H 5.5.2.12 IF T est Data MSR (IF_TEST_D A T A_MSR) 12:8 BLOCK Block Identifier . 00h: T arget RAM 0 (W ay 0). (Def ault) 01h: T arget RAM 1 (W ay 0). 02h: T arget RAM 2 (W ay 0).
120 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H IF_TEST_DA T A_MSR Register Map for T ag RAMs 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 4 6 45 44 43 42 41 40 39.
AMD Geode™ LX Processors Data Book 121 CPU Core Register Descriptions 33234H IF_TEST_D A T A_MSR Register Map for Le vel-0 COF Cache Addr ess 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 4 6 4.
122 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.13 IF Sequential Co unt MRS (IF_SEQCOUNT_MSR) IF SEQCOUNT MSR is a read only MSR cont aining the number of sequential instr uct ions ex ecuted sinc e the last change of flow .
AMD Geode™ LX Processors Data Book 123 CPU Core Register Descriptions 33234H 5.5.2.14 IF Built-In Sel f-T est MSR (IF_BIST_MSR) IF_BIST_MSR may be used to run built-in self-test (BIST) on the IF T ag and T a rget RAMs, and to get an indi cation of whether the BIST run passed or failed.
124 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.15 Exception Unit (XC) Co nfiguration MSR (XC_CONFIG_MSR) XC_CONFIG_MSR allows the processor to be configured so that when the proces sor is in it s HAL T state, it can r e quest that its clocks be turned off.
AMD Geode™ LX Processors Data Book 125 CPU Core Register Descriptions 33234H 5.5.2.16 XC Mode MSR (XC_MODE_MSR) XC_MODE_MSR contains information about the current sta tus of the processor .
126 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.17 XC Histor y MSR (XC_HIST_MSR) MSR Address 00001212h Ty p e R O Reset V alue 000 00000_00000000h XC_HIST_MSR Regi.
AMD Geode™ LX Processors Data Book 127 CPU Core Register Descriptions 33234H 5.5.2.18 XC Microcode Address MSR (XC_U ADDR_MSR) 5.5.2.19 ID Configura tio n MSR (ID_CONFIG_MSR) MSR Address 00001213h T.
128 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.20 SMM Contro l MSR (SMM_CTL_MSR) MSR Address 00001301h Ty p e R / W Reset V alue 000 00000_00000000h SMM_CTL_MSR R.
AMD Geode™ LX Processors Data Book 129 CPU Core Register Descriptions 33234H 5.5.2.21 Debug Management Inte rrupt (DMI ) Control Register MSR Address 00001302h Ty p e R / W Reset V alue 0000 0000_00.
130 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.22 T emporar y MSRs T emporary 0 MSR (TEMP0_MSR) T emporary 1 MSR (TEMP1_MSR) T emporary 2 MSR (TEMP2_ MSR) T emporary 3 MSR (TEMP3_ MSR) 1D M I _ G P F DMI Gene ral Protection Faults.
AMD Geode™ LX Processors Data Book 131 CPU Core Register Descriptions 33234H 5.5.2.23 Segment Selector/Flags MSRs The Segment Selector/Flag s MSRs provide access to the segment sele ctor and segment flags par ts o f a segment register . The conten ts of segmen t registers should be accessed us ing MO V or SVDC/ RSDC.
132 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.24 SMM Header MSR (SMM_HDR_MSR) The SMM_HDR_MSR provides access to the address r egister that contro ls w here SMI data is written. 19 X Executable Non-System Segment.
AMD Geode™ LX Processors Data Book 133 CPU Core Register Descriptions 33234H 5.5.2.25 DMM Header MSR (DMM_HDR_ MSR) DMM_HDR_MSR provides access to the address regist er that controls where DMI data is written.
134 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.26 Segment Base/Limit MSRs The segment base/limit MS Rs provi de access to the segment lim it and segment b ase par ts of a segmen t register . The limit value is the true limit; it does not need to be altered based on the limit granularity bit.
AMD Geode™ LX Processors Data Book 135 CPU Core Register Descriptions 33234H 5.5.2.27 Debug Registers 1 and 0 MSR (DR1_DR0_MSR) DR1_DR0_MSR provides access to Debug Register 1 (DR1 ) and Debug Register 0 (DR0). DR0 and DR1 each contain either an I/O por t number or a linear address f or use as a br eakp oint.
136 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.29 Debug Registers 7 and 6 MSR (DR6_DR7_MSR) DR7_DR6_MSR provides access to Debug Register 7 (DR7) and Debug Register 6 (DR6). DR6 contains status information about debug conditions that hav e occu rred.
AMD Geode™ LX Processors Data Book 137 CPU Core Register Descriptions 33234H 5.5.2.30 Extended Debug Registers 1 and 0 MSR (XDR1_XDR0_MSR) XDR1/XDR0_MSR provides access to Exte nded Debug Regist er 1 (XDR1) and Extende d Debug Register 0 (XDR0).
138 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.32 Extended Debug Registers 5 and 4 MSR (XDR5_XDR4_MSR) XDR5/XDR4_MSR provides access to Exte nded Debug Regist er 5 (XDR5) and Extende d Debug Register 4 (XDR4). XDR4 contains an opcode ma tch value .
AMD Geode™ LX Processors Data Book 139 CPU Core Register Descriptions 33234H XDR7_XDR6_MSR Bit Descriptions Bit Name Des cription 63:62 LEN3 Exten ded Breakpoint 3 Le ngth. 61:60 TYPE3 Extended Breakpoint 3 T ype . 59:58 LEN2 Exten ded Breakpoint 2 Le ngth.
140 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.34 Extended Debug Registers 9 and 8 MSR (XDR9_XDR8_MSR) XDR9_XDR8_MSR provides access to Extended Debug Re gister 9 (XDR9) and Extended Debug Register 8 (XDR8). XDR8 contains an opcode match value.
AMD Geode™ LX Processors Data Book 141 CPU Core Register Descriptions 33234H 5.5.2.35 Extended Debug Registers 11 and 10 MSR (XDR11_XDR10_MSR) XDR11_XDR10_MSR provides access to the e xtended I/O breakpoint. 5.5.2.36 EX Stage Instruction Pointer MSR (EX_IP_MSR) EX_IP_MSR provides access to the EX stage instruction pointer (e ffectiv e address).
142 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.37 WB Stage Instructio n Pointer MSR (WB_IP_MSR) WB_IP_MSR provides access to the WB stag e instruction pointer (e ffectiv e addre ss).
AMD Geode™ LX Processors Data Book 143 CPU Core Register Descriptions 33234H 5.5.2.39 WB Stage Line ar Instruction P ointer MSR (WB_LIP_MSR ) WB_LIP_MSR provides access to the WB stage linear instruction pointer.
144 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.41 C3/C2 Linear Instruc tio n P ointer MSR (C3_ C2_LIP_MSR) C3_C2_LIP_MSR provides access to linear instruct ion po inters when the code segment was loaded.
AMD Geode™ LX Processors Data Book 145 CPU Core Register Descriptions 33234H 5.5.2.43 Floating Point Envir onment Instruction Po inter (FPENV_IP_MSR) FPENV_IP_MSR provides access to the floating point (FP) envi ronment instr uction pointer .
146 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.45 Floating Point Envir onm ent Data Pointer (FPENV_DP_MSR) FPENV_DP_MSR p rovid es access to the f loating point (FP) en vironme nt data pointer .
AMD Geode™ LX Processors Data Book 147 CPU Core Register Descriptions 33234H 5.5.2.47 Address Calculation U nit Configuration MSR (A C_ CONFIG_MSR) MSR Address 00001380h Ty p e R O Reset V alue 000 .
148 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.48 Gener al Register MSRs General Regi ster EA X MSR (GR_EAX_MSR) General Regi ster EC X MSR (GR_ECX_MSR) General R.
AMD Geode™ LX Processors Data Book 149 CPU Core Register Descriptions 33234H 5.5.2.49 Extended Flags MSR (EFLA G_MSR) 5.5.2.50 Control Register 0 MSR (CR0_MSR) This is the standard x86 Control Reg ister 0 (CR0). CR1 , CR2, CR3, and CR4 are lo cated at MSRs 00001881h-00001884h (see Section 5.
150 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.51 Instruction Me mory Configuration MSR (IM_CONFIG_MSR) MSR Address 00001700h Ty p e R / W Reset V alue 000 00000_.
AMD Geode™ LX Processors Data Book 151 CPU Core Register Descriptions 33234H 8I C D Instruction Cache Disable. Completely disable L0 and L1 instruction caches. Contents of cache is not modified and no cache entr y is read. 0: Use standard x86 cache ability rules.
152 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.52 Instruction Cache Index MSR (IC_INDEX_MSR) 5.5.2.53 Instruction Cache Data MSR (IC_D A T A_MSR) MSR Address 0000.
AMD Geode™ LX Processors Data Book 153 CPU Core Register Descriptions 33234H 5.5.2.54 Instruction Cache T ag (IC_T A G_MSR) MSR Address 00001712h Ty p e R / W Reset V alue 000 00000_00000000h IC_T A.
154 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.55 Instruction Cache T ag with Increment (IC_T A G_I_MSR) 5.5.2.56 L0 Ins truction Cach e Data MSR (L0_IC_DA T A_MSR) 5.
AMD Geode™ LX Processors Data Book 155 CPU Core Register Descriptions 33234H 5.5.2.58 L1 Ins truction TL B Index (ITB_INDEX_MSR) The L1 Instruction TLB is accessible via an index/data mechanism. The index of the entry to access is se t via ITB_INDEX_MSR and an entr y is read or written via ITB_ ENTRY_MSR or ITB_ENTR Y_I_MSR.
156 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.59 L1 Ins truction TLB Le ast Recently Used MSR (ITB_LR U_MSR) MSR Address 00001721h Ty p e R / W Reset V alue 000 .
AMD Geode™ LX Processors Data Book 157 CPU Core Register Descriptions 33234H 5.5.2.60 L1 Ins truct ion TLB Entr y MSRs ITB Entry MSR (ITB_ENTR Y_MSR) ITB Entry with Incremen t MSR (ITB_ENTR Y_I_MSR).
158 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.61 Instruction Memor y Subsyste m BIST T ag MSR (IM_BIST_T A G_MSR) The Instruction Memor y s ubsystem suppor ts built-in self-test (BIST) f or the tag and data arra ys.
AMD Geode™ LX Processors Data Book 159 CPU Core Register Descriptions 33234H 5.5.2.63 Data Mem ory Subs ystem Configur ation 0 MSR ( DM_CONFIG0_ MSR) MSR Address 00001800h Ty p e R / W Reset V alue .
160 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 32 WBDIS Write Buffer Disable. Disabling the write buff er f orces st ores to be sent directly from th e output of the store queue to the bus controller .
AMD Geode™ LX Processors Data Book 161 CPU Core Register Descriptions 33234H 7 SPCDEC Decreas e Number of Speculative Reads of Data Cache. 0: Actively resync cache tag and data arrays so that loads can be speculatively handled in one clock if the MR U wa y is hit.
162 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.64 Data Mem ory Subs ystem Configur ation 1 MSR ( DM_CONFIG1_ MSR) MSR Address 00001801h Ty p e R / W Reset V alue .
AMD Geode™ LX Processors Data Book 163 CPU Core Register Descriptions 33234H 5.5.2.65 Data Memor y Subsystem Pr efetch Loc k MSR (DM_PFLOCK_MSR) 20 NOPFXEVCT No Prefetch Prefix Evictions.
164 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.66 Default Regi on Configur ation Pr oper ties MSR (RCONF_DEF AU L T_MSR) DM_PFLOCK_MSR Bit Descr iptions Bits Name Description 63:48 PFLOC KT2 Prefetch Lock out of PREFETCHT2.
AMD Geode™ LX Processors Data Book 165 CPU Core Register Descriptions 33234H 5.5.2.67 Region Configuration By pass MSR (RCONF_BYP ASS_MSR) 5.5.2.68 Region Configuration A 0000-BFFFF MSR (RCONF_A0_BF.
166 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.69 Region Configuration C 0000-DFFFF MSR (RCONF_C0_DF_MSR) 5.5.2.70 Region Configuration E 0000-FFFFF MSR (RCONF_E0.
AMD Geode™ LX Processors Data Book 167 CPU Core Register Descriptions 33234H 5.5.2.71 Region Configuratio n SMM MSR (RCONF_SMM_MSR) RCONF_E0_FF_MSR Bit Descript ions Bit Name Description 63:56 RPFC Region Properties for 000FC000-000FFFFF . 55:48 RPF8 Region Properties for 000F8000-000FBFFF .
168 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.72 Region Configuratio n DMM MSR (RCONF_DMM_MSR) MSR Address 0000180Fh Ty p e R / W Reset V alue 000 00001_00000001.
AMD Geode™ LX Processors Data Book 169 CPU Core Register Descriptions 33234H 5.5.2.73 Region Configuratio n Rang e MSRs 0 through 7 Region Configuration Ra ng e 0 MSR (RCONF0_MSR) Region Configurati.
170 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H Region Pr oper ties The region proper ties consist of an 8-bit field a s shown in T able 5-15. T able 5-16 and T able 5-17 describe the various region proper ties effects on read and wri te operations.
AMD Geode™ LX Processors Data Book 171 CPU Core Register Descriptions 33234H If paging is enabled, the region proper ties can be fur ther modified by the PCD and PWT flags in the page table entr y . The PCD flag is OR’ d with the CD bit of th e region proper ties, and the PWT bit is OR’ d with the WT bit of the region prope r ties.
172 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.74 x86 Control Register s MSRs (CR1, CR2, CR3, CR4) These are the standard x86 Con trol Registers CR1, CR2, CR 3, and C R4. CR0 is located at MSR 00001420h (see Se ction 5.
AMD Geode™ LX Processors Data Book 173 CPU Core Register Descriptions 33234H 5.5.2.76 Data Cache Data MSR (DC_DA T A_MSR) 5.5.2.77 Data Cache T ag MSR (DC_T A G_ MSR) MSR Address 00001891h Ty p e R .
174 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.78 Data Cache T ag with Increment MSR (DC_T A G_I_MSR) Bit descriptions for this register are the same as f o r MSR 00001892h, except read/write of th is register causes an auto- increment on DC_IN DEX_MSR (MSR 00001890h).
AMD Geode™ LX Processors Data Book 175 CPU Core Register Descriptions 33234H 5.5.2.79 Data/Instruction Cache Snoop Register (SNOOP_MSR) The SNOOP_MSR provides a mechanism f or injecting a “snoop-f or-write” request in to the memor y subsystem. Both the I and D caches are snooped for the specified physical address.
176 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.81 L1 Da ta TLB Least Recen tly Used MSR (L1DTLB_LRU_MSR) MSR Address 00001899h Ty p e R / W Reset V alue 000 00000.
AMD Geode™ LX Processors Data Book 177 CPU Core Register Descriptions 33234H 5.5.2.82 L1 Da ta TLB Entr y MSR (L1DTLB_ENTR Y_MSR) MSR Address 0000189Ah Ty p e R / W Reset V alue 000 00000_00000000h .
178 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.83 L1 Da ta TLB Entry with In crement MSR (L1DTLB_ENTR Y_I_MSR) Bit descriptions for this register are the same as for MSR 0 000189Ah, e xcept read /write of this register causes an auto- increment on the L1 TLB_INDEX_MSR (MSR 00001898h).
AMD Geode™ LX Processors Data Book 179 CPU Core Register Descriptions 33234H 5.5.2.85 L2 TLB/DTE/PT E Least Recently Used MSR (L2TLB_LRU_MSR) 15:6 RSVD (RO) Reserved (Read Onl y). (Default = 0) 5:0 INDEX DTE/PT E Index. Increments on every access to L2TLB_ENTR Y_I_MSR (MSR 0000189Fh).
180 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.86 L2 TLB/DTE/PTE En try MSR (L2TLB_ENTR Y_MSR) 21:16 PTE_ LR U 4M PTE Least Recently Used V alue. Bit 21: 4M PTE entry 0 more recent than entr y 1. Bit 20: 4M PTE entry 0 more recent than entr y 2.
AMD Geode™ LX Processors Data Book 181 CPU Core Register Descriptions 33234H 7 RSVD (RO) Reserved (Read On ly). 6D I R T Y Dirty Flag. A 1 indicates that the page has be en written to . 5A C C Acc essed Flag. A 1 indicates an entr y in the TLB. 4C D Cache Disable Flag.
182 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.87 L2 TLB/DTE/PTE Entr y with Increment MSR (L2T LB _ENTR Y_I_MSR) Bit descriptions for this register are the same as for MSR 0 000189Eh, e xcept read /write of this register causes an auto- increment on the L2TLB_IN DEX_MSR (MSR 0000189Ch).
AMD Geode™ LX Processors Data Book 183 CPU Core Register Descriptions 33234H 5.5.2.89 Bus C ontr oller Configuration 0 MSR (BC_CONFIG0_MSR) 5 RETEN_TLB L2 TLB Retention Timer . Enable retention timer f or L2 TLB BIST . 0: Disable. 1: Enable . 4 R UN_TLB L2 TLB Run.
184 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.90 Bus C ontr oller Configuration 1 MSR (BC_CONFIG1_MSR) This register is rese rved. Wr ite as read. 19:14 RSVD Reserved. Write as read. 13 CLK_ONS CPU Core Cloc ks On during Suspend.
AMD Geode™ LX Processors Data Book 185 CPU Core Register Descriptions 33234H 5.5.2.91 Reser ved Status MSR (RSVD_STS_MSR) 5.5.2.92 MSR Lock MSR (MSR_LOCK_MSR) MSR Address 00001904h Ty p e R O Reset V alue 000 00000_00000000h RSVD_STS_MSR Bit Descriptions Bit Name Description 63:0 RSVD (RO) Reserved (Read Onl y).
186 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.93 Real Time Stamp Counter MSR (RTSC_MSR) 5.5.2.94 TSC and RTSC Low D WORDs MSR (RTSC_TSC_MSR) MSR Address 00001910.
AMD Geode™ LX Processors Data Book 187 CPU Core Register Descriptions 33234H 5.5.2.95 L2 Ca che Configur ation MSR (L2_CONFIG_MSR) L2_CONFIG_MSR controls the behavior of the L2 cache.
188 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.96 L2 Ca che Status MSR (L2_ST A TUS_MSR) L2_ST A T US_MSR returns the sta tus of the L2 cache controller . 5.5.2.97 L2 Ca che Inde x MSR (L2_INDEX_MSR) L2_INDEX_MSR ha s the L2 cache inde x, the wa y and the data QWORD select for diagnostic accesses.
AMD Geode™ LX Processors Data Book 189 CPU Core Register Descriptions 33234H 5.5.2.98 L2 Ca che Data MSR (L2_D A T A_MSR) L2_D A T A_MSR is used to access the L2 cache data for diagnostic accesses. 5.5.2.99 L2 Cache T ag MSR (L2_T A G_MSR) L2_T AG_MSR has the L2 cache tag, MR U and valid bits f or diagnostic accesses.
190 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.100 L2 Cache T ag with Increment MSR (L2_T A G _I_MSR) The L2_T AG_I_MSR has the auto incremented L2 cache tag, MRU and valid bits f or d iagnostic accesses.
AMD Geode™ LX Processors Data Book 191 CPU Core Register Descriptions 33234H 10 BIST_T AG_GO_ WA Y 3 ( R O ) L2 Cache T ag BIST W ay 3 Result (Read Only). 0: F ail. (D ef au lt) 1: P ass. 9 BIST_T AG_GO_ WA Y 2 ( R O ) L2 Cache T ag BIST W ay 2 Result (Read Only).
192 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.102 L2 Cache T reatme nt Co ntrol MSR (L2_TR TMNT_CTL_MSR) MSR Address 00001927h Ty p e R / W Reset V alue 000 0000.
AMD Geode™ LX Processors Data Book 193 CPU Core Register Descriptions 33234H 5.5.2.103 P ower Mode MSR (PMODE_MSR) This MSR enables some modules to tur n their clocks off when they are idle to sav e power . Most of these bits a re off by default. It is recommended that they be set by BIOS.
194 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.104 Bus Controller Extended Debug Register s 1 and 0 MSR (BXDR1_ BXDR0_MSR) 5.
AMD Geode™ LX Processors Data Book 195 CPU Core Register Descriptions 33234H 5.5.2.106 Bus Controller Extended Debug Register s 6 and 7 MSR (BXDR6_ BXDR7_MSR) BXDR6 (bits [31:0]) contains the status of the e xtended bus controller breakpoints. When a breakpoint occurs, the corre- sponding status bit is set in this register .
196 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 41:40 LEN0 Exten ded Breakpoint 0 Le ngth. Selects the size of e x tende d breakpoint 1. See LEN3 (bits [47:46]) f or decode. 35 E3 Extended Breakpoint 3 Enable. Allows e xten ded breakpoint 3 to be enabled.
AMD Geode™ LX Processors Data Book 197 CPU Core Register Descriptions 33234H 5.5.2.107 Bus Controller Debu g Registers 0 through 3 MSR s Each of these registers specifies an address that must match the p h ysical address curr ently in the bus controller in order to trigge r the breakpoint.
198 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.108 Bus Controller Debug Register 6 MSR (BDR6_MSR) This register contains the stat us of the bus controller breakpoints. When a breakpoint occurs, the corresponding status bit is set in this register .
AMD Geode™ LX Processors Data Book 199 CPU Core Register Descriptions 33234H 31:28 TYPE3 Breakpoi nt 3 T ype. Selects the type of e xtended breakpoint 3. 0000: IM memor y read (Default). 0001: DM memory read. 0010: DM memory wr ite. 0011: DM memory read/write.
200 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.110 Memory Subsystem Ar ray Contr ol Enable MSR (MSS_ARRA Y_CTL_EN_MSR) The MSRs at addresses 00001980h -00001983h provide altern ate arra y delay control v alues fo r the MSS arra ys.
AMD Geode™ LX Processors Data Book 201 CPU Core Register Descriptions 33234H 5.5.2.112 Memory Subsyst em Array Contr ol 1 MSR (MSS_ARRA Y_CTL1_MSR) 5.
202 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.114 FPU Modes MSR (FP_MODE_MSR) 5.5.2.115 FPU Reserved MSR (FPU_RSVD_MSR) This register is reser ved for internal testing; do not write. 5.5.2.116 FPU Reserved MSR (FPU_RSVD_MSR) This register is reser ved for internal testing; do not write.
AMD Geode™ LX Processors Data Book 203 CPU Core Register Descriptions 33234H 5.5.2.117 FPU x87 Control W ord MSR (FPU_CW_MSR) 5.5.2.118 FPU x87 Status W ord MSR (FPU_SW_MSR) 5.
204 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.120 FPU Busy MS R (FPU_BUSY_MSR) 5.5.2.121 FPU Register Map MSR (FPU_MAP_MSR) FPU_TW_MSR Bit Descriptions Bit Name Description 63:16 RSVD Reserved. Write as read. 15:0 FPU_TW FPU T ag W ord.
AMD Geode™ LX Processors Data Book 205 CPU Core Register Descriptions 33234H 5.5.2.122 Mantissa of Rx MSRs Mantissa of R0 MSR (FPU _MR0_MSR) Mantissa of R1 MSR (FPU _MR1_MSR) Mantissa of R2 MSR (FPU.
206 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.123 Exponent of Rx MSRs Exponent of R0 MSR (FPU_ER0_MSR) Exponent of R1 MSR (FPU_ER1_MSR) Exponent of R2 MSR (FPU_E.
AMD Geode™ LX Processors Data Book 207 CPU Core Register Descriptions 33234H 5.5.2.124 FPU Reserved MSRs (FPU_RSVD_MSR) MSR addresses 00001A6 0h through 0000 1A6F are reser ved f or intern al storage pur poses and sh ould not be wr itten to . 5.5.2.
208 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H CPUIDx_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 C.
AMD Geode™ LX Processors Data Book 209 6 Integrated Function s 33234H 6.0 Integr ated Functions The integrated functions of the AMD Geode™ LX proces- sor are: • GeodeLink™ Memor y Controller (.
210 AMD Geode™ LX Processors Data Book GeodeLink™ Memor y Controller 33234H 6.1 GeodeLink™ Memory Controller The GeodeLink™ Memor y Controll er (GLMC) module sup- por ts the Unified Memor y Ar chitecture (UMA) of the AMD Geode™ L X processor and co ntrols a 64-bit DDR SDRAM interface without any e xter nal buffering.
AMD Geode™ LX Processors Data Book 211 GeodeLink™ Memo ry Controller 33234H Features • Suppor ts up to 400 MT/S (millio n transf e rs per second) DDR SDRAMs • Suppor ts 64-b it data interface .
212 AMD Geode™ LX Processors Data Book GeodeLink™ Memor y Controller 33234H A u to Low Order Interleaving The GLMC requires that mo dule banks [0:1], if both installed, be identical an d module banks [2:3], if both installed, be identical. St andard DIMMs and SODIMMs are configured this way .
AMD Geode™ LX Processors Data Book 213 GeodeLink™ Memo ry Controller 33234H T able 6-1. LOI - 2 DIMMs, Same Size, 1 DIMM Bank 1 KB Pa g e Size 2 KB P ag e Size 4 KB P age Siz e 1 KB Page Size 2 K .
214 AMD Geode™ LX Processors Data Book GeodeLink™ Memor y Controller 33234H T able 6-3. Non-A uto LOI - 1 or 2 DIMMs, Differ ent Siz es, 1 DIMM Bank 1 KB Pa g e Size 2 KB Page Size 4 KB P age Size.
AMD Geode™ LX Processors Data Book 215 GeodeLink™ Memo ry Controller 33234H 6.1.1.2 Arbitration The pipelining of the GLMC mod ule requests consists of the GLIU0 interface request plus two request buff ers: the C (closed) and O (open) slots (see Figure 6-7).
216 AMD Geode™ LX Processors Data Book GeodeLink™ Memor y Controller 33234H 6.1.1.3 Data P ath The wri te datapath utilizes three write buff ers to gather write data within a burst, each one is 4 deep x 64 bits. Writes to the buff ers ar e alter nated between the three buff- ers or whichev er one is empty .
AMD Geode™ LX Processors Data Book 217 GeodeLink™ Memo ry Controller 33234H Figure 6-9. DDR Writes mph1 m_sd_data drdyrx rqin_ready dain rqin_take wrx0 wrx1 wrx2 wrx3 drdywx wry0 dain_ready dain_t.
218 AMD Geode™ LX Processors Data Book GeodeLink™ Memor y Controller 33234H 6.1.2 P ower Co ntrol The GLMC em ploys so me methods of power control for power sa vings. One method i s that it TRI-ST A TEs the GLMC address and control pin s when there is no valid address or control data being dr iven (i.
AMD Geode™ LX Processors Data Book 219 GeodeLink™ Memor y Controller Register Descriptions 33234H 6.2 GeodeLink™ Memory Contro ller Register Descriptions All GLMC registe rs are Model Specific Registers (MSRs) and are accessed via the RDMSR and WRMSR instr uc- tions.
220 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Con troller Register Descriptions 33234H 6.2.1 Standar d GeodeLink™ Device (GLD) MSRs 6.2.1.1 GLD Capabilities MSR (GLD_MSR_CAP) 6.2.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG) - Not Used This register is not used in the GLMC module.
AMD Geode™ LX Processors Data Book 221 GeodeLink™ Memor y Controller Register Descriptions 33234H 6.2.1.4 GLD Err or MSR (GLD_MSR_ ERROR) MSR Address 20002003h Ty p e R / W Reset V alue 000 00000_.
222 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Con troller Register Descriptions 33234H 6.2.1.5 GLD P ower Management (GLD_MSR_PM) 6.2.1.6 GLD Diagnostic (GLD_MSR_DIA G) This register is reser ved f or intern al use by AMD and should not be written to .
AMD Geode™ LX Processors Data Book 223 GeodeLink™ Memor y Controller Register Descriptions 33234H 6.2.2 GLMC Spec ific MSRs 6.2.2.1 Ro w Addresses Bank0 DI MM0, Bank1 DIMM0 (MC_CF_BANK01) 6.
224 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Con troller Register Descriptions 33234H 6.2.2.3 Ro w Addresses Bank4 DI MM0, Bank5 DIMM0 (MC_CF_BANK45) 6.
AMD Geode™ LX Processors Data Book 225 GeodeLink™ Memor y Controller Register Descriptions 33234H 6.2.2.5 Ro w Addresses Bank0 DI MM1, Bank1 DIMM0 (MC_CF_BANK89) 6.
226 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Con troller Register Descriptions 33234H 6.2.2.7 Ro w Addresses Bank4 DI MM1, Bank5 DIMM1 (MC_CF_BANKCD) 6.
AMD Geode™ LX Processors Data Book 227 GeodeLink™ Memor y Controller Register Descriptions 33234H 6.2.2.9 Refresh and SDRAM Program (MC_CF07_D A T A) MSR Address 20000018h Ty p e R / W Reset V alu.
228 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Con troller Register Descriptions 33234H 36 D0_CB DIMM0 Component Banks. Number of component banks per module bank for DIMM0. 0: 2 Component banks. (Default) 1: 4 Component banks. 35 RSVD Reserved.
AMD Geode™ LX Processors Data Book 229 GeodeLink™ Memor y Controller Register Descriptions 33234H 6.2.2.10 Timing and Mode Program (MC_CF8F_D A T A) 2 RSVD Reserved. 1S O F T _ R S T Software Re set. Puts the GLMC in a known state. Does not change configuration regi s- ters.
230 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Con troller Register Descriptions 33234H MC_CF8F_D A T A Bit Descriptions Bit Name Description 63:56 ST ALE_REQ GLIU Max Stale Request Count. Non-high priority req uests (PRI = 0) are made high -pri- ority reque sts when the request is not ser viced within ma x stale request count clocks.
AMD Geode™ LX Processors Data Book 231 GeodeLink™ Memor y Controller Register Descriptions 33234H 6.2.2.11 Featur e Enab les (MC_CF1017_D A T A) 11:8 ACT2A CT AC T(0) to A CT(1) P e riod. tRRD . Minimum number of SDRAM cloc ks between A CT and A CT comman d to two diff erent component banks within the same module bank.
232 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Con troller Register Descriptions 33234H 6.2.2.12 Performance Counters (MC_CFPERF_CNT1) 2:0 WR2D A T Write Command T o Data Latency . Number of cloc ks between the write command and the first data beat.
AMD Geode™ LX Processors Data Book 233 GeodeLink™ Memor y Controller Register Descriptions 33234H 6.2.2.13 Counter and CAS Control (MC_PERCNT2) 6.2.
234 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Con troller Register Descriptions 33234H MC_CFCLK_DBUG Bit Descript ions Bit Name Description 63:35 RSVD Reserved. 34 B2B_DIS Back-to-Back Command Disab le. Setting this bit disables the issuing of DRAM com- mands within back-to-back cycles in both MTEST and normal fu nctional mode.
AMD Geode™ LX Processors Data Book 235 GeodeLink™ Memor y Controller Register Descriptions 33234H 6.2.2.15 Page Open Status (MC_CFPG_OPEN) 6.2.2.16 Reser ved Register This register is reser ved and should not be written to .
236 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Con troller Register Descriptions 33234H 6.2.2.17 PM Sensitivity Counters (MC_CF_PMCTR) MSR Address 20000020h Ty p e R / W Reset V alue 000.
AMD Geode™ LX Processors Data Book 237 Graphics Processor 33234H 6.3 Graphics Processor The Graphics Processor is based on the graphics proces- sor used in the AMD Geode™ GX pro cessor with se veral f eatures added to enhance performa nce and functionality .
238 AMD Geode™ LX Processors Data Book Graphics Processor 33234H T able 6-7. Graphics Pr ocessor Feature Comparison Feature AMD Geode™ GX Processor AMD Geode™ LX Processor Color Depth 8, 16, 32-.
AMD Geode™ LX Processors Data Book 239 Graphics Processor 33234H 6.3.1 Command Buffer The AMD Geode LX pr ocessor suppor ts a command buff er interf ace in addition to the nor mal two-deep pipelined regis- ter interf ace. It is advised that software use either the com- mand buff er inte rface or the register interface.
240 AMD Geode™ LX Processors Data Book Graphics Processor 33234H T able 6-9. V ector Command Buffer Struct ure 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W.
AMD Geode™ LX Processors Data Book 241 Graphics Processor 33234H Where: 6.3.2 Channel 3 Channel 3 is an additio nal DMA channel (in addition to the first two channels: source and destination) that can fetch data from memor y or receive it through host source writes.
242 AMD Geode™ LX Processors Data Book Graphics Processor 33234H 6.3.2.1 Rotating BL Ts This feature of the GP allows bitmaps to be rotated 90°, 180° or 270°.
AMD Geode™ LX Processors Data Book 243 Graphics Processor 33234H 6.3.2.4 P alletized Color Suppor t If the Preser ve LUT Data bit is set i n the GP_CH3_MODE_STR register (GP Memor y Offset 64h[20]) then 1K o f the 2K buffer space will be allocated to be a LUT .
244 AMD Geode™ LX Processors Data Book Graphics Processor 33234H 6.3.2.5 Anti-Aliased T ext Support Channel 3 can be setup to fetch 4-bpp alpha channel data that can be combined with either 16 o r 32-bpp color or monochrome source data using th e alpha unit in the GP .
AMD Geode™ LX Processors Data Book 245 Graphics Processor 33234H 6.3.2.8 Channel 3 Host Source Channel 3 also su ppor ts host source data wr ites. When the HS bit is set in the GP_CH3_MODE_STR regis.
246 AMD Geode™ LX Processors Data Book Graphics Processor 33234H 6.3.4 V ector O peration Generating a vector requires a similar setup to a BL T . Reg- isters must be written to spec ify the X and Y.
AMD Geode™ LX Processors Data Book 247 Graphics Processor 33234H 6.3.6.2 Color P atterns Color patter ns are enabled b y selecting the color patter n mode in the GP_RASTER_MODE register (GP Me mor y Offset 38h).
248 AMD Geode™ LX Processors Data Book Graphics Processor 33234H In 16-bpp mode, there is a total of two lin es of patter n, each line with eight pixels as illustrated in T ab le 6-18. In 32-bpp mode, there is only one line of patte rn with eight pixels .
AMD Geode™ LX Processors Data Book 249 Graphics Processor 33234H 6.3.7 8x8 Col or P atterns The new channel 3 hardware provides the capability of per- f or ming BL Ts with 64 pi x el color patter ns at all color depths.
250 AMD Geode™ LX Processors Data Book Graphics Processor 33234H 6.3.8.2 Host Source F or source data that is not already in the frame buff er region of memor y , so ftware can use the GP_HST_SRC register (GP Memor y Offset 48h) for loading the data i nto the Graphics Processor .
AMD Geode™ LX Processors Data Book 251 Graphics Processor 33234H 6.3.8.3 Sour ce Expansion The Graphics Processor contains hardware suppor t for color e xpansion of mo nochrome sour ce data.
252 AMD Geode™ LX Processors Data Book Graphics Processor 33234H 6.3.11 Image Compositing Using Alpha Whereas the raster operation allows different streams of data to be logically combined, alpha ch.
AMD Geode™ LX Processors Data Book 253 Graphics Processor 33234H A ov er B 1 1- α Α Displa y image A on top of image B. Where ver image A is transpar- ent, display image B. 000 10 A in B α B 0 Use image B to mask image A. Wherev er image B is non-trans- parent, display image A.
254 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4 Graphics Processor Register Definitions The registers associa ted with the Graphics Processor (GP) are the Standard GeodeLink™ Device (GLD) MSRs and Graphics Processor Configuration registers.
AMD Geode™ LX Processors Data Book 255 Graphics Processor Register Definitions 33234H 10h R/W Color Config Source Co lor F oreground (GP_SRC_COLOR_FG) 00000000h P age 262 14h R/W Color Config Source.
256 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4.1 Standard GeodeLink™ De vice (GLD) MSRs 6.4.1.1 GLD Capabilities MSR (GLD_MSR_CAP) This MSR contains the revision and de vice IDs f or the par ticu lar implementation of the Graph ics Processor .
AMD Geode™ LX Processors Data Book 257 Graphics Processor Register Definitions 33234H 6.4.1.3 GLD SMI MSR (GLD_MSR_SMI) This MSR contains the SMI and Mask bits for the GP . An SMI is asser t ed whenev er an i llegal address or an i llegal type is detected on the GLIU and the mask bit is not set.
258 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4.1.5 GLD P ower Management MSR (GLD_MSR_PM) This MSR contains the power management controls for the GP . Since there is only one clock domain within the GP , most bits in this register a re unused.
AMD Geode™ LX Processors Data Book 259 Graphics Processor Register Definitions 33234H 6.4.2 Graphics Proc essor Configuration Register s 6.4.2.1 Destination Of fset (GP_DST_ OFFSET) GP_DST_OFFSET is used to give a star ting location for the des tination of a BL T or vector in the destination region of mem- or y .
260 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4.2.3 V ector Erro r (GP_VEC_ERR) This register specifies the axial and di agonal error ter ms us ed by the Bresenham vector algorithm.
AMD Geode™ LX Processors Data Book 261 Graphics Processor Register Definitions 33234H 6.4.2.5 BL T W idth/Heig ht (GP_WID_HEIGHT) This register is used to specify the width and the height of the BL T in pixels. Note that operations that extend bey ond the bounds of the frame buffer space “wrap” into the other end of the frame buffer .
262 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4.2.7 Sour ce Color Foreground (GP_SRC_COLO R_FG) When source data is monoch rome, the contents of this regist.
AMD Geode™ LX Processors Data Book 263 Graphics Processor Register Definitions 33234H 6.4.2.8 Sour ce Color Backgr ound (GP_SRC_COLOR_BG) When source data is monochrome, the contents of this regi st.
264 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4.2.9 P a ttern Color (GP_P A T_COLOR_x) In solid patter n mode, the pattern hardware is disab led and GP_P A T_COLOR_0 is selected as the input to the raster oper- ation.
AMD Geode™ LX Processors Data Book 265 Graphics Processor Register Definitions 33234H 6.4.2.10 Pattern Data (GP_P A T_DA T A_x) In solid patter n mo de, these registers are not used. In monochrome patter n mode, GP_P A T_DA T A_0 and GP_P A T _D A T A_1 comb ine to hold the entire 8x8 patter n (64 bits).
266 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H GP_RASTER_MODE Bit Descriptions Bit Name Description 31:28 BPP/FMT Color Dept h and Format. 0000: 8-bpp , 3:3:2 f ormat. 0100: 16-bpp, 4:4:4:4 f ormat. 0101: 16-bpp, 1:5:5:5 f ormat.
AMD Geode™ LX Processors Data Book 267 Graphics Processor Register Definitions 33234H 6.4.2.12 V e ctor Mode (GP_VECT OR_MODE) Writing to this re gister configures the vector mode and initiates the render ing of the vector .
268 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4.2.13 BL T Mode (GP_BL T_MODE) Writing to this register configu res the BL T mode and initiates t he re ndering of the BL T .
AMD Geode™ LX Processors Data Book 269 Graphics Processor Register Definitions 33234H 6.4.2.14 Status and Reset (GP_BL T_ST A TUS, GP_RESET) This register is us ed to provide softw are with the current st atus of the GP in regards to operations pending and currently e x ecuting.
270 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4.2.16 Base Offset (GP_B ASE_OFFSET) This register is used to define the physical base addresses of the regio ns used f o r all GP read and write operations to mem- or y .
AMD Geode™ LX Processors Data Book 271 Graphics Processor Register Definitions 33234H 6.4.2.18 Command Bo ttom (GP_CMD_ BO T) This register defines the ending address of the co mmand buff er wit hin the command buff er re gion. Bits [23:0] of this register are combined with the CBASE in GLD_MSR_CONFIG (MSR A 0002001h) to form t he 32 bit address.
272 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4.2.20 Command Wr ite (GP_CMD_WRITE) This register points to the next location to be wri tten wit h command buffer data from the processor .
AMD Geode™ LX Processors Data Book 273 Graphics Processor Register Definitions 33234H 6.4.2.22 Stride (GP_CH3_MODE_STR) The GP_ CH3_MODE_STR register has multiple uses.
274 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 29 X X Direction for Fetch. Data is re versed if f etch directi on does not match destination direction. 0: Left to r ight direction. 1: Right to left direction. 28 Y Y Direction for Fetch.
AMD Geode™ LX Processors Data Book 275 Graphics Processor Register Definitions 33234H 6.4.2.23 Width/Heig ht (GP_CH3_WIDHI) This register is used to specify the wi dth and th e height of the bi tmap to be f e tched on channel 3 in pi x els.
276 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4.2.25 LUT Inde x (GP_LUT_INDEX) This register is used to initialize the LUT_INDEX pointer t hat is used for subsequent LUT operations. All LUT accesses are D WORD accesses so only the 9 LSBs of the pointer are used to index into the 2 KB LUT .
AMD Geode™ LX Processors Data Book 277 Graphics Processor Register Definitions 33234H 6.4.2.27 Interrupt Co ntrol (GP_INT_CNTRL) This register is used to co ntrol the inte rru pt signal from the GP . It contains a 16-b it mask and a 16-bit interr upt detect.
278 AMD Geode™ LX Processors Data Book Display Controller 33234H 6.5 Display Contr oller The Display Controller (DC) module retriev es graphics, video , and overlay streams from the frame b uffer , serial- izes the streams, perf or ms any necessar y color loo kups and output formatting, and interfaces to the VP f or dr iving the displa y device.
AMD Geode™ LX Processors Data Book 279 Display Controller 33234H The GUI bloc k, shown in Figure 6-13, provides sophisti- cated graphics functionality suitab l e f or a GUI environment such as Windows ® XP , Windows CE, or Linux ® operating systems.
280 AMD Geode™ LX Processors Data Book Display Controller 33234H The V GA block, shown in Figure 6-14, provides hardware suppor t for a compatib le VGA solution.
AMD Geode™ LX Processors Data Book 281 Display Controller 33234H 6.5.1 GUI Functional Overview 6.5.1.1 Display Mode Su pport The display modes listed in T able 6-32 are suppor ted by the GUI block. 32- and 24-bpp display suppor t is provided across all resolutions.
282 AMD Geode™ LX Processors Data Book Display Controller 33234H 1280 x 1024 8, 16, or 24/32 60 108.000 200 8, 16, or 24/32 70 129.600 200 8, 16, or 24/32 72 133.500 200 8, 16, or 24/32 75 135.000 200 8, 16, or 24/32 85 157.500 200 8, 16, or 24/32 90 172.
AMD Geode™ LX Processors Data Book 283 Display Controller 33234H 6.5.1.2 Display FIFO The DC module incor porates a 512-entr y x 64-bit display FIFO that queues up all disp lay data, including graphics frame buff er data, compressed display b uffer data, cursor and icon overla y da ta, and video overlay YUV data.
284 AMD Geode™ LX Processors Data Book Display Controller 33234H Cursor/Icon Buffer Formats In 2-bpp mode, the cursor buff e r is stored as a linear dis- pla y buff er containing i nterlaced AND and XOR QWORDs (8-byte segments). Each QWORD contains the appropriate mask f or 64 pixels.
AMD Geode™ LX Processors Data Book 285 Display Controller 33234H 6.5.1.4 Display Re fresh Compression T o reduce the system memor y contention caused by the display refresh, the GUI block contains compression and decompression logic for compressing the fr a me bu ff er image in real time as it is sent to the display .
286 AMD Geode™ LX Processors Data Book Display Controller 33234H 6.5.1.9 Video O verlay Support The GUI block also suppor ts a video overla y function. The DC has flexib le addressing capab ility f or YUV 4:2:2 and YUV 4:2:0 display surf aces. Video data is stored in a sepa- rate bu ff er within the off-screen frame buffer .
AMD Geode™ LX Processors Data Book 287 Display Controller 33234H 6.5.1.10 Output Formats Video Output Data Sequ encing The order that vi deo data is transmitted from the DC to th e VP depends on the format of the video data.
288 AMD Geode™ LX Processors Data Book Display Controller 33234H 6.5.4 V GA Block Functional Overvie w The V GA bloc k provides full hardware suppor t for a V GA graphics subsystem. It is comp atib le with the IBM V GA as defined in the IBM Video Sub system T echnical Ref erence manual.
AMD Geode™ LX Processors Data Book 289 Display Controller 33234H 6.5.5.2 Graphi cs Controller The graphics controller mana ges the CPU interaction with video memor y , and contains the vi deo serializers that feed the front end of the attr ibute controller .
290 AMD Geode™ LX Processors Data Book Display Controller 33234H 6.5.5.3 Write Modes There are four write modes suppo r ted by the graphics con- troller (mode 0, 1, 2, and 3). These wr ite modes provide assistance to the CPU when the frame buff er is in a planar graphics f or mat.
AMD Geode™ LX Processors Data Book 291 Display Controller 33234H 6.5.5.4 Read Modes There are two read modes provided to assist the CPU with graphics operations in planar modes. Read mode 0 simply retur ns the frame b uffer data. Read mode 1 allows the CPU to do a single col or compare across eight pix els.
292 AMD Geode™ LX Processors Data Book Display Controller 33234H Figure 6-19. Color Compare Operation 8x4 Input AND Compare Result [7:0] CC3 CC2 CC1 CC0 Memor y Data [31:0] 31:24 23:16 15:8 7:0 Colo.
AMD Geode™ LX Processors Data Book 293 Display Controller 33234H 6.5.6 Graphics Scaler/F ilter The DC incor porate s a 3x5 tap filter to be used for up/ downscaling of the graphics image. In order to suppor t the filter , three lines of buff er ing are also included .
294 AMD Geode™ LX Processors Data Book Display Controller 33234H Figure 6-20. Graphics Filter Bloc k Diagram (Continue d) 2 Pixel Latch x x x + x x x + 2 Pixel Latch H. Coefficient RAM X X X X X + Addresses for H. C oefficient RAM from H Phase Adder The entire structure is r epl icated f or each pixel component (red, green, blue, an d alpha).
AMD Geode™ LX Processors Data Book 295 Display Controller 33234H T o suppor t the flicker filter , the scaling filter then f eeds two additional line buffers . The se buff ers are 1024 pixels wide . The scaling filte r directly feeds a tap of the 3x1-tap flick er filter .
296 AMD Geode™ LX Processors Data Book Display Controller 33234H 6.5.7 Color Key Elimination Additional logic, not shown in the diagrams, i s used to pre- ser ve the color k ey color . This logic, when enabled, adjusts the alpha value f or ea ch filter input pi x el i n which a color ke y match is detected.
AMD Geode™ LX Processors Data Book 297 Display Controller 33234H 6.5.9 Interlaced Modes F or interlaced mode s, the V_A CTIVE and V_TO T AL fields are configured for the odd field. The Ev e n Field V er ti cal Timing registers (DC Me mor y Offsets 0E4h-0EC h) are configured for the corresponding e ven field.
298 AMD Geode™ LX Processors Data Book Display Controller 33234H 6.5.10 Interlaced Timing Examples Figure 6-22 shows how the DC's timing registers are used to control timings for interlaced display modes.
AMD Geode™ LX Processors Data Book 299 Display Controller 33234H T able 6-44 . Tim ing Regist er Settings for Interlaced Modes Timing Set Pa rameter Odd Regi ster Eve n Regist er Fo r m u l a V_Acti.
300 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6 Display Contr oller Register Descriptions This section provides information on the regi sters associ- ated with the Display Controller (DC) (i.
AMD Geode™ LX Processors Data Book 301 Display Contr oller Register Descriptions 33234H 020h R/W DC Video Y Buffer Start Addre ss Offset (DC_VID_Y_ST_OFFSET) xxxxxxxxh Page 323 024h R/W DC Video U B.
302 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 08Ch R/W DC Dir ty/V alid RAM Access (DC_D V_ACCESS) 0000000xh P a ge 340 Graphics Scaling Control Registers 09.
AMD Geode™ LX Processors Data Book 303 Display Contr oller Register Descriptions 33234H T able 6-48. V GA Block Configuration Register Summary DC Memory Offset T ype Regis ter Name Reset V alue Reference 100h R/W V GA Con figuration (V GA_CONFIG) 00000000 h P age 355 104h RO V GA Status (VGA_ST A TUS) 00000000h Page 355 T able 6-49.
304 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H T able 6-50. V GA Block Extend ed Register S ummar y VG A C RT C Index T ype Register Name Reset V alue Re fere.
AMD Geode™ LX Processors Data Book 305 Display Contr oller Register Descriptions 33234H 6.6.1 Standard GeodeLink™ De vice (GLD) Registers (MSRs) 6.
306 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.1.3 GLIU0 Device SMI MSR (GLD_MSR_SMI) MSR Address 80002002h Ty p e R / W Reset V alue 000 00000_00000000h .
AMD Geode™ LX Processors Data Book 307 Display Contr oller Register Descriptions 33234H 40 SEQIOR_SMI Sequencer Registe r Read SMI. Reading a 1 indicates that one or more of the VGA’ s Sequencer registers has been read; wr iting a 1 to this bit clears it.
308 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.1.4 GLD Err or MSR (GLD_MSR_ ERROR) 9G F X I O W _ M S K Graphics Contr oller Re gister Write SMI. When set to 1, disables generation of the SMI that indicates that one or more of the V G A’ s Graphics Controller registers h as been writte n.
AMD Geode™ LX Processors Data Book 309 Display Contr oller Register Descriptions 33234H GLD_MSR_ERROR Bit Descriptions Bit Name Description 63:38 RSVD Res erved. Set to 0. 37 CWD _CHECK_ERR Co nt ro l Word Ch eck E rro r. Reading a 1 indicates that an invalid control word w as read from the Display FIFO , which is indica ti ve of a FIFO underrun.
310 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.1.5 GLD P ower Management MSR (GLD_MSR_PM) 6.6.1.6 GLIU0 De vice Diagno stic MSR (GLD_MSR_DIA G) This register is reser ved for intern al use by AMD and should not be written to .
AMD Geode™ LX Processors Data Book 311 Display Contr oller Register Descriptions 33234H 6.6.2 Display Controller Specific MSRs 6.6.2.1 SP ARE MSR 6.6.
312 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.3 Configuration and Status Register s All DC registers are D WORD accessible only . 6.6.3.1 DC Unloc k (DC_UNLOCK) This register is provided to lock the most cr itical memo r y-ma pped DC registers to prev ent unwanted modification (wr ite operations).
AMD Geode™ LX Processors Data Book 313 Display Contr oller Register Descriptions 33234H DC_UNLOCK Bit Descriptions Bit Name Description 31:16 RSVD Reserved. 15:0 DC_UNLOCK Unlock Code. This register must be writ ten with th e value 4758h in order to write to the protected registers.
314 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.3.2 DC General Config uration (DC_GENERAL_CFG) This register contains general control bits f or the DC .
AMD Geode™ LX Processors Data Book 315 Display Contr oller Register Descriptions 33234H 24 SIGE Signature Enable. Eff ective immedi ately . 0: CRC Signa ture is reset to 000001h and h eld (no capture). 1: CRC Logic captu res the pixel data signature with each pixe l clock beginning with th e next le ading edge of ver tical blank.
316 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 11:8 DFHPSL Display-FIFO High Priority Start Level. This field speci fies the depth of the display FIFO (in multiples of 256 b ytes) at which a high-pr iority request is sent to the memor y controller to fill up the FIFO.
AMD Geode™ LX Processors Data Book 317 Display Contr oller Register Descriptions 33234H 6.6.3.3 DC Displa y Config uration (DC_DISPLA Y_CFG) This register contains config uration bits for co ntrolling the various display functions of the DC.
318 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 9:8 DISP_MODE Displa y Mode . Bits per pix el. 00: 8-bpp (also used in V G A emulation) 01: 16-bpp 10: 24-bpp (RGB 8:8:8) 11: 32-bpp 7 RSVD Reserved. 6T R U P Timi ng Register Update .
AMD Geode™ LX Processors Data Book 319 Display Contr oller Register Descriptions 33234H 6.6.3.4 DC Arbitration Co nfiguration (DC_ARB_CFG) This register contains con figura tion bits f or controlling the pr iority lev el of GLIU req uests by the DC.
320 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 3 HPEN_2LB_INV High Pr iority Enable when Any T wo Line Buffer s Inv alid. This bit enab les the DC to arbitrate at high prio rity if the scaler filter is enabled and any tw o of the three lin e buff ers that feed this filter are inv al id.
AMD Geode™ LX Processors Data Book 321 Display Contr oller Register Descriptions 33234H 6.6.4 Memor y Organization Registers The graphics memor y regio n is up to 16 MB in size.
322 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.4.2 DC Compression Buffer Start Address (DC_CB_ST_OFFSET) This register speci fies the offset at which the compressed displ a y b uffer starts.
AMD Geode™ LX Processors Data Book 323 Display Contr oller Register Descriptions 33234H 6.6.4.4 DC Video Y Buffer Start Addr ess Offset (DC_ VID_Y_ST_OFFSET) This register specifies th e offset at which the video Y (YUV 4:2: 0) or YUV (YUV 4:2:2) buff er star ts .
324 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.4.6 DC Video V Buffer Start Addr ess Offset (DC_ VID_V_ST_OFFSET) This register specifies th e offset at which the video V buff er star ts. Settings written to this register do not take eff ect until th e star t of the f ollowing frame or interlaced field .
AMD Geode™ LX Processors Data Book 325 Display Contr oller Register Descriptions 33234H 6.6.4.8 DC Line Si ze (DC_LINE_SIZE) This register specifies the number of bytes to transf er for a line of frame b uffer , compression buff er , an d video buff er data.
326 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.4.9 DC Graphics Pi tch (DC_GFX_PITCH) This register stores the pitch f or th e graphics displa y buff ers. 6.6.4.10 DC Video YUV Pi tch (DC_VID_YUV_PITCH) This register stores the pitch f or th e video buff ers.
AMD Geode™ LX Processors Data Book 327 Display Contr oller Register Descriptions 33234H 6.6.5 Timing Registers The DC timing registers control the generat ion of sync, blanking, and activ e displa y regions. These registers are generally programmed b y the BIOS from an INT 10h call or b y the extended mode driver from a displa y timing file.
328 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.5.1 DC Horizontal and T ota l Timing (DC_H_A CTIVE_TIMING) This register contains ho rizontal ac tive and t otal timing inf or mation.
AMD Geode™ LX Processors Data Book 329 Display Contr oller Register Descriptions 33234H 6.6.5.2 DC CR T Horizo ntal Blanking Timing (DC_H_BLANK_TIMING) This register contains CRT hori zontal b la nk timing information.
330 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.5.4 DC V ertical and T otal Timing (DC_V_ACTIVE_TIMING) This register contains ver tical active and total timing inf or m ation. The parameters per tain to both CRT and flat panel displa y .
AMD Geode™ LX Processors Data Book 331 Display Contr oller Register Descriptions 33234H 6.6.5.5 DC CR T V ertical Blan k Timing (DC_V_ BLANK_TIMING) This register contains ver tical blank timi ng information. All values are specified in lines. For interlaced display , no border is suppor ted, so blank timing is implied by the total/active timing.
332 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.5.7 DC Frame Buffer Active Region Register (DC_FB_A CTIVE) 6.6.6 Cursor P osition and Line Count/Status Register s The cursor registers contai n pixel coordinate inf or mation for t he cursor .
AMD Geode™ LX Processors Data Book 333 Display Contr oller Register Descriptions 33234H 6.6.6.2 DC Cur sor Y P o sition (DC_CURSOR_Y) This register contains the Y position information of the hardware cursor . Settings written to this register will not take eff ect until the star t of the f ollowi ng frame or interlaced field.
334 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H DC_LINE_CNT/ST A TUS Register Map 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1.
AMD Geode™ LX Processors Data Book 335 Display Contr oller Register Descriptions 33234H 6.6.7 Palett e Access FIFO Diagnostic Regist ers The P alette Acce ss registers are used for accessing the internal palette RAM and e xte nsions.
336 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.7.2 DC P alette Data (DC_P AL_ D A T A) This register contains the dat a f o r a palette access cycle. When a read or write to the palette RAM occurs, the pre vious out- put value is held f or one additional Do t clock period.
AMD Geode™ LX Processors Data Book 337 Display Contr oller Register Descriptions 33234H 6.6.7.4 DC Compression FIFO D iagnostic (DC_CF IFO_DIA G ) This register is provided to en able testability of the compress ed line buff er (FIFO) RAM.
338 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.8 Video Downscalin g 6.6.8.1 DC Video Do wnsca ling Delta (DC_VID_DS_DEL T A) This register is provided to allow downscaling of the vid eo ov er lay image by selective skipping of source lines.
AMD Geode™ LX Processors Data Book 339 Display Contr oller Register Descriptions 33234H 6.6.9 GLIU Control Register s 6.6.9.1 DC GLIU0 Memory Of fset (DC_GLIU0_MEM_OFFSET) This register is used to set a base address for the graphics memo ry regio n.
340 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.9.3 DC Dirty/V alid RAM Access (DC_DV_A CCESS) 11:10 D V_LINE_SIZE DV L in e S i z e . This field determ ines how many b ytes of frame buff e r space correspond to an entry in the D V RAM.
AMD Geode™ LX Processors Data Book 341 Display Contr oller Register Descriptions 33234H 6.6.10 Grap hics Scaling Control Registers 6.6.10.1 DC Graphics Filte r Scale (DC_GFX_SCALE) DC Memor y Offset.
342 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.10.2 DC IRQ/Filte r Co ntrol (DC_IRQ_FIL T_CTL) DC Memor y Offset 094h Ty p e R / W Reset V alue 000 00000h.
AMD Geode™ LX Processors Data Book 343 Display Contr oller Register Descriptions 33234H 6.6.10.3 DC Filter Coef ficient Da ta Register 1 (DC_FIL T_COEFF1) Any read or write of this register causes a read or write of th e horizontal or filter coeffi cient RAM.
344 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.10.4 DC Filter Coef ficient Da ta Register 2 (DC_FIL T_COEFF2) Any read or write of this register causes a read or write of th e horizontal or filter coeffi cient RAM.
AMD Geode™ LX Processors Data Book 345 Display Contr oller Register Descriptions 33234H 6.6.11.2 DC VBI Odd Cont rol (DC_VBI_ODD_ CTL) Settings written to this register do not take eff ect until the sta r t of the f o llowing frame or interlaced field.
346 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.11.4 DC VBI Odd Line Enable (DC_VBI_LN_ODD) Settings written to this register do not take eff ect until the sta r t of the f o llowing frame or interlaced field.
AMD Geode™ LX Processors Data Book 347 Display Contr oller Register Descriptions 33234H 6.6.11.6 DC VBI Pitch and Size (DC_VBI_PITCH) 6.6.12 Color Key Control Registers 6.
348 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.12.2 DC Color Key Mask (DC_CLR_KEY_MASK) 6.6.12.3 DC Color Key Horizont al P osition (DC_CLR_KEY_X) Settings written to this register do not take eff ect until the sta r t of the f o llowing frame or interlaced field.
AMD Geode™ LX Processors Data Book 349 Display Contr oller Register Descriptions 33234H 6.6.12.5 DC Interrupt (DC_IRQ) DC_CLR_KEY_Y Bit Descriptions Bit Name Description 31:27 RSVD Reserved. Set to 0. 26:16 CLR_KEY _Y_ END Color Ke y V ertical End. This field represents the ver tical end position of the color ke y region minus 1.
350 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.13 Interrupt an d GenLoc k Registers 6.6.13.1 DC GenLock Co ntrol (DC_GENLK_CTL) Settings written to this r.
AMD Geode™ LX Processors Data Book 351 Display Contr oller Register Descriptions 33234H 6.6.14 Even Field Video Ad dress Registers 6.6.14.1 DC Even Field Video Y Start Ad dress Offset (DC_VID_EVEN_Y_ST_OFFSET) Settings writte n to this register do not take eff e ct until the sta r t of the ne xt ev en inter laced field.
352 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.14.2 DC Even Field Vide o U Start Address Offset (DC_VID_EVEN_U _ST_OFFSET) Settings writte n to this register do not take eff e ct until the sta r t of the ne xt ev en inter laced field.
AMD Geode™ LX Processors Data Book 353 Display Contr oller Register Descriptions 33234H 6.6.15 Even Field V ertical Timing Registers 6.6.15.1 DC V er tical and T o tal Timing for Even Fiel ds (DC_V_A CTIVE_EVEN_TIMING) This register contains vertical active and total timing inform atio n.
354 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.15.2 DC CRT V ertical Blank Timing for Even Fields (DC_V_BLANK_EVEN_TIMING) This register contains ver tical blank timing informati on. All va lues are specified in lines.
AMD Geode™ LX Processors Data Book 355 Display Contr oller Register Descriptions 33234H 6.6.16 V GA Blo ck Configuration Re gisters 6.6.16.1 V GA Configur ation (V GA_CONFIG) This register controls palette wr ite operations.
356 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.17 V GA Bloc k Standard Regi sters 6.6.17.1 V GA Misc ellaneous Output 2 VBLANK_SMI VBLANK SMI. If = 1, an SMI was generated due to leading edge ver tical blank.
AMD Geode™ LX Processors Data Book 357 Display Contr oller Register Descriptions 33234H 6.6.17.2 V GA Input Status Register 0 6.6.17.3 V GA Input Status Register 1 6.
358 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.18 V GA Se quencer Regi sters The Sequencer register s are accessed by writing an index v a lue to the Sequencer Index register (3C4h) and reading or writing the register using the Sequencer Data regi ster (3C5h).
AMD Geode™ LX Processors Data Book 359 Display Contr oller Register Descriptions 33234H 6.6.18.4 V GA Clocking Mode 6.6.18.5 V GA Ma p Mask These bits enable (bit = 1) writing to their corresponding bytes in each DW ORD of the frame buff er (i.e., EM3 enables b y te 3, EM2 enables b y te 2, etc.
360 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.18.6 V GA Cha racter Map Select Character Map A (bits [5,3 :2]) and Character Map B (bits [4,1:0]) deter mi ne which font tables are used when displa ying a character in text mode.
AMD Geode™ LX Processors Data Book 361 Display Contr oller Register Descriptions 33234H 6.6.19 V GA CRT Contr oller Registers The CRTC registers are accessed by writing an index v a lue to the CRTC Inde x reg ister (3B4h or 3D4h) an d reading or wr it- ing the register using the CRTC Data register (3B5h or 3D5h).
362 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.19.1 CRTC Index T able 6-54. CRTC Registers Summar y Index T ype Regis ter Reset V alue Reference -- R/W CR.
AMD Geode™ LX Processors Data Book 363 Display Contr oller Register Descriptions 33234H 6.6.19.2 CRTC Data 6.6.19.3 Horizonta l T otal 6.6.19.4 Horizonta l Display Enab le End 6.6.19.5 Horizonta l Blank Start Data Address 3B5h or 3D5h Ty p e R / W Reset V alue 00h CRT C Data Regist er Bit Descript ions Bit Name Description 7 RSVD Reserved.
364 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.19.6 Horizon tal Blank End 6.6.19.7 Horizonta l Sync Start 6.6.19.8 Horizonta l Sync End Index 03h Ty p e R / W Reset V alue 00h Horizontal Blan k End Register Bit Descrip tions Bit Name Description 7 RSVD Reserved.
AMD Geode™ LX Processors Data Book 365 Display Contr oller Register Descriptions 33234H 6.6.19.9 V er tical T otal 6.6.19.10 Overflow These are the high-o rder bits for se veral of the vertical prog ramming values. See the description s of the respective v er tical registers for descriptions of these fields.
366 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.19.12 Maximum Scan Line 6.6.19.13 Cursor Start 6:5 BYPE_P AN Byte Panning. This v alue causes the pixel data stream to be f etched zero , one, two , or three character positions early for use with pel panning in the attribute controller .
AMD Geode™ LX Processors Data Book 367 Display Contr oller Register Descriptions 33234H 6.6.19.14 Cursor End 6.6.19.15 Start Address High 6.6.19.16 Start Address Low 6.6.19.17 Cursor Location High Index 0Bh Ty p e R / W Reset V alue 00h Cursor End Re gister Bit Descriptions Bit Name Description 7 RSVD Reserved.
368 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.19.18 Cursor Location Low 6.6.19.19 V er tical Sync Star t 6.6.19.20 V er tical Sync End Index 0Fh Ty p e R / W Reset V alue 00h Cursor Location Low Register Bit Descriptions Bit Name Description 7:0 CURS_LOW Cursor Location Register Bits [7:0].
AMD Geode™ LX Processors Data Book 369 Display Contr oller Register Descriptions 33234H 6.6.19.21 V er tical Di splay Enable End 6.6.19.22 Offset 6.6.
370 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.19.24 V er tical Blank Star t 6.6.19.25 V er tic al Blank End 6.6.19.26 CRTC Mode Contr ol Index 15h Ty p e R / W Reset V alue 00h V ertical Blank Start Register Bit Descriptions Bit Name Description 7:0 V_BL_ST V er tical Blank Start Registe r Bits [7:0].
AMD Geode™ LX Processors Data Book 371 Display Contr oller Register Descriptions 33234H T able 6-55 illustrates the various frame buff er addressing schemes. In the table, MAx represents the frame b uffer memor y address signals, Ax represents the CRTC address counter si gnals, RSx represents row sc an counter output bits.
372 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.19.27 Line Compare 6.6.19.28 CPU Data Latch State 6.6.19.29 Attribute Inde x /Data FF State Index 18h Ty p e R / W Reset V alue 00h Line Compare Regi ster Bit Desc riptions Bit Name Description 7:0 LINE_COMP[7:0] Line Compare Register Bits [7:0].
AMD Geode™ LX Processors Data Book 373 Display Contr oller Register Descriptions 33234H 6.6.19.30 Attribute Inde x State 6.6.20 V GA Graphics Cont roller Registers The graphics controller registers .
374 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.20.2 V GA Gra phics Contro ller Data 6.6.20.3 V GA Se t/Reset Bits [3:0] allow bits in their respectiv e maps to be set or reset through wr ite modes 0 or 3. See Section 6.
AMD Geode™ LX Processors Data Book 375 Display Contr oller Register Descriptions 33234H 6.6.20.5 V GA Color Compare Bits [3:0] specify a compare value that allows the CPU to co mpare pixels in planar modes. Read mode 1 performs a com- parison b ased on these bits combined with the Co lor Don’t Care bits.
376 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.20.7 V GA Read Map Select 6.6.20.8 V GA Gra phics Mode Index 04h Ty p e R / W Reset V alue xxh V GA Read Map Select Regi ster Bit Descriptions Bit Name Description 7:2 RSVD Reserved.
AMD Geode™ LX Processors Data Book 377 Display Contr oller Register Descriptions 33234H 6.6.20.9 V GA Misc ellaneous 1:0 WR_MD Wr ite Mode. This field specifies how CPU data is written to the frame b uffer .
378 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.20.10 V GA Color Don’t Care 6.6.20.11 V GA Bit Mask 6.6.
AMD Geode™ LX Processors Data Book 379 Display Contr oller Register Descriptions 33234H 6.6.21.1 Attribute Contr oller Index/Data The attribute control ler registers do not have a separate addr ess for wr iting index and data inf or mation. Instead, an inter nal flip-flop alter nates between index and data registers.
380 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.21.3 Attribute Mode Control 6.6.21.4 Overscan Color Index 10h Ty p e R / W Reset V alue xxh Attrib ute Mode Control Register Bit Descriptions Bit Name Description 7 P5:4_SEL P5:4 Select.
AMD Geode™ LX Processors Data Book 381 Display Contr oller Register Descriptions 33234H 6.6.21.5 Color Plane Enable 6.6.21.6 Horizontal Pel P ann ing Index 12h Ty p e R / W Reset V alue xxh Color Plane En able Re gister Bit Descr iptions Bit Name Description 7:4 RSVD Reserved.
382 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.21.7 Color Sele ct 6.6.22 Vide o D AC Registers Video D AC palette registers are accessed by writing the Pa.
AMD Geode™ LX Processors Data Book 383 Display Contr oller Register Descriptions 33234H 6.6.22.1 Video DA C Palette Address 6.6.22.2 Video DA C State 6.
384 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.22.4 Video DA C Palette Mask 6.6.23 V GA Bloc k Extended Registers The Extended registers are accessed by writing an index v al ue to the CRTC Index register (3B4h or 3D4h) and reading or writing the register using th e CR TC Data re gister (3B5h or 3D 5h).
AMD Geode™ LX Processors Data Book 385 Display Contr oller Register Descriptions 33234H 6.6.23.1 Extende dRegisterLock 6.6.23.2 Extende dModeControl 6.6.23.3 ExtendedStar tAddress CRTC Inde x 030h Ty p e R / W Reset V al ue FFh ExtendedRegisterLoc k Register Bit Description s Bit Name Description 7:0 LOCK Lock.
386 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.23.4 WriteMemor yAperture 6.6.23.5 ReadMemor yAperture 6.6.
AMD Geode™ LX Processors Data Book 387 Display Contr oller Register Descriptions 33234H 6.6.23.7 BlinkCounter This register is for simulation and test only . 6.6.23.8 V GALa tchSa vRe s 6.6.23.9 DA CIFSavRes CRTC Inde x 061h Ty p e R O Reset V alue 00h BlinkCounter Register Bit Descriptions Bit Name Description 7:5 RSVD Reserved.
388 AMD Geode™ LX Processors Data Book Video Processor 33234H 6.7 Video Processor The Video Processor (VP) module provides a high-perfor- mance, low-po wer CRT/TFT disp la y or video output inter- f ace. There are three ma in functions co ntained withi n the VP: the Video Processor , the TFT controller, and the video output por t (VOP).
AMD Geode™ LX Processors Data Book 389 Video Processor 33234H Figure 6-23. Video Process or Bloc k Diagram Video Data Interf ace (YUV) Control Registers Interf ace Graphics Data Interf ace (RGB) Vid.
390 AMD Geode™ LX Processors Data Book Video Processor 33234H 6.7.2 Functional Description The VP receives the input video stream in either YUV (4:2:2 or 4:2:0) or RGB (5:6:5) format. The VP has an inte- grated color space conv er ter to convert YUV d ata to RGB data.
AMD Geode™ LX Processors Data Book 391 Video Processor 33234H 6.7.2.1 Video Formatter The Video Processor mo dule accepts video d ata at a rate asynchronous to the GLIU clock rate . The byte order of video input data can be configured using the VID_FMT bits in the Video Configuration register (VP Memor y Offset 000h[3:2]).
392 AMD Geode™ LX Processors Data Book Video Processor 33234H 6.7.2.3 Horizontal Downscaling The Video Processor module suppor ts horizontal down- scaling (see Figure 6-25). Th e downscaler can be imple- mented in the Video Processor module to shrink the video windo w by a f actor of up to 8: 1, in one-pix el increments .
AMD Geode™ LX Processors Data Book 393 Video Processor 33234H 6.7.3 X and Y Upscaler After the video data has been buff e red, the upscaling algo- rithm is applied. The Vi deo Processor module employs a Digital Differential Analyzer-style (DD A) algor ithm for both horizontal and ver tical upscaling.
394 AMD Geode™ LX Processors Data Book Video Processor 33234H 6.7.5 Video Overla y Video data is mixed with gr aphics data accordi ng to the video window position. The video win dow position is pro- grammab le via the Video X P ositi on (VP Memor y Offset 010h) and Video Y P o sition (VP Memor y Offset 018h) reg- isters.
AMD Geode™ LX Processors Data Book 395 Video Processor 33234H Figure 6-27 . Mi xer Block Diagram CSC_VIDEO Video YUV Graphics GV_P AL_BP RGB/YUV VSYNC Current Pix el Color K ey and Blending Logic P .
396 AMD Geode™ LX Processors Data Book Video Processor 33234H Figure 6-28. Color Key and Alpha-Blending Logic No Ye s Ye s No Ye s No No Ye s No Ye s Notes: 1) V G_CK: Video/Graphics color ke y select (VP Memor y Offset 008h[20]). Selects whether graphic data is used f or color ke yin g or video data is used for chroma k eying.
AMD Geode™ LX Processors Data Book 397 Video Processor 33234H T able 6-60 represents the same logic that is display ed in Fig ure 6-28 on page 396. 6.7.5.2 Gamma RAM Either the graphics or video stream can be routed through an integrated palette RAM f or gamma-correction of the data stream or (f or video data) contrast/brightn ess adjust- ments.
398 AMD Geode™ LX Processors Data Book Video Processor 33234H 6.7.6 Video Output P or t 6.7.6.1 Functio nal Over view The Video Output P or t (VOP) receiv es YUV 4:4:4 encoded data from the VP and formats t he data into a video-stream that is BT .656) or BT .
AMD Geode™ LX Processors Data Book 399 Video Processor 33234H 6.7.6.3 HBLANK and VBLANK Signals HBLANK and VBLANK signals are different from HSYNC and VSYNC. The HSYNC and VSYNC signals are only active f or a por tion of the blanking time, while the HBLANK and VBLANK signals are active through the en tire time.
400 AMD Geode™ LX Processors Data Book Video Processor 33234H Figure 6-32. HBLANK and VBLANK for Lines 263, 525 Figure 6-33. HBLANK and VBLANK for Lines 1- 18, 264-281 Figure 6-34.
AMD Geode™ LX Processors Data Book 401 Video Processor 33234H 6.7.6.4 Interface to Video Pr ocessor The output from the Video Processor is connected via a 24-bit bus.
402 AMD Geode™ LX Processors Data Book Video Processor 33234H 6.7.6.5 Operating Modes BT .656 Mode BT .656 is the basic standard that specifies the encoding of the control lines into the data bus. In this mode the sepa- rate control lines are encoded into the data bus as speci- fied by Recommendation ITU-R BT .
AMD Geode™ LX Processors Data Book 403 Video Processor 33234H VIP 2.0 Modes (8 or 16 bits) VIP 2.0 mode builds on VIP 1.1 with the following changes/ additions: — Video Flags T , F , and V are v alid in the EA V and SA V code, valid values must appear no later then the SA V of the first scan line of the ne xt active region (see Figure 6-35).
404 AMD Geode™ LX Processors Data Book Video Processor 33234H 6.7.6.6 New VIP 2.0 Video Flags F our bits are defin ed (shown in T able 6-64) b y the VIP specification that allow the VIP slave to comm un icate field/ frame-specific informati on to the graphics chip during th e video stream output.
AMD Geode™ LX Processors Data Book 405 Video Processor 33234H 6.7.7 Flat Panel Display Controller 6.7.7.1 FP Functional Overview The flat panel (FP) display controller conv er ts the digital RGB output of the Video Mixer b lock to digital output suit- able f or dr iving a TFT flat panel LCD .
406 AMD Geode™ LX Processors Data Book Video Processor 33234H 6.7.7.3 FP Functional Description The FP connects to the RGB por t of the video mixer . LCD Interface The FP interfaces directly to industry stand ard 18-bit or 24- bit activ e matr ix thin-film-tran sistor (TFT).
AMD Geode™ LX Processors Data Book 407 Video Processor 33234H Maximum Frequency The FP will operate at a DO TCLK frequency of up to 170 MHz. There is no minimum frequency; howe ver , many flat panels hav e signal ti mings that require minimum frequen- cies.
408 AMD Geode™ LX Processors Data Book Video Processor 33234H Figure 6-37. Dithered 8x8 Pix e l P attern All discussions to this point hav e referred to a 6-bit dither- ing scheme.
AMD Geode™ LX Processors Data Book 409 Video Processor 33234H Figure 6-38. N-Bit Dithering P attern Sch e mes 15 13 14 12 000 001 010 011 100 111 101 110 000 001 010 011 100 111 101 110 75 31 11 9 4.
410 AMD Geode™ LX Processors Data Book Video Processor 33234H CRC Signature The FP contains hardware/logic that performs Cyclical Redundancy Checks (CRCs) on the panel data digital pipe- line. This feature is used f or error detecti on and makes it possible to capture a unique 24- or 32-bit signature f or any given mode setup .
AMD Geode™ LX Processors Data Book 411 Video Processor 33234H 6.7.8 VP Resolu tion T able Suppor ted CRT and flat panel resolutions of the VP are provided in T able 6-32 on page 281. All resolutions can be up to 8 bits per color , or 2 4 bits per pixel.
412 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8 Video Processor Re gister Descriptions This section provides information on the regi sters associ- ated with t.
AMD Geode™ LX Processors Data Book 413 Video Processor Register Descriptions 33234H 050h R/W Miscellaneous (MISC) 00000000_ 00000C00h Page 430 058h R/W CRT Cloc k Sele ct (CCS) 00000000_00 000000h P.
414 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H Flat Panel 400h R/W Panel Timing Register 1 (PT1) 0000 0000_00000000h P a ge 451 408h R/W Panel Timing Register 2 .
AMD Geode™ LX Processors Data Book 415 Video Processor Register Descriptions 33234H 6.8.1 Standard GeodeLink™ De vice MSRs 6.8.1.1 GLD Capabilities MSR (GLD_MSR_CAP) 6.
416 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 15 FPC Simultaneous Flat P anel (or V OP) and CRT . Pri mar y displa y is fl at panel. Setting this bit activates the CR T D AC interf ac e to allow simultaneous displa y of both pane l and CRT .
AMD Geode™ LX Processors Data Book 417 Video Processor Register Descriptions 33234H 6.8.1.3 GLD SMI MSR (GLD_MSR_SMI) The Video Processo r does not produce SMI interrupts, therefore this register is not used.
418 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.1.5 GLD P ower Management MSR (GLD_MSR_PM) 6.8.1.6 GLD Diagnostic MSR (GLD_MSR_DIA G) This register is reser ved for intern al use by AMD and should not be written to .
AMD Geode™ LX Processors Data Book 419 Video Processor Register Descriptions 33234H 6.8.2 Video Processor Module Specific MSRs 6.8.2.1 VP Diag nostic MSR (MSR_DIA G_VP) MSR Address 48002010h Ty p e .
420 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.2.2 P ad Select MSR (MSR_P ADSEL) MSR Address 48002011h Ty p e R / W Reset V alue 000 00000_00000000h MSR_P AD.
AMD Geode™ LX Processors Data Book 421 Video Processor Register Descriptions 33234H 6.8.3 Video Processo r Module C ontr ol/Configuration Register s 6.
422 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.2 Display Configuratio n (DCFG) 5 SC_BYP Scaler Bypass. Bypass scaling math functi ons. Should only be used f o r non-scaled video outputs. Scale f actors set to 10000h.
AMD Geode™ LX Processors Data Book 423 Video Processor Register Descriptions 33234H DCFG Bit Descriptions Bit Name Description 63:32 RSVD (RO) Reserved (Read Only). Reads back as 0. 31:28 SP Spa res. Bits are read/write, but hav e no function. 27 RSVD (RO) Reserved (Rea d Only).
424 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.3 Video X P osition (VX) 2 VSYNC_EN CRT V ertical Sync Enable. Enables/disab les CR T vertical sync (used for VESA DPMS suppor t). 0: Disable. 1: Enable. 1 HSYNC_EN CRT Horizontal Sync Enab le .
AMD Geode™ LX Processors Data Book 425 Video Processor Register Descriptions 33234H 6.8.3.4 Video Y P osition (VY) 6.8.3.5 Video Scale (SCL) VP Memor y Offset 018h Ty p e R / W Reset V alue 000 0000.
426 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.6 Video Color Ke y Register (VCK) 30 GB (RO) GLIU Behind (Read Only). This bit set indicates the GLIU line buff er fill is falling behind the Dot displa y . This bit clears on read.
AMD Geode™ LX Processors Data Book 427 Video Processor Register Descriptions 33234H 6.8.3.7 Video Co lor Mask (VCM) 23:0 VID_CLR_KEY Video Color Ke y .
428 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.8 P alette Address (P AR) 6.8.3.9 P alette Data (PDR) VP Memor y Offset 038h Ty p e R / W Reset V alue 000 0.
AMD Geode™ LX Processors Data Book 429 Video Processor Register Descriptions 33234H 6.8.3.10 Saturation Scale (SLR) VP Memor y Offset 048h Ty p e R / W Reset V alue 000 00000_00000000h SLR Register .
430 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.11 Miscella neous (MISC) VP Memor y Offset 050h Ty p e R / W Reset V alue 000 00000_00000C00h MISC Register .
AMD Geode™ LX Processors Data Book 431 Video Processor Register Descriptions 33234H 6.8.3.12 CRT Cloc k Select (CCS) This register is made up of read only reser v ed bits and spare bits w ith no functi ons.
432 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.15 Video Downscaler Control (VDC) VXS Bit Descriptions Bit Name Description 63:32 RSVD (RO) Reserved (Read Only). Reads back as 0. 31:20 X_ACC_INIT X Accumulator Initial V alue .
AMD Geode™ LX Processors Data Book 433 Video Processor Register Descriptions 33234H 6.8.3.16 CRC Signature (CRC) VP Memor y Offset 088h Ty p e R / W Reset V alue 000 00000_00000000h CRC Register Map.
434 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.17 32-Bit CRC Signature (CRC32) 6.8.3.18 Video De-Interlacing and Alpha Control (VDE) VP Memor y Offset 090h.
AMD Geode™ LX Processors Data Book 435 Video Processor Register Descriptions 33234H 17:16 A1P Alpha Window 1 Priority . Indicates the prio rity of alpha wind ow 1. A higher number indi- cates a higher prior ity . Prior ity is used to deter mine display order f or overlapping alpha windows.
436 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.19 Cursor Color Key (CCK) 8G F X _ I N S _ VIDEO Graphics Wind ow inside Video Window . 0: Disable . The video window is assumed to be inside the graphics window .
AMD Geode™ LX Processors Data Book 437 Video Processor Register Descriptions 33234H 6.8.3.20 Cursor Co lor Mask (CCM) 6.8.3.21 Cursor Color 1 (CC1) VP Memor y Offset 0A8h Ty p e R / W Reset V alue 0.
438 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.22 Cursor Color 2 (CC2) 6.8.3.23 Alpha Window 1 X P osition (A1X) VP Memor y Offset 0B8h Ty p e R / W Reset .
AMD Geode™ LX Processors Data Book 439 Video Processor Register Descriptions 33234H 6.8.3.24 Alpha Window 1 Y P osition (A1Y) 6.8.3.25 Alph a Window 1 Color (A1C) VP Memor y Offset 0C8h Ty p e R / W.
440 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.26 Alpha Wi ndow 1 Control (A1T) A1C Bit Descriptions Bit Name Description 63:25 RSVD (RO) Reserved (Read Only). Reads back as 0. 24 ALPHA1_ COLOR_REG_ EN Alpha Window 1 Color Register Enable.
AMD Geode™ LX Processors Data Book 441 Video Processor Register Descriptions 33234H 6.8.3.27 Alpha Window 2 X P osition (A2X) A1T Bit Descriptions Bit Name Description 63:19 RSVD (RO) Reserved (Read Only). Reads back as 0. 18 PP A1_EN P er-Pixel Al pha Windo w 1 Enable.
442 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.28 Alpha Window 2 Y P osition (A2Y) 6.8.3.29 Alph a Window 2 Color (A C2) VP Memor y Offset 0E8h Ty p e R / .
AMD Geode™ LX Processors Data Book 443 Video Processor Register Descriptions 33234H 6.8.3.30 Alpha Wi ndow 2 Control (A2T) A2C Bit Descriptions Bit Name Description 63:25 RSVD (RO) Reserved (Read Only). Reads back as 0. 24 ALPHA2_ COLOR_REG_ EN Alpha Window 2 Color Register Enable.
444 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.31 Alpha Window 3 X P osition (A3X) 16 ALPHA2_WIN_ EN Alpha Window 2 En able. Enable bit for alpha window 2. 0: Disable alpha window 2. 1: Enable alpha window 2.
AMD Geode™ LX Processors Data Book 445 Video Processor Register Descriptions 33234H 6.8.3.32 Alpha Window 3 Y P osition (A3Y) 6.8.3.33 Alph a Window 3 Color (A3C) VP Memor y Offset 108h Ty p e R / W.
446 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.34 Alpha Wi ndow 3 Control (A3T) A3C Bit Descriptions Bit Name Description 63:25 RSVD (RO) Reserved (Read Only). Reads back as 0. 24 ALPHA3_ COLOR_REG_ EN Alpha Window 3 Color Register Enable.
AMD Geode™ LX Processors Data Book 447 Video Processor Register Descriptions 33234H 6.8.3.35 Video Request (VRR) 16 ALPHA3_WIN_ EN Alpha Window 3 En able. Enable bit for alpha window 3. 0: Disable alpha window 3. 1: Enable alpha window 3. 15:8 ALPHA3_INC Alpha Windo w 3 Increment.
448 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.36 Alpha Watc h (A WT) Alpha values ma y b e automatically incr emented/decrem ented f or successiv e frames. T his register can be used to read alpha values that are being used in the current frame.
AMD Geode™ LX Processors Data Book 449 Video Processor Register Descriptions 33234H 6.8.3.38 Even Video Y P osition (VYE) 6.8.3.39 Even Alpha W indow 1 Y P osition (A1YE) VP Memor y Offset 138h Ty p.
450 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.40 Even Alpha W indow 2 Y P osition (A2YE) 6.8.3.41 Even Alpha W indow 3 Y P osition (A3YE) VP Memor y Offse.
AMD Geode™ LX Processors Data Book 451 Video Processor Register Descriptions 33234H 6.8.3.42 Video Coefficient RAM (VCR) 6.8.3.43 Panel Timing Register 1 (PT1) VP Memor y Offset 1000h-1FFFh Ty p e R.
452 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 29 FP_HSYNC_ POL FP_HSYNC Input P olarity . Selects p ositive or negativ e po larity of th e FP_HSYNC input. Program t his bit to match the polarity of the incoming FP_HSYNC signal.
AMD Geode™ LX Processors Data Book 453 Video Processor Register Descriptions 33234H 6.8.3.44 Panel Timing Register 2 (PT2) VP Memor y Offset 408h Ty p e R / W Reset V alue 000 00000_00000000h PT2 Re.
454 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.45 Po wer Management (PM) 19 MCS Colo r/Mono Select. Selects color or monochrome LCD panel. 0: Color . 1: Monochrome. 18:16 PIXF Pixe l Output Format . These bits define the pixel output f or mat.
AMD Geode™ LX Processors Data Book 455 Video Processor Register Descriptions 33234H 25 D Display Off Control Sour ce . Selects how DISPEN is controlled. Independent contro l ma y be used to disable the bac k light to sav e power e ven if the panel is otherwise ON.
456 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.46 Dither a nd Frame Rate Control (DFC) VP Memor y Offset 418h Ty p e R / W Reset V alue 000 00000_00000000h.
AMD Geode™ LX Processors Data Book 457 Video Processor Register Descriptions 33234H 6.8.3.47 Dither RA M Control and Address (DCA) 0D E N B Dithering Enable . Enable/disable dithering. The dither bit must be enabled in order for dither RAM reads or writes to occur .
458 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.48 Dither Memor y Data (DMD) 6.8.3.49 Panel CRC Signature (CRC) VP Memor y Offset 450h Ty p e R / W Reset V .
AMD Geode™ LX Processors Data Book 459 Video Processor Register Descriptions 33234H 6.8.3.50 32-Bit Panel CRC (CRC32) 6.8.3.51 Video Output Port Configuration (V OP_CONFIG ) VP Memor y Offset 468h T.
460 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 18 INV VS POL Invert VSYNC Polarity . Set to 1 to inv er t polar ity of VSYNC (for 6 01 mode only). 17 INV HS POL In ver t HSYNC Polarity . Set to 1 to inv er t polar ity of HSYNC (for 601 mode only).
AMD Geode™ LX Processors Data Book 461 Video Processor Register Descriptions 33234H 6.8.3.52 Video Output Po rt Signature (V OP_ SIG) 6 SC120X_MODE SC120X Compatible Mode . Creates EA V/SA V codes consistent with the AMD Geode™ SC1200 and SC1201 processor’ s VOP .
462 AMD Geode™ LX Processors Data Book Video Input Port 33234H 6.9 Video Input P or t 6.9.1 Featu res • VESA 1.1, 2.0 and BT .601, BT .656 compliant, 150 MHz (e xcl udes host interf ace). — Standard 9 or 17 pin interf ace (8/16 data + clock) — 8/16-bit BT .
AMD Geode™ LX Processors Data Book 463 Video Inpu t P or t 33234H 6.9.2 VIP Block Desc riptions Figure 6-39. VIP Block Diagra m 8/16 Address address F ormatter Generator Memor y Registers VIP Data V.
464 AMD Geode™ LX Processors Data Book Video Input Port 33234H 6.9.2.1 Input Formatter The Input Formatter rece ives 8- or 16-bit VIP input data, It does a 4:2:2 to 4:2:0 translation (if enabled) and f or mats it into either linear data or planar data for storage in the Cap- ture RAM.
AMD Geode™ LX Processors Data Book 465 Video Inpu t P or t 33234H 6.9.3 Functi onal Descript ion The Video Input Po r t (VIP) receives 8- or 16-bit video or ancillar y data, 8-bit message data, or 8-bit raw video , and passes it to data buff ers lo cated in system memor y .
466 AMD Geode™ LX Processors Data Book Video Input Port 33234H 6.9.5 Mode 1a,b,c - VI P Input Data (simplified BT .656) The VIP 2.0 specific ation descri bes an 8- or 16-bit data stream incor porating both con trol and data. The data/co n- trol is delivered in pack e ts.
AMD Geode™ LX Processors Data Book 467 Video Inpu t P or t 33234H VIP 2.0 Video Flags T wo new video flags are defined in the VIP 2.0 specification to decode whether the input video is interlaced or noninter- laced and whether the data i s merely a repeated field.
468 AMD Geode™ LX Processors Data Book Video Input Port 33234H Figure 6-41. 525 line, 60 Hz D igital V er tical Timing Line 1 (V = 1) Line 20(V = 0) Line 264 (V = 1) Line 283 (V = 0) Line 525 (V = 0.
AMD Geode™ LX Processors Data Book 469 Video Inpu t P or t 33234H 6.9.5.2 Ancillary P ackets Ancillar y pack e ts are receiv ed during ver tical and/or hor i- zontal b l anking. The ancillar y pack e t has a 6-byte header of 00-FF-FF-DID-SDID-NN. T he first three bytes are the pre-amble .
470 AMD Geode™ LX Processors Data Book Video Input Port 33234H 6.9.6 Messag e P assing Mod e The Message Passing mode (MSG) allows an e xter nal device to pass ra w d ata pack ets to the AMD Ge ode LX pro- cessor system memory (see Figure 6-43).
AMD Geode™ LX Processors Data Book 471 Video Inpu t P or t 33234H 6.9.8 BT .601 Mode BT .601 mode all ows reception of 8- or 16-bit vi deo input which consists of HSYNC, VSYNC , and 8/16 bit data. V er ti- cal and hor izontal star t/stop registers provide th e informa- tion for data capture in each field/fr a me.
472 AMD Geode™ LX Processors Data Book Video Input Port 33234H . Figure 6-46. BT .601 Mode Progr ammable Field Detectio n Figure 6-47. BT .601 Mode Horizontal Timing HSYNC VSYNC odd_field_detect_sta.
AMD Geode™ LX Processors Data Book 473 Video Inpu t P or t 33234H Figure 6-48. BT .601 Mode V ert ical Timing 6.9.9 YUV 4:2:2 to YUV 4:2:0 T ransl ation The VIP provides the option to translate incoming 4:2:2 co- sited video to YUV 4:2:0. The U and V values of e ven lines are simply discarded.
474 AMD Geode™ LX Processors Data Book Video Input Port 33234H Figure 6-49. YUV 4:2:2 to YUV 4:2:0 T ranslation 1 2 4 6 3 5 7 1 2 4 6 3 5 7 YUV 4:2:2 YUV 4:2:0 12 3 45 6 12 3 45 6 1 2 4 3 1 [1] [2] .
AMD Geode™ LX Processors Data Book 475 Video Inpu t P or t 33234H 6.9.10 Soft ware Model The VIP receives data and st ores it into system memory . The VIP input modes with associated data types are shown in T able 6-74. VIP 2.0 is the VESA VIP 2.0 Lev el I (8-bit) standard or the VESA VIP 2.
476 AMD Geode™ LX Processors Data Book Video Input Port 33234H 6.9.10.1 Video Data Buffers Video data buff ers can be organized in linear or plan ar f or- mats. Linear b uffers pack YUV v alues contiguous in mem- or y . Planar buff ers hav e separate subb uffers f or each set of YUV values in a field or frame .
AMD Geode™ LX Processors Data Book 477 Video Inpu t P or t 33234H Figure 6-51 . E xample VIP YUV 4:2: 2 SA V/EA V P ackets Stored in Syst em Memory in a Linea r Buffer 0 1 2 3 vid_base (buff er star.
478 AMD Geode™ LX Processors Data Book Video Input Port 33234H Figure 6-52. Example VIP YUV 4:2:0 Pl anar Buffer (all base registers are 8-byte aligned) U Buff er V Buff er line #1 Y values Y pitch .
AMD Geode™ LX Processors Data Book 479 Video Inpu t P or t 33234H Figure 6-53. Example VIP 8/16- and 10-bit Ancillary Pac kets Stored in Syste m Memory 0 1 2 3 (8-byte aligned) 00 FF FF DID SDID NN=.
480 AMD Geode™ LX Processors Data Book Video Input Port 33234H 6.9.11 Bob and Wea ve Bob and Wea ve are two methods of outputting interlaced video , capture d by the VIP , in a progressive scan format.
AMD Geode™ LX Processors Data Book 481 Video Inpu t P or t 33234H V er tical Timing Error (Frame or Address Err or) /Me s- sage Missed Error - This error indicate s a frame error or an address error . A frame error occurs when the time between VSYNCs exceeds the window defined b y the VIP_SYNC_ERR_COUNT regist er (VIP Memor y Offset 78h).
482 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10 Video Input P or t Register Descriptions The registers associated with the VIP are the Standard GeodeLink Device (GLD) MSRs (accessed via the RDMSR and WRMSR instr uctions) and VIP Co nfiguration/Control Register s.
AMD Geode™ LX Processors Data Book 483 Video Input Port Register Descriptions 33234H 44h R/W VIP T ask B VBI Odd Base/VBI Start (VIP_T ASK_B_VBI_ODD_BASE_VBI_ST ART) 00000000h Page 502 48h R/W V IP .
484 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.1 Standar d GeodeLink™ Device (GLD) MSRs 6.10.1.1 GLD Capabilities MSR (GLD_MSR_CAP) 6.
AMD Geode™ LX Processors Data Book 485 Video Input Port Register Descriptions 33234H 6.10.1.3 GLD SMI MSR (GLD_MSR_SMI) MSR Address 54002002h Ty p e R / W Reset V alue 000000 000_ xxxx7FFFh GLD_MSR_.
486 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.1.4 GLD Error MSR (GLD_MSR_ERROR) MSR Address 54002003h Ty p e R / W Reset V alue 000 000000_ 00000000h GLD_.
AMD Geode™ LX Processors Data Book 487 Video Input Port Register Descriptions 33234H 6.10.1.5 GLD Po wer Ma nagement Register (GLD_MSR_PM) 6.10.1.6 GLD Diagnostic MSR (GLD_MSR_DIA G) This register is reser ved for intern al use by AMD and should not be written to .
488 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2 VIP Contr o l/Configuration Register s 6.10.2.1 VIP Control Regi ster 1 (VIP_CTL_REG1) VIP Memory Offset 0.
AMD Geode™ LX Processors Data Book 489 Video Input Port Register Descriptions 33234H 19 NI No n-Interlaced Vide o Input. This bit deter mines if the star t/end-of-frame ev ent occurs each field (for non-interlace d video) or at the end of the odd field (for interlaced video).
490 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.2 VIP Control Regi ster 2 (VIP_CTL_REG2) 3:1 VIP_MODE VIP Operating Mode . 000: IDLE. This mode forces VID[ 15:0] to 0 from pads to VIP . 001: VIP 2.0 8-bit mode.
AMD Geode™ LX Processors Data Book 491 Video Input Port Register Descriptions 33234H 26 ANCPEN Ancillary P arity Check Enab le. Wh en set to 1, ancillar y DID , SDID , NN, and check sum bytes are chec ked for e ven parity . The error is repor ted on MSR 4002002h[23].
492 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.3 VIP Status (VIP_ST A TUS) VIP Memory Offset 08h Ty p e R / W Reset V alue xxxxxxxxh VIP_ST A TUS Registe.
AMD Geode™ LX Processors Data Book 493 Video Input Port Register Descriptions 33234H 14 MSG_BERR Message Buffer Error . 0: No error . 1: Message buff er was ov erwri tten. This occurs when both msg buff ers are full and a msg/dstrm packet is receiv ed.
494 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.4 VIP Interrupt (VIP_INT) VIP Memory Offset 0Ch Ty p e R / W Reset V alue xxxxFFFEh VIP_INT Register Map 3.
AMD Geode™ LX Processors Data Book 495 Video Input Port Register Descriptions 33234H 6.10.2.5 VIP Current/T arget (VIP_CUR_T AR) 6.10.2.6 VIP Max Address (VIP_MAX_ADDR) VIP Memory Offset 10h Ty p e .
496 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.7 VIP T ask A Video Even Base Address (VIP_T ASK_A_VID_EVEN_BASE) 6.
AMD Geode™ LX Processors Data Book 497 Video Input Port Register Descriptions 33234H 6.10.2.9 VIP T ask A VBI Even Base Address (VIP_T ASK_A_VBI_EVEN_BASE) 6.
498 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.11 VIP T ask A Video Pi tch (VIP_T A SK_A_VID_PITCH) 6.10.
AMD Geode™ LX Processors Data Book 499 Video Input Port Register Descriptions 33234H 6.10.2.13 VIP T ask A V Offset (VIP_T ASK_A_V_OFFSET) 7E F D Even Field UV Decimation. When set to 1, the U and V values of the e ven frame will be discarded. Note: The DD bit (VIP Memor y Offset 00h[16]) should be set to 1 or e ven lines will also be decimated.
500 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.14 VIP T ask A U Offset (VIP_T ASK_A_U_OFFSET) 6.10.2.15 VIP T ask B Video Even Base/Horizon tal End (VIP_.
AMD Geode™ LX Processors Data Book 501 Video Input Port Register Descriptions 33234H 6.10.2.16 VIP T ask B Video Odd Base/Horizontal Star t (VIP_T ASK_B_VID_ ODD_BASE_HORIZ_ST ART) 6.
502 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.18 VIP T ask B VBI Odd Base/VBI St ar t (VIP_T ASK_B_VBI_ODD_BASE_VBI_ST ART) 6.10.2.19 VIP T ask B Data Pitch/V er tical Start Even (VIP_T ASK_B_D A T A_PITCH_VER T_ST ART_EVEN) 11:0 VBI_END VBI End.
AMD Geode™ LX Processors Data Book 503 Video Input Port Register Descriptions 33234H 6.10.2.20 VIP T ask B V Offset (VIP_T ASK_B_V_Offset) 27:16 VER TICAL_ END_EVEN (e ven/second field) V er tical End Even. This register is redefined in BT .601 mode.
504 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.21 VIP T ask B U Offset (VIP_ T ASK_B_U_OFFSET ) 6.10.2.22 VIP Ancillar y Data/Message Passing/Data Stream.
AMD Geode™ LX Processors Data Book 505 Video Input Port Register Descriptions 33234H 6.10.2.23 VIP Ancill ary Data/Message Passing/Data Streaming Buffer 2 Base Address (VIP_AN C_MSG_2_BASE) 6.
506 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.25 VIP P age Offset/ P age Count (VIP_P AGE_OFFSET ) 6.10.
AMD Geode™ LX Processors Data Book 507 Video Input Port Register Descriptions 33234H 6.10.2.27 VIP FIFO Address (VIP_FIFO_R_W_ADDR) 6.10.2.28 VIP FIFO Da ta (VIP_FIFO_D A T A) VIP Memory Offset 70h .
508 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.29 VIP VSYNC Error Co unt (VIP_SYNC_ERR_COUNT) 6.10.2.30 VIP T ask A U Ev en Off set (VIP_T ASK_A_U_EVEN _.
AMD Geode™ LX Processors Data Book 509 Video Input Port Register Descriptions 33234H 6.10.2.31 VIP T ask A V Even Offs et (VIP_T ASK_A_V_EVEN_OFFSET) VIP Memory Offset 80h Ty p e R / W Reset V alue .
510 AMD Geode™ LX Processors Data Book Security Block 33234H 6.11 Security Block The Secur ity Block provides a hardware Advanced Encr yp- tion Standard (AES) encr yption/decr yption engine and interf ace for accessing EEPR OM memor y for storing unique IDs and/or security keys.
AMD Geode™ LX Processors Data Book 511 Security Block 33234H 6.11.2 Functiona l Description The AES engine provides ECB a nd CBC 128-bit hardware encr yption and decr yption for the AMD Geode LX proces- sor using the Advanced Encrypti on Standard algor ithm.
512 AMD Geode™ LX Processors Data Book Security Block 33234H 6.11.2.1 EEPROM ID Interface The EEPROM ID interf ace provides an interf ace to an EEPROM non-v olatile memor y av ailable f or storing ID numbers, k eys, or other securi ty related inform ation.
AMD Geode™ LX Processors Data Book 513 Security Block Register Descriptions 33234H 6.12 Security Bloc k Register Descriptions This section provides information on the regi sters associ- ated with th.
514 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 048h R/W SB CBC Initializa tion V ector 2 (SB_CBC_IV _2) 00000000h Page 528 04Ch R/W SB CBC Initiali zation V ector.
AMD Geode™ LX Processors Data Book 515 Security Block Register Descriptions 33234H 6.12.1 Standar d GeodeLink™ (GLD) Device MSRs 6.12.1.1 GLD Capabilities MSR (GLD_MSR_CAP) 6.
516 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 6.12.1.3 GLD SMI MSR (GLD_MSR_SMI) 6.12.1.4 GLD Error MSR (GLD_MSR_ERROR) MSR Address 58002002h Ty p e R / W Reset .
AMD Geode™ LX Processors Data Book 517 Security Block Register Descriptions 33234H GLD_MSR_ERROR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 3.
518 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 6.12.1.5 GLD Po wer Ma nagement MSR (GLD_MSR_PM) 6.12.1.6 GLD Diagnostic MSR (GLD_MSR_DIA G) This register is reser ved for intern al use by AMD and should not be written to .
AMD Geode™ LX Processors Data Book 519 Security Block Register Descriptions 33234H 6.12.2 Security Block Specific MSRs 6.12.2.1 GLD Control MSR (GLD_MSR_CTRL) MSR Address 58002006h Ty p e R / W Rese.
520 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 6.12.3 Securit y Block Config uration/Contr ol Registers 6.12.3.1 SB Control A (SB_CTL_A) 2 SBI Swap Bits. This bit con trols a bit-sw appi ng f eature within the AES module.
AMD Geode™ LX Processors Data Book 521 Security Block Register Descriptions 33234H 6.12.3.2 SB Control B (SB_CTL_B) 0S T A Start for A P ointer . When set, this bit commands t he AES to start a new operation based on the current control re gister setting and the settin gs in SB Memor y Offset 010h and 014h.
522 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 6.12.3.3 SB AES Interrupt (SB_AES_INT) 6.12.3.4 SB Source A (SB_SOURCE_A) SB Memor y Offset 008h Ty p e R / W Reset.
AMD Geode™ LX Processors Data Book 523 Security Block Register Descriptions 33234H 6.12.3.5 SB Destination A (SB_DEST_ A) 6.12.3.6 SB Length A (SB_LENGTH_A) SB Memor y Offset 014h Ty p e R / W Reset.
524 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 6.12.3.7 SB Source B (SB_SOURCE_B) 6.12.3.8 SB Destination B (SB_DEST_ B) SB Memor y Offset 020h Ty p e R / W Reset.
AMD Geode™ LX Processors Data Book 525 Security Block Register Descriptions 33234H 6.12.3.9 SB Length B (SB_LENGTH_B) 6.12.3.10 SB Writable Ke y 0 (SB_WKEY_0) SB Memor y Offset 028h Ty p e R / W Res.
526 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 6.12.3.11 SB Writable Ke y 1 (SB_WKEY_1) 6.12.3.12 SB Writable Ke y 2 (SB_WKEY_2) SB Memor y Offset 034h Ty p e W O.
AMD Geode™ LX Processors Data Book 527 Security Block Register Descriptions 33234H 6.12.3.13 SB Writable Ke y 3 (SB_WKEY_3) 6.12.3.14 SB CBC Initializatio n V ector 0 (SB_CBC_IV_0) SB Memor y Offset.
528 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 6.12.3.15 SB CBC Initializatio n V ector 1 (SB_CBC_IV_1) 6.12.3.16 SB CBC Initializatio n V ector 2 (SB_CBC_IV_2) 6.
AMD Geode™ LX Processors Data Book 529 Security Block Register Descriptions 33234H 6.12.3.18 SB Random Number (SB_RANDOM_NUM) 6.12.3.19 SB Random Number Status (SB_RANDOM_NUM_ST A TUS) SB Memor y Of.
530 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 6.12.3.20 SB EEPROM Co mmand (SB_EE PROM_COMM) SB Memor y Offset 800h Ty p e R / W Reset V alue 000 00000h SB_EEPRO.
AMD Geode™ LX Processors Data Book 531 Security Block Register Descriptions 33234H 6.12.3.21 SB EEPROM A ddress (SB_EEPROM _ ADDR) 6.12.3.22 SB EEPROM Data (SB_EEPROM_D A T A) This register co ntains the Data bits for writing to or reading from the EEPR OM.
532 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 6.12.3.23 SB EEPROM Security State (SB_EEPROM_SEC_ST A TE) This read only register contains th e curr ent state of the access control bits for controlling reads and wr ites from/to the EEPROM.
AMD Geode™ LX Processors Data Book 533 GeodeLink™ Con trol Pr oc essor 33234H 6.13 GeodeLink™ Contr ol Pr ocessor The GeodeLink Contro l Processor (GLCP) functionality cov ers these areas (see F.
534 AMD Geode™ LX Processors Data Book GeodeLink™ Con trol Pr oc essor 33234H T able 6-81. T AP Contr ol Instructio ns (25-Bit IR) Instruction DR Length IR Name Description 123FFF Ah 8 BYP ASS_MODES This register is read/write.
AMD Geode™ LX Processors Data Book 535 GeodeLink™ Con trol Pr oc essor 33234H EXTEST JT A G Instruction The EXTEST instructi on a ccesses the boundary scan chain around the chip and controls the pin logic such that the boundar y scan data control s the data and enable sig- nals for the pins.
536 AMD Geode™ LX Processors Data Book GeodeLink™ Con trol Pr oc essor 33234H Figure 6-56. Processor Cloc k Generation 6.13.4 Compan ion Device Interfac e The AMD Geod e companion device interf ace for I/O con- nections (GIO) provides the system interf ace between the AMD Geode CS55 36 companion device and the AMD Geode LX processor .
AMD Geode™ LX Processors Data Book 537 GeodeLink™ Con trol Pr oc essor 33234H Figure 6-57. GIO Interface Bloc k Diagram GIO_GLIU GIO_SYNC GIO_PCI GIO_A20M GIO_NMI GIO_SUSP GIO_IN IT GIO_INPUT _DIS.
538 AMD Geode™ LX Processors Data Book GeodeLink™ Con trol Pr oc essor 33234H GIO_PCI Serial Pr otocol The GIO can override the func tionality of its SUSP# pin to create a serial bus called CPU Interface Serial (CIS). The reset mode for this pin is the SUSP# function.
AMD Geode™ LX Processors Data Book 539 GeodeLink™ Control Processor Register Descriptions 33234H 6.14 GeodeLink™ Contr ol Pr ocessor Register Descriptions All GeodeLink Control Processor registers are Model Spe- c if i c R e g i st e r s ( M S Rs ) and are ac c es s e d v i a th e R D M S R and WRMSR instr uctions.
540 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 4C000015h R/W GLC P Dot Clock PLL Control (GLCP_DO TPLL) 000000D7_02000000 h Page 557 4C000016h R/W.
AMD Geode™ LX Processors Data Book 541 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.1 Standar d GeodeLink™ Device MSRs 6.14.1.1 GLD Capabilities MSR (GLD_MSR_CAP) 6.
542 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 6.14.1.3 GLD SMI MSR (GLD_MSR_SMI) MSR Address 4C002002h Ty p e R / W Reset V alue 000 00000_000000.
AMD Geode™ LX Processors Data Book 543 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.1.4 GLD Error MSR (GLD_MSR_ERROR) MSR Address 4C002003h Ty p e R / W Reset V alue 000 00000_00.
544 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 6.14.1.5 GLD Po wer Ma nagement MSR (GLD_MSR_PM) The debug logic powers up selecting GLIU1 for its cloc k. Deb ug cl ock select is in GLCP_DBGCLKCTL (MSR 4C000016h[2:0]).
AMD Geode™ LX Processors Data Book 545 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2 GLCP Specif ic MSRs - GLC P Control MSRs 6.
546 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 28 GLCPDBG GLCP Debug Clock Off. When set, disables GLCP DBG logic clock. 27 GLCPGLIU GLCP GLIU Clock Off. When set, disables GLCP GLIU clock. 26 GLCPPCI GLCP GIO PCI Cl ock Off.
AMD Geode™ LX Processors Data Book 547 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.3 Chip Fabrication Inf o rmation (GLCP_F AB) This read only register i s used to track v ar ious fab , process, and product family parameters. It is meant f or AMD inter nal use only .
548 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.5 GLCP Debug Output fr om Chip (GLCP_DBGOUT) This register is reser ved for intern al use by AMD and should not be written to .
AMD Geode™ LX Processors Data Book 549 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.7 GLCP DO WSER (GLCP_DOWSER) 6.14.2.8 GLCP I/O Delay Controls (GLCP_DELA Y_CONTROLS ) MSR Ad.
550 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 59 SDCLK_SET SDCLK Setup . 0: Full SDCLK set up . 1: Half SDCLK setup for control signals. 58:56 DDR_RLE DDR read latch enable position. 55 SDCLK_DIS SDCLK disa ble [1,3,5].
AMD Geode™ LX Processors Data Book 551 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.9 GLCP Clock Control (GLCP_ CLK OFF) This register has bits that, when set, force clocks off usin g GeodeLink™ Clock Control (GLCC) logic in the system.
552 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.10 GLCP Clock Ac tive (GLCP_CLKA CTIVE) See "GLCP_CLK OFF Bi t Descripti ons" on page 55 1 fo r bit description s. 11 DCDO T_ 0 DC Dot Clock Off.
AMD Geode™ LX Processors Data Book 553 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.11 GLCP Clock Mask f or Debug Cloc k Stop Action (GLCP_CLKDISABLE) See "GLCP_CLK OFF Bi t Descripti ons" on page 55 1 fo r bit description s.
554 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.13 GLCP System Reset an d PLL Control (GLCP_SYS_RSTPLL) This register is initiali zed during POR, bu t otherwise is not itself reset by any “sof t-reset” f eatures.
AMD Geode™ LX Processors Data Book 555 GeodeLink™ Control Processor Register Descriptions 33234H 23:16 HOLD_COUNT Hold Count. The number of PLL ref erence clock cycl es (divided by 16 ) that the PLL is powered down for , and also the nu mber bef ore releasing CHIP_RESET .
556 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H The PW1 pin (66 MHz PCI) is wired directly to the COREDI V and GL DIV signals dur ing rese t. The IRQ13 pin (stall after reset) has no effect on the PLL controls but is still st ored in the BOOTSTRAP bits (MSR 4C000018h[7:1]).
AMD Geode™ LX Processors Data Book 557 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.14 GLCP Dot Cloc k PLL Co ntrol (GLCP_DO TPLL) This register does not include hardware hand shake controls lik e the GLCP_SYS_RSTPLL register (MSR 4C0 00014h), so care should be taken when changing the settings.
558 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H GLCP_DO TPLL Bit Descriptions Bit Name Description 63:49 RSVD Res erved. Wr ite as read. 48 DIV4 Divide by 4. When set, the PLL output is divided b y 4 before cloc king the logic.
AMD Geode™ LX Processors Data Book 559 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.15 GLCP Debug Cloc k Control (GLCP_DBGCLKCTL) Note that after the mux to select the clock, a standard cloc k control gate e xists. This regi ster should nev e r be changed from one non-zero value to another .
560 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.17 GLCP Control (GLCP_CNT) This register is used in conju nction wit h GLIU1 P ower Management. I/O writes, which include the lowest byte of this regis- ter , may trigger an SMI if GLD_MSR_SMI (MSR 4C002002h ) is configured appropri ately .
AMD Geode™ LX Processors Data Book 561 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.19 GLCP Thro ttle or C2 Start Delay (GLCP_TH_ SD) 6.
562 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.21 GLCP Proc essor Thr o ttle Off Delay (GLCP_TH_OD) 6.14.3 GLCP IG NNE I/Os The GLCP’ s GLIU is re sponsible f o r all the GLIU functional it y .
AMD Geode™ LX Processors Data Book 563 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.4 GLCP Specific MSRs - GLCP Debug Interface MSRs 6.14.4.1 GLCP DA C (GLCP_D A C) This register has D AC diagnostic controls and status. It ties directly to inputs and outputs on the D AC module.
564 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 6.14.5 GLCP Specif ic MSRs - GLC P Companion Device Interf ace MSRs 6.
AMD Geode™ LX Processors Data Book 565 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.5.3 GLIU Device Inte rrupt Status (MSR_INT AX) This is a read only MSR with the status of interr upt signals fr om the various bloc ks. This register is intended for deb ug pur- poses.
566 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge 33234H 6.15 GeodeLink™ PCI Bridge The GeodeLink™ PCI Br idge (GLPCI) module provides a PCI interface f or GeodeLink Interface Unit-based designs.
AMD Geode™ LX Processors Data Book 567 GeodeLink™ PCI Brid ge 33234H 6.15.1 GeodeLink™ Interface Bloc k The Geod eLink Inte rface b lock pro vides a thin p rotocol conv ersi on la yer between the T ransaction Forw arding bloc k and GeodeLink Interface Unit 1 (GLIU1).
568 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge 33234H Figure 6-59. Atomic MSR Accesses Acr oss the PCI Bus GLIU1 De vice-A Device-B De vice-C PCI-de vice = 1 PCI-de vice = 15 PCI-de vi ce = 25 PCI-device = 30 2 4 3 6 5 1 2 7 3 AMD Geode™ LX Pr ocessor 2.
AMD Geode™ LX Processors Data Book 569 GeodeLink™ PCI Brid ge 33234H 6.15.4 PCI Bus Interface B lock The PCI Bus Interface block is compliant to the PCI 2.2 specification, except in t he handling of SERR#/PERR# sig- nals. These signals are not available .
570 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge 33234H 6.15.5 PCI Arbite r The PCI arbiter implements a fa ir arbitration scheme with special suppor t for the companion device. By de f ault it operates as a simple round-robin arbiter that rotates p rior- ity in circular fashion (see Figure 6-60).
AMD Geode™ LX Processors Data Book 571 GeodeLink™ PCI Brid ge 33234H 6.15.6 Exception Handling 6.15.6.1 Out-Bound Write Exceptions When performing an out-bound wr ite on the PCI bus, two errors may occur: target abor t and PERR# asser tion. When a target abor t occurs, the PCI Bus Interface b lock must flush any stored write data.
572 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16 GeodeLink™ PCI Bridge Register Descriptions All GeodeLink™ PCI Br idge (G LPCI) registers are Model Specific Registers (MSRs) and are accessed via the RDMSR and WRMSR instru ctions.
AMD Geode™ LX Processors Data Book 573 GeodeLink™ PCI Bridg e Register Descriptions 33234H 5000201Dh R/W GLPCI Memor y Regio n 5 Configuration (GLPCI_R5) 00000000_00000000h Page 593 5000201Eh R/W .
574 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.1 Standar d GeodeLink™ Device (GLD) MSRs 6.16.1.1 GLD Capabilities MSR (GLD_MSR_CAP) 6.
AMD Geode™ LX Processors Data Book 575 GeodeLink™ PCI Bridg e Register Descriptions 33234H 6.16.1.3 GLD SMI MSR (GLD_MSR_SMI) MSR Address 50002002h Ty p e R / W Reset V alue 000 00000_0000003Fh GL.
576 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.1.4 GLD Error MSR (GLD_MSR_ERROR) MSR Address 50002003h Ty p e R / W Reset V alue 000 00000_0000003F.
AMD Geode™ LX Processors Data Book 577 GeodeLink™ PCI Bridg e Register Descriptions 33234H 6.16.1.5 GLD Po wer Ma nagement MSR (GLD_MSR_PM) 6.16.1.6 GLD Diagnostic MSR (GLD_MSR_DIA G) This register is for AMD use only and shoul d not be written to.
578 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.2 GLPCI Speci fic Registers 6.16.2.1 GLPCI Global Control (GLPCI_CTRL) MSR Address 50002010h Ty p e .
AMD Geode™ LX Processors Data Book 579 GeodeLink™ PCI Bridg e Register Descriptions 33234H 42 SL TO Subseque nt Latency Timeout Select. Specifie s the subsequent target latency timeout limit. If within a burst, the GLPCI module does not respond with the configured number of clock tic ks, the PCI interface will terminate the PCI bu s cycle.
580 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 24 MARS Master Abort Re ceive ASMI. Allow reception of a PCI bu s master abor t to be repor ted in the T ARE bit (MSR 50002002h[17]). 0: Disable. 1: Enable.
AMD Geode™ LX Processors Data Book 581 GeodeLink™ PCI Bridg e Register Descriptions 33234H 6.16.2.2 GLPCI Arbite r Control (GLPCI_ARB) 9L D E Latency Disconnect Enable. Wr iting 1, causes the PCI interface to disconnect from a PCI bus master when a latency timer expirati on occurs .
582 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H GLPCI_ARB Bit Definitions Bit Name Description 63:60 CR CPU Repeat. Controls the number of consecutive gr an ts given to the CPU before rotat- ing to the ne xt requestor .
AMD Geode™ LX Processors Data Book 583 GeodeLink™ PCI Bridg e Register Descriptions 33234H 20 O V0 Override 0. Enab les requester0 to ov err ide the repeat-count and grant-hold f o r other requestors. When O V0 is set and REQ0# is asser ted, repea t-count and grant-hold mech- anisms for other masters are temporarily disabled.
584 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.2.3 GLPCI VPH / PCI Configur ation Cycle Control (GLPCI_PBUS) The PBUS model specific register is us ed to control the way that the GLPCI module generates (or does not gene rate) PCI configuration cycles onto the PCI b us.
AMD Geode™ LX Processors Data Book 585 GeodeLink™ PCI Bridg e Register Descriptions 33234H 6.16.2.6 GLPCI Fixed Region Con figuration A0-BF (GLPCI_A0) GLPCI_REN Bit Descriptions Bit Name Description 63:32 Spare Spare Bits. Extra bits a vailable f or future use.
586 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.2.7 GLPCI Fixed Region Con figuration C0-DF (GLPCI_C0) GLPCI_A0 Bit Descriptions Bit Name Description (Note 1) 63:56 BC BC Properties. Region proper ties for BC000 through BFFFF .
AMD Geode™ LX Processors Data Book 587 GeodeLink™ PCI Bridg e Register Descriptions 33234H 6.16.2.8 GLPCI Fixed Region Con figuration E0-FF (GL PCI_E0) 39:32 D0 D0 Properties. Region proper ties for D0000 through D3FFF . 31:24 CC CC Properties. Region proper ties for CC000 through CFFFF .
588 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.2.9 GLPCI Memory Region 0 Configuration (GLPCI_R0) MSR Address 50002018h Ty p e R / W Reset V alue 0.
AMD Geode™ LX Processors Data Book 589 GeodeLink™ PCI Bridg e Register Descriptions 33234H 6.16.2.10 GLPCI Memory Region 1 Configuration (GLPCI_R1) MSR Address 50002019h Ty p e R / W Reset V alue .
590 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.2.11 GLPCI Memory Region 2 Configuration (GLPCI_R2) MSR Address 5000201Ah Ty p e R / W Reset V alue .
AMD Geode™ LX Processors Data Book 591 GeodeLink™ PCI Bridg e Register Descriptions 33234H 6.16.2.12 GLCPI Memory Region 3 Configuration (GLPCI_R3) MSR Address 5000201Bh Ty p e R / W Reset V alue .
592 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.2.13 GLCPI Memory Region 4 Configuration (GLPCI_R4) MSR Address 5000201Ch Ty p e R / W Reset V alue .
AMD Geode™ LX Processors Data Book 593 GeodeLink™ PCI Bridg e Register Descriptions 33234H 6.16.2.14 GLPCI Memory Region 5 Configuration (GLPCI_R5) MSR Address 5000201Dh Ty p e R / W Reset V alue .
594 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.2.15 GLPCI External MSR Access Configuration (GLPCI EXT_MSR) Note: MSR accesses addressed to P or t 0 are handled directly by the GLPCI module.
AMD Geode™ LX Processors Data Book 595 GeodeLink™ PCI Bridg e Register Descriptions 33234H 6.16.2.16 GLPCI Spare MSR Address 5000201Fh Ty p e R / W Reset V alue 000 00000_00000003h GLPCI Spare 63 .
596 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.2.17 GLPCI General Pu rpose I/O (GLPCI_GPIO) MSR Address 50002020h Ty p e R / W Reset V alue 000 000.
AMD Geode™ LX Processors Data Book 597 7 Electrical Specifications 33234H 7.0 Electr ical Specifications This section provides information on electr ical connections, absolute maximum ratings, operating conditions, and DC/A C ch aracteristic s f or the AMD Geode™ LX processor .
598 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H 7.3 Operating Conditions T able 7-2 lists the operating conditions for the AMD Geode LX processor . T able 7-2. Operating Conditions Symbol P arameter (Note 1) Note 1. The AMD Geode LX 900@ 1.
AMD Geode™ LX Processors Data Book 599 Electrical Specifications 33234H 7.4 DC Current DC current is not a simple measuremen t. Three of the AMD Geode LX proc essor’ s power states (ON, Active Idle , and Sleep) were selected for measurement.
600 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H The data bus on the DDR SDRAM has a low voltage s win g when actively terminated (ter minate d topology). The ter mi- nated topology suppor ts higher data transf e r rates and is less constrained, but it consumes more pow er .
AMD Geode™ LX Processors Data Book 601 Electrical Specifications 33234H T able 7-4. AMD Geode LX 800@0.9W Pr ocessor DC Currents LX 800@0.9W (500 MHz), No EEPROM, V CORE = 1.
602 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H T able 7-5. AMD Geode LX 700@0.8W Pr ocessor DC Currents LX 700@0.8W (433 MHz), No EEPROM or EEPROM, V CORE = 1.
AMD Geode™ LX Processors Data Book 603 Electrical Specifications 33234H T able 7-6. AMD Geode LX 600@0.7W Pr ocessor DC Currents LX 600@0.7W (366 MHz), No EEPROM, V CORE = 1.
604 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H 7.5 DC Characteristics All DC parameters and current measurements in th is section were measured under t he operating co nditions listed in T able 7-2 "Operating Conditions", unless otherw ise noted.
AMD Geode™ LX Processors Data Book 605 Electrical Specifications 33234H I LEAK Input Leakage Current Includi ng Hi-Z Output Leakage, Note 1 PCI -3.0 3.0 µA 24/Q3 -3.0 3.0 µA 24/Q5 -3.0 3.0 µA 24/Q7 -3.0 3.0 µA 5V -3.0 3.0 µA If V IH > V IO , I LEAK max = 20 µA DDR -3.
606 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H I OL Output Low Current , Note 1 V O = V OL (Max) PCI 1500 µA 24/Q3 24.0 mA 24/Q5 24.
AMD Geode™ LX Processors Data Book 607 Electrical Specifications 33234H 7.6 A C Characteristics The follo win g tables list the A C character istics including output delays , in put setup requirements, input hold require- ments, and output float dela ys.
608 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H Figure 7-3. Drive Level and Measurement P oints f or Switching Characteristics T able 7-8. System Interface Signals Symbol P a rameter Min Max Unit Comments t CK SYSREF Cycle time 15.
AMD Geode™ LX Processors Data Book 609 Electrical Specifications 33234H Figure 7-4. P ower Up Sequencing Figure 7-5. Drive Level and Measurement P oints f or Switching Characteristics V CORE V IO ,V MEM RESET# SYSREF SYSREF cycle time not to scale with other delays in this figure.
610 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H Figure 7-6. Drive Level and Measurement P oints f or Switching Characteristics T able 7- 10. VIP Interface Si gnals Symbol P a rameter Min Max Unit Comments t CK VIPCLK period 12.
AMD Geode™ LX Processors Data Book 611 Electrical Specifications 33234H Figure 7-7. Drive Level and Measurement P oints f or Switching Characteristics T able 7-11. Flat Panel I nterface Signals Symbol P a rameter Min Max Unit Comments t CK DO TCLK per iod 6.
612 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H T able 7-12. C RT Interface Sign als Symbol P a rameter Min Max Unit Comments t CK DO TCLK P e riod 2.8 ns 350 MHz t CH DO TCLK High ti me 1.2 ns 45% t CK t CL DO TCLK Low time 1.
AMD Geode™ LX Processors Data Book 613 Electrical Specifications 33234H T able 7- 14. CR T Di splay Analog (DA C) Characte ristics Symbol Parameter Min T yp Max Units Comments (Note 1) V OS Ou tput V oltage Saturation Limit 1.25 V I OV A R Ou tput Current 18.
614 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H T able 7- 15. Memory (DDR ) Interface Signals Symbol (Note 1) Parameter Min Max Unit Comments t CK SDCLK[5:0]P , SDCLK[5: 0]N period 5.0 ns Note 2 t CH SDCLK[5:0]P , SDCLK[5:0] N High time 2.
AMD Geode™ LX Processors Data Book 615 Electrical Specifications 33234H Figure 7-8. DDR Write Timing Measurement Poi nts SDCLK[5:1]P Non-DQ Outputs V REF V alid Output n+1 V alid Output n V REF t VA.
616 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H Figure 7-9. DDR Read Timing Measurement P oints DQ Inputs V REF DQ t V REF DQ t-1 SDCLK0 DQS ‘Late’ Input V REF other DQS .
AMD Geode™ LX Processors Data Book 617 Electrical Specifications 33234H T able 7-16. JT A G Interface Signal s Symbol P a rameter Min Max Unit Comments TCLK per iod 15 ns No te 1 TCLK High time 4 ns 40% period TCLK Lo w time 4 ns 40% period TDI, TMS Setup time to TCLK rising edge 1.
618 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H.
AMD Geode™ LX Processors Data Book 619 8 Instruction Set 33234H 8.0 Instr uction Set This chapt er provide s the gener al instruction set f ormat and detailed inf ormation on th e AMD Geo de™ LX proc essor’s instruc tions/ instru ction encodings.
620 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.1.1 Prefix (Op tional) Prefix bytes can be placed in front of any instruction to mo di fy the operation of that instr uction. Wh en more than one prefix is used, the order is not impor tant.
AMD Geode™ LX Processors Data Book 621 Instruction Set 33234H 8.1.2 Opc ode The opcode field specifies the operation to be perf or med by the instr uction. The opcode field is either one or two bytes in length and may be fur ther defined by additional bits in th e mod r/m byte.
622 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.1.2.4 eee Field (MO V -Instr uction Register Selection) The eee field (bits [5:3]) is used to sel ect the control, debug, and test registers in the MO V instructions. The type of regist er and bas e re gis ters sel ecte d by the eee fie ld are lis ted in T able 8-7.
AMD Geode™ LX Processors Data Book 623 Instruction Set 33234H 01 000 DS:[BX+SI+d8] DS:[EAX+d8] 01 001 DS:[BX+DI+d8] DS:[ECX+d8] 01 010 SS:[BP+SI+d 8] DS:[EDX+d8] 01 011 SS:[BP+DI+d8] DS:[EBX+d8] 01 .
624 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.1.4 reg Fie ld The reg field (T able 8-10) determines w hich general regist ers are to be used. The selected register is depe ndent on whether a 16-bit or 3 2-bit operation is current and on the status of the w bit.
AMD Geode™ LX Processors Data Book 625 Instruction Set 33234H 8.1.5 s-i-b Byte (Scale, Inde xing, Base) The s-i- b fie lds pro vide sc ale f actor , i nde xing, and a base f ield f or addr ess sele ctio n. The ss, ind e x, and base fields are described next.
626 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.1.5.3 Base Field (s-i-b Present) In T ab le 8-8 on page 622, the note “s-i-b is present” f o r cer tain e ntr ies forces t he us e of th e mo d and base fiel d as l iste d in T able 8-15.
AMD Geode™ LX Processors Data Book 627 Instruction Set 33234H 8.2 CPUID Inst ruction Set The CPUID instru ction (opcode 0F A2) allows softw are to mak e processor inquir ies as to the vendor , f amil y , model, step- ping, f ea tures, and specific cache organization inf or mation.
628 AMD Geode™ LX Processors Data Book Instruction Set 33234H T able 8-18. CPUID Instruction Codes with EAX = 00000000 Register Reset V alue Description Comment EAX[31:28] 0x0 Reser ved EAX[27:20] 0.
AMD Geode™ LX Processors Data Book 629 Instruction Set 33234H 8.2.2 Extended CPUID Level s T esting for e xtended CPUID inst r uction suppor t can be accomp lished by e xec uting a CPUID instruction with the EAX regis- ter initialized to 80000000h.
630 AMD Geode™ LX Processors Data Book Instruction Set 33234H T able 8-21. CPUID Instruct ion Codes with EAX = 80000001h Register Reset V alue Description Comment EAX[31:28] 0x0 Reser ved EAX[27:20].
AMD Geode™ LX Processors Data Book 631 Instruction Set 33234H 8.2.2.3 CPUID Instruct ion with EAX = 80000002h, 80000003h, or 80000004h Extended functions 80 000002h through 8000 0004h (EAX = 8000000.
632 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.2.2.4 CPUID Instruct ion with EAX = 80000005h Extended function 80000005h (EAX = 80000005h) of the CPUID in str uction returns informatio n on the inter nal L1 cache and TLB structures.
AMD Geode™ LX Processors Data Book 633 Instruction Set 33234H 8.3 Processor Core Instruction Set The instruction set for the AMD Geode LX processor core is summarized in T able 8-26. The table uses se veral symbols and abbre viation s that are descr ibed next and listed in T able 8-25.
634 AMD Geode™ LX Processors Data Book Instruction Set 33234H T able 8-26 . P r ocessor Core Instruction Se t Instruction Opcode Clock Count (Reg/Cache Hit) Flags Notes Real Mode Prot’d Mode OD I .
AMD Geode™ LX Processors Data Book 635 Instruction Set 33234H BTS T est Bit and S et --------x b h Register/Memory , Immediate 0F BA [mod 101 r/m] # 2 2 Register , Register 0F AB [mod reg r/m] 2 2 M.
636 AMD Geode™ LX Processors Data Book Instruction Set 33234H CMO VNS Move if Not Sign 0 F 4 9 [ m o d r e g r / m ] 1 1 --------- r Register , Register/Memory CMP Comp are Integers x- - - xxxxx b h.
AMD Geode™ LX Processors Data Book 637 Instruction Set 33234H IMUL Integer (Signed) Multiply x ---x x u u x b h Accumulator b y Register/Memor y Multiplier: Byte Wor d Doubleword F [011w] [mod 101 r.
638 AMD Geode™ LX Processors Data Book Instruction Set 33234H JNBE/JA J ump on Not Below or Equal /Abov e -------- r 8-bit Displacement 77 + 1 1 Full Displacement 0F 87 +++ 1 1 JNE/JNZ J ump on Not .
AMD Geode™ LX Processors Data Book 639 Instruction Set 33234H LOOPNZ/LOOPNE Offset E 0 + 2 2 --------- r LOOPZ/LOOP E Offset E 1 + 2 2 --------- r LSL Load Segme nt Limit -----x --- F rom Register/M.
640 AMD Geode™ LX Processors Data Book Instruction Set 33234H OUT Output to P or t --------- m Fixed P ort E [011w] # 8 8/23 V ariable P or t E [111 w] 8 8/23 OUTS Output String 6 [ 1 1 1 w ] 1 2 1 .
AMD Geode™ LX Processors Data Book 641 Instruction Set 33234H REP CMPS CX==0 66 CX==1 13 13 CX>1 10+3C 10+3C REP INS I nput String F 3 6 [ 1 1 0 w ] --------- b h , m CX==0 99 / 2 4 CX==1 CX>1.
642 AMD Geode™ LX Processors Data Book Instruction Set 33234H SAL Shift Left Arithmetic bh Register/Memory by 1 D[000w] [mod 100 r/m] 1 1 x - - - x x u x x Register/Memory by CL D[001w] [mod 100 r/m.
AMD Geode™ LX Processors Data Book 643 Instruction Set 33234H SFENCE 11 SGDT Store GDT Register b, c h T o R e g i s t e r / M e m o r y 0 F 0 1 [ m o d 0 0 0 r / m ] 6 6 --------- SIDT Store IDT Re.
644 AMD Geode™ LX Processors Data Book Instruction Set 33234H WRMSR Write to Model S pecific Register 0 F 3 0 1 0 1 0 --------- XADD Exchange and Add x- - - xxxxx Register1, Register2 0F C[000w] [11.
AMD Geode™ LX Processors Data Book 645 Instruction Set 33234H Instruction Notes for Instruction Set Summary Notes a through c apply to real address mode only: a. This is a protec ted mode instruction. Attempted e xecut i on in real mode results in ex ce ption 6 (inv alid opcode ).
646 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.3.4 Non-Stand ard Pr oce ssor Core Instruc tions 8.3.4.1 DMINT - Enter Deb ug Management Mode Operation Opcode Instruction C locks Des.
AMD Geode™ LX Processors Data Book 647 Instruction Set 33234H Description The DMINT instru ction sav es por tions of the processors stat e to the Debug Management Mode (DMM) he ader , alters the processors state for DMM, enters DMM, and then call s the DMM mode hand ler .
648 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.3.4.3 MO V - Move to /fr om T est Registers Operation IF (CPL <> 0) THEN #GP(0); ELSE DEST <= SRC; Description The abov e f o.
AMD Geode™ LX Processors Data Book 649 Instruction Set 33234H 8.3.4.4 RDM - Lea ve Debug Management Mode Operation Description The RDM instru ction restores the state of the pro cessor from the DMM header, and then jumps to the address in dicated in the NEXT_IP field of the DMM header.
650 AMD Geode™ LX Processors Data Book Instruction Set 33234H Exceptions #UD If current privilege le vel is not 0, or the DMM_INST_ EN = 0 and if the processor is not in SMM an d if the processor is not in DMM. Notes Data address breakpoints o n DMM header addresses a re i gnored dur ing the ex ecution of the RSM instruction.
AMD Geode™ LX Processors Data Book 651 Instruction Set 33234H 8.3.4.6 RSLDT - Restore Local Descri ptor T able Register and Descriptor Operation Description Restore the Local De scriptor T able register and descriptor from memor y . Be low is the f orm at of the descri ptor contents in memor y .
652 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.3.4.7 RSM - Lea ve S ystem Management Mode Operation Description The RSM instruction restores the state of the pr ocessor from the System Managem ent Mode (S MM) header , and then jumps to the address indicated by the NEXT_IP field of the SMM header .
AMD Geode™ LX Processors Data Book 653 Instruction Set 33234H Notes The RSM instr uction does not check the values th at it reads from the SMM header f or validity . The RSM instr uction set the curr ent pr ivilege lev e l to the SS DPL value read from the SMM header .
654 AMD Geode™ LX Processors Data Book Instruction Set 33234H Exceptions None. Notes None. 8.3.4.10 SMINT - Enter System Management Mode Operation Opcode Instruction C locks Description 0F 38 SMINT .
AMD Geode™ LX Processors Data Book 655 Instruction Set 33234H Description The SMINT instruction sav es por tions of the processors state to the System Management Mode (SMM) h eader , alters the processors state for SMM, enters SMM, and then calls the SMM handler .
656 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.3.4.12 SVDC - Save Segmen t Register and Descriptor Operation Description Write the specified segmen t descriptor (either DS, ES, FS , GS, SS , or CS) to memory . Below is the f or mat of the descriptor contents in memor y .
AMD Geode™ LX Processors Data Book 657 Instruction Set 33234H Exceptions #UD If current privilege lev el is not 0, or the SMM_INST_EN = 0 and if the processor is not in SMM and if the processor is not in DMM. Notes The reg field within the mod r/m byte must be zero f or the SVLDT instr uction to be recognized.
658 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.4 MMX™, FPU , and AMD 3DNo w!™ T echnology In structions Sets The CPU is functional ly divided into the Flo ating P oint Uni t (FPU) unit and the Integer Unit.
AMD Geode™ LX Processors Data Book 659 Instruction Set 33234H windex 1 (imm8) The range given b y [in de x1 (imm8) + 15: index1 (imm8)]. windex 2 (imm8) The range given b y [in de x2 (imm8) + 15: index2 (imm8)]. windex 3 (imm8) The range given b y [i ndex3 ( imm8) r15: indes3 (imm8)].
660 AMD Geode™ LX Processors Data Book Instruction Set 33234H T able 8-28. MMX™ Instruction Set MMX™ Instructions Opcode Operation Clock Ct Notes EMMS Empty MMX Stat e 0F77 T ag Word <--- FFF.
AMD Geode™ LX Processors Data Book 661 Instruction Set 33234H P ADDUSW Add Unsi gned Word with Saturation MMX Register 2 to MMX Register 1 0FDD [11 mm1 mm2] MMX reg 1 [word] <--- sat --- (MMX reg.
662 AMD Geode™ LX Processors Data Book Instruction Set 33234H PCMPGTD P ack Compare Greater Than Dword MMX Register 2 to MMX Registe r 1 0F66 [11 mm1 mm2] MMX reg 1 [dwo rd] <--- FFFF FFFFh --- i.
AMD Geode™ LX Processors Data Book 663 Instruction Set 33234H PMINSW P acked Minimum Signed Word MMX Register 1with MMX Register 2 0FEA [11 mm1 mm2] MMX reg 1 [word] <--- MMX reg 1 [w ord] --- if.
664 AMD Geode™ LX Processors Data Book Instruction Set 33234H PSHUFW P acked Shuff le Word MMX Register1, MMX Regi ster2, imm8 0F70 [11 mm1 mm2] # MMX reg 1 [w ord] <--- MMX re g 2 [windexall (im.
AMD Geode™ LX Processors Data Book 665 Instruction Set 33234H PSUBB Subtract Byte With Wrap-Around MMX Regist er 2 to MMX Reg ister 1 0FF 8 [11 mm1 mm2] MMX reg 1 [byt e] <--- MMX reg 1 [byte] - .
666 AMD Geode™ LX Processors Data Book Instruction Set 33234H 1) This instruction must wait f or the FPU pipeline to flush. Cycle count depends on what inst ructions are in the pipe line.
AMD Geode™ LX Processors Data Book 667 Instruction Set 33234H T able 8-29. FPU Instruction Set FPU Instruction Opcode Operation Clock Ct Single/Dbl (or extended) Notes F2XM1 Functi on Evaluation 2x-.
668 AMD Geode™ LX Processors Data Book Instruction Set 33234H FDECSTP Decrement Stack pointer D9 F6 Decrement top of stack pointer 1 3 FDIV Float ing P oint Divide T op of Stack DC [1111 1 n] ST(n) <--- ST(n) / T OS 12/47 80-bit Register D8 [1111 0 n] TOS <--- T OS / ST(n) 12/47 64-bit Real DC [mod 110 r/m] T OS <--- TOS / M.
AMD Geode™ LX Processors Data Book 669 Instruction Set 33234H FP A T AN Function Eval: T an-1(y/ x) D9 F3 ST(1) <--- A T AN[ST(1) / TOS]; t hen pop TOS 269 - 354 3 FPREM Floating P oint Remainder.
670 AMD Geode™ LX Processors Data Book Instruction Set 33234H All ref erences to T OS and ST(n) refer to stac k lay out prior to ex ecu tion. V alues popped off the stack are discarded. A POP from the stack increments the top of stac k poi nter . A PUSH to the stac k decremen ts the top of stack pointer .
AMD Geode™ LX Processors Data Book 671 Instruction Set 33234H T able 8- 30. AMD 3DNow!™ T echnology Instruction Set AMD 3DNow!™ Instructions Opcode/imm8 Operation Clk Cnt Notes FEMMS F aster Exi.
672 AMD Geode™ LX Processors Data Book Instruction Set 33234H PFMAX P ack ed Floating-P oint MAXimum 2 MMX Register1 with MMX Register2 0F0F [11 mm1 mm2] A4 MMX reg 1[dword] <--- MMX reg 1 [d wor.
AMD Geode™ LX Processors Data Book 673 Instruction Set 33234H 1) These instructions must w a it f or the FPU pipeline to flus h. Cycle count dep ends on what instructions are in the pi pe- line. 2) The AMD Geode LX processor perf or ms PFRCP and PFRSQRT to 24- bit accuracy in one cycle , so these instructions are unnecessar y .
674 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.4.1 Non-Standard AMD 3DNo w!™ T echnology Instruction s 8.4.1.1 PFRCPV - Floating-Point Reciprocal Appr o x imation Operation DEST[3.
AMD Geode™ LX Processors Data Book 675 9 Pac kage Specifications 33234H 9.0 P ac kage Specifications 9.1 Physical Dimensions The figures in this section provide the mechanical package outline for the BGU481 (481-ter minal Ball Grid Array Ca vi ty Up) Figure 9-1.
676 AMD Geode™ LX Processors Data Book Pac kage Specificatio ns 33234H Figure 9-2. BGU481 Bottom Vie w /Dimensions.
A AMD Geode™ LX Processors Data Book 677 Appendix A: Suppor t Document ation 33234H Appendix A Suppor t Documentation A.1 Or der Information Ordering information for the AMD Geode™ LX proce ssors is c ontained i n this section. The order ing par t number (OPN) is f orm ed by a combination of elements.
678 AMD Geode™ LX Processors Data Book Appendix A: Order Information 33234H T able A-1. V alid OP N Combinations Fam ily Architecture MTDP Per fo r m an c e Indicator Pac k ag e Ty p e Operating Vo .
AMD Geode™ LX Processors Data Book 679 Appendix A: Data Book Revision Histor y 33234H A.2 Data Book Revision History This document is a repor t of the revi sion/creation process of the data book fo r the AMD Geode™ LX processors. Any re vi- sion (i.
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