IBMメーカー750GLの使用説明書/サービス説明書
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IBM PowerPC 75 0GX and 750GL RISC Micro- processor User ’s Manual V ersion 1.2 March 27, 2006 Tit le P ag e.
® Copyright and Disclaimer © Copyr ight Interna tional Bus iness M achines C orporation 2004, 2006 All Rights Reserved Printed in the Uni ted States of America March 20 06.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor 750gx_umTOC.fm.(1.2) March 27, 2006 Page 3 of 377 List of Figures ............. .......... .............. ......... .............. .............. ......... .............. .......... .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Page 4 of 377 750gx_umTOC.fm.(1.2) March 27, 2006 2. Progr amming Model ....................... ......... .............. .......... .............. ......... .............. ..... 57 2.1 Power PC 750GX P rocessor Re gister Set .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor 750gx_umTOC.fm.(1.2) March 27, 2006 Page 5 of 377 2.3.6.1 Sy stem Lin kage Ins tructions— OEA ............... ............. ................... ............. ................. 118 2.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Page 6 of 377 750gx_umTOC.fm.(1.2) March 27, 2006 4.2 Exception Rec ogn iti on and Prio riti es ......... ....... ...... ............. ...... ....... ...... ....... ............. .....
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor 750gx_umTOC.fm.(1.2) March 27, 2006 Page 7 of 377 5.1.8 MMU In structions and Regi ster Summa ry .......................... ............. ............. ................... .... 19 4 5.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Page 8 of 377 750gx_umTOC.fm.(1.2) March 27, 2006 6.6.1.3 Com pletio n-Unit Resou rce Requir ements ................ .................... ............. ............. ...... 237 6.7 Instruc tion Latenc y Summ ary .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor 750gx_umTOC.fm.(1.2) March 27, 2006 Page 9 of 377 7.2.11.4 Ti me Base Ena ble (TBE N)—Input ..................... ............. .................... ............. .......... 274 7.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Page 10 o f 377 750gx_umTOC.fm.(1.2) March 27, 2006 8.6.2 No-DR TRY Mode ................ ............. .................... ............ .................... ............. ...........
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor 750gx_umTOC.fm.(1.2) March 27, 2006 Page 11 o f 377 11.1 Per formance-Mon itor Interr upt ............ ............. ................... ............. .................... ..........
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Page 12 o f 377 750gx_umTOC.fm.(1.2) March 27, 2006.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor 750gx_umLOF.fm.(1.2) March 27, 2006 List of Figures Page 13 o f 377 List of Figures Figure 1-1. 750GX M icroprocesso r Block D iagram ........... ................... ............. ..
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor List of Figures Page 14 o f 377 750gx_umLOF.fm.(1.2) March 27, 2006 Figure 8-5. First Level Address Pipelin ing ... ............. ............. ................... ............. ......
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor 750gx_umLOT.fm.(1.2) March 27, 2006 List of Tables Page 15 o f 377 List of T ables Table 1 -1. Architectur e-Defined Re gisters (Excluding SPRs) ...... .................... .........
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor List of Tables Page 16 o f 377 750gx_umLOT.fm.(1.2) March 27, 2006 Table 2-34. SPR Enc odings fo r 750GX- Defined Reg isters (mfspr) ................ .................... .............
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor 750gx_umLOT.fm.(1.2) March 27, 2006 List of Tables Page 17 o f 377 Table 5 -7. Table-Se arch Operati ons to Upd ate History Bits—TLB Hi t Case ... ............. ............. .....
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor List of Tables Page 18 o f 377 750gx_umLOT.fm.(1.2) March 27, 2006 Table 1 1-7. HID2 Check stop Control Bits .................. ............. ................... ............. ........
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_preface.fm.(1.2) March 27, 2006 Page 19 o f 377 About This Manu al This u ser’s man ual def ines the f unctional ity of the Power PC ® 75 0GX a nd 750GL RISC microp roce ssors.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Page 20 o f 377 gx_preface.fm.(1.2) March 27, 2006 Conventions Used in This Manual Notational Conventions mnemonics Inst ruction mnemon ics ar e shown in lower case bo ld. italics Italics indi cate vari able com mand param eters.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_preface.fm.(1.2) March 27, 2006 Page 21 o f 377 Terminology Conventions The foll owing tabl e describ es termino logy con ventions used in this man ual and the equiv alent ter minology used in t he Powe rPC Arch itecture specifi cation.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Page 22 o f 377 gx_preface.fm.(1.2) March 27, 2006 Using This Manual w ith the Pr ogramming Environments Manual Becaus e the Po werPC.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_01.fm.(1.2) March 27,2006 PowerPC 750GX Overview Page 23 o f 377 1. PowerPC 750GX Overview The IBM PowerPC 750GX red uced in str.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor PowerPC 750GX Overview Page 24 o f 377 gx_01.fm.(1.2) March 27,2006 and dat a block-a ddress-tr anslati on (IBA T and DBA T) array s, defined by the Po werPC Architec ture.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_01.fm.(1.2) March 27,2006 PowerPC 750GX Overview Page 25 o f 377 1.2 750GX Microprocessor Features This sec tion list s features of the 750GX. The interre lations hip of t hese featu res is sh own in Figure 1-1 on page 25.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor PowerPC 750GX Overview Page 26 o f 377 gx_01.fm.(1.2) March 27,2006 made ava ilabl e from the instruct ion cache . T ypi cally , if a fetch acc ess hits the B TIC, it pro vides the firs t two instruc tions i n the target s tream effectivel y yieldin g a ze ro-cycle b ranch.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_01.fm.(1.2) March 27,2006 PowerPC 750GX Overview Page 27 o f 377 – Retires as many as two ins tructio ns per cl ock. • Separate on- chip L1 instruc tion and data ca ches (H arvard archite cture) .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor PowerPC 750GX Overview Page 28 o f 377 gx_01.fm.(1.2) March 27,2006 • TLBs a re hardw are-relo adable ( the page table sea rch is per formed b y hardwa re). • Bus interf ace featur es: – Enhance d 60x bus that pipelin es back-to- back re ads to a depth of fou r .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_01.fm.(1.2) March 27,2006 PowerPC 750GX Overview Page 29 o f 377 1.2.1 Instruction Flow As show n in Fig ure 1-1 , 750GX M icrop.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor PowerPC 750GX Overview Page 30 o f 377 gx_01.fm.(1.2) March 27,2006 are flushed fr om the pro cessor, an d instruc tion fetch ing resumes along th e correct pa th.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_01.fm.(1.2) March 27,2006 PowerPC 750GX Overview Page 31 o f 377 For a mo re deta iled d iscussi on of instru ction co mplet ion, see Section 6.6.1, B ranch, D ispatch, and Comple - tion-Uni t Resource Requirem ents, o n page 2 37.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor PowerPC 750GX Overview Page 32 o f 377 gx_01.fm.(1.2) March 27,2006 1.2.2.3 Load/Store Unit (L SU) The LSU executes a ll load- and-sto re inst ructions and pro vides t he data-tran sfer interfac e between t he GPRs , FPRs, and t he data-c ache/mem ory sub system.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_01.fm.(1.2) March 27,2006 PowerPC 750GX Overview Page 33 o f 377 The 750G X suppo rts the f ollowing types of m emory tr anslati.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor PowerPC 750GX Overview Page 34 o f 377 gx_01.fm.(1.2) March 27,2006 written i nto an 8-w ord buffer. S ubsequen t doubl e words are fetch ed from eithe r the L2 c ache or the sys tem memory and written into the buff er.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_01.fm.(1.2) March 27,2006 PowerPC 750GX Overview Page 35 o f 377 instruc tion-c ache flash inval idate bit (HID 0[ICFI]). The inst ructio n cache can be lo cked by settin g HID0[ILOCK ].
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor PowerPC 750GX Overview Page 36 o f 377 gx_01.fm.(1.2) March 27,2006 The addres s and da ta buse s opera te independ ently . Address and data ten ures of a memory acces s are decouple d to prov ide m ore flex ible con trol of bu s tra ffic.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_01.fm.(1.2) March 27,2006 PowerPC 750GX Overview Page 37 o f 377 The syst em interf ace supp orts addr ess pi pelining , which al lows the address tenure o f one tran saction to overla p the data te nure of an other .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor PowerPC 750GX Overview Page 38 o f 377 gx_01.fm.(1.2) March 27,2006 Note: A bar ov er a si gnal na me indi cates that the si gnal is active l ow—for ex ample, AR TRY (addr ess retry) and TS (tr ansfer st art).
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_01.fm.(1.2) March 27,2006 PowerPC 750GX Overview Page 39 o f 377 Signal f unctio nality i s desc ribed in detail in Chapter 7, S ignal Descr iptions, on page 249 and Chap ter 8, B us Interfac e Operation , on pag e 2 79.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor PowerPC 750GX Overview Page 40 o f 377 gx_01.fm.(1.2) March 27,2006 1.2. 9 Clo ckin g The 750G X requires a sing le system clock input, S YSCLK, that r epresen ts the bus interfa ce frequen cy.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_01.fm.(1.2) March 27,2006 PowerPC 750GX Overview Page 41 o f 377 The P owerPC Ar chitectu re cons ists of t he followi ng layers , and ad herence to the PowerP C Architec ture c an be descr ibed in terms of which of t he followi ng level s of the arc hitecture i s imple mented.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor PowerPC 750GX Overview Page 42 o f 377 gx_01.fm.(1.2) March 27,2006 1.4 PowerPC Registers and Programming Model The PowerP C Archit ecture de fines r egister -to-regi ster oper ations fo r most co mputati onal in structi ons.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_01.fm.(1.2) March 27,2006 PowerPC 750GX Overview Page 43 o f 377 The OEA defines nu mero us Speci al-Pur pose Reg isters that se.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor PowerPC 750GX Overview Page 44 o f 377 gx_01.fm.(1.2) March 27,2006 Table 1 -3 describe s the SPRs i n 750GX that are n ot defin ed by the PowerPC A rchite cture.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_01.fm.(1.2) March 27,2006 PowerPC 750GX Overview Page 45 o f 377 1.5 Instruction Set All Powe rPC ins tructio ns are e ncoded as single -word ( 32-bit) in stru ctions.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor PowerPC 750GX Overview Page 46 o f 377 gx_01.fm.(1.2) March 27,2006 – T ranslat ion -loo kas i de-bu ffer managemen t instr uc tions These cate gories do not ind icate the execu tion u nit that ex ecutes a particu lar inst ructio n or group o f inst ruc- tions.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_01.fm.(1.2) March 27,2006 PowerPC 750GX Overview Page 47 o f 377 1.5.2 750GX Micr o pro ce ssor In stru ctio n Set 750GX ins truction set is defi ned as fol lows. • 750GX p rovides ha rdware sup port for all PowerP C instru ctions.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor PowerPC 750GX Overview Page 48 o f 377 gx_01.fm.(1.2) March 27,2006 1.7 Exception Model The foll owing se ctions d escribe th e PowerP C exception model and the 750 GX impl ementation .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_01.fm.(1.2) March 27,2006 PowerPC 750GX Overview Page 49 o f 377 The P owerPC A rchite cture su pports f our type s of exc eptions: 1.7.2 750GX Microprocessor Exception Implement ation The 750G X exce ption cl asses d escri bed above are show n in the Table 1 -4 .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor PowerPC 750GX Overview Page 50 o f 377 gx_01.fm.(1.2) March 27,2006 T abl e 1-5. Ex cepti ons a nd Co nditi ons Exception T ype V ector Of fset (hex) Causing Conditions Reserve d 00000 — System reset 00100 Assertion of either HRESET or S RESET or a power-on reset.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_01.fm.(1.2) March 27,2006 PowerPC 750GX Overview Page 51 o f 377 1.8 Memory Management The foll owing sub section s descri be the memo ry-man agement fea tures of the Powe rPC Ar chitectu re, and the 750GX i mplementa tion.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor PowerPC 750GX Overview Page 52 o f 377 gx_01.fm.(1.2) March 27,2006 1.8.2 7 50GX Mic roprocessor Memory-Ma nagement Imp lementation The 750G X impl ements se parate MM Us for i nstruct ions and data.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_01.fm.(1.2) March 27,2006 PowerPC 750GX Overview Page 53 o f 377 Note: Figure 1-5 does not s how fea tures such as reserva tion stati ons and r ename bu ffers tha t reduce stalls and im prove ins truction throughp ut.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor PowerPC 750GX Overview Page 54 o f 377 gx_01.fm.(1.2) March 27,2006 • The executi on units proce ss instruc tions from their rese rvatio n stations usin g the operand s provid ed from dispatch, an d notif ies the c omple tion stage when the in structi on has fi nished ex ecution .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_01.fm.(1.2) March 27,2006 PowerPC 750GX Overview Page 55 o f 377 In addition, the 750 GX allows softwa re-con trolled togg ling between two oper ating freq uencies .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor PowerPC 750GX Overview Page 56 o f 377 gx_01.fm.(1.2) March 27,2006 The TAU i s controll ed throu gh the pri vileged mtspr a nd mfspr instru ctions to the four SP Rs prov ided for configur ing and c ontroll ing th e sensor c ontrol l ogic.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 57 o f 377 2. Programm ing Model This cha pter d escribes the 750 GX prog ramm ing model , empha sizing those featu res sp ecific t o the 750G X processo r and su mmariz ing those that are com mon to P owerPC pro cessors.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 58 o f 377 gx_02.fm.(1.2) March 27, 2006 Figure 2-1. Power PC 750GX Micro processor Program ming M odel—Reg.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 59 o f 377 The PowerPC UISA regis ters are user- level. Genera l Purpose Registe rs (GPRs) and Floating Point Register s (FPRs) are acces sed thro ugh in struction o perands .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 60 o f 377 gx_02.fm.(1.2) March 27, 2006 “PowerPC R egiste r Set” of th e PowerP C Micropr ocessor Fa mily: T he Progra mming Env ironme nts Manual .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 61 o f 377 – Memory -mana gem ent re gis ters • Block-A ddress Translation (BA T) Regi sters.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 62 o f 377 gx_02.fm.(1.2) March 27, 2006 Register 1 ( SRR1)” in Chapter 2, “Po werPC Regi ster Set” of the PowerPC Mi crop rocess or Fam - ily: T he Program ming En vironmen ts Manual for more i nformatio n.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 63 o f 377 – Hardware -Implementat ion-Depe ndent Regis ter 0 ( HID0)—This.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 64 o f 377 gx_02.fm.(1.2) March 27, 2006 2.1. 2 Power PC 750GX-Specific Re gisters This sec tion de scribe s registe rs that ar e defined for the 75 0GX but a re not included in the Pow erPC Ar chite c- ture.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 65 o f 377 2.1.2.2 Hardwar e-Implem entation-De pendent Register 0 (HID0) The H ardware-Im plemen tation-Depen dent Reg ister 0 (HID0) controls the state o f several functions within 750GX.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 66 o f 377 gx_02.fm.(1.2) March 27, 2006 9N A P 2 Nap mode ena ble. Operates in conjunct ion with MSR[POW]. 0 Nap mode disabled. 1 Nap mode enabled. Doze mode is invoked by s etting MSR[POW] wh ile this bit is set.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 67 o f 377 18 ILOCK Instruction-cac he lock 0 Normal operation. 1 Instruction cache is locked. A locked cac he supplies data norm ally on a hit, but is treated as a cache-inhibited transaction on a miss.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 68 o f 377 gx_02.fm.(1.2) March 27, 2006 22 SPD Speculative cache access disable 0 Speculative bus accesses to nonguarded space (G = 0) from both the instruction and data caches are enabled.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 69 o f 377 29 BHT Branch history table enable 0 BHT disabled.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 70 o f 377 gx_02.fm.(1.2) March 27, 2006 2.1.2.3 Hardwar e-Implem entation-De pendent Register 1 (HID1) The H ardware-Im plemen tation-Depen dent Reg ister 1 (HID1) reflects the state o f the PL L_CFG[0:4] s ignals.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 71 o f 377 2.1.2.4 Hardwar e-Implem entation-De pendent Register 2 (HID2) The H ardware-Im plemen tation-Depen dent Reg ister 2 (HID2) enables par ity.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 72 o f 377 gx_02.fm.(1.2) March 27, 2006 2.1.2.5 Performan ce-Mon itor Regist ers Thi s sectio n desc ribe s .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 73 o f 377 User Monito r Mode Co ntrol Register 0 (UMMCR0 ) The content s of MM CR0 are refl ected to UM MCR0, whic h can be rea d by user- level soft ware.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 74 o f 377 gx_02.fm.(1.2) March 27, 2006 Monitor Mod e Control Register 1 (M MCR1) The M onitor M ode Contro l Registe r 1 (MM CR1) funct ions as an event s elector fo r Perform ance-Mo nitor Counter Re gisters 3 and 4 (PM C3 and P MC4).
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 75 o f 377 The foll owing tabl es lis t the sele ctabl e events a nd thei r encoding s: • T able 1 1-2, PMC1 Even ts—MMC R0 [19 :25 ] Sele ct Enc od ing s , on page 352.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 76 o f 377 gx_02.fm.(1.2) March 27, 2006 User Sa mpled Ins truction A ddress Register (USIA) The content s of S IA are refl ected to US IA, which can be read by user -level softw are.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 77 o f 377 2.1.3 Instruction Cache Throttling Control Register (ICTC) Reducing the rate o f inst ruction fetching can contr ol junc tion tempe rature w ithout t he comple xity an d over- head of dynamic clock c ontrol.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 78 o f 377 gx_02.fm.(1.2) March 27, 2006 2.1.4 Thermal-Ma nagement Re gisters ( THRMn) The on-ch ip therm al-.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 79 o f 377 2.1.4.2 Thermal -Managem ent Register 3 (THRM3) The THR M3 register is used to enabl e the ther mal assis t unit and t o contro l the timi ng of the ou tput sa mple compari son.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 80 o f 377 gx_02.fm.(1.2) March 27, 2006 2.1.4.3 Thermal -Managem ent Register 4 (THRM4) Due to proc ess and t hermal sens or varia tions, a temperat ure offset is prov ided that c an be read via an mfspr instruc tion to THRM 4.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 81 o f 377 2.1.5 L 2 Cache Co ntro l Register (L2CR) The L2 Ca che Contr ol Regis ter is a superv isor-level , impleme ntatio n-specifi c SPR us ed to conf igure an d operate t he L2 cache.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 82 o f 377 gx_02.fm.(1.2) March 27, 2006 2.2 Operand Conventions This sec tion des cribes the operand conventi ons as they are rep resented in two level s of the P owerPC A rchi- tecture— UISA and V EA.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 83 o f 377 2.2.3 Floating-Point Operand and Execution Models—UISA The IEEE 754-1 985 standa rd defines convention s for 64-bit and 32-bit arithm etic.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 84 o f 377 gx_02.fm.(1.2) March 27, 2006 2.2.3.3 Time-Critical Floating-Point Op eration For time- critica l .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 85 o f 377 Table 2 -6 summarize s the mode b ehavior fo r results .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 86 o f 377 gx_02.fm.(1.2) March 27, 2006 2.3 Instruction Set Summary This sec tion des cribes in structi ons and a ddress ing modes defined fo r the 750G X.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 87 o f 377 that the archite cture spec ificati on refer s to sim plified m nemonic s as ext ended mnem onics.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 88 o f 377 gx_02.fm.(1.2) March 27, 2006 2.3.1.3 Illegal Instruc tion Class Illegal i nstruc tions ca n be grou ped in to the fo llowing cate gories : • Instructio ns not defined i n the Power PC Archi tecture.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 89 o f 377 2.3.1.4 Reserve d Instruct ion Class Reserved i nstruc tions ar e alloca ted to sp ecific i mplementa tion- dependent p urposes not defin ed by the PowerPC Archit ecture.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 90 o f 377 gx_02.fm.(1.2) March 27, 2006 2.3.2.3 Effective Addr ess Calcu lation An effe ctive ad dress is th.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 91 o f 377 For exam ple, if t he mtmsr sets the MSR[P R] bit, unless an isy nc.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 92 o f 377 gx_02.fm.(1.2) March 27, 2006 Summa ry” in the Powe rPC Micropr ocessor Fa mily: T he Program ming E nvironment s Manu al .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 93 o f 377 Although there is no Su btract Im mediate in stru ction, it s effect can be a chieved by usin g an addi instruct ion with the immedia te operand negated .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 94 o f 377 gx_02.fm.(1.2) March 27, 2006 Integer L ogical In stru ctions The log ical ins tructi ons shown in Tabl e 2-9 on page 94 perform bit-paral lel oper ations on the specifi ed oper- ands.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 95 o f 377 The inte ger rotate i nstruc tions ar e summar ized in Table 2-1 0 . For more i nformation, see the Po werPC Micro- processo r Fami ly: The Progra mming En vironme nts Manua l .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 96 o f 377 gx_02.fm.(1.2) March 27, 2006 Double -preci sion arith metic i nstruc tions, ex cept tho se invol ving mul tipli cation ( fmul , fmadd , fms ub , fnmadd , fnmsub ) execute wi th the sam e late ncy as t heir singl e-precis ion e quivalen ts.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 97 o f 377 Example s of us es of these ins tructions to pe rform var ious conv.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 98 o f 377 gx_02.fm.(1.2) March 27, 2006 Note: The Pow erPC Arch itecture states th at, in some im plementa t.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 99 o f 377 Little En dian M isalign ed Acce sses The 750G X supp orts misa ligne d single regist er load- and-st ore acc esses in littl e-endian mode w ithout ca using an alignm ent excep tion.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 100 of 377 gx_02.fm.(1.2) March 27, 2006 Imp leme nta ti on N ote s —The following notes des cribe the 750G.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 101 o f 377 Integer Store Instr uctions For in teger sto re inst ruction s, the co ntents o f the s ource regi ster ( r S) are stor ed into the byte, half word, or word in m emory a ddressed b y the EA .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 102 of 377 gx_02.fm.(1.2) March 27, 2006 If store gathering is enabled and the stores do not f all under th e.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 103 o f 377 Integer L oad-and- S tore String Instru ctions The inte ger load-a nd-store s tring ins truction s allow m ovement o f data from memory to register s, or fro m registe rs to memor y, without conc ern for a lignment.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 104 of 377 gx_02.fm.(1.2) March 27, 2006 For softwa re compa tibil ity, th e other two mode e ncodings, imp recise-n onrecover able mod e and i mpre- cise -rec over able mode , de faul t to t he pr ecis e mod e .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 105 o f 377 Table 2 -24 summa rizes the si ngle -preci sion and doubl e-precis ion flo ating-poi nt store an d stfiwx i nstruct ions.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 106 of 377 gx_02.fm.(1.2) March 27, 2006 Archi tecturally , all si ngle-pr ecisio n and doub le-prec ision f loatin g-point n umbers are repre sented in double - precisio n form at within t he 750GX .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 107 o f 377 specula tively executed instruc tions a nd restore the mac hine sta te to im mediately after th e branch . This cor - rection can be do ne immedi ately up on resoluti on of th e Conditio n Registers bits.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 108 of 377 gx_02.fm.(1.2) March 27, 2006 T rap Inst ruction s The tr ap instruc tio ns show n in Tabl e 2-29 are prov ided to te st for a specif ied set of c ondition s.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 109 o f 377 Imp leme nta ti on N ote : The P owerPC A rchitecture i ndicate s .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 110 of 377 gx_02.fm.(1.2) March 27, 2006 DBAT7L 575 10001 11111 Su pervisor (OEA) Both DBAT7U 574 10001 11110.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 111 o f 377 TBL 2 268 01000 01100 User (VEA) mfspr 284 01000 11100 Supervisor (OEA) mtspr TBU 2 269 01000 01101 User (VEA) mfspr 285 01000 11101 Supervisor (OEA) mtspr XER 1 00000 00001 User (UI SA) B oth T able 2-33.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 112 of 377 gx_02.fm.(1.2) March 27, 2006 Enco dings for th e 750G X-speci fic SPRs are lis ted in Table 2-34 .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 113 o f 377 2.3.4.7 Memory Synchronization Inst ructions —UISA Memory synchr.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 114 of 377 gx_02.fm.(1.2) March 27, 2006 Table 2 -36 shows th e mftb instruc tion.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 115 o f 377 2.3.5.3 Memory Co ntrol Ins tructions—V EA Memory control instru.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 116 of 377 gx_02.fm.(1.2) March 27, 2006 Table 2 -38 summar izes th e cache ins tructio ns define d by the VEA . Note th at these i nstruction s are ac ces- sible to user-lev el progra ms.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 117 o f 377 2.3.5.4 Optional Extern al Contro l Instru ctions The P owerPC Ar .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 118 of 377 gx_02.fm.(1.2) March 27, 2006 output t he 4-bit re source ID (RID) field l ocated in the EAR. The eciwx in structi on als o loads a word fr om the data bu s that is output by the sp ecial de vice .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_02.fm.(1.2) March 27, 2006 Programming Model Page 119 o f 377 2.3.6.3 Memory Con trol Instr uctions—OE A Memory control instruc tions i nclude th e followin g. • Cache-m anagement i nstruc tions (su pervisor -level and user-lev el).
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Programming M odel Page 120 of 377 gx_02.fm.(1.2) March 27, 2006 T ra nslati on Looka side Buffer Ma nageme nt Instruc tions—(O EA).
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_03.fm.(1.2) March 27, 2006 Instruction- Cache and Data-Cache Opera tion Page 121 o f 377 3.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Instruction-Cache an d Data-Cache Operation Page 122 of 377 gx_03.fm.(1.2) March 27, 2006 Both cac hes are tig htly cou pled into the 750GX ’s bus interface u nit (BIU) to allow efficien t access to the system memo ry cont roller and ot her bus master s.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_03.fm.(1.2) March 27, 2006 Instruction- Cache and Data-Cache Opera tion Page 123 o f 377 3.1 D ata-Cache Orga nization The data cach e is organi zed a s 128 set s of eight ways as shown in Figure 3-2 .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Instruction-Cache an d Data-Cache Operation Page 124 of 377 gx_03.fm.(1.2) March 27, 2006 3.2 Instruction-C ache Organization The inst ructio n cache also co nsists of 128 se ts of e ight ways , as sho wn in Fi gure 3- 3 on page 125.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_03.fm.(1.2) March 27, 2006 Instruction- Cache and Data-Cache Opera tion Page 125 o f 377 3.3 Memory and Cache Coher ency The prima ry obje ctive of a cohere nt memory s ystem i s to provi de the sam e image of memory to all dev ices using the system .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Instruction-Cache an d Data-Cache Operation Page 126 of 377 gx_03.fm.(1.2) March 27, 2006 These b its allow bo th unip rocess or and m ultiproc essor s ystem des igns to exploit n umerous system-l evel perform ance opti mization s.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_03.fm.(1.2) March 27, 2006 Instruction- Cache and Data-Cache Opera tion Page 127 o f 377 The 750G X provid es dedic ated ha rdware t o provide m emory c oherenc y by sn ooping bus transa ction s.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Instruction-Cache an d Data-Cache Operation Page 128 of 377 gx_03.fm.(1.2) March 27, 2006 Sec t ion 3.7 , MEI St ate Tr ansactio ns, on page 147 provid es a detai led lis t of MEI tr ansitio ns for var ious ope r- ations an d WIM bit settin gs.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_03.fm.(1.2) March 27, 2006 Instruction- Cache and Data-Cache Opera tion Page 129 o f 377 Anothe r conside ratio n is pag e table al iasing.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Instruction-Cache an d Data-Cache Operation Page 130 of 377 gx_03.fm.(1.2) March 27, 2006 3.3.5 PowerPC 750GX-In itiated Loa d/Store Oper ations Load-and -store ope rations are assum ed to be weakly ord ered on t he 750GX.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_03.fm.(1.2) March 27, 2006 Instruction- Cache and Data-Cache Opera tion Page 131 o f 377 atomic a ccess to n oncohe rent memo ry. For deta iled info rmation o n these i nstruct ions, se e Chap ter 2, Pr o- grammin g Model, o n page 57.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Instruction-Cache an d Data-Cache Operation Page 132 of 377 gx_03.fm.(1.2) March 27, 2006 3.4.1.1 Data-Cac he Flash Invalidat ion The data cach e is autom aticall y inval idated whe n the 75 0GX is powe red up an d during a hard reset.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_03.fm.(1.2) March 27, 2006 Instruction- Cache and Data-Cache Opera tion Page 133 o f 377 3.4.1.4 Instructio n-Cache Flash Invali dation The inst ructio n cache is automa tically inva lidated wh en the 7 50GX is po wered up and dur ing a hard reset .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Instruction-Cache an d Data-Cache Operation Page 134 of 377 gx_03.fm.(1.2) March 27, 2006 are not bro adcast, unles s broadcas t is enable d through the HID 0[ABE] co nfigurati on bit.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_03.fm.(1.2) March 27, 2006 Instruction- Cache and Data-Cache Opera tion Page 135 o f 377 For this reason, av oid usin g dcbz for.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Instruction-Cache an d Data-Cache Operation Page 136 of 377 gx_03.fm.(1.2) March 27, 2006 3.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_03.fm.(1.2) March 27, 2006 Instruction- Cache and Data-Cache Opera tion Page 137 o f 377 Figure 3-5.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Instruction-Cache an d Data-Cache Operation Page 138 of 377 gx_03.fm.(1.2) March 27, 2006 If all eig ht blocks are valid, then a b lock is sel ected for replaceme nt accor ding to th e PLRU bit encoding s shown in Ta bl e 3-3 .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_03.fm.(1.2) March 27, 2006 Instruction- Cache and Data-Cache Opera tion Page 139 o f 377 The d ata-cache flush assi st bit, HID0 [DCFA], sim plifies the so ftware flushi ng proc ess.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Instruction-Cache an d Data-Cache Operation Page 140 of 377 gx_03.fm.(1.2) March 27, 2006 Burst tra nsact ions on th e 750GX alway s transf er eight words of d ata at a tim e, and are alig ned to a dou ble- word boun dary.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_03.fm.(1.2) March 27, 2006 Instruction- Cache and Data-Cache Opera tion Page 141 o f 377 3.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Instruction-Cache an d Data-Cache Operation Page 142 of 377 gx_03.fm.(1.2) March 27, 2006 3.6.3 Snooping The 750G X maint ains data-cac he coheren cy in ha rdware b y coord inating a ctivity be tween the data cac he, the bus i nterface log ic, the L2 cache, a nd the m emory sy stem.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_03.fm.(1.2) March 27, 2006 Instruction- Cache and Data-Cache Opera tion Page 143 o f 377 the data tr ansactions to mem ory in or der).
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Instruction-Cache an d Data-Cache Operation Page 144 of 377 gx_03.fm.(1.2) March 27, 2006 Write-with-kill 00110 A write-with-kill operation is a burst transaction initiated due to a castout, caching- enabled push, or s noop copy-back.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_03.fm.(1.2) March 27, 2006 Instruction- Cache and Data-Cache Opera tion Page 145 o f 377 3.6.5 T ransfer Attr ibutes In addition to the address and transfe r type signal s, the 750GX supports the tr ansfer attribute signals : TBST , TSIZ[0–2], WT , CI , and GB L .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Instruction-Cache an d Data-Cache Operation Page 146 of 377 gx_03.fm.(1.2) March 27, 2006 T able 3-6.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_03.fm.(1.2) March 27, 2006 Instruction- Cache and Data-Cache Opera tion Page 147 o f 377 3.7 M EI S t ate T ransactions Table 3 -7 shows ME I state transit ions for variou s opera tions.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Instruction-Cache an d Data-Cache Operation Page 148 of 377 gx_03.fm.(1.2) March 27, 2006 dcbst Data -cache- block store No xxx I, E Sam e dcbst . — Pass clean. Clean Same Same No act ion.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_03.fm.(1.2) March 27, 2006 Instruction- Cache and Data-Cache Opera tion Page 149 o f 377 tlbi e TLB invalidate No xxx x x Pas s TL B I. — No action. — sync Synchroniza- tion No xxx x x Pass sync.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Instruction-Cache an d Data-Cache Operation Page 150 of 377 gx_03.fm.(1.2) March 27, 2006.
User’s Ma nua l IBM PowerPC 750 GX and GL RISC Micropr o ces sor gx_04.fm.(1.2) March 27, 2006 Exceptions Page 151 o f 377 4. Exceptions The operat ing env ironme nt architec ture (OE A) portion of .
User’s M anual IBM PowerPC 750GX and GL RISC Micropro ces sor Exceptions Page 152 of 377 gx_04.fm.(1.2) March 27, 2006 Note: The PowerPC A rchitectu re docu mentation ref ers to exc eptions a s interrupts .
User’s Ma nua l IBM PowerPC 750 GX and GL RISC Micropr o ces sor gx_04.fm.(1.2) March 27, 2006 Exceptions Page 153 o f 377 4.2 Exception Recogni tion and Priorities Excepti ons are roughly pr ioritize d by e xceptio n class, as follows . 1. Nonmask able, async hronous excepti ons have priority over all other exc eptio ns.
User’s M anual IBM PowerPC 750GX and GL RISC Micropro ces sor Exceptions Page 154 of 377 gx_04.fm.(1.2) March 27, 2006 • Exception s cause d by asy nchronous events (inter rupts). These e xceptio ns are fu rther dis tinguish ed by whether th ey are m askable and recov erable.
User’s Ma nua l IBM PowerPC 750 GX and GL RISC Micropr o ces sor gx_04.fm.(1.2) March 27, 2006 Exceptions Page 155 o f 377 T abl e 4-3. Ex cepti on Pr iori tie s Priority Exception Cause Asynchronou.
User’s M anual IBM PowerPC 750GX and GL RISC Micropro ces sor Exceptions Page 156 of 377 gx_04.fm.(1.2) March 27, 2006 System reset a nd machi ne-check exc eptions ca n occur a t any time and are not delaye d even if an ex ception is being handled. As a res ult, stat e informa tion fo r an interr upted ex ception m ight be lost.
User’s Ma nua l IBM PowerPC 750 GX and GL RISC Micropr o ces sor gx_04.fm.(1.2) March 27, 2006 Exceptions Page 157 o f 377 4.3.2 Machine St atu s Save/Re store R egister 1 (S RR1) SRR1 is us ed t o .
User’s M anual IBM PowerPC 750GX and GL RISC Micropro ces sor Exceptions Page 158 of 377 gx_04.fm.(1.2) March 27, 2006 4.3.3 Machine St ate Register (MSR) Reserved POW Reserved ILE EE PR FP ME FE0 S.
User’s Ma nua l IBM PowerPC 750 GX and GL RISC Micropr o ces sor gx_04.fm.(1.2) March 27, 2006 Exceptions Page 159 o f 377 The IEEE flo ating-po int excep tion mo de bits (FE 0 and FE1) tog ether defi ne whether fl oating- point excepti ons are hand led prec isely, imprec isely, o r whether they ar e take n at all.
User’s M anual IBM PowerPC 750GX and GL RISC Micropro ces sor Exceptions Page 160 of 377 gx_04.fm.(1.2) March 27, 2006 4.3.4 Enabling and Disabling Exceptions When a c ondition e xists t hat mig ht cause an excep tion to be gener ated, it mus t be de termined whe ther th e excepti on is ena bled fo r that co ndition.
User’s Ma nua l IBM PowerPC 750 GX and GL RISC Micropr o ces sor gx_04.fm.(1.2) March 27, 2006 Exceptions Page 161 o f 377 0x000 n_n nnn . If IP i s set, except ions are vec tored to the physical ad dress 0x FFF n_nnnn .
User’s M anual IBM PowerPC 750GX and GL RISC Micropro ces sor Exceptions Page 162 of 377 gx_04.fm.(1.2) March 27, 2006 4.4 Process Switching The foll owing ins tructions are use ful for res toring p roper cont ext du ring proc ess swit ching: • The Sy nchr oni za tio n ( sync ) instruc tion ord ers the e ffects of in structi on exec ution.
User’s Ma nua l IBM PowerPC 750 GX and GL RISC Micropr o ces sor gx_04.fm.(1.2) March 27, 2006 Exceptions Page 163 o f 377 The set ting of the excep tion pre fix bit (IP ) determ ines how e xceptio ns are v ectored . If the bit i s clea red, excepti ons are vec tored to the physic al addres s 0x000 n _nnnn (where n nnnn is the vecto r offset).
User’s M anual IBM PowerPC 750GX and GL RISC Micropro ces sor Exceptions Page 164 of 377 gx_04.fm.(1.2) March 27, 2006 4.5.1.1 Soft Rese t If SRE SET is ass erted, the processor is firs t put in a recover able sta te.
User’s Ma nua l IBM PowerPC 750 GX and GL RISC Micropr o ces sor gx_04.fm.(1.2) March 27, 2006 Exceptions Page 165 o f 377 The har d reset ex ceptio n is a no nrecover able, nonm aska ble, asy nchronous exce ption.
User’s M anual IBM PowerPC 750GX and GL RISC Micropro ces sor Exceptions Page 166 of 377 gx_04.fm.(1.2) March 27, 2006 T able 4-7. Settings Ca used b y Hard Rese t Register Setting BATs Un known Cache, instruction cache, and data cache All blocks are unc hanged from before HRES ET .
User’s Ma nua l IBM PowerPC 750 GX and GL RISC Micropr o ces sor gx_04.fm.(1.2) March 27, 2006 Exceptions Page 167 o f 377 The foll owing is also tr ue after a hard re set oper ation: • Externa l check stops are enab led. • The on-ch ip test i nterface has given c ontrol o f the I/Os to the rest o f the chip for func tional us e.
User’s M anual IBM PowerPC 750GX and GL RISC Micropro ces sor Exceptions Page 168 of 377 gx_04.fm.(1.2) March 27, 2006 A TEA indicat ion o n the b us can re sult fr om any load or stor e oper ation i nitiated by the pro cessor.
User’s Ma nua l IBM PowerPC 750 GX and GL RISC Micropr o ces sor gx_04.fm.(1.2) March 27, 2006 Exceptions Page 169 o f 377 When a machine -check exc eption is take n, instruct ion fetc hing re sumes at offset 0x00200 fr om the ph ysical base addr ess in dicated b y MSR [IP].
User’s M anual IBM PowerPC 750GX and GL RISC Micropro ces sor Exceptions Page 170 of 377 gx_04.fm.(1.2) March 27, 2006 stops di spatchi ng and waits f or all p ending in structi ons to co mplete . This all ows any i nstruc tions in progress that nee d to take a n except ion to do s o before the exter nal inter rupt is taken.
User’s Ma nua l IBM PowerPC 750 GX and GL RISC Micropr o ces sor gx_04.fm.(1.2) March 27, 2006 Exceptions Page 171 o f 377 4.5.8 Floating-Po int Una vailable Exce ption (0 x00800) The floa ting-poi nt unavai lable ex ception is im plemented as def ined in th e PowerP C Architec ture.
User’s M anual IBM PowerPC 750GX and GL RISC Micropro ces sor Exceptions Page 172 of 377 gx_04.fm.(1.2) March 27, 2006 4.5.13 Performance-Monitor I nterrupt (0x00 F00) The 750G X microp rocess or pr.
User’s Ma nua l IBM PowerPC 750 GX and GL RISC Micropr o ces sor gx_04.fm.(1.2) March 27, 2006 Exceptions Page 173 o f 377 4.5.14 Instruct ion Addre ss Brea kpoint Exc eption ( 0x01300 ) An in struc.
User’s M anual IBM PowerPC 750GX and GL RISC Micropro ces sor Exceptions Page 174 of 377 gx_04.fm.(1.2) March 27, 2006 Like the external interrupt , a system m anagem ent interru pt is signa led to t he 750GX by the as sertion of an input sign al.
User’s Ma nua l IBM PowerPC 750 GX and GL RISC Micropr o ces sor gx_04.fm.(1.2) March 27, 2006 Exceptions Page 175 o f 377 The t hermal- managemen t interrupt is sim ilar to the s ystem m anagement a nd ex ternal inter rupt.
User’s M anual IBM PowerPC 750GX and GL RISC Micropro ces sor Exceptions Page 176 of 377 gx_04.fm.(1.2) March 27, 2006 4.5.19 Exception Latencies Latencie s for tak ing var ious exce ptions ar e vari able bas ed on the s tate of t he machin e when c ondition s to produce an exc eption occur.
User’s Ma nua l IBM PowerPC 750 GX and GL RISC Micropr o ces sor gx_04.fm.(1.2) March 27, 2006 Exceptions Page 177 o f 377 4.5.21 Timer Facilities At power -on r eset (POR) , the 750G X initi alizes.
User’s M anual IBM PowerPC 750GX and GL RISC Micropro ces sor Exceptions Page 178 of 377 gx_04.fm.(1.2) March 27, 2006.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_05.fm.(1.2) March 27, 2006 Memory M anagement Page 179 o f 377 5. Memo ry Man agement This ch apter describe s the 750GX mic rop.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Memory Management Page 180 of 377 gx_05.fm.(1.2) March 27, 2006 Basic features of the 7 50GX MMU imple mentation defined by the O EA .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_05.fm.(1.2) March 27, 2006 Memory M anagement Page 181 o f 377 5.1.1 M emory Add ressing A progr am referen ces memo ry using t .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Memory Management Page 182 of 377 gx_05.fm.(1.2) March 27, 2006 the mem ory subs ystem.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_05.fm.(1.2) March 27, 2006 Memory M anagement Page 183 o f 377 Figure 5-1. MMU Concep tual Block Diagram Optional Instructio n A.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Memory Management Page 184 of 377 gx_05.fm.(1.2) March 27, 2006 Figure 5-2. Power PC 750GX Mi cropr ocessor IM MU Bl ock Diag ram BPU.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_05.fm.(1.2) March 27, 2006 Memory M anagement Page 185 o f 377 Figure 5-3. 750GX Mi croproc essor D MMU Bloc k Diagra m DTLB DBA.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Memory Management Page 186 of 377 gx_05.fm.(1.2) March 27, 2006 5.1.3 Address-T ranslat ion Mechan isms PowerPC proces sors supp ort .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_05.fm.(1.2) March 27, 2006 Memory M anagement Page 187 o f 377 When t he proce ssor gener ates an access, an d the c orrespond i.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Memory Management Page 188 of 377 gx_05.fm.(1.2) March 27, 2006 The no-ex ecute opti on prov ided in th e segment registe r lets th e operating system program determi ne whether in structi ons can be fetched from an area of memory.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_05.fm.(1.2) March 27, 2006 Memory M anagement Page 189 o f 377 5.1.6 General Fl ow of MMU Ad dress T ranslation The foll owing se ctions d escribe th e general flow use d by PowerP C process ors to tran slate effe ctive address es to vi rtual an d then phy sical addr esses.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Memory Management Page 190 of 377 gx_05.fm.(1.2) March 27, 2006 5.1.6.2 Page-A ddress-Trans lation Selec tion If addres s trans lation i s enabled and the effect ive addr ess inf ormation does n ot match a BAT arr ay entry , then the segment descriptor must be locat ed.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_05.fm.(1.2) March 27, 2006 Memory M anagement Page 191 o f 377 Figure 5-6. General Flow of Page and D irect- S t ore Inter face .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Memory Management Page 192 of 377 gx_05.fm.(1.2) March 27, 2006 If the T b it in the S egment Regi ster is cleared (S R[T] = 0 ), then pag e-addre ss transl ation is selecte d. The informat ion in the segme nt des criptor i s then us ed to ge nerate the 52-bit v irtual address .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_05.fm.(1.2) March 27, 2006 Memory M anagement Page 193 o f 377 The state sav ed by the proces sor for each of these exce ptions con tains inform ation tha t identifies the ad dress of the faili ng instru ction.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Memory Management Page 194 of 377 gx_05.fm.(1.2) March 27, 2006 5.1.8 MMU Instru ctions and Re gister Su mmary The MMU instruc tions and reg isters allo w the operating sy stem to set up the block- address- transla tion areas and the pag e table s in mem ory.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_05.fm.(1.2) March 27, 2006 Memory M anagement Page 195 o f 377 Figure 5- 6 summa rizes the reg isters tha t the op erating sy stem use s to progra m the 750G X’s MMU s. Th ese registe rs are access ible to s uper visor-lev el so ftware onl y.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Memory Management Page 196 of 377 gx_05.fm.(1.2) March 27, 2006 For infor matio n on the sy nchroniz ation req uiremen ts for chan ges to MSR[IR] and M SR[DR], see Section 2.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_05.fm.(1.2) March 27, 2006 Memory M anagement Page 197 o f 377 page-add ress tran slation and not for transl ations ma de with the BAT mec hanism or for a ccesses that corre- spond to d irect-st ore (T = 1) segments .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Memory Management Page 198 of 377 gx_05.fm.(1.2) March 27, 2006 • Accesse s that cau se exce ptions an d are not complete d.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_05.fm.(1.2) March 27, 2006 Memory M anagement Page 199 o f 377 For more informat ion, see “ Page His tory Re cording ” in C hapter 7, “Memory M anagem ent,” of the Power PC Microp rocess or Fam ily: The P rogram ming Env ironmen ts Manual .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Memory Management Page 200 of 377 gx_05.fm.(1.2) March 27, 2006 Each TLB co ntains 12 8 entries organi zed as a 2-way s et-associ ative ar ray wit h 64 se ts as sh own in Figure 5- 7 for the DTLB (the I TLB or ganizati on is the same).
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_05.fm.(1.2) March 27, 2006 Memory M anagement Page 201 o f 377 To uniq uely ide ntify a TLB ent ry as the r equired PTE, ea ch TLB entry cont ains, in additi on to the PTE, a n additiona l 4-bit field cal led the E xtended P age Index (EPI).
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Memory Management Page 202 of 377 gx_05.fm.(1.2) March 27, 2006 Other th an the pos sible TLB miss o n the next instruc tion pre fetc.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_05.fm.(1.2) March 27, 2006 Memory M anagement Page 203 o f 377 Figure 5-8. Page-Ad dress- T ranslatio n Flow—T LB Hit (See The.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Memory Management Page 204 of 377 gx_05.fm.(1.2) March 27, 2006 5.4.5 Page T able- Sea rch Operat ion If the trans lation i s not found i n the TLB s (a TLB m iss), the 75 0GX ini tiates a ta ble-sea rch operat ion, whi ch is describe d in thi s secti on.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_05.fm.(1.2) March 27, 2006 Memory M anagement Page 205 o f 377 Figure 5-9. Prim ary Pa ge T abl e Search (From Figure 5-10 on pa.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Memory Management Page 206 of 377 gx_05.fm.(1.2) March 27, 2006 The l oad stor e unit (LSU ) initia tes out-o f-order acc esses w ithout k nowin g whether it i s legal to do so.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_05.fm.(1.2) March 27, 2006 Memory M anagement Page 207 o f 377 5.4.6 Page T able Updates When T LBs ar e implem ented (as in the 750GX), t hey a re defin ed as non coher ent caches of t he page ta bles.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Memory Management Page 208 of 377 gx_05.fm.(1.2) March 27, 2006.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 209 o f 377 6. Instruction Ti ming This cha pter d escribes how the PowerPC 7 50GX mi croproce ssor fe tches, di spatche s, and ex ecutes i nstruc- tions and ho w it reports the r esults of in stru ction execut ion.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 210 of 377 gx_06.fm.(1.2) March 27, 2006 Fetch The process o f brin ging ins tructio ns from t he syste m memory (such as a cache or the main m emory) i nto the ins tructio n queue.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 211 o f 377 6.2 Instruction T iming Overvi ew The 750G X design m inimiz es a.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 212 of 377 gx_06.fm.(1.2) March 27, 2006 • 64-bit floa ting- point unit (FPU) • Load/stor e unit ( LSU) • Syst em regi ster unit (S RU) Figure 6- 1 repres ents a gene ric pipel ined e xecution unit.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 213 o f 377 The inst ruction pi peli ne stages are descr ibed as follows: •.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 214 of 377 gx_06.fm.(1.2) March 27, 2006 The nota tion conv ention s used i n the ins truction timing ex amples are as fo llows: Figure 6- 3 shows the stages of the 750GX’s e xecution units .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 215 o f 377 6.3 Timing Considerations The 7 50GX is a supers calar pro cessor.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 216 of 377 gx_06.fm.(1.2) March 27, 2006 The 750GX’s in structi on-cache throttlin g feature, manage d.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 217 o f 377 6.3.2.1 Cache Arb itratio n When th e instru ction fetc her request s ins truction s from the i nstruct ion cach e, two thin gs might h appe n.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 218 of 377 gx_06.fm.(1.2) March 27, 2006 Figure 6-4. Instruct ion Flow Di agram SRU IU2 FPU Complete (Re.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 219 o f 377 Figure 6- 5 on page 220 shows a s imple exam ple of instruc tion fetc hing that h its in th e L1 ca che.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 220 of 377 gx_06.fm.(1.2) March 27, 2006 Figure 6-5. Instructio n Timing—C ache Hit 6 fadd 1 fadd 0 ad.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 221 o f 377 The instr uction ti ming for this ex ample is des cribe d cycle-by- cycle as follows : 1. In cycle 0 , inst ructions 0 –3 are fetched from the in structi on ca che.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 222 of 377 gx_06.fm.(1.2) March 27, 2006 10. In cycle 9 , inst ruction 1 1 comple tes, ins truction 12 co ntinues th rough the FPU p ipeline , and in structi ons 13 and 14 a re dispatc hed.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 223 o f 377 Figure 6-6. Instruc tion Timing—C ache M iss 6 fadd * 7 fadd * .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 224 of 377 gx_06.fm.(1.2) March 27, 2006 6.3.2.4 L2 Cach e Access Timing Co nsideratio ns If an inst ruction fetch miss es both the BTIC and the L1 ins truction c ache, the 750GX ne xt look s in the L 2 cache.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 225 o f 377 When t he dispat ch unit di spatches a n instr uction to its exec ution uni t, it allo cates a Re name Re gister (o r registe rs) for t he resul ts of that i nstruc tion.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 226 of 377 gx_06.fm.(1.2) March 27, 2006 Perfor mance feat ures su ch as br anch fol ding, BT IC, dynami.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 227 o f 377 Figure 6- 8 shows the remov al of fa ll-throug h branch instru ctions, wh ich occ urs when a branch is not tak en or is pred icted as not taken .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 228 of 377 gx_06.fm.(1.2) March 27, 2006 In this ex ample, th e Branch Co nditio nal ( bc ) instr uction i s encod ed to decr ement the CTR. It is predict ed as not- tak en in c lock cycle 0.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 229 o f 377 does not w rite b ack its r esults t o the ar chitec ted regist ers. In stead, it s talls i n the com pletio n queue .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 230 of 377 gx_06.fm.(1.2) March 27, 2006 Predic ted Bran ch Timin g Exam ples Figure 6- 10 on page 231 shows ca ses wh ere branch instru ctions ar e predic ted.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 231 o f 377 1. During cloc k cycle 0, ins tructi ons 0 and 1 are dis patched to their res pective executio n units. Instruc tion 2 is a bran ch instru ction that updates the CT R.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 232 of 377 gx_06.fm.(1.2) March 27, 2006 2. In clock c ycle 1, instruc tions 2 and 3 enter the dis patch entrie s in the IQ . Instru ction 4 ( a secon d bc instruc tion) a nd 5 are fe tched.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 233 o f 377 6.4.5 L oad/Store Unit E xecution Timing The exe cution of most load -and-st ore instr uctions is pipe lined. The L SU has two pipel ine stage s.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 234 of 377 gx_06.fm.(1.2) March 27, 2006 6.4.7 Integer Store Gathering The 750GX perform s store gatheri ng for write- through operatio ns to nong uarded s pace.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 235 o f 377 6.5 Memory Performance Considerations Beca use the 750GX c an have a maximu m instr uction t hroug hput of thr ee inst ruction s per c lock cy cle, lac k of memory bandwidt h can affect performa nce.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 236 of 377 gx_06.fm.(1.2) March 27, 2006 6.5.2 Effect of TL B Miss If a page-ad dress tran slation i s not in a tra nslation lookaside bu ffer (TLB) , the 750GX hardware se arches the page table s and updates th e TLB when a transla tion is fo und.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 237 o f 377 6.6.1 Branch, Dispatch, and Completion-Unit Resource Requirement .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 238 of 377 gx_06.fm.(1.2) March 27, 2006 • Requirem ents for com pleting a n instru ction from CQ1: – Instructio n in CQ0 must comp lete in s ame cycle .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 239 o f 377 Move-from Spe cial Purpose Register mfspr (data block-addre ss tr.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 240 of 377 gx_06.fm.(1.2) March 27, 2006 Table 6 -6 list s condit ion r egiste r logica l instr uction latenc ies. Table 6 -7 shows in teger instruc tion late ncies.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 241 o f 377 AND Immediate Shifted andis.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 242 of 377 gx_06.fm.(1.2) March 27, 2006 Table 6 -8 shows la tencie s for float ing-poin t ins truction s. Pipel ined floa ting- point instr uctions are show n with the number of cloc ks in e ach pipelin e stag e separated by dashe s.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 243 o f 377 Floating Multiply- Subtract Single fmsubs [ . ] 59 28 FPU 1-1-1 — Floating Multiply- Subtract fmsub [ . ] 63 28 FPU 2-1-1 — Floating Multiply Single fm uls [ .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 244 of 377 gx_06.fm.(1.2) March 27, 2006 Table 6 -9 shows l oad-and-s tore ins truction latencies . Pipeli ned loa d/store i nstruct ions are sho wn with cy cles of total la tency an d through put cycles separa ted by a c olon.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 245 o f 377 Load Floating-Point Single Indexed lfsx 31 535 LS U 2:1 — Load .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 246 of 377 gx_06.fm.(1.2) March 27, 2006 Store Floating-Point Double stfd 54 — LSU 2:1 — Store Float.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_06.fm.(1.2) March 27, 2006 Instruction Timing Page 247 o f 377 Store Word with Update Indexed stwux 31 183 LS U 2:1 — Store Word I ndexed stwx 31 151 LS U 2:1 — TLB Invalidate Entry tlbie 31 306 LSU 3:4 1 Execution T able 6-9.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor In str ucti on T imi ng Page 248 of 377 gx_06.fm.(1.2) March 27, 2006.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_07.fm.(1.2) March 27, 2006 Signal Descriptions Page 249 o f 377 7. Signal Descriptions This cha pter d escribes the 750G X micropr ocess or’s externa l signa ls.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Signal Descriptions Page 250 of 377 gx_07.fm.(1.2) March 27, 2006 7.1 Signal Configuration Figure 7- 1 illustr ates the 7 50GX’s signal config uration, sh owing h ow the sig nals ar e grouped .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_07.fm.(1.2) March 27, 2006 Signal Descriptions Page 251 o f 377 7.2 Signal Descriptions This sec tion sum marizes th e func tions of i ndividual signa ls on the 750GX, g rouped ac cording to Figure 7-1 .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Signal Descriptions Page 252 of 377 gx_07.fm.(1.2) March 27, 2006 7.2.1.2 Bus Gra nt (BG )—Input 7.2.1.3 Address Bu s Busy (ABB ) The addres s bus b usy (ABB ) signa l is both an inpu t and an o utput s ignal.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_07.fm.(1.2) March 27, 2006 Signal Descriptions Page 253 o f 377 Addres s Bus B usy (A BB ) — Input 7.2.2 Address T ransfer Start Signals Addres s trans fer start s ignals a re in put and out put signa ls tha t indicat e that a n addres s-bus t ransfer has begun.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Signal Descriptions Page 254 of 377 gx_07.fm.(1.2) March 27, 2006 7.2. 3 Addr ess T ran sfer Sig nals The addres s transfer signal s are used to trans mit the add ress a nd to gener ate and mo nitor parity for the address transfe r.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_07.fm.(1.2) March 27, 2006 Signal Descriptions Page 255 o f 377 7.2.3.2 Addres s-Bus Pari ty (AP[ 0–3]) The a ddress-b us pari.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Signal Descriptions Page 256 of 377 gx_07.fm.(1.2) March 27, 2006 7.2.4.1 Transfe r T ype (TT[0–4]) The transfe r type (TT [0–4]) sig nals cons ist of five i nput/out put signals on the 750GX .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_07.fm.(1.2) March 27, 2006 Signal Descriptions Page 257 o f 377 Table 7 -2 describe s the 6 0x bus spec ificati on trans fer enco dings and the 750 GX bus snoop respons e on an address h it.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Signal Descriptions Page 258 of 377 gx_07.fm.(1.2) March 27, 2006 7.2.4.2 Transfer Size (TS IZ [0–2] ) —O utpu t eieio Addres s o.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_07.fm.(1.2) March 27, 2006 Signal Descriptions Page 259 o f 377 7.2.4.3 Transfer Burst (TBST ) The tra nsfer burs t (TBST ) signal i s an inp ut/outpu t signal on t he 750G X.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Signal Descriptions Page 260 of 377 gx_07.fm.(1.2) March 27, 2006 7.2.4.4 Cache In hibit (CI )—Output The cach e inhib it (CI ) signal i s an outpu t signal on the 7 50GX. 7.2.4.5 Wri te-Through (WT )—Outpu t The write- through (WT ) signa l is an output s ignal on the 750GX .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_07.fm.(1.2) March 27, 2006 Signal Descriptions Page 261 o f 377 7.2.4.6 Global (G BL ) The glo bal (GBL ) s ignal is an input/ output sig nal on the 750GX.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Signal Descriptions Page 262 of 377 gx_07.fm.(1.2) March 27, 2006 7.2.5 Address T ransf er T er mination Signals The addres s transfe.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_07.fm.(1.2) March 27, 2006 Signal Descriptions Page 263 o f 377 7.2.5.2 Addres s Retry (ARTRY ) The addres s retry (ARTRY ) si gnal is b oth an inp ut and o utput sign al on the 750GX .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Signal Descriptions Page 264 of 377 gx_07.fm.(1.2) March 27, 2006 Addres s Retr y (ARTR Y )—Input 7.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_07.fm.(1.2) March 27, 2006 Signal Descriptions Page 265 o f 377 7.2.6.2 Data-Bus Write-O nly (DBWO ) The data- bu s wri te- onl y (D BWO ) signal is an input- only s ignal on t he 750G X.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Signal Descriptions Page 266 of 377 gx_07.fm.(1.2) March 27, 2006 Data Bu s Busy (D BB )—Input 7.2.7 Data-T r ansfer S igna ls Like the address transfe r signa ls, the da ta-transfer signal s are used to trans mit data an d to gen erate and monitor parity f or the data transfe r.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_07.fm.(1.2) March 27, 2006 Signal Descriptions Page 267 o f 377 Data Bus (DH[ 0–31], DL[0–3 1])—Outp ut Data Bus (DH[ 0–31], DL[0–3 1])—In put 7.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Signal Descriptions Page 268 of 377 gx_07.fm.(1.2) March 27, 2006 Data-Bus Pa rity (DP[ 0–7])— Input 7.2.7.3 Data Bus Disable (DBDIS )—Input 7.2.8 Data-T r ansfer T ermi nation Signals Data termi nation s ignals a re requir ed after e ach data b eat in a da ta transfe r.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_07.fm.(1.2) March 27, 2006 Signal Descriptions Page 269 o f 377 7.2.8.2 Data Retr y (DRTRY )—Input 7.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Signal Descriptions Page 270 of 377 gx_07.fm.(1.2) March 27, 2006 7.2.9 System St atus Signals Most sy stem stat us signa ls are inp ut signal s that indicate when exc eptions a re receiv ed, whe n checkst op conditio ns have occu rred, and whe n the 75 0GX mus t be res et.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_07.fm.(1.2) March 27, 2006 Signal Descriptions Page 271 o f 377 7.2.9.3 Machin e-Check Interrupt ( MCP )—Input 7.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Signal Descriptions Page 272 of 377 gx_07.fm.(1.2) March 27, 2006 7.2.10 Reset Sig nals There ar e two rese t signal s on th e 750GX— hard re set (HRESET ) a nd soft r eset (SRESET ).
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_07.fm.(1.2) March 27, 2006 Signal Descriptions Page 273 o f 377 7.2.1 1 Pro cessor Status Signals Process or status signal s indic ate the sta te of the proces sor.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Signal Descriptions Page 274 of 377 gx_07.fm.(1.2) March 27, 2006 7.2.1 1.4 Time Base Enable (TBEN)—Input 7.2.1 1.5 TLB Invalidate Synchronize (TLBISYNC )—Input The TLB In vali date Sync hroniz e (TLBIS YNC ) s ignal i s an input-o nly signal.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_07.fm.(1.2) March 27, 2006 Signal Descriptions Page 275 o f 377 7.2.13 I/O V oltage Select Sign als Table 7 -7 shows the settings for the I/ O vo ltage sig nals.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Signal Descriptions Page 276 of 377 gx_07.fm.(1.2) March 27, 2006 7.2.14.3 L1_TS TCLK 7.2.14.4 L2_TS TCLK 7.2.14.5 BVSE L 7.2.15 Clock Sign als The 750 GX requ ires a s ingle s ystem c lock inpu t (SYS CLK).
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_07.fm.(1.2) March 27, 2006 Signal Descriptions Page 277 o f 377 7.2.15.1 System Clock (SYSCLK)—Input The 750G X requires a single syst em clock (SYSCLK) i nput. This inpu t sets the frequency of operatio n for the bus interfa ce.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Signal Descriptions Page 278 of 377 gx_07.fm.(1.2) March 27, 2006 7.2.15.4 PLL Range (PLL_RNG[0:1])—Input 7.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 279 o f 377 8. Bus Interface Operat ion This cha pter desc ribes the PowerPC 750GX mi croproc essor’s bus inter face and its oper ation.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 280 of 377 gx_08.fm.(1.2) March 27, 2006 8.1 B us Interfac e Overvie w The bus interface p riori tizes r.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 281 o f 377 In additio n to the loads, s tores, and i nstruc tion fetch .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 282 of 377 gx_08.fm.(1.2) March 27, 2006 Cache li nes are selected for replac ement bas ed on a pseudo l east-rec ently-use d (PLRU) al gorithm. Each time a cache li ne is access ed, it is tagged as the most-rec ently- used line of the se t.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 283 o f 377 one, two, or eight bea ts dep ending on the size of the p rogram transactio n and th e cache mod e for t he address .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 284 of 377 gx_08.fm.(1.2) March 27, 2006 8.2 M em ory-Ac ce ss Prot ocol Memory accesses are d ivided i nto addr ess and data tenures. Each te nure has three phases —bus ar bitration, transfer, a nd termi nation.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 285 o f 377 Data tenur e: The 750G X generate s an a ddress-o nly bus tr.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 286 of 377 gx_08.fm.(1.2) March 27, 2006 8.2.2 Miss-under-Miss To improv e proce ssor p erforma nce, a f.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 287 o f 377 data cac he. If ther e is a m iss in the L2 cache , then t he request i s pass ed on to th e bus interfac e unit ( BIU) via three add itional L 2-to-B IU reload-r equest qu eues.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 288 of 377 gx_08.fm.(1.2) March 27, 2006 The BIU has both AR buffers and a 4-deep relo ad-requ est queue.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 289 o f 377 Load mu ltiple a nd load s tring in structions allow on e MuM ( two outsta nding miss requ ests) to pipelin e on the 60x bu s.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 290 of 377 gx_08.fm.(1.2) March 27, 2006 8.2.2.2 Speculative Loads and Conditional Branches Loads tha t are d ispatch ed before a preced ing cond itiona l branc h is resol ved are specula tive.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 291 o f 377 Externa l arbiters must al low only one devi ce at a tim e to be the addre ss-bus m aste r.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 292 of 377 gx_08.fm.(1.2) March 27, 2006 System designer s shoul d note that it is pos sible t o ignore the ABB s ignal, a nd regene rate the s tate of AB B loca lly within each dev ice by mon itoring th e TS and AACK inp ut signals.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 293 o f 377 Figur e 8-8.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 294 of 377 gx_08.fm.(1.2) March 27, 2006 8.3.2.1 Addres s-Bus Pari ty The 750GX always generates 1 bit of c orrect od d-byte par ity for eac h of the 4 bytes o f addres s when a valid address is on th e bus.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 295 o f 377 The bas ic cohere ncy si ze of the bu s is def ined to be 32 b ytes (cor respon ding to one cac he line).
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 296 of 377 gx_08.fm.(1.2) March 27, 2006 8.3.2.4 Effect of Align ment in Dat a Transfers Table 8 -4 lists the align ed trans fers that ca n occur on the 750 GX bus.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 297 o f 377 The 7 50GX suppo rts misal igned mem ory ope rations, althou gh their use can sub stantial ly degr ade perfor- mance.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 298 of 377 gx_08.fm.(1.2) March 27, 2006 Effect of Align ment in Data T ransfers (32-Bi t Bus) The aligne d data-tr ansfer cas es for 32- bit data-bus mode are shown i n Table 8-6 on page 298.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 299 o f 377 Misali gned da ta transf ers when the 750GX is con figur ed .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 300 of 377 gx_08.fm.(1.2) March 27, 2006 8.3.2.5 Alignment of External Control Instructions The size o f the data tr ansfer ass ociated with th e eciwx an d ecowx instru ctions is a lways 4 bytes.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 301 o f 377 address tenures occur un til the cu rrent s noop pu sh from the 750GX is com pleted.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 302 of 377 gx_08.fm.(1.2) March 27, 2006 A qualif ied dat a-bus g rant can b e expre ssed as the follow ing: QDBG = DBG asserted wh ile DBB , DRTRY , and ARTRY (as sociat ed with the data-bus operatio n) are negated.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 303 o f 377 8.4.2 Data-Bus W rite-Only As a re sult of ad dress p ipelini ng, the 7 50GX can h ave up to t wo data t enure s queued t o perfor m when it receiv es a quali fied DBG .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 304 of 377 gx_08.fm.(1.2) March 27, 2006 (or only) data bea t, the 75 0GX nega tes DBB b ut still conside rs the da ta beat active a nd waits fo r another assert ion of TA .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 305 o f 377 Normal te rmination o f a burst transfer o ccurs whe n TA is a sserted for four bus clock cycl es, as shown in Figure 8- 13 .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 306 of 377 gx_08.fm.(1.2) March 27, 2006 For read bursts, DRT RY can b e asserted one bus clock c ycle a.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 307 o f 377 Figure 8- 15 show s the eff ect o f using DRT RY dur ing a bu rst re ad. It al so show s the effect o f usi ng TA to pace the data- transfer rate.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 308 of 377 gx_08.fm.(1.2) March 27, 2006 Note: T EA generate s a ma chine- check e xception depend ing on MS R[ME].
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 309 o f 377 8.5 Tim ing Examples This s ection s hows t iming di agrams f or va rious sc enarios . Figu re 8- 17 on page 310 illus trates th e fastest single- beat rea ds poss ible for the 750GX .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 310 of 377 gx_08.fm.(1.2) March 27, 2006 Figure 8-17. Fastest S ingle-B eat Reads BR BG ABB TS A[0–31].
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 311 o f 377 Figure 8- 18 illu strates the fastes t single -beat writes sup ported by the 75 0GX. Al l bidirect ional signals are tristate d between bu s tenu res.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 312 of 377 gx_08.fm.(1.2) March 27, 2006 Figure 8- 19 shows three way s to del ay single- beat rea ds using data-del ay control s: • The TA sign al can r emain neg ated to insert w ait states in cloc k cyc les 3 and 4.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 313 o f 377 Figure 8- 20 shows data-del ay contro ls in a s ingle- beat write operatio n. Note th at all bi directiona l signal s are tristate d between bu s tenu res.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 314 of 377 gx_08.fm.(1.2) March 27, 2006 Figure 8- 21 shows the use o f data-del ay control s wit h burst tra nsfers. Note that all bidi rectional signals are tristate d bet ween bus tenure s.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 315 o f 377 Figure 8- 22 shows the use o f the TEA signal . Note that al l bid irectio nal signal s are tr istated b etween b us tenures .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 316 of 377 gx_08.fm.(1.2) March 27, 2006 8.6 Option al Bus Configur ation The 750G X supports optional bu s conf iguratio ns that are selected during the negation of th e HRESE T signal .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 317 o f 377 An examp le of a two- beat data transfer ( with DRTRY asserted during e ach data te nure) is shown in Figure 8- 24 .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 318 of 377 gx_08.fm.(1.2) March 27, 2006 The 750GX selec ts 64-b it or 32- bit data bu s mode at startup by sampli ng the st ate of the TLBIS YNC signa l at the negati on of HRESE T .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 319 o f 377 8.7 Proce ssor S t ate S ignals This se ction desc ribes the 750GX's su pport for atom ic update and memory throug h the use of the lwar x and stwcx.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 320 of 377 gx_08.fm.(1.2) March 27, 2006 8.9 Using Dat a-Bus Write-Only The 750G X supports split-t ransac tion pip elined tra nsact ions.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_08.fm.(1.2) March 27, 2006 Bus Interface Operation Page 321 o f 377 Note that al though the 750GX can pipe line any wr ite trans action b ehind the read trans action, s pecial c are should b e used when usin g the en veloped write feat ure.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Bus Interface Operation Page 322 of 377 gx_08.fm.(1.2) March 27, 2006.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_09.fm.(1.2) March 27, 2006 L2 Cache Page 323 o f 377 9. L2 Cache Thi s chapt er de scri bes th e 750G X micr opro cess or‘s implem enta tion of the 1-MB L2 cach e. Note: The L2 c ache is initial ly disa bled fo llowing a power-o n or hard r eset.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor L2 Cache Page 324 of 377 gx_09.fm.(1.2) March 27, 2006 If mult iple read r equests from the L 1 caches ar e pendin g, the L 2 cache c.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_09.fm.(1.2) March 27, 2006 L2 Cache Page 325 o f 377 Wheneve r a way i n the set i s referen ced, the LRU bits ar e updated.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor L2 Cache Page 326 of 377 gx_09.fm.(1.2) March 27, 2006 110 x011 1 1x1 xxx0 3 1x1 xx01 2 101 0x11 0 111 x011 1 T able 9-3.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_09.fm.(1.2) March 27, 2006 L2 Cache Page 327 o f 377 Figure 9-1. L2 Cache 60x Bus 64-bit Bus Interface Unit Data-Out Req uest Da.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor L2 Cache Page 328 of 377 gx_09.fm.(1.2) March 27, 2006 The exec ution of th e St ore W ord Co ndit iona l Inde xed ( stwcx. ) instruct ion results in single- beat wri tes from the L1 d ata cach e.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_09.fm.(1.2) March 27, 2006 L2 Cache Page 329 o f 377 9.3 L2 Cache Control Reg ister (L2CR) The L2 Cache Co ntrol Reg ister is us ed to conf igure an d enabl e the L2 c ache.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor L2 Cache Page 330 of 377 gx_09.fm.(1.2) March 27, 2006 9.6 L2 Ca che Used as On -Chip Me mor y The L2 c ache ca n be co nfigured to b e unlo cked, par tially lock ed, or com pletely l ocked.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_09.fm.(1.2) March 27, 2006 L2 Cache Page 331 o f 377 9.6.1.1 Loading the Locked L2 Cache Contents a re loaded into t he L2 c ache simpl y by ex ecuting load inst ructions to cach eable addresses that miss i n the L1.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor L2 Cache Page 332 of 377 gx_09.fm.(1.2) March 27, 2006 The dcbz inst ruction has no effect on th e L2-cach e state, whether th e sta te is l ocked o r not. T he dcbi in stru c- tion caus es inv alidatio n of the block in th e case of an L2 h it, for bot h normal and lo cked ca ches.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_09.fm.(1.2) March 27, 2006 L2 Cache Page 333 o f 377 9.8.2 L2 Cache T e stin g A typica l test for veri fying the proper operatio n of the 750GX micropr ocessor’s L2-cac he memo ry follows this seque nce: 1.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor L2 Cache Page 334 of 377 gx_09.fm.(1.2) March 27, 2006.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_10.fm.(1.2) March 27, 2006 Power and T hermal Managemen t Page 335 o f 377 10. Power and Thermal Management The 750GX micr oproce ssor is specifi cally d esigned f or low-p ower operat ion.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Power and Thermal Management Page 336 of 377 gx_10.fm.(1.2) March 27, 2006 Figure 10-1.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_10.fm.(1.2) March 27, 2006 Power and T hermal Managemen t Page 337 o f 377 10.2.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Power and Thermal Management Page 338 of 377 gx_10.fm.(1.2) March 27, 2006 750GX wi ll then b e able respond to a sn oop cycle . Asser tion of QACK follo wing the s noop cyc le will aga in disable the 750 GX’s sno op cap ability.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_10.fm.(1.2) March 27, 2006 Power and T hermal Managemen t Page 339 o f 377 10.2.1.4 Sleep M ode Sleep mode consu mes the least am ount of powe r of the fou r modes sinc e all funct ional units are disa bled.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Power and Thermal Management Page 340 of 377 gx_10.fm.(1.2) March 27, 2006 10.2.2 Power Management Sof tware Consider at ions Since th e 750GX is a d ual-issu e process or with ou t-of-order execu tion capa bility, car e must b e taken in how the power manage ment mode i s entere d.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_10.fm.(1.2) March 27, 2006 Power and T hermal Managemen t Page 341 o f 377 Note: If the P LL softwar e con figurati on is used, suffic ient tim e must be allowed for the c hosen PL L to lo ck.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Power and Thermal Management Page 342 of 377 gx_10.fm.(1.2) March 27, 2006 10.3.3 Dual P LL Implementation Switchi ng between the two PLLs on the 750GX is intend ed to be a seaml ess, 3-cycle operati on.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_10.fm.(1.2) March 27, 2006 Power and T hermal Managemen t Page 343 o f 377 10.4 Therma l Assist Unit With the i ncreasin g power.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Power and Thermal Management Page 344 of 377 gx_10.fm.(1.2) March 27, 2006 The TAU pr ovides th ermal c ontrol by pe riodic ally co m.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_10.fm.(1.2) March 27, 2006 Power and T hermal Managemen t Page 345 o f 377 10.4.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Power and Thermal Management Page 346 of 377 gx_10.fm.(1.2) March 27, 2006 10.4.2.2 T AU Dual-Thr eshold Mode The configu ratio n and.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_10.fm.(1.2) March 27, 2006 Power and T hermal Managemen t Page 347 o f 377 10.4.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Power and Thermal Management Page 348 of 377 gx_10.fm.(1.2) March 27, 2006 The bit field set tings of th e ICTC SPR are shown in Table 10- 4 on page 348. T able 10-4. ICTC Bit Fi eld Settings Bits Nam e Description 0-22 Res erved Bits reserved fo r future use.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_11.fm.(1.2) March 27, 2006 Performance Monitor and System Related Features Page 349 o f 377 1 1.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Performance Monitor and Syst em Related Features Page 350 of 377 gx_11.fm.(1.2) March 27, 2006 As a re sult of a per formance- monitor exception b eing ta ken, th e action t aken depe nds on the program mable events.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_11.fm.(1.2) March 27, 2006 Performance Monitor and System Related Features Page 351 o f 377 1 1.2.1 Performance-Monitor Registers Thi s sectio n desc ribe s the r egis ter s used b y the perfo rmanc e mo nitor .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Performance Monitor and Syst em Related Features Page 352 of 377 gx_11.fm.(1.2) March 27, 2006 Software is expecte d to us e the mtspr instruc tion to ex plicitl y set P MC to nonov erflowed value s.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_11.fm.(1.2) March 27, 2006 Performance Monitor and System Related Features Page 353 o f 377 Bits MM CR1[0:4] spe cify events associa ted with PM C3, as sh own in T able 11-4 . 00 0101 C ounts L1 instruction-cache miss es.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Performance Monitor and Syst em Related Features Page 354 of 377 gx_11.fm.(1.2) March 27, 2006 Bits MM CR1[5:9] spe cify events associa ted with PM C4, as sh own in T able 11-5 .
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_11.fm.(1.2) March 27, 2006 Performance Monitor and System Related Features Page 355 o f 377 1 1.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Performance Monitor and Syst em Related Features Page 356 of 377 gx_11.fm.(1.2) March 27, 2006 1 1.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_11.fm.(1.2) March 27, 2006 Performance Monitor and System Related Features Page 357 o f 377 1 1.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Performance Monitor and Syst em Related Features Page 358 of 377 gx_11.fm.(1.2) March 27, 2006 • Internal registe rs (such as the g.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_11.fm.(1.2) March 27, 2006 Performance Monitor and System Related Features Page 359 o f 377 11 . 8 R e s e ts The 750GX support s two ty pes of r esets: a hard and a soft reset . 1 1.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Performance Monitor and Syst em Related Features Page 360 of 377 gx_11.fm.(1.2) March 27, 2006 1 1.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_11.fm.(1.2) March 27, 2006 Performance Monitor and System Related Features Page 361 o f 377 1 1.9 Checkst op s A check stop ca uses the proces sor to ha lt and ass ert the c heckstop output p in, CKST P_OUT .
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Performance Monitor and Syst em Related Features Page 362 of 377 gx_11.fm.(1.2) March 27, 2006 Table 1 1-7 shows th e contro l bits for H ID2. The che ckstop inp ut pin (CK STP_IN ) a lways c auses a checkstop regardl ess of t he state of the MSR[ME ] bi t.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_11.fm.(1.2) March 27, 2006 Performance Monitor and System Related Features Page 363 o f 377 1 1.10 750GX Parity Parity is impleme nted for t he foll owing ar rays: ins truction cach e, instruc tion ta g, data cac he, data ta g, and L2 tag.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Performance Monitor and Syst em Related Features Page 364 of 377 gx_11.fm.(1.2) March 27, 2006 1 1.10.1 P arity Control and S tatus Parity is enabled with the Hardware- Implementa tion-Depe ndent Regis ter 2 ( HID2).
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_acronyms.fm .(1.2) March 27, 2006 Acronyms and Abbreviations Page 365 o f 377 Acronyms and Abbreviations BAT block -addre ss tra.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Acronyms a nd Abbreviations Page 366 of 377 gx_acronyms.fm.(1. 2) March 27, 2006 FPR Fl oati ng Po int Reg ister FPSCR F loating-Po i.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_acronyms.fm .(1.2) March 27, 2006 Acronyms and Abbreviations Page 367 o f 377 NaN not a n umber no-op no operation OEA ope ratin.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Acronyms a nd Abbreviations Page 368 of 377 gx_acronyms.fm.(1. 2) March 27, 2006 THRM n T hermal-Ma nagement Re giste rs TLB trans la.
User’s Ma nua l IBM Po werP C 750G X and 75 0GL R I SC Mi crop roce ssor 750gx_umIX.fm.(1.2) March 27, 2006 Index Page 369 o f 377 Index A AACK (add ress acknowl edge) sig nal , 262 ABB (addres s bu.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Index Page 370 of 377 750gx_umIX.fm.(1.2) March 27, 2006 L2 interface cache g lobal invalida tion , 329 cache i nitial ization , 329 cach e test ing , 333 dcbi , 328 eieio , 328 operation , 323 stwcx.
User’s Ma nua l IBM Po werP C 750G X and 75 0GL R I SC Mi crop roce ssor 750gx_umIX.fm.(1.2) March 27, 2006 Index Page 371 o f 377 register s ettings MSR , 162 SRR0/SRR1 , 156 rese t exce ptio n , 1.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Index Page 372 of 377 750gx_umIX.fm.(1.2) March 27, 2006 integer , 99 byte revers e instruc tion s , 102 floating -point mov e , 98 f.
User’s Ma nua l IBM Po werP C 750G X and 75 0GL R I SC Mi crop roce ssor 750gx_umIX.fm.(1.2) March 27, 2006 Index Page 373 o f 377 O OEA exceptio n mec hanism , 151 memory m anage ment spe cific ati.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Index Page 374 of 377 750gx_umIX.fm.(1.2) March 27, 2006 DABR , 62 DAR , 61 DEC , 62 DSISR , 61 EAR , 62 HID0 , 65 , 337 HID1 , 70 IA.
User’s Ma nua l IBM Po werP C 750G X and 75 0GL R I SC Mi crop roce ssor 750gx_umIX.fm.(1.2) March 27, 2006 Index Page 375 o f 377 Stal l, def ini tion , 21 1 Stat ic br anch pr edic tio n , 216 , 229 stwcx.
User’s M anual IBM PowerP C 750GX and 750GL RISC Micropr ocessor Index Page 376 of 377 750gx_umIX.fm.(1.2) March 27, 2006.
User’s Ma nua l IBM Pow erPC 750GX an d 750GL RISC Microproces sor gx_revlog.fm.(1.2) March 27, 2006 Revision Log Page 377 o f 377 Revision Log Revision Date Contents of Modification February 27, 2004 Initial release (version 1.0) September 30, 2 004 (version 1.
デバイスIBM 750GLの購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
IBM 750GLをまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはIBM 750GLの技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。IBM 750GLの取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。IBM 750GLで得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
IBM 750GLを既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はIBM 750GLの不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、IBM 750GLに関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちIBM 750GLデバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
