Intelメーカー31154の使用説明書/サービス説明書
ページ先へ移動 of 72
Order Number : 278944- 001 Intel ® 31 154 13 3 MH z PCI Bridge Design Guide Desig n Guide April 2 004.
2 Inte l ® 3 1154 133 MHz PCI Bridge Desi gn Guide INFORMA TION IN THIS DOCUME NT IS PROV IDED IN CONNECTION WITH INT EL ® PRODUCTS. E XCEP T A S PROVIDED I N INTEL ’S TERMS AND CONDITIONS OF SALE.
Inte l ® 31154 13 3 MHz PCI Br idge Desi gn Guide 3 Contents Content s 1 About T his Documen t ................. .. ..... .. ..... ..... ....... .. ..... ..... .. ..... ....... .. ..... ..... .. ....... ..... .. ..... ..... .. ..... .... 7 1.1 Te rmi n o lo g y and Def initi o n s .
4 Inte l ® 3 1154 133 MHz PCI Bridge Desi gn Guide Contents 7.2.4 .2 PIC MG 1.2 Syste m Overvi ew .... .... ..... ..... ....... ..... .... ..... ....... ..... ..... .... .... 52 8 Power Consi derat ions ....... ..... ..... .... ..... ..... ..... ....
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide 5 Contents 9 Secondary Bus F requency I nitialization ............... ............ ....... ................. ......... ............ .............. 33 10 PCI- X Init iali zatio n Pat tern ..... .... ..
6 Inte l ® 3 1154 133 MHz PCI Bridge Desi gn Guide Contents Revision History Date Revision Description Ap ril 2004 001 Ini tial rel ea se.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 7 Ab ou t Thi s Doc um e nt About This Document 1 This docu ment prov ide s layout infor m ati on and guideline s for design ing plat form or add-in board appli cati ons wi th th e Intel ® 31 154 133 MHz PCI Bridg e.
8 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide About This Do cumen t § § Ag gres sor An ag gre ssor net work is a net work th at tra nsmit s a coup led si gn al to an other net work . Vi ct im A n etw or k t hat rece iv es a co up led cr os s-t a lk signa l fro m a not her n etw ork is a c al led t he vi cti m netw ork.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 9 Int roduc tio n Introduction 2 2.1 Prod uct Overview The Inte l ® 31 154 133 MHz PCI Bridge (cal led hereaft er the “31 154”) is a PCI compone nt that functi ons as a high ly con current , low-lat en c y trans pa rent bridg e betwee n two PC I buse s .
10 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide In trod uct ion The 31 154 ha s a dditio nal hardwa re s upport for Com pactPCI* Hot Swap a nd Re dundant System Sl ot via queue flush, arbite r l oc k, and clock out put tristatin g.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 11 Int roduc tio n 2.3 Related External S peci fications • PCI L oca l Bus Spe ci fica tio n , Revis ion 2.3 • PCI-t o-PC I Bridge Arc hitec tu re Speci ficat ion , Rev ision 1.1 • PCI Bus Power Manag ement Inte r face Speci ficat ion , Rev is ion 1.
12 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide In trod uct ion THIS PAG E I NTENTI ONAL LY LEFT BL ANK.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 13 Packa ge Informa tion Pack age Inform ation 3 The Inte l ® 31 154 133 MHz PCI Bridge is of fe r ed in a 421-lead PBGA packag e. The mechanic a l dimens ions for th is package are pr ovided in Figu re 2 on page 14 .
14 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Packag e Informatio n Figu re 2. Inte l ® 3 1 1 54 1 33 M Hz PCI Bridge Package B1290-01 BOTTOM VIEW SIDE VIEW TOP VIEW 1.27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B C D E F G H J K L M N P R AA Y W U T C Ø B A 0.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 15 Packa ge Informa tion Fi gur e 3 . In tel ® 31 154 133 MH z PCI Bridge Ball Map—T op V iew, Left S ide B2240-01 A 1 2 3 4 5 6 7 8 .
16 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Packag e Informatio n Figu re 4. Inte l ® 31 1 54 133 M Hz PCI Bri dge Ball Map—T op Vi ew, Right Sid e B2241-01 A 13 14 15 16 17 18.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 17 Packa ge Informa tion 3.1 T ot al Sign al Count § § Ta b l e 4 . To t a l S i g n a l C o u n t Inter face Si gna ls PCI bus in ter.
18 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Packag e Informatio n THIS PAG E I NTENTI ONAL LY LEFT BL ANK.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 19 T ermin atio ns T erminations 4 This cha pter d etails all the r ecommen ded Intel ® 31 154 133 MHz P CI Br idge terminati ons requi red for the dif fere nt operat ing m odes . The chapt er provide s th e recommende d pull -up a nd pull- down te r mination s for a 31 154 la yout.
20 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide T ermin atio ns P_GN T# Co nnect to GN T# of th e pri mar y PCI bu s. P_ ID SEL # Con nec t to o ne o f the AD l ines of th e pri mary PCI bus o r to th e ID SEL# si gnal o f th e PCI edge conn e cto r ( f or add-i n c ar d ap pli c ation s ).
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 21 T ermin atio ns S_AD[3 1:17] Thes e si gn al s can b e us ed a s IDS EL l in es and are con nec ted to IDS EL of the s econd ary PC I b us th ro ugh a n ex ter na l se rie s coup li ng res ist or (a re si st or of 2 K Ω is use d on the cus t ome r re fer en ce boar d) .
22 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide T ermin atio ns S_GCLKOEN Wh en th e in tern al c lo ck o f t he 31 1 5 4 is us ed, pul l high to V CC 33 thr oug h an ext ern al 8. 2 K Ω r e sist or. Whe n an extern al c lo ck sour ce is us ed, t ie t o GND thr oug h a 330 Ω ex terna l res istor.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 23 T ermin atio ns HS _FRE Q[1: 0] For H ot S wap : • D ep endi ng on P r imar y P C I Bu s fr equ en cy 00 = PCI Mo de , 33 or 66 M H z (de fault ) 01 = PCI- X 66 MHz 10 = PCI -X 100 MHz 1 1 = P CI- X 133 MHz When not us in g Hot S w ap: • Tie l o w to GND.
24 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide T ermin atio ns OP AQUE _E N T o en able Op aqu e Memor y Base /Lim it R eg ister s to e st a bl ish a pri vat e memo ry sp ac e fo r sec on da ry bu s us ag e : • P ull h ig h to 3. 3 V thr oug h an exte rn al 8.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 25 T ermin atio ns JT A G TCK Pu ll lo w wh en n ot us ed. TDI When not u sed , pul l u p to 3. 3 V thr ough an ext ern al 8. 2 K Ω re sist or . TD O NC wh en no t u s ed TRST # Whe n n ot use d, pull lo w to G ND t hro ug h an ex te rnal 1 K Ω res i s t o r.
26 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide T ermin atio ns RS TV0 Tie to G ND thr oug h a 0 Ω extern al resistor . RSRV1/CRSTEN T ie to GND t hrough a 0 Ω ext ernal resi stor .
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 27 T ermin atio ns § § NT_MA SK# • Whe n forc ed reti rem ent o f t he 31 15 4 int ernal re qu es t queue s an d dat a buf fe r is not desir ed in t he ap pli cati on , t hi s pin mu st be pul led u p to 3.
28 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide T ermin atio ns THIS PAG E I NTENTI ONAL LY LEFT BL ANK.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 29 PCI/PCI -X Interface PCI/PCI- X Interfa ce 5 This cha pter provi de s gui de lines for de signi ng wit h the Intel ® 31 154 133 MHz PCI Bridge PCI/PCI-X bus interface in your a pplication .
30 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI /PC I -X Interfa c e 5.3 IDSEL L ines The IDSE L li nes act as chi p se lect s dur ing th e co n figur atio n cy cles . Co n figur atio n cy cles al l ow r ead and write access to on e of th e device c onfig uratio n space reg ister s.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 31 PCI/PCI -X Interface 5.3. 3 Sec onda r y IDS EL Masking The 31 154 suppor ts pr iva te devi ce s th rough the use of IDSEL maski ng.
32 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI /PC I -X Interfa c e 5. 6 PCI-X Initi alizat i on Clocki ng M od e s Both of the PCI b us inte rfaces can oper ate at a variety of freque ncies, and in ei the r convent ion a l PCI mode, or in PCI-X mo de.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 33 PCI/PCI -X Interface T a ble 8. P CI-X Clocki ng Modes PCI -X Mod e PC I Mod e PC IXCAP (pin on P CI conn ec tor) P_ M6 6E N Not capa.
34 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI /PC I -X Interfa c e Ta b l e 1 0 des cri bes the bus mode and freq uency ini ti alizati on pa t te rn that the 31 154 signa ls on its se condary bus whe n com ing out of S_RS T#, a fter h a ving evalu ated the above infor m ation.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 35 Ro u t in g G u id e l in es Routing Guidel ines 6 This ch apt er provide s some bas ic rout ing guide lin es for la yout and design of a printe d circu it bo ard (PCB) usi ng the In tel ® 31 154 133 MHz PCI Bri dge .
36 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Routi ng Guidel ines 6.1 Cro sstal k Cros stal k is caus ed by c apac itive and induct ive c oupl ing between s ign als. Cr os stalk i s compose d of both bac kward a nd for ward cros stalk co mponents .
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 37 Ro u t in g G u id e l in es 6.2 EMI Considerations It is hi ghly recommend ed tha t you follow good EMI desig n pr ac tice s when des ign ing with the 31 154: • T o mini mize EMI on your PCB, a us eful techni que is not to extend th e power planes to the edge of th e board.
38 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Routi ng Guidel ines 6. 3 Power Dis t ri but ion an d Deco upling Ensure that t here is ample decoupli ng t o groun d for t he power pl anes , to minimiz e the e ffec ts of t he switc hing cur rents.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 39 Ro u t in g G u id e l in es 6.4 T race Impedance The PCI-X Adden dum to the PCI Local Bus Spe cific at ion , Revi sion 1.0b, reco m mends that a l l sign al l ayers ha ve a c ontroll ed impe da nce of 57 Ω ±10% for add-in c ard appl ic ations .
40 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Routi ng Guidel ines THIS PAG E I NTENTI ONAL LY LEFT BL ANK.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 41 PC I -X Lay out Gu ide l in es PCI-X Layout Gui delines 7 For acce pta ble signa l integr ity with bus speed s up to 133 MHz, it is impo rta nt for the PCB des ign layou t to ha v e con trolle d imp eda nce.
42 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI-X L ayout G uidelines 7.1 PCI Clock Layo ut Guidelines The PCI-X Adde ndum to th e PCI Local Bus Speci ficat ion , Re visio n 1.0a , allows a maxi mum of 0.5 ns clock skew ti ming for each of the P C I-X fr equ encies : 66 MHz , 100 MHz, and 13 3 MHz.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 43 PC I -X Lay out Gu ide l in es Figure 8. P CI Clock Distribution and Matching Requiremen ts Device 8 Device 7 Device 6 Device 5 Devic.
44 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI-X L ayout G uidelines 7. 2 PCI-X T opol ogy La y out Guide li nes The PCI-X Adde ndum to th e PCI Local Bus Speci ficat ion , Re visio n 1.0a , recommends the f ollowing guidelin e s f or the num ber o f loa ds for your PCI -X designs ( Ta b l e 1 3 ).
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 45 PC I -X Lay out Gu ide l in es 7.2 .1 Sing le S l ot at 13 3 MHz Figure 9 shows o ne o f the c hip s et P CI AD li nes conn ecte d thr ough the W1 an d W12 line segme nts to a si ngl e -slo t connec tor through t he W13 li ne segment to the 31 154.
46 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI-X L ayout G uidelines 7. 2.1.1 Inte l ® 31 154 13 3 MHz PC I Bridg e Embedded Appl ication at 133 MHz Fi gure 10 shows the 31 154 a pplic ation in a stand-a l one embedded appli cation.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 47 PC I -X Lay out Gu ide l in es 7. 2.2 Du al- Slot at 1 00 MH z Figure 1 1 shows one of t he secon dary bridg e PCI AD line s branch ing i nto two se gments with e ach going thr ough slot connect ors to a buffe r on an add-i n ca rd.
48 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI-X L ayout G uidelines 7. 2.2.1 Em bedded In tel ® 31 154 133 MHz PCI B ridge Appl ication at 100 MHz Fi gure 12 shows the PCI -X layo ut for a embe dded 13 3 MHz design . In this appli cation the 3 115 4 is drivi ng thre e loa ds.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 49 PC I -X Lay out Gu ide l in es 7. 2.3 Quad -S lo ts at 66 MHz Figure 13 shows one of the bridge s eco ndar y AD lines bra nchi ng to four seg ments with each seg ment conne cting to a slot co nne ctor to a bu ffer on an add-in c ard.
50 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI-X L ayout G uidelines W15 0.6 0.6 – – inch es W1 6 1.12 5 1. 12 5 – – in che s W21 0.8 1 .2 0.8 1.2 in che s W22 0.1 0 .5 0.1 0.5 in che s W23 0.75 1.5 1. 75 2.75 i nches W32 0.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 51 PC I -X Lay out Gu ide l in es 7.2. 3.1 Emb edded Int el ® 31 154 133 MHz PCI Br idge Ap plication a t 66 MHz Figure 14 shows an 311 54 in a s ta nd-alone embedd e d appli c ati on. In this appl icati on the 31 154 is shown dri ving four loa ds.
52 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI-X L ayout G uidelines 7. 2.4 PCI - X at 33 MH z The 31 154 s upp orts running in an eight -slot PIC MG 1.2 style pass ive backpl ane environm ent at 33 MHz. T o verif y this , sim ulat ions were run b a se d on the tr a ce imped ance of 57 Ω ± 10%.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 53 PC I -X Lay out Gu ide l in es Figure 15 shows an examp le of this syst em with dua l 64-bit bus es wit h four expans ion sl ots on each bus. T he b a ckp lan e exa mp le s ho ws th e S HB in a n I SA ch as sis.
54 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI-X L ayout G uidelines Figure 16. PCI-X D ata Bus PICMG 1. 2 Style Back plane T ab le 20. Wi ring Lengths for PICMG 1.2 Backplan e Segm ent AD Bu s Units Min im um Le ngt h Ma ximum L ength W1 0.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 55 PC I -X Lay out Gu ide l in es § § Figure 17. P CI-X Clock PICM G 1.2 S tyl e Backp lane T a ble 21. PCI-X Clock Wiring Lengths for PICMG Backpl ane Se gme nt Clock Point to Po int Unit s Minim um L eng th Maximu m Len gth S1 0 0.
56 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide PCI-X L ayout G uidelines THIS PAG E I NTENTI ONAL LY LEFT BL ANK.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 57 Pow er Consid eration s Power Considerations 8 8.1 Anal og Power Pin s The an alog v o lt age pins S_V CCA an d P _VCCA re quire a lo w - pas s filt er . Thi s is imp l ement ed by conne cting th e P _ VCCA and S _VCCA pin s to a 10 Ω series resi stor and 0.
58 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Powe r Co nsi dera tions 8.2 Power S equencing When either P _VIO or S_VIO is connect ed to a po wer suppl y othe r than V CCP , you m ust perform on e of the followi ng steps (l isted in order fr om most favo rably recommende d to lea st favorab ly r ecommended) : 1.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 59 Customer Referen ce Board Cust omer Re f ere nce Boa rd 9 This cha pte r provides inf orm ati on on the custome r refe rence board base d on the Int el ® 31 154 133 MHz PCI Bridge—th e Inte l ® IQ31 154 Cus tomer Referen ce Board (CRB).
60 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Customer Referen ce Boar d The I Q 3 1154 CR B is im pl em en t ed on ei gh t lay e r s. Th es e lay e r s are de ta il e d in Ta b l e 2 2 . T h is exa mple is provi ded as a re ference; each individ ual 3 115 4 applic ation m ay vary .
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 61 Debu g Connecto rs and Logic Analyzer Connec tivity Debug Connectors an d Logic Analyzer Connectivity 10 10.
62 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Debug Con nectors and Log ic Analy zer Connectivity T ab le 23. Logic An alyzer Po d 1 Mict or- 38 #1 Pin Num be r Odd Pod Logic Ana ly.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 63 Debu g Connecto rs and Logic Analyzer Connec tivity T a ble 24. Logic Analyzer Pod 2 Mict or - 38 #1 P in Nu mber O dd Pod Log ic A n.
64 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Debug Con nectors and Log ic Analy zer Connectivity T ab le 25. Logic An alyzer Po d 3 Mict or -38 #2 Pin Num be r Odd Pod Log ic Ana l.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 65 Debu g Connecto rs and Logic Analyzer Connec tivity T a ble 26. Logic Analyzer Pod 4 Mict or - 38 #2 P in Nu mber O dd Pod Log ic A n.
66 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Debug Con nectors and Log ic Analy zer Connectivity T ab le 27. Logic An alyzer Po d 5 Mict or -38 #3 Pin Num be r Odd Pod Log ic Ana l.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 67 Debu g Connecto rs and Logic Analyzer Connec tivity The recom mende d place ment of the Mictor con nector s is at either e nd of t he bus s egm en t.
68 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide Debug Con nectors and Log ic Analy zer Connectivity THIS PAG E I NTENTI ONAL LY LEFT BL ANK.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 69 The rmal Sol ution s Thermal Solutions 11 The Int el ® 31 154 133 MHz PCI Bri dge is p ackaged i n a 421 -lead PB GA pac kage. T he mechanic al dimens ions for th is package are pr ovided in Figu re 2, “Intel ® 31 154 133 MHz PCI Bridge Pa ck ag e ” on pa g e 14 .
70 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide The rmal So lu tions THIS PAG E I NTENTI ONAL LY LEFT BL ANK.
Inte l ® 31154 13 3 M Hz PCI Bridge Design G uide Design Guide 71 Referenc es Refe rences 12 12.1 Related Do cument s Ta b l e 3 0 list s sev era l books and spe ci ficat ion s th at a r e hel pful for design ing with the Inte l ® 31 154 133 MHz PCI Bri dge.
72 Inte l ® 3115 4 133 MHz PCI Bridge Design Guide Design Guide References THIS PAG E I NTENTI ONAL LY LEFT BL ANK.
デバイスIntel 31154の購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
Intel 31154をまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはIntel 31154の技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Intel 31154の取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Intel 31154で得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Intel 31154を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はIntel 31154の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Intel 31154に関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちIntel 31154デバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
