Intelメーカー8080の使用説明書/サービス説明書
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In December 1973 Intel shipped the first 8-bit, N-channel microprocessor, the 8080. Since then it has become the most widely used microprocessor in the industry. Applications of the 8080 span from large, intelligent systems terminals to decompression computers for deep sea divers.
CONTENTS INTRODUCTION General . Advantages of Designing with Microcomputers . . ii Microcomputer Design Aids iii Application Example . . . . . . . . . .
ROMs 8702A Erasable PROM (256 x 8) Data Sheet ... ............. ...... .. 5-37 8708/8704 Erasable PROM (1 K x 8) Data Sheet . . . . . . . . . . . . . . . . . . . . . . .. 5-45 8302 Mask ROM (256 x 8) Data Sheet . . . . . . . . . . . . . . . . . . . . .
Since their inception, digital computers have contin- uously become more efficient, expanding into new appli- cations with each major technological improvement. The advent of minicomputers enabled the inclusion of digital computers as a permanent part of various process control systems.
Product definition System and logic design Debug PC card layout Documentation Cooling and packaging Power distribution Engineering changes CONVENTIONAL SYSTEM Done with logic diagrams Done with conven.
APPLICATIONS EXAMPLE The 8080 can be used as the basis for a wide variety of calculation and control systems. The system configura- tions for particular applications will differ in the nature of the peripheral devices used and in the amount and the type of memory required.
APPLICATION PERIPHERAL DEVICES ENCOUNTERED Intelligent Terminals Cathode Ray Tube Display Printing Units Synchronous and Asynchronous data lines Cassette Tape Unit Keyboards Gaming Machines Keyboards,.
This chapter introduces certain basic computer con- cepts. It provides background information and definitions which will be useful in later chapters of this manual.
registers eliminates the need to "shuffle" intermediate re- sults back and forth between memory and the accumulator, thus improving processing speed and efficiency. Program Counter (Jumps, Subroutines and the Stack): The instructions that make up a program are stored in the system's memory.
Code or Operation Code. An eight-bit word used as an in- struction code can distinguish between 256 alternative actions, more than adequate for most processors. The processor fetches an instruction in two distinct operations. First, the processor transmits the address in its Program Counter to the memory.
with a clearly defined activity is called a State. And the inter- val between pulses of the timing oscillator is referred to as a Clock Period. As a general rule, one or more clock periods are necessary for the completion of a state, and there are several states in a cycle.
from memory to output devices goes by way of the processor. Some peripheral devices, however, are capable of transferring information to and from memory much faster than the processor itself can accomplish the transfer.
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The 8080 is a complete 8-bit parallel, central processor unit (CPU) for use in general purpose digital computer sys- tems. It is fabricated on a single LSI chip (see Figure 2-1). using Intel's n-channel silicon gate MaS process. The 8080 transfers data and internal state information via an 8-bit, bidirectional 3- state Data Bus (00-07).
ARCHITECTURE OF THE 8080 CPU The 8080 CPU consists of the following functional units: • Register array and address logic • Arithmetic and logic unit (ALU) • I nstruction register and control section • Bi-directional, 3-state data bus buffer Figure 2-2 illustrates the functional blocks within the 8080 CPU.
Arithmetic and Logic Unit (ALU): The ALU contains the following registers: • An 8-bit accumulator • An 8-bit temporary accumulator (ACT) • A 5-bit flag register: zero, carry, sign, parity and auxiliary carry • An 8-bit temporary register (TMP) Arithmetic, logical and rotate operations are per- formed in the ALU.
be synchronized with the pulses of the driving clock. Thus, the duration of all states are integral multiples of the clock period. To summarize then, each clock period marks a state; three to five states constitute a machine cycle; and one to five machine cycles comprise an instruction cycle.
While no one instruction cycle will consist of more then five machine cycles, the following ten different types of machine cycles may occur within an instruction cycle: (1 ) FETCH (M1) (2) MEMORY READ (3) MEMORYWRITE (4) STACK REAO (5) STACK WRITE (6) INPUT (7) OUTPUT (8) INTERRUPT (9) HALT (10) HALT.
Symbols INTA* STACK °2 HLTA °3 OUT °4 M, °5 INP* °6 MEMR* 0 7 Instructions for the 8080 require from one to five machine cycles for complete execution. The 8080 sends out 8 bit of status informatton on the data bus at the beginning of each machine cycle (during SYNC time).
G)_RESET Till READY + HLTA HOLD (3) SET INTERNAL HOLD F/F RESET INTERNAL HOLD F/F INT. INTE YES I I I I (31 I HOLD I MODE I I I I __ .J SET INTERNAL HOLD F/F YES (2) READY. HLTA NO READY ~~ I ... -------------~ READY 7 ?~~---- YES NO RESET HLTA NO NO RESET INTERNAL HOLD F/F HOLD SET INTERNAL INT F/F (1),NTE F/F IS RESET IF INTERNAL INT F/F IS SET.
The events that take place during the T3 state are determined by the kind of machine cycle in progress. In a FETCH machine cycle, the processor interprets the data on its data bus as an instruction. During a MEMORY READ or a STACK READ, data on this bus is interpreted as a data word.
~ ..... -- .. , ..... -- ... ,~ - FLOATING . _J BYTE ONE 411 _n~---frr~----Ifn~~n~~n,-- ......... n-.-- ....... n,--~n~---.n~ ......... n~----4 ~ _.J._J.J.J.L.IlLi.~~l.-.l:1cd:J. -~-- I UNKNOWN BYTE X INPUT DATA TO TWO ACCUMULATOR ---..-.-+--- .......
"data output delay" interval (tOO) following the </>2 clock's leading edge. Data on the bus remains stable throughout the remainder of the machine cycle, until replaced by up- dated status information in the subsequent T 1 state. Observe that a READY signal is necessary for completion of an OUTPUT machine cycle.
INTERRUPT SEQUENCES The 8080 has the built-in capacity to handle external interrupt requests. A peripheral device can initiate an inter- rupt simply by driving the processor's interrupt (INT) line high. The interrupt (INT) input is asynchronous, and a request may therefore originate at any time during any instruction cycle.
Mn M n + 1 l--OR~ I I ¢l_n ~ n ~n n ~ n ¢2 -+--sLJJlL-..rrL~LJLLJTLJJ.lJL ! i : I I I I I! A'5·0 : I ! I -:- - - - - - - - - -:- - - - - - - - - 1 1 I FLOATING I OJ·O ~ .1 -I----------I---------- ...... --~ 'i. - - -..II I : HOLD U ~ I 1 REQUEST - (1) i HOLD .
HOLD SEQUENCES The SOSOA CPU contains provisions for Direct Mem- ory Access (DMA) operations. By applying a HO LD to the appropriate control pin on the processor, an external device can cause the CPU to suspend its normal operations and re- linquish control of the address and data busses.
TWH TWH ,...-+---- - - - - - - Tl ~--..-----~-- - - - - - - T, 91 92 A1S·0 PC 07-0 SYNC OBIN WAIT STATUS INFORMATION NOTE: ® Refer to Status Word Chart on Page 2-6 Figure 2-11. HALT Timing TO STATE NO TW orT 3 TO STATE YES Tl TO STATE Tl Figure 2-12.
Tn+i Tn+(i-1) Tn +3 Tn+2 Tn+1 ~~~~t==p----~--·_-~--- ,--~~-----+-----""'----"'~-+---""" Tn (1) cP1 A15.0~ __ .1 RESET INTERNAL RESET SYNC -+- ..... ..... -+- -/~-----~---- .... -_....I DBIN -+----- ..... ----- .
MNEMONIC OP CODE M1[1] M2 o SSS T3 T5 x X [3] x OAA-A, F LAGS[10] x T4 x x x x x (RP)-1 ~. (RP) + 1 ~~ x x (OOO)-TMP (TMP)+l-ALU x (SSS)-TMP (A)-ACT x (OOOJ-TMP (TMP) + 1-ALU (SSS)-TMP (A)-ACT (A)-ACT.
PC OUT STATUS[6] [9] [9] [9] M3 PC = PC + 1 PC = PC + 1 PC = PC + 1 PC = PC + 1 M4 2-17 M5.
MNEMONIC OP CODE Ml[l] M2 07 0 6 0 5 0 4 03 0 2 0 1 DO Tl T2[2] T3 T4 T1 T2[2] T3 ANI data 1 1 1 0 0 1 1 0 PC OUT PC = PC + 1 INST-TMP/IA (A)-ACT PC = PC + 1 STATUS XAAr 1 0 1 0 S S S (A)-ACT (ACT)+(T.
M3 M4 M5 SP OUT SP :: SP + 1 STATUS[15] SP OUT SP :: SP + 1 STATUS[15] (ACT)+(TMP)-A T1 WZOUT (WZ) + 1-PC STATUS[ll] PC OUT PC:: PC + 1 ~iA~~[ll,12] (WZ) + 1- PC STATUS[6] PC OUT PC:: PC + 1 ~iA~~~[11.
NOTES: 1. The first memory cycle (M 1) is always an instruction fetch; the first (or only) byte, containing the op code, is fetched during this cycle. 2. If the READY input from memory is not high during T2 of each memory cycle, the processor will enter a wait state (TW) until READY is sampled as high.
This chapter will illustrate, in detail, how to interface the 8080 CPU with Memory and I/O. It will also show the benefits and tradeoffs encountered when using a variety of system architectures to achieve higher throughput, de- creased component count or minimization of memory size.
The following pages will cover the detailed design of the CPU Module with the 8080. The three Busses (Data, Address and Control) will be developed and the intercon- nection to Memory and I/O will be shown.
OSCILLATOR CLOCK GENERATOR 7486 DB OB 74163 DC OC .......--...-------' 74S04 ~ 20MHz 330 330 ~""""--01 >- ...... ------------ ....... -------- .... OSC 7486 READY r-----IIIIII---- SYNC AUXILIARY FUNCTIONS WA IT REO ------41---1 0 a 74574 ClK '----.
Auxiliary Timing Signals and Functions The Clock Generator can also be used to provide other signals that the designer can use to simplify large system timing or the interface to dynamic memories. Functions such as power-on reset, synchronization of external requests (HOLD, READY, etc.
The input level specification impl ies that any semi- conductor memory or I/O device connected to the 8080 Data Bus must be able to provide a minimum of 3.3 volts in its high state. Most semiconductor mem- ories and standard TTL I/O devices have an output capability of between 2.
INTERFACING THE 8080 CPU TO MEMORY AND I/O DEVICES The 8080 interfaces with standard semiconductor Memory components and I/O devices. In the previous text the proper control signals and buffering were developed which will produce a simple bus system similar to the basic system example shown at the beginning of this chapter.
RAM memory must be provided, such as: Floppy Disk, Paper Tape, etc. The CPU treats RAM in exactly the same manner as ROM for addressing data to be read.
I/O INTERFACE Figure 3-9. Isolated I/O. Memory Mapped I/O It is easy to see that from the list of possible "new" instructions that this type of I/O architecture could have a drastic effect on increased system throughput.
10--------...--- MEMR The second example uses Memory Mapped I/O and linear select to show how thirteen devices (8255) can be ad- dressed without the use of extra decoders. The format shown could be the second and third bytes of the LDA or STA in- structions or any other instructions used to manipulate I/O using the Memory Mapped technique.
The two (2) 8255s provide twenty four bits each of programmable I/O da~a and control so that keyboards, sen- sors, paper tape, etc., can be interfaced to the system.
A computer, no matter how sophisticated, can only do what it is "told" to do. One "tells" the computer what to do via a series of coded instructions referred to as a Pro- gram. The realm of the programmer is referred to as Soft- ware, in contrast to the Hardware that comprises the actual computer equipment.
Condition Flags: There are five condition flags associated with the exe- cution of instructions on the 8080. They are Zero, Sign, Parity, Carry, and Aux iI iary Carry, and are each represented by a l-bit register in the CPU. A flag is "set" by forcing the bit to 1; "reset" by forcing the bit to O.
accumulator Register A addr 16-bit address quantity data 8-bit data quantity Symbols and Abbreviations: The following symbols and abbreviations are used in the subsequent description of the 8080 instr.
6. The last four lines contain incidental information about the execution of the instruction. The num- ber of machine cycles and states required to exe- cute the instruction are listed first. If the instruc- tion has two possible execution times, as in a Conditional Jump·, both times will be listed, sep- arated by a slash.
high-order addr o I 0 I 1 I 1 1 1 1 0 I 1 I 0 low-order addr LOA addr (Load Accumulator direct) (A) ~ ((byte 3) (byte 2)) The content of the memory location, whose address is specified in byte 2 and byte 3 of the instruction, is moved to register A.
ADC r (Add Register with carry) (A) ~ (A) + (r) + (CY) The content of register r and the content of the carry bit are added to the content of the accumulator. The result is placed in the accumulator. Cycles: States: Addressing: Flags: Arithmetic Group: This group of instructions performs arithmetic oper- ations on data in registers and memory.
SUB M (Subtract memory) (A) ~ (A) - ((H) (L)) The content of the memory location whose address is contained in the Hand L registers is subtracted from the content of the accumulator.
OCR M (Decrement memory) ((H) (L)) ..- ((H) (L)) - 1 The content of the memory location whose address is contained in the Hand L registers is decremented by one.
ANI data (AND immediate) (A) ~ (A) / (byte 2) The content of the second byte of the instruction is logicaJly anded with the contents of the accumu lator .
CPI data (Compare immediate) (A) (byte 2) The content of the second byte of the instruction is subtracted from the accumulator. The condition flags are set by the result of the subtraction. The Z flag is set to 1 if (A) = (byte 2). The CY flag is set to 1 if (A) < (byte 2).
CMC (Complement carry) (CY)~ (CY) The CY flag is complemented. No other flags are affected. dress is specified in byte 3 and byte 2 of the current instruction.
Ccondition addr (Condition call) If (CCC), ((SP) -1) ~ (PCH) ((SP) - 2) ~ (PCl) (SP) ~ (SP) - 2 (PC) ~ (byte 3) (byte 2) If the specified condition is true, the actions specified in the CAll instruction (see above) are performed; otherwise, control continues sequentially.
Stack, I/O, and Machine Control Group: FLAG WORD This group of instructions performs I/O, manipulates the Stack, and alters internal control flags. Unless otherwise specified, condition flags are not affected by any instructions in this group.
XTHL (Exchange stack top with Hand L) (L) ~((SP)) (H) ~ ((SP) + 1) The content of the L register is exchanged with the content of the memory location whose address is specified by the content of register SP. The content of the H register is exchanged with the content of the memory location whose address is one more than the content of register SP.
INSTRUCTION SET Summary of Processor Instructions Instruction Code [11 Clock 121 Instruction Code [11 Clock [21 Mnemonic Description try 06 Os 04 03 02 0, DO Cycles Mnemonic Description 07 06 Os 04 03.
CPU Group 8224 Clock Generator 5-1 8228 System Controller ....... .............. .. 5-7 8080A Central Processor 5-13 8080A-1 Central Processor (1.3#ls) ••..•.••.••.••.• 5- 20 8080A-2 Central Processor (1.5#ls) •...•..•..•.••.
8224 8228 8080A CPU Group 8080A-1 8080A-2 M8080-A.
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Schottky Bipolar 8224 CLOCK GENERATOR AND DRIVER FOR 8080A CPU • Single Chip Clock Generator/Driver for 8080A CPU • Power-Up Reset for CPU • Ready Synchronizing Flip-Flop • Advanced Status Strobe • Oscillator Output for External System Timing • C.
SCHOTTKY BIPOLAR 8224 FUNCTIONAL DESCRIPTION General The 8224 is a single chip Clock Generator/Driver for the S080A CPU. It contains a crystal-controlled oscillator, a "divide by nine" counter, two high-level drivers and several auxiliary logic functions.
SCHOTTKY BIPOLAR 8224 STSTB (Status Strobe) At the beginning of each machine cycle the aOaOA CPU is- sues status information on its data bus. Th is information tells what type of action will take place during that machine cycle.
SCHOTTKY BIPOLAR 8224 D.C. Characteristics T A = O°C to 70°C; Vee = +5.0V ±5%; Voo = +12V ±5%. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions IF Input Current Loading -.25 rnA VF = .45V IR Input Leakage Current 10 J.lA VR = 5.25V Ve Input Forward Clamp Voltage 1.
SCHOTTKY BIPOLAR 8224 A.C. Characteristics vcc = +5.0V ± 5%; Voo = +12.0V ± 5%; TA = O°C to 70°C Limits Test Symbol Parameter Min. Typ. Max. Units Conditions tq,1 cP1 Pulse Width 2tcy -- 20ns 9 t&.
SCHOTTKY BIPOLAR 8224 WAVEFORMS ......... ----to2-----..r 1'4------t</l2---~ ~-------------tey---------------.I <l>2fTTL) SYNC (FROM 8080A) RDYIN OR RESIN ~--------toss-------.....----- t..-----tORH------.t READY OUT RESET OUT VOLTAGE MEASUREMENT POINTS: cP1, cP2 Logic "0" = 1.
Schottky Bipolar 8228 SYSTEM CONTROLLER AND BUS DRIVER FOR 8080A CPU • Sing.le Chip System Control for MCS:SO Systems • Built-in Bi-Directional Bus Driver for Data Bus Isolation • Allows the use of Multiple Byte Instructions (e.
SCHOTTKY BIPOLAR 8228 FUNCTIONAL DESCRIPTION General The 8228 is a single chip System Controller and Data Bus driver for the 8080 Microcomputer System. It generates all control signals required to directly interface MCS-80™ family RAM, ROM, and I/O components.
SCHOTTKY BIPOLAR 8228 DATA BUS INTA MEMR MEM W CONTROL BUS I/O R I/OW 3 CONTROL BUSEN __ .... 22 a _ 18 WRn-------....., DBINt-=-1.:....7----..-----, HDLA ~2;.;.1 ~_--. 8080A °O~10~~-I CPU 011-9--l~-I °2~8--l~~ ..... 0 3 1-7--l~-I 0 4 1-3--l~-I °51-4--l~-I 0 6 .
SCHOTTKY BIPOLAR 8228 WAVEFORMS DBIN STATUS STROBE INTA, lOR, MEMR DURING HLDA HLDA --------+----+-----'1 8080 DATA BUS -----...".I'~~+--,.,.I"-------------------- lOW OR MEMW 8080 BUS DURING READ· ------- - - 8080 BUS DURING WRITE SYSTEM BUS DURING READ SYSTEM BUS DURING WRITE - - - - - - - - - < ~ we1= SYSTEM BUS ENABLE.
SCHOTTKY BIPOLAR 8228 D.C. Characteristics TA = O°c to 70°C; Vee = 5V ±5%. Limits Symbol Parameter Min. Typ.[1] Max. Unit Test Conditions Ve Input Clamp Voltage, All Inputs .75 -1.0 V Vee=4.75V; le=-5mA IF Input Load Current, STSTB 500 IlA Vee=5.25V 02&06 750 IlA VF=O.
SCHOTTKY BIPOLAR 8228 ADDRESS BUS DB O DB 1 DB 2 DB 3 DATA BUS DB 4 DBs DB 6 D~ INTA MEM R MEMW CONTROL BUS I/O R I/OW 2 25 - GND. · Ao Ao 20 26 A 1 +5V A 1 11 27 A 2 -5V A 2 28 29 -- A 3 +12V · A 3 30 A 4 A 4 31 As AS 32 A 6 A 6 8080A 33 A 7 CPU A 7 I- 34 AS AS 13 35 A g SYSTEM DMA REO.
intel® Silicon Gate MOS 8080 A SINGLE CHIP a-BIT N-CHANNEL MICROPROCESSOR The 8080A is functionally and electrically compatible with the Intel® 8080.
· SILICON GATE MOS 8080'A - . 8080A FUNCTIONAL PIN DEFINITION The following describes the function of all of the 8080A I/O pins. Several of the descriptions refer to internal timing periods.
SILICON GATE MOS 8080 A ABSOLUTE MAXIMUM RATINGS· Temperature Under Bias ' O°C to +70° C Storage T emperatu re . . . . . . . . . . . . . . . _65° C to + 150° C All Input or Output Voltages With Respect to VSS -0~3V to +20V Vcc, Voo and VSS With Respect to Vss -0.
SILICON GATE MOS 8080A A.C. CHARACTERISTICS T A = O°C to 70°C, VOO = +12V ± 5%, VCC = +5V ± 5%, Vas = -5V ± 5%, Vss = OV, Unless Otherwise Noted Symbol Parameter Min. Max. Unit Test Condition tCy[3] Clock Period 0.48 2.0 J1sec t r , tf ·Clock Rise and Fall Time 0 50 nsec ~1 f/J1 Pulse Width 60 nsec tq,2 cf>2 Pu.
SILICON GATE MOS 8080A A.C. CHARACTERISTICS (Continued) TA = O°C to 70°C, Voo = +12V ± 5%, Vee = +5V ± 5%, Vss = -5V'± 5%, V 5 5 = OV, Unless Otherwise Noted Symbol Parameter Min.
SILICON GATE MOS 8080 A INSTRUCTION SET The accumulator group instructions include arithmetic and logical operators with direct, indirect, and immediate ad- dressing modes.
SILICON GATE MOS 8080.A INSTRUCTION SET Summary of Processor Instructions Instruction Code [1 J Clock [2] Instruction Code (1) Clock[2J Mnemonic Description D7 D6 Os D4 D3 02 0, Do Cycles Mnemonic Description D7 06 Os 04 Da ~ 0, Do Cycles MOV r1 .
infel® Silicon Gate MOS 8080A-1 SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSOR • TTL Drive Capability • 1.3 J.Ls Instruction Cycle • Powerful Problem Solving Instruction Set • Six General Purpose.
SILICON GATE MOS 8080A-1 ABSOLUTE MAXIMUM RATINGS· Temperature Under Bias O°C to +70° C Storage Temperature -65°C to +150°C All I nput or Output Voltages With Respect to Vaa -0.3V to +20V Vee, VOO and Vss With Respect to Vaa -0.3V to +20V Power Dissipation .
SILICON GATE MOS 8080A-1 A. c. C HA RACTE RI STI CS CA UTlON: When operating the 8080A·l at or near full speed, care must be taken to assure precise timing compatibility between 8080A·', 8224 and 8228. TA = O°C to 70°C, Voo = +12V ± 5%, VCC = +5V ± 5%, VSS = -5V ± 5%, VSS = OV, Unless Otherwise Noted Symbol Parameter Min.
SILICON GATE MOS 8080A-1 A.C. CHARACTERISTICS (Continued) T A = O°C to 70°C, Vo o = +12V ± 5%, Vee = +5V ± 5%, Vss = -5V ± 5%, V ss = OV, Unless Otherwise Noted Symbol Parameter Min.
infel® Silicon Gate MOS 8080 A-2 SINGLE CHIP a-BIT N-CHANNEL MICROPROCESSOR • TTL Drive Capability • 1.5 J.Ls Instruction Cycle • Powerful Problem Solving Instruction Set • Six General Purpos.
SILICON GATE MOS 8080A-2 ABSOLUTE MAXIMUM RATINGS· Temperature Under Bias O°C to +70° C Storage T emperatu re .. . . . . . . . . . . . .. _65° C to + 150° C All Input or Output Voltages With Respect to Vas -0.3V to +20V Vee, Voo and Vs s With Respect to V ss -0.
SILICON GATE MOS 8080A-2 A.C. CHARACTERISTICS T A = O°C to 70°C, Vee = +12V ± 5%, VCC = +5V ± 5%, V ss = -5V ± 5%, Vss = OV, Unless Otherwise Noted Symbol Parameter Min.
SILICON GATE MOS 8080A-2 A.C. CHARACTERISTICS (Continued) TA = O°C to 70°C, VOD = +12V ± 5%, Vee = +5V ± 5%, V BB = -5V ± 5%, V ss = OV, Unless Otherwise Noted Symbol Parameter Min.
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intel® . Silicon Gate MOS M8080A SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSOR • Full Military Temperature Range -55°C to +125°C • ±10% Power Supply Tolerance • 2 J-Ls Instruction Cycle • Pow.
SILICON GATE MOS M8080A INSTRUCTION SET The accumulator group instructions include arithmetic and logical operators with direct, indirect, and immediate ad- dressing modes.
SILICON GATE MOS M8080A INSTRUCTION SET Summary of Processor Instructions Instruction Code (1) Clock (21 Instruction Code [n Clock (2) Mnemonic Description 07 06 Os 04 03 02 0, Do Cycles Mnemonic Desc.
SILICON GATE MOS M8080A M8080A FUNCTIONAL PIN DEFINITION The following describes the function of all of the M8080A I/O pi ns. Several of the descriptions refer to internal tim ing periods.
SILICON GATE MOS M8080A ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias -55°C to +125°C Storage T emperatu re .. . . . . . . . . . . . . . _65° C to + 150° C All Input or Output Voltages With Respect to VBB -0.3V to +20V Vcc, Voo and Vss With Respect to VBB -0.
SILICON GATE MOS M8080A A.C. CHARACTERISTICS (Continued) T A = -55°C to +125°C, VOO = +12V ±10%, Vee = +5V ±10%, VBB = -5V ±10%, Vss = OV, Unless Otherwise Noted.
SILICON GATE MOS M8080A A.C. CHARACTERISTICS TA = -55°C to +125°C, Voo = +12V ±10%, Vee = +5V ±10%, VBB = -5V ±10%, Vss = OV, Unless Otherwise Noted.
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8702A 8704 8708 ROMs 8302 8308 8316A.
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Silicon Gate MOS 8702A 2048 BIT ERASABLE AND ELECTRICALLY REPROGRAMMABLE READ ONLY MEMORY • Inputs and Outputs TTL Compatible • Three-State Output - OR-Tie Capability • Simple Memory Expansion Chip Select Input Lead • Access Time -1.3 ~sec Max.
SILICON GATE MOS 8702A PIN CONNECTIONS The external lead connections to the 8702A differ, depending on whether the device is being programmed (1) or used in read.
SILICON GATE MOS 8702A A.C. CHARACTERISTICS T A = 00 C to + 70°C, V cc = +5V ±5%, V oo = -9V ±5%, V GG = -9V ±5% unless otherwise noted SYMBOL TEST MINIMUM TYPICAL MAXIMUM UNIT Freq. Repetition Rate 1 MHz tOH Previous read data val id 100 ns tAcc Address to output delay 1.
SILICON GATE MOS 8702A TYPICAL CHARACTERISTICS '00 CURRENT VS. TEMPERATURE OUTPUT CURRENT VS. VDO SUPPLY VOLTAGE OUTPUT CURRENT VS. TEMPERATURE I ' Vee = +5V - r v oo = -9V - r V aa = -9V ' INPUTS" Vee - I. f' OUTPUTS ARE OPEN I I I I" '" I ~ NS=V ee I" I" I- -- ~ 'l CS = 0.
SILICON GATE MOS 8702A PROGRAMMING OPERATION D.C. AND OPERATING CHARACTERISTICS FOR PROGRAMMING OPERATION T A = 25°C, Vee = OV, V ss = +12V ± 10%, CS = OV unless otherwise noted SYMBOL TEST MIN.
SILICON GATE MOS 8702A SWITCHING CHARACTERISTICS FOR PROGRAMMING OPERATION PROGRAM OPERATION Conditions of Test: Input pulse rise and fall times :s 1J1sec CS = OV PROGRAM WAVEFORMS BINARY ADDRESS OF WORD TO BE PROGRAMMED I I I I I ~tvoi I ~ f--tATW ---.
SILICON GATE MOS 8702A PROGRAMMING INSTRUCTIONS FOR THE 8702A I. Operation of the 8702A in Program Mode Initially, all 2048 bits of the ROM are in the "0" state (output low). Information is introduced by seectively program- ming "1 "s (output high) in the proper bit locations.
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Silicon Gate MOS 8708/8704 8192/4096 BIT ERASABLE AND ELECTRICALLY REPROGRAM MABLE READ ONLY MEMORY • 8708 1024x8 Organization • 8704 512x8 Organization • Fast Programming - Typ.
SILICON GATE MOS 8708/8704 Absolute Maximum Ratings~· Temperature Under Bias ,. -25°C to +85°C Storage Temperature -~5°C to +125°C All Input or Ou'tput Voltages with Respect to VBB (except Program) .... .. ....... ..... ..... .. .. +15V to -0.
SILICON GATE MOS 8708/8704 A.C. Characteristics TA = O°C to 70°C, Vee = +SV ±S%, Vo o = +12V ±S%, Vee = -SV ±S%, Vss = OV, Unless Otherwise Noted.
SILICON GATE MOS 8708/8704 PROGRAMMING OPERATION Description Initially, and after each erasure, all bits of the 8708/8704 are in the "1" state (Output High). Information is introduced by select- ively programming "0" into the desired bit locations.
SILICON GATE MOS 8708/8704 Waveforms (Logic levels and timing reference levels same as in the Read Mode unless noted otherwise.) A) Program Mode CS/WE = +12V ~ __ AD_D_R_ESS_1_....c ~_--·-·-·----.lX'---A-D-D-RE-SS-1-0-23--~ ADDRESS 0 ...---------------ONE PROGRAM LOOP ---------------.
SILICON GATE MOS 8708/8704 Typical Characteristics (Nominal supply voltages unless otherwise noted): OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE RANGE OF SUPPLY CURRENTS VS. TEMPERATURE 100 80 60 ALL POSSIBLE OPERATING CONDITIONS: Vee = 5.25V V oo = 12.6V V aa = -5.
Silicon Gate MOS 8302 2048 BIT MASK PROGRAMMABLE READ ONLY MEMORY • Static MOS - No Clocks Required • Simple Memory Expansion - Chip Select Input Lead • 24-Pin Dual-In-Line Hermetically Sealed Ceramic Package • Access Time-1 p'sec Max.
SILICON GATE MOS 8302 Absolute Maximum Ratings ~~ Ambient Temperature Under Bias oOc to +70 o C Storage Temperature -65°C to +125 0 C Soldering Temperature of Leads (10 sec) ...... .. +300 o C Power Dissipation 2 Watts Input Voltages and Supply Voltages with respect to V cc +O.
SILICON GATE MOS 8302 A.C. Characteristics T A = (1J C to + 70°C, Vee = +5V ±5%, V oo = -9V ±5%, V GG = -9V ±5% unless otherwise noted SYMBOL TEST MINIMUM TYPICAL MAXIMUM UNIT Freq. Repetition Rate 1 MHz tOH Previous read data val id 100 ns tACC Address to output delay .
SILICON GATE MOS 8302 Typical Characteristics 100 CURRENT VS. TEMPERATURE ACCESS TIME VS. LOAD CAPACITANCE OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE I vee = +5V - ~ v oo = -9V - v GG = -9V " INPUTS:: Vee - ~ I" OUTPUTS ARE OPEN I I I ' ~ I l' NSIIV ee .
Silicon Gate MOS 8308 8192 BIT STATIC MOS READ ONLY MEMORY Organization --1024 Words x 8 Bits • Fast Access - 450 ns • Directly Compatible with 8080 CPU at Maximl)m Processor Speed • Two Chip Se.
SILICON GATE MOS 8308 Absolute Maximum Ratings* Ambient Temperature Under Bias -25°C to +85°C Storage Temperature -65°·C to-i-150°C Voltage On Any Pin With Respect To V aa .
SILICON GATE MOS 8308 - - A.C. Characteristics TA = oo.c to'+70~C, VCC = +5V ±5%; VO_D = +12V ±5%, VBB = -5V _±5%, VSS_= OV, Unless Otherwise Specif.i~d. Limits[2] Symbol Parameter Unit Min. Typ. Max. tACC Address to Output Delay Time 200- 450 ns tC01 Chip Select 1 to Output Dela.
SILICON GATE MOS 8308 Typical Characteristics (Nominal supply voltages unless .otherwise noted.) 100 VS. TE""PERATURE (NORMALIZED) A OUTPUT CAPACITANCE VS. A OUTPUT DELAY +100 +50 o -50 -40 L..- __ ...I..- __ ...Io....- __ .......I.- __ --' -100 +40 r-----~--_r__--~---, ~ CAPACITANCE (pF) _ +20 t----+-----+----~<------f u W (I) .
MCS™ CUSTOM ROM ORDER FORM 8308 ROM APp _ S# _ STO _ CUSTOMER _ P.O. NUMBER . _ OATE _ For Intel use only PPpp--------- zz, _ 00 _ OATE . _ All custom 8308 ROM orders must be submitted on this form. Programming information should be sent in the form of computer punched cards or punched paper tape per the formats designated on this order form.
a. Title Card MCS™ CUSTOM ROM ORPER _ FOR.M_ 8308 NO. OF OUTPUTS TITLE CARD 4 or 8 DESIGNATION CUSTOMER'S INTEL P/Nl '1 CUSTOMER'S DIVISION OR 1 DECIMAL NUMBER ~ INDICATING THE COMPANY NAME LOCATION CUSTOMER:S PIN I' i ~ TRUTH TABLE NUMBER ~"/~ G.
intel® Silicon Gate MOS ROM 8316A 16,384 BIT STATIC MOS READ ONLY MEMORY Organization-2048 Words x 8 Bits -- . Access Time-SSO ns max • Single + 5 Volts Power Supply Voltage • Directly TTL Compatible - All Inputs and Outputs • Low Power Dissipation of 31.
SI~ICON GATE MOS ROM 8316A ABSOLUTE MAXIMUM RATINGS· Ambient Temperature Under Bias O°C to 70°C Storage Temperature -65°C to +150°C Voltage On Any Pin With Respect To Ground. . . . . . . . . . . . . . . . . . . . .. -0.5V to +7V Power Dissipation ~ .
SILICON GATE MOS ROM 831.6A WAVEFORMS ADDRESS PROGRAMMABLE CHIP SELECTS tOF 5-63 OU~TVALID 1111..
S.ILICO.N GATE MOS ROM 8316A TYPICAL D.C. CHARACTERISTICS ACCESS TIME VS. AMBIENT TEMPERATURE V,N LIMITS VS. TEMPERATURE 50 60 70 10 20 TYPICAL 1.8 r----,r----r--.,r---r---.,r---r--_ 1.6 t----1t-----t----1t---t---I----f------f VCC:;;: 5.0V 1.2 t---t---l--t---t--------"t---t-------4 1.
MCS™ CUSTOM ROM ORDER FORM 8316A ROM CUSTOMER,------------------ P.O. NUMBER ----.;. _ OATE _ APp _ S# ----:. STO _ For I ntel use only pppp-------- zz, _ 00 _ OATE _ All custom 8316A ROM orders must be submitted on this form.
a. Title Card NO. OF OUTPUTS TITLE CARD 4 or 8 CUSTOMER'S 1 DESIGNATION CUSTOMER'S INTEL PIN DECIMAL NUMBER 1 DIVISION OR I COM~ANY NAME LOCATION CUSTOMER'S PIN I INDICATING THE I' ,----....1..-------,,1 r--L-, ~ TRUTH TABLE NUMBER r--;,~·'I·~l.
8101-2 8111-2 8102-2 8102A-4 81078-4 RAMs 5101 8210 8222.
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Silicon Gate MOS 8101-2 1024 BIT (256 x 4) STATIC MOS RAM WITH SEPARATE 1/0 • 256 x 4 Organization to Meet Needs for Small System Memories • Access Time - 850 nsec Max.
SILICON GATE MOS 8101-2 Absolute Maximum Ratings* Ambient Temperature Under Bias. . . . .. O°C to 70° C Storage T emperatu re .. ......... -65 0 C to + 150 0 C Voltage On Any Pin With Respect to Ground. . . . . . . .. -0.5V to +7V Power Dissipation .
SILICON GATE MOS 8101-2 A.C. Characteristics READ CYCLE T A = o°c to 70°C, Vee = 5V ±5~/~, unless otherwise specified. Symbol Parameter =I Min. Typ. Max. Unit Test Conditions -- ~--_._--- tRey Read Cycle ~ ns ----- .- --.-- tA Access Time 850 ns ____ .
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Silicon Gate MOS 8111-2 1024 BIT (256 x 4) STATIC MOS RAM WITH COMMON I/O AND OUTPUT DISABLE • Organization 256 Words by 4 Bits • Access Time - 850 nsec Max.
SILICON GATE MOS 8111-2 Absolute Maximum Ratings* Ambient Temperature Under Bias. . . . .. O°C to 70°C Storage Temperature -65°C to +150°C Voltage On Any Pin With Respect to Ground .
SILICON GATE MOS 8111-2 A.C. Characteristics READ CYCLE T A = o°c to 70°C, Vee = 5V ±5%, unless otherwise specified. Symbol Parameter Min. Typ. Max.
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Silicon Gate MOS 8102-2 • Simple Memory Expansion - Chip Enable Input • Fully Decoded - On Chip Address Decode • Inputs Protected - All Inputs Have Protection Against Static Charge • Low Cost Packaging -16 Pin Plastic Dual-In-Line Configuration 1024 BIT FULLY DECODED STATIC MOS RANDOM ACCESS MEMORY • Access Time - 850ns Max.
SILICON GATE MOS 8102-2 ABSOLUTE MAXIMUM RATINGS· Ambient Temperature Under Bias Storage Temperature Voltage On Any Pin With Respect To Ground Power Dissipation -O.5V to +7V . 1 Watt *COMMENT: Stresses above those listed under "Absolute Maxi- mum Rating" may cause permanent damage to the device.
SILICON GATE MOS 8102-2 A.C. CHARACTERISTICS T A = ooe to 70 o e, Vee = 5V ±5% unless otherwise specified SYMBOL READ CYCLE PARAMETER LIMITS --·---r----mT---- _.~~_~ ... _ ... l}YP._... ..L _~?<~. _._ UNIT os ns ns ns ns --t R-e------r-R--EA~D-C-Y--C-L-E--·------- --_ .
SILICON GATE MOS 8102·2 TYPICAL D.C. CHARACTERISTICS INPUT CURRENT VS. INPUT VOLTAGE -7.5 -1 OUTPUT SINK CURRENT VS. bUTPUT VOLTAGE 1.5 1.0 VOL (VOLTS) 0.5 VIN (VOLTS) EFFECTIVE INPUT CHARACTERISTIC I Vee g 5.0V ~~~b~.J VIL MAX. ( VIH MIN. V IN (VOLTS) +1 +2 +3 +4 +5 +6 Vee~ 5.
Silicon Gate MOS 8102A-4 1024 BIT FULLY DECODED STATIC MOS RANDOM ACCESS MEMORY • Access Time -450 ns Max. • Single + 5 Volts Supply Voltage • Directly TTL Compatible - All Inputs and Output •.
SILICON GATE MOS 8102A-4 ABSOLUTE MAXIMUM RATINGS· Ambient Temperature Under Bias Storage Temperature Voltage On Any Pin With Respect To Ground Power Dissipation -O.5V to +7V 1 Watt *COMMENT: Stresses above those listed under "Absolute Maxi- mum Rating" may cause permanent damage to the device.
SILICON GATE MOS 8102A-4 A. C. Characteristics T A = O°C to 70°C, Vee = 5V ±5% unless otherwise specified Limits Symbol Parameter TypJ1 ] Unit Min. Max.
SILICON GATE MOS 8102A-4 Typical D. C. and A. C. Characteristics POWER SUPPLY CURRENT VS. AMBIENT TEMPERATURE POWER SUPPLY CURRENT VS. SUPPLY VOLTAGE 15 o 10 20 30 40 50 60 70 T A (OC) Vee (VOLTS) I f-- T A "'25°C- V ./ / ~PICAL /r / I 35 5 1 10 15 25 30 ct ! 20 I I VeeMAX.
Silicon Gate MOS 81078·4 FULLY DECODED RANDOM ACCESS 4096 BIT DYNAMIC MEMORY * Access Time·· 270 ns max. * Read, Write Cycle Times--470 ns max. * Refresh Period -- 2 ms • Low Cost Per Bit • Add.
SILICON GATE MOS 81078·4 Absolute Maximum Ratings* Temperature Under Bias ooc to 70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65°C to +150 0 C All I nput or Output Voltages with Respect to the most Negative Supply Voltage, Vee .
SILICON GATE MOS 81078·4 ADDRESS CAN CHANGE 0 14-----------t ce (300) ----------~ 'JH -- ... --~-+------------------------_t-;-.....,r_----.,...-- tAC(O)- ....... -~ V ,HC ----+-----+-I..-oI!""!!----------------------- ..... CE t cO (2S0) ---------.
SILICON GATE MOS 81078·4 A. C. Characteristics T A = oOc to 70 0 C, V oo = 12V ± 5%, V CC = 5V ± 10%, Va a = -5V ± 5%, READ, WRITE, AND READ MODIFY /WRITE CYCLE vss = OV, unless otherwise noted.
SILICON GATE MOS 81078·4 Typical Characteristics Fig. 1. 100 AV VS. TEMPERATURE Fig. 2. TYPICAL 100 AVERAGE VS. CYCLE TIME t CE = 300ns ---f'~-t--""'~_t__-___t_-__1 I I tCE = 230n5 O~- ......... ---....---'O""--------.
SILICON GATE MOS 81078·4 Read Modify Write Cycle£1] Symbol Parameter Min. Max. Unit Conditions t RWC Read Modify Write( RMW) 590 ns tT = 20ns Cycle Time t CRW CE Width During RMW 420 3000 ns WC WE to CE on 0 ns t w WE to CE off 150 ns C load = 50pF, Load = One TTL Gate, twp WE Pulse Width 50 ns Ref = 2.
SILICON GATE MOS 81078·4 Typical Current Transients Ys. Time 100 200 300 400 500 0 100 200 300 400 500 I I I I I I I I I I I CE ~ WRITE J READ CYCLE CYCLE 30 20 A J Ice 10 (rnA) 0 V V 2.0 1.5 NORMALIZED 100 1.0 0.5 a 20 Iss 10 (rnA) 0 -10 --f- ....
SILICON GATE MOS 81078·4 Typical System Below is an example of a 16K x 8 bit memory circuit. Device decoding is done with the CE input. All devices are unselected during refresh with CS input. The 8210, 8205 and 8212 are standard Intel products. REFRESH 0----+0- CS 8228 {MEMW MEMR------------- 8080 1 ~~ Do .
intel e Silicon Gate CMOS 5101, 5101-3, 5101L, 5101L·3 1024 BIT (256 x 4) STATIC CMOS RAM *Ultra Low Standby Current: 15 nA/Bit for the 5101 • Fast Access Time - 650 ns • Single +5 V Power Supply.
SILICON GATE CMOS 5101,5101-3, 5101L, 5101L-3 Absolute Maximum Ratings * Ambient Temperature Under Bias. . . .. O°C to 70°C Storage Temperature -65°C to +150°C Voltage On Any Pin With Respect to Ground .... -0.3V to Vee +0.3V Maximum Power Supply Voltage +7.
SILICON GATE CMOS 5101,5101-3, 5101L, 5101L-3 A.C. Characteristics for 5101, 5101· 3, 5101 L, 5101 L- 3 READ CYCLE T A = o°c to 70°C, Vcc = 5V ±5%, unless otherwise specified.
SILICON GATE CMOS 5101,5101-3, 5101L, 5101L-3 Waveforms WRITE CYCLE DATA IN STABLE 14----- t ew1 --- ... 1..------- t we ------~ ~I----- t CW2 ------.t 1..---- tDw---~ --. tAW 104----t wP ----.I ~ __ -+ __ RIW CE2 DATA IN ADDRESS 00 (COMMON I/O) (4) CE2 DATA OUT ADDRESS READ CYCLE .
Schottky Bipolar 8210 TTL-TO-MOS LEVEL SHIFTER AND HIGH VOLTAGE CLOCK DRIVER • Four Low Voltage Drivers • One High Voltage Driver • TTL and OTl Compatible Inputs • Outputs Compatible with 8107.
SCHOTTKY BIPOLAR 8210 A.C. Characteristics TA = O°C to 70°C, VCC = 5.0V ± 5%, VDD = 12V ± 5% Symbol Parameter Min. Typ. Max. Unit tLd+ Delay Plus Rise Time for Low Voltage Drivers 5 13 20 ns tLd- .
SCHOTTKY BIPOLAR 8210 Absolute Maximum Ratings* Temperature Under Bias o°c to 70°C Storage Temperature -65°C to +150°C Supply Voltage, Vee -0.5 to +7V Supply Voltage, V oo -0.5 to +13V All Input Voltages -1.0 to +5.5V Outputs for Low Voltage Drivers .
SCHOTTKY BIPOLAR 8210 Typical System Below is an example of a 16K x 8 bit memory circuit. Device decoding is done with the CE input. All devices are unselected during refresh with CS i~put. The 8210, 8205 and 8212 are standard Intel products. REFRESH 0-----+--1 cs 8228 {MEMW MEMR -----4 __ -----~ 8080 f ~~ Do .
Schottky Bipolar 8222 DYNAMIC MEMORY REFRESH CONTROLLER BLOCK DIAGRAM • I nternal Address Multiplexer • Up to 6 Ro . (64x 64,t}' 'ff PIN CONFIGURATION • Adjustable Refresh Request Oscillator • Ideal for 8107A, 81078 4K RAM Refresh START CYCLE CYC.
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I/O 8212 8255 8251.
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Schottky Bipolar 8212 EIGHT-BIT INPUT/OUTPUT PORT • Fully Parallel 8-Bit Data Register and Buffer • Service Request Flip-Flop for Interrupt Generation • Low Input Load Current - .
SCHOTTKY BIPOLAR 8212 OUTPUT BUFFER -INTERNAL SR FLIP-FLOP CLR (OS1- 0S 2) STB -SR tNT 0 0 0 , , 0 , 0 , 0 , 1 '- 0 0 , 1 0 1 0 , 0 0 1 , 1 , ~I , 0 ~D18-------~ ..... ~ 01 7 -------+-1-1 DATA LATCH ff§> D IS ------- .............. IE> CLR-----001 ~~_ .
SCHOTTKY BIPOLAR 8212 8080 Status Latch 8008 System 8080 System: 8 Input Ports 8 Output Ports 8 Level Priority Interrupt Applications Of The 8212 -- For Microcomputer Systems I Basic Schematic Symbol VII II Gated Buffer VIII III Bi-Directional Bus Driver IX IV Interrupting Input Port V Interrupt Instruction Port VI Output Port I.
SCHOTTKY BIPOLAR 8212 BI-DIRECTIONAL BUS DRIVER III. Bi-Directional Bus Driver A pair of 8212's wired (back-to-back) can be used as a symmetrical drive, bi-directional bus driver. The devices are controlled by the data bus input control which is connected to D81 on the first 8212 and to D82 on the second.
SCHOTTKY BIPOLAR 8212 VI. Output Port (With Hand-Shaking) The 8212 can be used to transmit data from the data bus to a system output. The output strobe could be a hand-shaking signal such as "reception of data" from the device that the system is outputting to.
SCHOTTKY BIPOLAR 8212 VIII. 8008 System This shows the 8212 used in an 8008 microcomputer system. They are used to multiplex the data from three different sources onto the 8008 input data bus. The three sources of data are: memory data, input data, and the interrupt instruction.
SCHOTTKY BIPOLAR 8212 . IX. 8080 System This drawing shows the 8212 used in the I/O section of an 8080 microcomputer system. The system con- sists of 8 input ports, 8 output ports, 8 level priority systems, and a bidirectional bus driver. (The data bus within the system is darkened for emphasis).
SCHOTTKY BIPOLAR 8212 8080 ADDRESS .:... BUS (See Note 1) A O -' A 1 --+- A 2 --+- 8205 ~ ~ E 1 ::=:- ~ --0 E 2 ::- Vee - .. E_ 3 __ .. I/O DEVICE SELECTOR ST;~;T:¢ ST: 212 tt:7:::~~llllltnn~ 8212 => ~:~~T ~ ;:N~~- :IIII[ _~L~ee? INP -- .....
SCHOTTKY BIPOLAR 8212 Absolute Maximum Ratings· Temperature Under Bias Plastic .. -65°C to + 75°C Storage Temperature -65°C to +160°C All Output or Supply Voltages - 0.5 to + 7 Volts ,All Input Voltages -1.0 to 5.5 Volts Output Currents 125 mA D.
SCHOTTKY BIPOLAR 8212 Typical Characteristics INPUT CURRENT YS. INPUT YOLTAGE OUTPUT CURRENT VS. OUTPUT "LOW" YOLTAGE .8 .6 .4 .2 O'---~~'-----'-----.L..------' o « E I- 60 z w a: a: :::J u I- 40 :;) a. .... :;) 0 20 100 .
SCHOTTKY BIPOLAR 8212 Timing Diagram DATA 1.5Vy----------y.5V _____ -J. I;==t pw ~I_ tH :.j'---- STB or oSl • oS2 1.5vl ''-1._5V _ ~twE=J OUTPUT -/'10-: - - - - - -- oSl. OS2 1.5Vj 1.5V ________ l_tE_~ r _ ~E~~~W_) __ ~-t-D-~---- Y VOH OUTPUT X ~----,~t- VOL ~tpw~ f I I .
SCHOTTKY BIPOLAR 8212 A.C. Characteristics T A = O°C to + 75°C Vee = +5V ± 5% Symbol Parameter Limits Unit Test Conditions Min. Typ. Max. t pw Pulse Width 30 ns t pd Data To Output Delay 30 ns t we.
Silicon Gate MOS 8255 PROGRAMMABLE PERIPHERAL INTERFACE • 24 Programmable I/O Pins • Completely TTL Compatible • Fully Comp.atible with MCS™-8 and MCS TM'_80 Microprocessor Families • D.
SILICON GATE MOS 8255 8255 BASIC FUNCTIONAL DESCRIPTION General The 8255 is a Programmable Peripheral Interface (PPI) de- vice designed for use in 8080 Microcomputer Systems. Its function is that of a general purpose I/O component to inter- face peripheral equipment to the 8080 system bus.
SILICON GATE MOS 8255 (RESET) Reset: A "high" on this input clears all internal registers in- cluding the Control Register and all ports (A, B, C) are set to the input mode. Group A and Group B Controls The functional configuration of each port is programmed by the systems software.
SILICON GATE MOS 8255 8255 DETAILED OPERATIONAL DESCRIPTION Mode Selection There are three basic modes of operation that can be select- ed by the system software: Mode 0 - Basic Input/Output Mode 1 - Strobed Input/Output Mode 2 - Bi-Directional Bus When the RESET input goes "high" all ports will be set to the Input mode (Le.
SILICON GATE MOS 8255 CONTROL WORD r 0 7 t 0 6 I 0 5 1 0 4 I 0 3 1 O 2 I 0, I DO I I I I L BIT SET/RESET ,x X x, 1 = SET I 0:: RESET DON'T CARE BIT SELECT o 1 2 3 4 5 6 7 o 1 o 1 o 1 o 1 801 o 0 .
SILICON GATE MOS 8255 MODE 0 PORT DEFINITION CHART A B GROUPA GROUPB 04 PORTC PORTC 03 01 DO PORTA (UPPER) # PORT B (LOWER) 0 0 0 0 OUTPUT OUTPUT 0 OUTPUT OUTPUT 0 0 0 1 OUTPUT OUTPUT 1 OUTPUT INPUT 0.
SILICON GATE MOS 8255 CONTROL WORD #4 A 18 , 8255 ,4 c{ , . • ,4 -, B 1 8 I CONTROL WORD #5 0 , 0 5 P~.PBO CONTROL WORD #8 0 7 0 6 Os 0 4 0 3 ,0 2 0, DO A . ,8 I 8255 ,4 c{ , . . ,4 -, B 18 -, CONTROL WORD #9 0 7 0 6 0 5 0 4 0 3 O 2 0, DO A ,8 -, 8255 ,4 c{ -, .
SILICON GATE MOS 8255 CONTROL WORD #12 0 7 0 6 0 5 0 4 03 O 2 01 A ,8 F 8255 c{ · ,4 / • . ,4 , B ,8 I ~ CONTROL WORD #13 0 7 0 6 0 5 0 4 0 3 O 2 0, DO CONTROL WORD #14 0 7 0 6 0 5 0 4 0 3 O 2 0, DO A .
SILICON GATE MOS 8255 Input Control Signal Definition STB (Strobe (nput) A "low" on this input loads data into the input latch. IBF (Input Buffer Full F/F) A "high" on this output .
SILICON GATE MOS 8255 PC, OBF B P~.PBo 8 r- - -, I INTE I I A I __ .J MODE 1 (PORT A) MODE 1 (PORT B) CONTROL WORD CONTROL WORD 0 7 0 6 Os 0 4 0 3 O 2 0, Do INTEA Controlled by bit set/reset of PC 6.
SILICON GATE MOS 8255 Combinations of Mode 1 Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications. PA 7 -PA O 8 PC 7 OBF A PC 6 -+-- ACK A PC 3 INTRA 2 PC 4 • 5 I/O PB 7 -PB o PC 2 STB B PC, IBF B PC o INTR B CONTROL WORD PC, 2 PC 6 • 7 .
SILICON GATE MOS 8255 CONTROL WORD Mode 2 Control Word OBF A pC 200 ACK A 1 = INPUT 0= OUTPUT PORTB r--l 1 = INPUT IN;E I PC 4 . STB A 0= OUTPUT L __ J PC s IBF A WR GROUP B MODE 0= MODE 0 1 = MODE 1 3 AD PC 200 .
SILICON GATE MOS 8255 MODE 2 AND MODE 0 (INPUT) MODE 2 AND MODE 0 (OUTPUT) PC 3 INTRA PC 3 INTRA PA 7 -PA O PA 7 -PAo ~ OBF A P~ OBF A CONTROL WORD PC 6 . ACK A CONTROL WORD PC 6 . ACK A 0 7 0 6 05 04 03 O 2 0, DO 0 7 0 6 0 5 0 4 0 3 O 2 0, DO PC 4 STB A PC 4 .
SILICON GATE MOS 8255 MODE DEFINITION SUMMARY TABLE MODE 0 IN OUT PAO IN OUT PA1 IN OUT PA2 IN OUT PA3 IN OUT PA4 IN OUT PAS IN OUT PAe IN OUT PA7 IN OUT PBO IN OUT P81 IN OUT PB2 IN OUT PB3 IN OUT PB.
SILICON GATE MOS 8255 Printer Interface APPLICATIONS OF THE 8255 TERMINAL ADDRESS STi PC 3 - PAo R o 8255 PA, R, PA 2 R 2 FULLY PA 3 R 3 DECODED KEYBOARD PA 4 R 4 MODE 1 _ PAs R s (INPUT) PA 6 SHIFT P.
SILICON GATE MOS 8255 STi PC 3 r-- PB O Do PB, 0, PB 2 O 2 PB 3 0 3 FLOPPY DISK PB 4 . . 0 4 CONTROLLER AND DRIVE PBs D S MODE 2- PB 6 0 6 PB 7 0 7 PC 4 DATA STB PC S ACK (IN) PC 7 DATA READY _Pe 6 ACK (OUT) 8255 PC 2 TRACK "0" SENSOR PC o SYNC READY PC, INDEX r- PAO ENGAGE HEAD PAl FORWARD/REV.
~v ~V "",,-/7 "v '7 8080 MEMORY 8255 CPU ROM AND 8255 MODE 2 RAM A ~~ ..t. ~ 8255 MODE 2 SILICON GATE MOS 8255 I r--- ~---- MASTER CPU SYSTEM BUS (0, A, AND C) I- ----, ,-- 1-- --.
SILICON GATE MOS 8255 D.C. CHARACTERISTICS TA = o°c to 70°C; Vee = +5V ±5%; vss = OV Symbol Parameter Min. Typ. Max. Unit Test Conditions Vil Input Low Voltage .8 V V IH Input High Voltage 2.0 V Val Output Low Voltage .4 V IOl = 1.6mA VOH Output High Voltage 2.
SILICON GATE MOS 8255 INPUT A1,AO .. t RP ~ ~ ~ 7 I[ .--t'R---' ~tHR-----" >: K tAR ~tRA--" ~~ :~ ~tCR----' t RC ~ JV :0- ----- -- -- ---- ~ t RD .. too .. Mode 0 (Basic Input) A1,AO cs OUTPUT twp .. ~ { ,-- 7 f-- ~tDW~ ~twD--' )( K tAW .
SILICON GATE MOS 8255 IBF ~tRI INTR INPUT FROM _ PERIPHERAL I...-----t ps -----.· Mode 1 (Strobed Input) INTR OUTPUT Mode 1 (Strobed Output) 5-132.
SILICON GATE MOS 8255 . WR tAO OBF INTR ACK STB IBF PERIPHERAL _ BUS DATA FROM PERIPHERAL TO 8255 Mode 2 (Bi-directional) 5-133 DATA FROM 8255 TO 8080.
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Silicon Gate MOS 8251 PROGRAMMABLE COMMUNICATION INTERFACE .. Synchronous and Asynchronous Operation • Synchronous: 5-8 Bit Characters Internal or External Character Synchronization Automatic Sy.
SILICON GATE MOS 8251 8251 BASIC FUNCTIONAL DESCRIPTION General The 8251 is a Universal Synchronous! Asynchronous Re- ceiver/Transmitter designed specifically for the 8080 Micro- computer System. like other I!O devices in the 8080 Micro- computer System its functional configuration is programmed by the systems software for maximum flexibility.
SILICON GATE MOS 8251 Modem Control The 8251 has a set of control inputs and outputs that can be used to simplify the interface to almost any Modem. The modem control signals are general purpose in nature and can be used for functions other than Modem control, if necessary.
For Example: SILICON GATE MOS 8251 Receiver Buffer The Receiver accepts serial data, converts this serial input to parallel format, checks for bits or characters that are unique to the communication technique and sends an "assembled" character to the CPU.
SILICON GATE MOS 8251 DETAILED OPERATION DESCRIPTION General The complete functional definition of the 8251 is program- med by the systems software. A set of control words must be sent out by the CPU to initialize the 8251 to support the desired communications format.
SILICON GATE MOS 8251 Mode Instruction Definition The 8251 can be used for either Asynchronous or Synchro- nous data communication. To understand how the Mode Instruction defines the functional operation of the 8251 the designer can best view the device as two separate components sharing the same package.
SILICON GATE MOS 8251 o 0 1 1 5 6 7 8 BITS BITS BITS BITS L.....- -.. PARITY ENABLE (1 = ENABLE) (0 = DISABLE) 1 0 CHARACTER LENGTH o L.....- .. EVEN PARITY GENERATION/CHECK 1 c EVEN 0=000 Synchronous Mode (Transmission) The TxD output is continuously high until the CPU sends its first character to the 8251 which usually is a SYNC character.
SILICON GATE MOS 8251 COMMAND INSTRUCTION DEFINITION Once the functional definition of the 8251 has been pro- grammed by the Mode Instruction and the Sync Characters are loaded (if in· Sync Mode) then the device is ready to be used for data communication.
SILICON GATE MOS 8251 APPLICATIONS OF THE 8251 ADDRESS BUS ADDRESS BUS CONTROL BUS CONTROL BUS DATA BUS DATA BUS r----' I EIA TO TTL :. QJ) I CONVERT I PHONE (OPT) 8251 L ____ J :: ASYNC LINE MOD.
SILICON GATE MOS 8251 D.C. Characteristics: Symbol Parameter Min. Typ. Max. Unit Test Conditions V,L Input Low Voltage Vss-·5 0.8 V VIH Input High Voltage 2.0 Vee V VOL Output Low Voltage 0.45 V IOl = 1.6mA VOH Output High Voltage 2.2 V IOH = -1001lA ( DB o-7) IOH = -1001lA (Others) IOL Data Bus Leakage 50 IJ.
SILICON GATE MOS 8251 A.C. Characteristics: TA = o°c to 70°C; VCC = 5.0V ±5%; Vss = OV Symbol Parameter Min. Typ. Max. Unit Test Conditions tCY Clock Period .
SILICON GATE MOS 8251 READ AND WRITE TIMING CID,CS. ..,1'----------------""1"---------"1'-- D 7 -D O -----..--'I~ ~-- t DS -------1~ .. -- *WRITE ------J---..:.-/'..--- twR 1 ""-'-----...,t.......
Peripherals 8205 8214 8216/8226.
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Schottky Bipolar 8205 HIGH SPEED 1 OUT OF 8 BINARY DECODER • 110 Port or Memory Selector • Simple Expansion - Enable Inputs • High Speed Schottky Bipolar Technology - 18ns Max. Delay • Directly Compatible with TTL Logic Circuits • Low Input Load Current - .
SCHOTTKY BIPOLAR 8205 FUNCTIONAL DESCRIPTION Decoder The 8205 contains a one out of eight binary decoder. It ac- cepts a three bit binary code and by gating this input, creates an exclusive output that represents the value of the input code.
SCHOTTKY BIPOLAR 8205 APPLICATIONS OF THE 8205 The 8205 can be used in a wide variety of applications in microcomputer systems. I/O ports can be decoded from the address bus, chip select signals can b.
SCHOTTKY BIPOLAR 8205 Logic Element Example Probably the most overlooked application of the 8205 is that of a general purpose logic element. Using the lion-chip" enabl ing gate, the 8205 can be c.
SCHOTTKY BIPOLAR 8205 ABSOLUTE MAXIMUM RATINGS· T emperatu re Under Bias: Ceram ic Plastic Storage Temperature All Output or Supply Voltages All Input Voltages Output Cu rrents -65°C to +125° C -65°C to +75°C -65°C to +160 0 C -0.5 to +7 Volts -1.
SCHOTTKY BIPOLAR 8205 8205 SWITCHING CHARACTERISTICS CONDITIONS OF TEST: TEST LOAD: Input pulse amplitudes: 2.5V Input rise and fall times: 5 nsec between 1V and 2V Measurements are made at 1.5V 390n 2K All Transistors 2N2369 or Equivalent. e L = 30 pF ---.
Schottky Bipolar 8214 PRIORITY INTERRUPT CONTROL UNIT • Eight Priority Levels • Current Status Register • Priority Comparator • Fully Expandable • High Performance (50ns) • 24-Pin Dual In-Line Package The 8214 is an eight level priority interrupt control unit designed to simplify interrupt driven microcomputer systems.
SCHOTTKY BIPOLAR 8214 INTERRUPTS IN MICROCOMPUTER SYSTEMS Microcomputer system design requires that I/O devices such as keyboards, displays, sensors and other components re- ceive servicing in an efficient method so that large amounts of the total systems tasks can be assumed by the micro- computer with little or no effect on throughput.
SCHOTTKY BIPOLAR 8214 FUNCTIONAL DESCRIPTION General 'he 8214 is a device specifically designed for use in real time, interrupt driven, microcomputer systems.
SCHOTTKY BIPOLAR 8214 Control Signals The 8214 also has several inputs that enable the designer to synchronize the interrupt issued to the microprocessor and to allow or disallow such an issuance. Also, signals are pro- vided that perm it simple expansion to other 8214s so that more than eight levels can be controlled.
SCHOTTKY BIPOLAR 8214 APPLICATIONS OF THE 8214 8 Level Controller (8080) The most common of applications of the 8214 is that of an eight level priority structure for 8080 or 8008 microcom- puter systems.
SCHOTTKY BIPOLAR 8214 DO 8080 BI-ol RECTIONAL BUS ~ ~ ~ ~ ~ ~ ~ ~ 0 5 T 0 4 ~ I T ~ ~ I IT ~ I I I T 0 7 ~10K mmn ~ INT p23 I I I I I I I I c4> '(808~Np1N 14) 1K~ ~ ~: INTE • I I I I • I 7.
SCHOTTKY BIPOLAR 8214 APPLICATIONS OF THE 8214 Cascading the 8214 When greater than eight levels of interrupts must be priori- tized and serviced, the 8214 can be cascaded with other 8214s to support such an .
SCHOTTKY BIPOLAR 8214 D.C. AND OPERATING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias O°C to 70°C Storage Temperature -65°C to +150°C All Output and Supply Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCHOTTKY BIPOLAR 8214 A.C. CHARACTERISTICS AND WAVEFORMS TA = o°c to +70°C, vcc = +5V ±5% Limits Symbol Parameter Min. Typ.[1] Max. Unit tCY ClK Cycle Time 80 50 ns tpw ClK, ECS, INT Pulse Width 25.
SCHOTTKY BIPOLAR 8214 WAVEFORMS ENLG -----------------"'j( -------- -J. _ NOTES: (1) Typical values are for T A = 25°C ,Vee = 5.0V. (2) Required for proper operation if ISE is enabled during next clock pulse. (3) These times are not required for proper operation but for desired change in interrupt flip-flop.
Schottky Bipolar 8216/8226 4 BIT PARALLEL BIDIRECTIONAL BUS DRIVER • Data Bus Buffer Driver for 8080 CPU • Low Input Load Current - .25 mA Maximum • High Output Drive Capability for Driving System Data Bus • 3.
SCHOTTKY BIPOLAR 8216/8226 FUNCTIONAL DESCRIPTION DB, DB, ----OOB O ------oOB O '--------1- ----0 cs OlEN cs 0 0 Ol~ DB 1 0 OB~ DO 0 1 }HIGH IMPEDANCE 1 1 01 3 0-------+----1 >--+--.. 01, 0-------+---1 "--4--.. DO, o------t--~ I--~---' OlEN ~-------- .
SCHOTTKY BIPOLAR 8216/8226 APPLICATIONS OF 8216/8226 . 15 4 01 OlEN 3 0 0 2 DO DB OB o 7 0 1 6 OB 1 5 9 8216 8226 10 D 2 11 OB 2 12 13 DB 3 0 3 14 cs SYSTEM 8080 OATA 15 BUS 01 OlEN 3 D 4 OB OB 4 DO 6.
SCHOTTKY BIPOLAR 8216/8226 D.C. AND OPERATING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ' O°C to 70°C Storage Temperature -6SoC to +150°C All Output and Supply Voltages. ................... . .. ............. ..... .... .
SCHOTTKY BIPOLAR 8216/8226 WAVEFORMS INPUTS -'X'-:,_5V _ l--t FD OUTPUT ENABLE .5V ---+---V OH f VOL .5V A.C. CHARACTERISTICS TA = O°C to +70°C, Vcc = +5V ±5% Limits Symbol Parameter Min.
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Coming Soon 8253 8257 8259.
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Silicon Gate MOS 8253 PROGRAMMABLE INTERVAL TIMER GATE 0 It uses nMOS technology ~----"OUT2 ClKO ClK2 ClK 1 ...------..OUT 0 COU':;TER 14'-_ GATE 2 COUNTER #1 GATE 1 .
SILICON GATE MOS 8253 8253 PRELIMINARY FUNCTIONAL DESCRIPTION GATE 2 GATE 0 ClK 1 CLKO CLK2 OUT2 OUT 1 GATE 1 COUNTER #2 READ/ WRITE lOGIC DATA BUS BUFFER INTERNAL BUS cs-------' AD --___.
Silicon Gate MOS 8257 PROGRAMMABLE DMA CONTROLLER ORO 3 oACK 2 OACK 3 ORO 2 OACK 1 OACK 0 +-- ORO 1 cl}mputer systems. Its pri- allow the peripheral to ac- ; the system bus. I t also keeps "grar11mable terminal count has ~<, amon9,$fl'e four channels, program- for s~~tbred data transfers, an auto- /'dur!~:~i)DMA cycles.
SILICON GATE MOS 8257 8257 PRELIMINARY FUNCTIONAL DESCRIPTION The transfer of data between a mass storage device such as a floppy disk or mag cassette and system RAM memory is often limited by the speed of the microprocessor.
Silicon Gate MOS 8259 PROGRAMMABLE INTERRUPT CONTROLLER r up to 64 vectored priority technology and requires a IR 0 4---IR 1 REQUEST IR 2 LATCH 4--- IR 3 INTERRUPT MASK .
SILICON GATE MOS 8259 8259 PRELIMINARY FUNCTIONAL DESCRIPTION I INTERRUPT REQUESTS 8259 IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ 765 4 ~ 2 1 0 SLAVE PROG. ADDRESS BUS (16) 8259 System Interface.
CPU GROUP ROMs RAMs I/O PERIPHERAL COMING SOON Intel Standard Number Product Package Of Pins Comments Number Type 8224 C 0 P 16 - 8228 C 0 P 28 8080A C 40 Including 8080A-1, 8080A-2 and M8080A 8702A C.
PACKAGING INFORMATION Dimensions in inches and (millimeters). 16-LEAD CERAMIC DUAL IN-LINE PACKAGE (C) 16-LEAD CerDIP DUAL IN-LINE PACKAGE (D) I---l-~ ~ TYP . .11012,7941 ~:[O:::JJ I .735~ I .830 121,0821 ~!2.ill1_ .023 10,5841 :Q!Q~- . 06511.651 ~~ .
PACKAGING INFORMATION Dimensions in inches and (millimeters). 22-LEAD PLASTIC DUAL IN-LINE PACKAGE (P) PIN 1 ~ I ·34o~ .360 19.144) .126 13.175) I 1;r==i="-.=:::::p;;;;;r==:p;;;;r=;~==p:;r=::::p;:;;;;r=:::;;:::;;r==Fr===r;;;;;:;==;:;:or="'~ .
SALES AND MARKETING OFFICES U.S. SALES AND MARKETING OFFICES U.S. MARKETING HEADQUARTERS NATIONAL SALES MANAGER 3065 Bowers Avenue Hank O'Hara Santa Clara, California 95051' 3065 Bowers Avenue Tel (408) 246-7501 Sanla Clara.
u.s. DISTRIBUTORS u.s. DISTRIBUTORS WEST ARIZONA Cramer/Arizona 2643 East University Drive Phoenix 85034 Tel: (602) 263·1112 Hamilton/Avnet Electronics 2615 South 21st Street Phoenix 85034 Tel: (602) 275·7851 CALIFORNIA Hamilton/Avnet Electronics 575 E.
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INSTRUCTION SET Summary of Processor Instructions Instruction Code 11 J Clock(2) Instruction Code 11 J Clock (2) Mnemonic Description 07 06 Os 04 03 02 0, Do Cycles Mnemonic Description 07 06 Os 04 03 02 0, Do Cycles MOV r1 • r2 Move register to register 0 1 0 0 0 S S S 5 RZ Return on zero 0 0 '1 0 0 0 5/11 MOVM.
~ INSTRUCTION SET Summary of Processor Instructions By Alphabetical Order Instrumon Cod.lll Clock 121 Illstrudion Cod.(1) C1cckl2J Mnemonic Desaiptioll 07 06 0 5 04 03 02 01 DO Cychs Mn.
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