MitsubishiメーカーWS-48513の使用説明書/サービス説明書
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MITSUBISHI ELECTRIC MITSUBISHI DIGIT AL ELECTRONICS AMERICA, INC. T 2003 ECHNICAL RAINING Projection T elevision T echnical T raining & T roubleshooting Manual W S-48613 W S-65713 WS - 55813 W S-5.
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T 2003 ECHNICAL RAINING V23 Chassis Projection Television T echnical Training & Troubleshooting Manual Copyright © 2003, Mitsubishi Digital Electronics America, Inc.
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I Introduction ... New Technologies Models ............................................................................................................... 1 Features .....................................................................................
II Chapter 5 ... Video/Color Circuitry Overall Block Diagram ....................................................................................... 5-1 PCB- Terminal ....................................................................................
1 Introduction The V23 Chassis is carried in the Gold , Gold Plus , Platinum and Diamond series models for 2003 and 2004. This full featured, integrated HDTV chassis represents the latest technologies in C RT based pro- jection television. A breakdown of V23 models is shown in Table 1 .
2 Feature Explaination ATSC and Unscrambled QAM Reception Greater Sensitivity NetCommand™ 3.0 Home Theater Control by Firewire or IR Five-Format Memory Card Reader For viewing JPEG digital photos and listening to MP3 or WMA audio recordings.
3 NetCommand 3.0 NetCommand allows most common home theater products to be connected and controlled by way of the TV's re- mote control by simply selecting on- screen icons.
4 5 Format Memor y Card Reader Digital music and photography can now be enjoyed in the home theater environment thanks to the memory card reader featured in the V23 chassis.
5 Compatibility Users having difficulties with the memory card reader should be aware of the following requirements: For JPEG Pictures up to 128mb: 1. Still images recorded using the Exchangable Image File Format (EXIF) for digital still cam- eras and Design Rules for Camera File Sys- tems (DCF).
6 MonitorLink™ MonitorLink is a new digital interface introduced in Mitsubishi's 2003-2004 model line, including the V23 chassis. MonitorLink provides a proprietary connection for Mitsubishi's HD-5000, Monitor/Receive r, allowing Mitsubishi's upgradeability promise to be fulfilled using a digital, rather than analog, interface.
7 Used with its optional copy protection scheme, DVI makes it possible to view full resolution signals with- out exposing the signal to copyright infringement. It is the digital equivalent of component DTV con- nections ( Y ,P r,Pb) that can be configured for use in a copy protected environment.
8 Display Data Channel (DDC) The VES A standard Display Data Channel, shown in Figure 10, is part of the DVI specification. It is an I 2 C bus used for data communications between the two devices. The data can include information specifying the type of display device connected and can also be used to support copy protection.
9 High-bandwidth Digital Content Protection (HDCP) HDCP is a system designed to protect the outputs of a DVI device from being copied. The protection can be applied in various ways.
10 P IN S IG NAL P IN S IG NAL 1 TMDS Da ta 2- 16 Ho t Plug Detect 2 TMDS Da ta 2+ 17 TMDS Da ta 0- 3 TMDS 2&4 S h ie ld 18 TMDS Da ta 0+ 4 TMDS Da ta 4- (N A) 19 TMDS 0&5 S h ie ld 5 TMDS Da .
11 Figure 13: V23 Chassis DVI Input Block Diagram.
12 Chassis Option Menu Adjustment Mode Convergence Mode OSD Position VZ5/VZ6/V15 1-3-7-0 2-3-5-7 2-3-5-9 <6><5><4> Adjust Mode VZ7/VZ8/V16 1-2-7-0 1-2-5-7 1-2-5-9 <6><5>&.
1-1 Chapter 1 Disassembly and Service Figure 1-1: Lightbox Removal - 48” Models With 11 different models, mechanical features and disassembly procedures vary in the V23. Since all features and disassembly procedures are in the Ser- vice Manual, this chapter will only provide a gen- eral discussion.
1-2 The lightbox removal procedure for 48” V23 mod- els is shown in Figure 1-1 . 1. Remove the Back Board by removing 7 screws (a), 2 screws (b) and 8 screws (c). 2. Remove the Back Cover by removing 8 screws (d). 3 Remove 4 screws (e) to remove the Board Slide.
1-3 Figure 1-2: Main Chassis Removal Figure 1-3: DM Replacement Step 1 Step 2 Step 3 TOP VIEW REAR VIEW TOP VIEW.
1-4 Figure 1-4: PCB Locations Figure 1-5: Main Component Locations.
1-5 PCB & Major Component Locations PCB and major component locations are shown in Figures 1-4 and 1-5. The major circuit functions performed on each PCB is listed in Table 1-1 .
1-6 V23+++ Composite Cabinet Back The WS-55813 and WS-65813 feature a unique cabi- net similar to last year ’s WS-65712. It has a com- posite cabinet back that offers several advantages. • Rounded edges in the back have a modern appearance. • Unit construction gives it high strength.
2-1 Chapter 2 Alignment Procedures With the exception of the Service Menu access codes, the general alignment procedures for the V23 chas- sis remains the same as previous HD chassis. A chart showing all recent Service Menu Access Codes is provided on page 12 of the Introduction.
2-2 Audio Edit Setup Clock Setting Manual Volume 30% Review Time 12:00 AM Bass 50% Antenna A ( v ) Enabled Day Monday Treble 50% Antenna B ( v ) Enabled Balance 50% Input DTV ( v ) Enabled Analog Capt.
2-3 Circuit Adjustment Mode Most of the adjustments can only be performed us- ing the remote hand unit. See Figure 2-2 . Many of the adjustments must be performed in both the 480i and 1080i modes. V ideo/Color adjustments must be performed in the 480i and 1080i modes, and data must be preset in the 480P (DVD) and VG A modes.
2-4 Selection of adjustment Functions and Adjustment Items To select an adjustment item in the circuit adjustment mode, first select the adjustment function that includes the specific adjust- ment item to be selected. Then select the adjustment item. Refer to the following pages for the listing of adjustment functions and adjustment items.
2-5 Convergence Adjustment Mode The Convergence mode is used to perform raster ge- ometry correction and convergence adjustments. These adjustments must be made in both the SD (NTSC 480i) and HD (1080i) modes. Note: Before activating the Convergence mode, turn “ V ideo Mute” Off.
2-6 1) Use AUDIO button to select a Sub Function 2) Use the VIDEO button to select an Adjustment Item. 3) Use the ADJUST buttons to change data. FINE CONV (Press 4) This mode is used to perform Fine Raster Correction, and Fine Red and Blue Conver- gence Adjustments.
3-1 Chapter 3 Power Supply From the above diagram, it is apparent that the V23 Chassis has four Power Supply Operational Modes. 1) Low Energy Mode 2) Standard Standby Supply Mode. 3) Time Shift Recording Mode. 4) Conventional PTV On Mode. Lo w Energ y Mode When the Low Energy Mode is activated the TV uses less than 3 Watts while the set is Off.
3-2 A 132 kHz internal Oscillator drives an internal Output FE T . The signal from the FET at pin 5 of IC9A10, drives transformer T9A10. Signal from pin 10 of T9A10 is rectified, generating the 9VS suppl y. The signal from pin 2 of the transformer is rectified and takes two paths: 1) To pin 1 of IC9A10, adding to an internally generated 6.
3-3 Low Energy Power Distribution Figure 3-4 shows the Low Energy Mode Power Dis- tribution. As stated earlie r , the Low Energy 9VS is the source for the 5VS, 3.3 V -ES and 3.3VS-1. The 5VS and 3.3VS-1 supplies power to the IC7A00 the PTV Control µPC.
3-4 Standard Standby Supply The Standard Standby Regulator circuit is shown in Fig- ure 3-5. Start-up The Start-up V oltage Supply is from R9A18 in the Low Energy Mode circuit, refer to Figure 3-2 . The SUB- POWER command from the Control Circuitry activates the Standby Suppl y.
3-5 Standard Standby Supplies Two Standby supplies are generated directly from T9A20, 12VS and 6VS. Both of these supplies are directed to the DM module, and are denoted as 12 V- DM and 6 V -DM. A 30VS supply is derived from the 12VS source using voltage doubler circuitr y , comprised of D9A31, D9A32, C9A32 and C9A27.
3-6 When PON-1 goes High, Q9A21 turns Off, allowing Q9A20 to turn On. With Q9A20 conducting, the 12V supply is generated from the 12VS suppl y . The 12V supply enables IC9A22 and the 5 V -1 supply is gener- ated. Time Shift Supply Power Distribution Figu re 3-8 illustrates the Power Distribution for the Time Shift supplies.
3-7 gence Generator, 3DYC and Signal Select circuitr y , and to IC2E65. IC2E65 generates 2.5 V olts for 3DYC. The 12V supply provides power for Tuners and C RT Protect circuitr y . It also is the source of four additional DC Supplies: • 9V-1 for the Signal Select circuitry • 5V-DECOD for the NTSC Decoders.
3-8 the oscillator drive to the FE T . The PWM is automati- cally changed to maintain a constant 110V source. Five supplies are directly generated by signal from T9A50, 210 V , 110 V , 17 V , +24V and -24 V. Power Distributions Figure 3-10 shows the Switched Supplies Power Dis- tribution.
3-9 If the LED does not flash: • Check that t he DM board is seated properl y. • Check that t here is Standby 9VS (Fig. 3-2) . • Check that t he SUB-POWER command line does not go High (Fig. 3-5 ). • Chirping sound - check the Standby Regulato r, IC9A20 (Fig.
3-10.
4-1 Chapter 4 Control Circuitry As in the two earlier integrated HDTV chassis, V19 and V21, the V23 uses two Microprocessors in the Control circuitr y. 1) TV µPC … controlling the analog circuitr y. 2) DM µPC … controlling the digital circuitr y.
4-2 we are not showing the details of the DM circuitr y . Fig- ure 4-1 shows only the DC supplies and Reset signal going to the DM module. Reset Circuitry Figure 4-2 illustrates the Reset circuitry in more detail. The normal and Reset logic are shown in the diagram.
4-3 Both the µPCs have the ability to reset each other if communication is lost. IC7C30 serves as a Reset inter- face between the two µPCs and the front panel Reset button. If the TV µPC gets no response from the DM, it outputs a High at pin 73 of IC7A00.
4-4 IR signals from a Mitsubishi Remote are directed to the RMC input of IC7A00. The signals are filtered, pro- cessed and directed over the IR-IN-BUSY line to the SYS-5 µPC on PCB-DTV TUNER. If the SYS-5 cir- cuitry is bus y , it holds the IR-IN-BUS Y line Low until it is clear to receive data.
4-5 Note that the output of the Wide Band Preamp (IR-IN) is also directed to the SYS-5 µPC. This connection was not used in the V19 and V21. It enables the Learn- ing feature. The signals from the units Remote are memo- rized by the SYS-5 circuitr y.
4-6 SHO RT Detect The short Detect circuitry is shown in Figu re 4-6 and is the same as in the V19 and V21 chassis. If a short occurs in the + or – 24V supplies, pin 46 on IC7A00 goes Low indicating a short and the TV shuts Off. With -24V shorted, the 12VS supply turns Q9A53 On, pull- ing the SHO RT line Lo w .
4-7 Parallel Outputs Most of the parallel outputs are listed in Table 4-2. Most of them have been used before and need no explana- tion. Howeve r, the function of two items should be de- scribed. BWC (Band Width Control) This line is directed to the Doubler circuitr y , and auto- matically becomes active when the signal source is NTSC.
4-8 The PerfectColor feature is performed in the Doubler circuit, therefore all signal sources must pass through the Double r . With DM signal sources, any OSD is al- ready inserted in the signal before it goes to the Dou- ble r . The PerfectColor circuitry can cause incorrect color in the OSD.
5-1 Chapter 5 Video/Color Circuitry The above block diagram illustrates the V ideo/Color circuitry in the V23 chassis. Although initially it looks the same as in the V21, there are differences. The A/V Switch circuitry still selects main and sub picture signals from NTSC signal sources.
5-2 PCB-TERMIN AL Video Path Figu re 5-1 illustrates the Video Signal Path on the PCB- TERMINAL. The AV -Switch circuitry has not changed, IC2L00 and IC2K00 are the same ICs used in the V21 chassis. The 3DYC Motion Adaptive Come Filter provides a clean separation of luminance (Y) and chroma (C) sig- nals.
5-3 The Sub picture signals from IC2B00 are directed to IC2G00, the Sub Decode r . Switch circuitry in IC2G00 selects Sub picture signals from IC2B00 or the AV- SW(2), IC2K00. As in previous chassis, the main and sub selected YPbPr signal are direct to the PCB-SIGNAL.
5-4 The outputs of the Doubler circuit, ASIC- Y , ASIC-Pb and ASIC-Pr are directed to the VCJ. The signals are processed in the VCJ and C RT RGB drive signals are output at pins 64, 63, and 62. CRT Drive & Protect Circuitry Figu re 5-3 shows the C RT Drive circuitr y .
5-5 Digital Signal Path The basic Digital Signal path was shown in Figure 5-2. Figu re 5-4 shows the Digital Path in more detail. Digi- tal signal sources are the DTV/AQM Tuner, 1394 In- puts and the front panel Card Reade r . There are two 1394 inputs at the rear of the DM module.
5-6 Monitor Out Circuit Figu re 5-5 shows that the Monitor Output signal source is limited to an NTSC source, or the DM Module. The NTSC Y and C signals from the 3DYC Comb Filte r, are directed back to IC2L00. IC2L00 directs the sig- nals to the monitor Inputs of IC2K00.
6-1 Chapter 6 Sync, Deflection & High Voltage The Overall Sync, Deflection and Hign V oltage cir- cuitry in the V23 is shown in the Block Diagram at the top of the page. The V23 can display either of two scanning formats, 480p or 1080i. The horizon- tal scanning frequency for 480p is 31.
6-2 Sync Signal Path Figure 6-1 illustrates the Sync Signal Path for the Main Picture signals on the PCB- Terminal. IC2K00, IC2A00, IC2B00 and IC2A95 comprise the Main Picture Sync Select Circuitr y . Sync must be extracted from NTSC, Composite and Component Format Y Signals.
6-3 Figure 6-2 illustrates the Sub Sync Signal Path for the Sub-Picture signals on the PCB- Terminal. It functions the same as the Main Sync Signal Path using different pin sets on the same ICs. The sub sync signals are used by Doubler circuitry for POP/ PIP signal processing.
6-4 From the flip-flops, sync pulses are directed to the VCJ, IC2V01. Both Horizontal and V ertical Drive Generators are in the VCJ. Horizontal drive is out- put at pin 40, and vertical drive is output at pins 52 and 53. The signals are directed to their respective output circuitry on the PCB-MAIN.
6-5 Vertical Deflection Figure 6-4 shows the V ertical Deflection circuitr y. The V ertical Deflection Generator in the VCJ out- puts push-pull type of vertical deflection drive sig- nal. +VDR at pin 53 and –VDR atz pin 52. Both signals are applied to the V ertical Output IC, IC4B01.
6-6 Horizontal Deflection DC Supply Circuitry The DC supplies for Q5A32 and Q5A31 are derived from Horizontal Deflection DC Supply circuitr y . The 31K line from the Control µPC controls the DC volt- age for Q5A31. Q5A31 supply voltage is approxi- mately 10 volts higher for the 33.
6-7 The DEFL-MUTE line from the µPC and Q5A08 reduce the DC supply during scan frequency change by the same method. The DC supply for the Horizontal Drive transisto r, Q5A32, is derived from the Horizontal Output DC supply through R5A36, R5A37 and Q5A34.
6-8 HV & HV Regulation Figure 6-8 illustrates the HV and HV Regulation cir- cuitr y . Drive from the Horizontal Deflection Out- put circuitry is applied the HD-IN input of IC5A00. IC5A00 amplifies the signal which is output at pin 1, and through Q5A07 and Q5A09, is applied to the gate of Q5A51.
6-9 DO NOT measure the H V -DC-FB voltage at pin 13 of the T5A51. The meter may load down the inter- nal resistive divide r, resulting in excessive H V. X-Ray Protect X-Ray Protect circuitry is the basically the same as in previous models, as shown in Figure 5.
6-10 Q5A20 and its associated circuitry comprise an Arc Protect circuit. If a C RT Arcs this circuitry immedi- ately removes HV Drive. If X-Ray Protect shuts the TV Off, pressing the Power button will turn the TV back On (it may shut Off again if the problem still exists).
7-1 Chapter 7 Convergence Circuitry The Overall Block Diagram in Figure 7-1 shows the the V23 Convergence Circuitr y .. A W aveform Gen- erator generates the convergence correction signals timed from horizontal and vertical sync pulses. The correction signals from the Waveform Generator are in a serial digital format.
7-2 Waveform Generator & D/A Converter Figure 7-2 illustrates the Convergence Waveform Generator and Digital/Analog Converter circuitr y. Horizontal Sync from the doubler circuitry is applied to pin 34 of IC8D00. V ertical Sync is applied to pin 27.
7-3 LPF & Summing Amps Figure 7-3 illustrates the LPF and Summing Ampli- fiers. The circuitry consists of three ICs, IC8E00, IC8E01 and IC8E02. Each correction signal from IC8D00 goes through two stages of amplification: 1) The first stage is part of the LP F.
7-4 Convergence Output Circuitry Figure 7-4 shows the Convergence Output circuitry located on the PCB-Powe r . The correction signals Figure 7-4: Convergence Output Circuitry are amplified and directed to the Sub V ertical and Sub Horizontal coils located within their respective red, green and blue Deflection Y okes.
8-1 Chapter 8 Sound Circuitry The V23 Sound Circuitry is shown above in the Over- all Block Diagram, Figure 8-1 . The Sound Source Select circuitry selects the sound source for both the main and sub pictures.
8-2 Figure 8-2: Overall Sound Circuitry Block Diagram.
8-3 Overall Sound Signal Path Figure 8-2 illustrates the Overall Sound Circuitry Block Diagram. The AV/SW ICs, IC2L00 and IC2K00, used to select Main and Sub Picture V ideo/ Color are also used to the select the Sound sources.
8-4.
9-1 Chapter 9 Troubleshooting Tips Use the following tips when troubleshooting the source of a problem in the V23 chassis. Using The Front Panel LED The Front Panel LED helps isolate the cause of the following problems. • The TV will not turn On. • The TV turns On, and then Shuts Off.
9-2 DM Module Check When the TV turns On, but a problem exists that may be caused by the DM Module, perform the following two checks: 1) Select the DTV Antenna as the source an select and HD Channel. 2) Select an analog 480i signal as the source and note if an On Screen Display (OSD) is present.
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Copyright © 2003 Mitsubishi Digital Electronics America, Inc. 9351 Jeronimo Road • Irvine, CA 92618-1904 T/M V23.
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