Arm EnterprisesメーカーGP4020の使用説明書/サービス説明書
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GP40 20 GP S Ba se band Pr oces sor D esi g n Man ual Publication Nu mber: DM 5280 Issue: 3 Re visi on : 002 Issued: Janu ary 2002 Zarlink Se miconductor , Chene y Manor Swindon, Wiltshire, U nited K .
ii Manu al Revision History Vers ion Re visio n Da te Up date Su mmary 1 001 Fe brua ry 20 00 Fi rst Ver sion 2 00 1 Aug ust 20 00 GN D a n d VD D p ins mar ked as t yp e “PW R” in t abl es 2 .2 and 20 .1. Modif i ed T EST MOD E ( pin 74 ) def in iti on.
GP4020 GPS Baseband Processor Design Manual iii Contents Page Co nte nts ....................................................................................................................... ..................iii Re late d P rodu cts and Doc ume nts.
iv GP4020 GPS Baseband Processor Design Manual 8.3 DM AC Tri gg e ring ................................................................................................................ 99 8.4 Cautionary No tes ..........................................
GP4020 GPS Baseband Processor Design Manual v 19.2 GP4020 F ir e fly MF1 A ddress M ap ..................................................................................... 183 20 INPU T / OU TPU T PIN CH AR A CTERIS TICS .............................
vi GP4020 GPS Baseband Processor Design Manual Docum ent Refer ences Re fer e nces to t he following d ocumen ts are made w ithin the GP4020 GPS Ba seband P roce ssor De si gn Manua l: 1) "ARM7TDM I Technical Re f e r e nce M anual " ARM DDI 0029F , Rev 4 Copyrigh t ARM Limited 20 01.
1: Int r oduc tion GP4020 GPS Baseband Processor Design Manual 1 1 INTRODUCTION 1.1 GP4020 GPS Baseband Pr ocessor Ov erv iew This de si gn manua l describe s the GP4020 GPS Base band Processor , which is base d on the Zarlink Se mi condu ct o r Fire f ly M F1 M i c rocontroller Co re ( r e f.
1: Int r oduc tion 2 GP4020 G PS Ba seband P rocessor Des ign M anual 1.3 Fun ctional Descripti on 12 CHANNEL GPS CORRELATOR RAM (2k x 32) MPC UIM ARM7TDMI MICRO JTAG UART1 DMAC TIC SSM INTC Firefly M.
1: Int r oduc tion GP4020 GPS Baseband Processor Design Manual 3 1.3. 1 A RM P rocesso r (A RM7T DMI ) The ARM7TDM I is a 32 -bit RISC microp rocesso r core de signed b y Advance d RI SC Machine s (ARM ) .
1: Int r oduc tion 4 GP4020 G PS Ba seband P rocessor Des ign M anual De tai ls ca n be found in s ection 6 "B µ ILD SER IAL INPU T OUTPUT ( BSI O) INTER FACE" on page 33. 1.3. 5 12 Chan nel Correlato r (CORR) This m odu le contains 1 2 channe ls of P RN code correlators for spre ad-spectrum correlation of 12 s imultaneous signals.
1: Int r oduc tion GP4020 GPS Baseband Processor Design Manual 5 1.3. 9 Gen eral Purpose Inpu t Output (GPIO) This m odu l e prov i de s e ight I/O pins, w hi c h may be b i t or byte addresse d and configured i n a l atche d or t r ans parent mode.
1: Int r oduc tion 6 GP4020 G PS Ba seband P rocessor Des ign M anual Since the in t e rnal SRAM i s hi gh-spe ed, it can be a ccesse d with Zero wait-state s through the M e m ory Pe ripheral Cont roll e r . Refer t o section 11 "ME MORY PERI PHERAL C O NTR OLLER (M PC)" on p age 1 09, for more i nfor mati on.
1: Int r oduc tion GP4020 GPS Baseband Processor Design Manual 7 Further de tail s of the function and p rogramming S yste m Se rvices Modu le can be found in Sec tions 2 and 8 o f the "Firefl y M F1 Core D esign Manual" DM5003, avai lable from Za rlink S emi conductor .
1: Int r oduc tion 8 GP4020 G PS Ba seband P rocessor Des ign M anual 1.4 T y pical A pplication ANTENNA 470 470 1k SAMPCLK SIGN0 MAG0 (58) (59) (61) (62) (63) (64) (56) GP4020 (84) BuILD _CLK M_CLK P.
1: Int r oduc tion GP4020 GPS Baseband Processor Design Manual 9 Figure 1.2 above shows a typ i ca l GPS re ceive r e m ploying a GP 2015 RF front–end, and a GP4020 correla tor. The RF sect i on, GP2015, performs d own conve rsion of the L1 (1575.42MHz ) signal f o r digita l baseband p r oce ssing.
1: Int r oduc tion 10 GP4020 GPS Baseband Processor Design Manual Thi s page intentional ly left bl ank..
2: G P4020 Package and El ectrical Conn ections GP4020 GPS Baseband Processor Design Manual 11 2 GP40 20 PACK AGE A ND ELEC TRIC AL CONNE CTIONS 2.1 GP4020 100 -pin Packa ge Dimen sions The GP4020 GPS B aseband P rocessor is available from Zarlink Se m i c onductor in a 1 00-pin gull-w i ng Thin Quad Flat Package (TQFP ).
2: G P4020 Package and El ectrical Conn ections 12 GP4020 GPS Baseband Processor Design Manual Figure 2.2 GP4020 100-pin p ackage ou tline draw i ng.
2: G P4020 Package and El ectrical Conn ections GP4020 GPS Baseband Processor Design Manual 13 Symbol Dimens ions i n millim etres MI N N om in a l MA X A 1.4 0 1.60 A1 0.0 5 0.15 A2 1.3 5 1.45 D 15. 80 16.20 D1 13. 80 14.20 D3 12. 00 E 15. 80 16.20 E1 13.
2: G P4020 Package and El ectrical Conn ections 14 GP4020 GPS Baseband Processor Design Manual Pi n No . Signal N ame T ype Circui t Bl oc k De scr ip tion N o t es 24 SDATA[7] I/O MPC System Dat a bi.
2: G P4020 Package and El ectrical Conn ections GP4020 GPS Baseband Processor Design Manual 15 Pi n No . Signal N ame T ype Circui t Bl oc k De scr ip tion N o t es 61 SIG N0 I COR R S ampl ed Si g n .
2: G P4020 Package and El ectrical Conn ections 16 GP4020 GPS Baseband Processor Design Manual Pi n No . Signal N ame T ype Circui t Bl oc k De scr ip tion N o t es 88 TDO / bdiag[2] / XBurs t I/O JTA.
2: G P4020 Package and El ectrical Conn ections GP4020 GPS Baseband Processor Design Manual 17 TEST (pin 67) T ESTM OD E (pin 7 4) TEST FUNCTI ON GND (0) GND (0) N o rm al Operation VDD (1) GND (0) Fi.
2: G P4020 Package and El ectrical Conn ections 18 GP4020 GPS Baseband Processor Design Manual iii) NIC E = Hig h an d NT RS T = Lo w: Fir e fly MF 1 Syste m Te st Co ntrol input signal s are connecte.
3: ARM7T DMI TM Microp r o cessor GP4020 GPS Baseband Processor Design Manual 19 3 A RM7TDMI MICROPROCESSOR Th e ARM 7T DM I is a m e m b er of t he A dv an c ed R I SC Ma chi n es ( AR M) f am il y o f g ener a l - pur po s e 32 - bit microproce ssors, which o ff e r hi g h per formance for very low powe r cons umption and pri ce .
3: ARM7T DMI TM M i croprocesso r 20 GP4020 GPS Baseband Processor Design Manual If a 16-b it arch itecture on ly has 16 -bit inst ructions, a nd a 32 -bit arch itecture only h as 32-bit instruction s, then ove rall the 16-b it archi t e ctur e will have be t ter code de nsity.
3: ARM7T DMI TM Microp r o cessor GP4020 GPS Baseband Processor Design Manual 21 M nemonic Instr ucti on Actio n AD C Ad d w ith c a rry Rd := Rn + Op2 + Car ry ADD Add Rd := Rn + Op2 AND AND Rd := Rn.
3: ARM7T DMI TM M i croprocesso r 22 GP4020 GPS Baseband Processor Design Manual M nemonic Instr ucti on Actio n Lo/Hi regi ster oper ands Condi tion co des se t AD C Ad d w i th Ca rry Rd := Rd + Rs .
3: ARM7T DMI TM Microp r o cessor GP4020 GPS Baseband Processor Design Manual 23 • Syste m (sys) A privilege d user mode for the operating syste m • Unde fi ned (un d) Entere d whe n an unde fi ne.
3: ARM7T DMI TM M i croprocesso r 24 GP4020 GPS Baseband Processor Design Manual System & Use r FIQ Superv isor Abor t IRQ Undef ined R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R3 R3 R3.
3: ARM7T DMI TM Microp r o cessor GP4020 GPS Baseband Processor Design Manual 25 An int errupt impul se to t he ARM 7TDMI will cause it to e xit SLEEP m ode. I n cert a i n cir cumstances, t his m ay cause th e ARM7TDMI to e nt er an UNDEF ( Undefi ned Instr uction) t rap ( to a d dr ess 0x04).
3: ARM7T DMI TM M i croprocesso r 26 GP4020 GPS Baseband Processor Design Manual Thi s page intentional ly left bl ank..
4: Boot ROM GP4020 GPS Baseband Processor Design Manual 27 4 BOOT ROM 4.1 Fun ctional Descripti on The GP4020 Boot R OM is an internal part of t he IC. Th e code i n t he Boot ROM will a ll ow t he GP4020 base d GPS r ecei ver t o u p-l oa d a sof t w ar e ro uti ne i nt o RA M f rom a n ext er n al d at a so u rc e ( e.
4: Boot ROM 28 GP4020 GPS Baseband Processor Design Manual 0000, and the ROM space from 0x6000 000 0. The ARM7TDM I will then be gi n exe cut ion of code downloade d to the I nternal RAM , s t a rting a t ad dress 0x 6000 0000 .
4: Boot ROM GP4020 GPS Baseband Processor Design Manual 29 HEADER BYTE 1 (MSB) HEADER BYTE 2 HEADER BYTE 3 (LSB) DATA BYTE 1 Header Bytes 1, 2, 3 produce 24-bit number indicating total number of Data Bytes (N) to be received. Byte 1 = Most Significant.
4: Boot ROM 30 GP4020 GPS Baseband Processor Design Manual Thi s Page intenti onall y l ef t bl ank..
5: T h e B µ ILD BUS GP4020 GPS Baseband Processor Design Manual 31 5 The B µ ILD BUS The GP4020 Base band Pro cessor CPU subsys tem is i nt e rnally b ased ar ound the B µ IL D bu s. T he AR M7 TD MI processor i s conne cted to pe ripherals through i ts B us for µ Controll er I nt eg r ati o n i n L ow - Powe r D esigns (B µ ILD ).
5: T h e B µ ILD BUS 32 GP4020 GPS Baseband Processor Design Manual Exa m ple sl a v e dev i c es ar e: • UART • Mem ory / Periph eral Contr oller • Ge ne ral Pu rpose Inpu t Ou tpu t 5.
6: BSIO Interface GP4020 GPS Baseband Processor Design Manual 33 6 B µ ILD SERI AL INPU T OUTPUT (BSIO ) INTERFACE 6.1 Overv iew A 3- w ir e se rial input/output is include d i n the GP4020 to al l ow se rial dat a co nnection to any device wi t h a thre e-pin s eri al i nt er f ac e.
6: BSIO Interface 34 GP4020 GPS Baseband Processor Design Manual 6.1. 3 A rch itect ure BSIO_SS[0] BSIO_SS[1] BSIO_DATA BSIO_CLK GP4020 BSIO SERIAL INTERFACE CS CS CLK CLK DATA DATA IN EEPROM LCD DATA OUT Figur e 6.1 Using B µ I LD Serial Input Outpu t ( BSIO) with EEPROM and LCD pe ripher a l s 6.
6: BSIO Interface GP4020 GPS Baseband Processor Design Manual 35 • After all data ha s bee n sent, s ince there is no read da ta, a re ad data interrupt is gene r ated imme di a tely. If reading dat a, a re ad inter r upt w ould be ge nerated afte r each f our by tes o f data a re read and a f ter the l as t byte of data is read.
6: BSIO Interface 36 GP4020 GPS Baseband Processor Design Manual READ BU FFER WRITE BU FFER FREQ UENCY DIV IDER SLAVE SELECT LOGIC INT ERRUPT CONT ROL SEQ UENCER status status BSIOCLK BSIODATA BSIOSS[.
6: BSIO Interface GP4020 GPS Baseband Processor Design Manual 37 N SCLK SLAVE DATA IN SLAVE DATA OUT SS0 - SS1 High Z 1 2 3 4 N TSERCDC TSERDOD (N-5)SCLK TSERCEC 1 2 3 4 (X-5)SCLK X TSERSU TSERHD Note: Last SCLK cycle shown for reference only - not actually generated in BSIO Figure 6.
6: BSIO Interface 38 GP4020 GPS Baseband Processor Design Manual SCLK SDIO DATA OUT SDIO DATA IN SCLK SDIO DATA OUT SDIO DATA IN SCLK SDIO DATA OUT SDIO DATA IN WRPOL = 1, RDPOL = 0, CYCDELAY = 0 SCLK.
6: BSIO Interface GP4020 GPS Baseband Processor Design Manual 39 Standard and P age Mode s, w it h the width of t he Cont rol W ord be ing con figurable be t we en 2-bits and 32 -bits via t he CW ORD bit s . In Standa r d Mode , the star t of an Operation is de f ine d as whe n the first wo rd is wr itt e n to the Re ad/Write Buffer.
6: BSIO Interface 40 GP4020 GPS Baseband Processor Design Manual SSEL OPERATION SS0 - SS1 SCLK_INT 01H 00H 02H 03H 03H 00H Note: ENPOL = 0000 Enable Slave Enable Slave Enable Slave Enable Slave Figur e 6.7 B SIO SCLK P olarity Timing SCLKON in the Configuration R egiste r all ow s SCLK_ INT to be stoppe d during a n Ope rati on .
6: BSIO Interface GP4020 GPS Baseband Processor Design Manual 41 6. 5 BSIO Int errup t Co nt rol Th e Ac t iv e H i gh I N T out p ut i s pr o vi d ed t o al l ow t h e BS IO t o o p er at e i n an i nt er r u pt d ri v en en v ir o nm ent .
6: BSIO Interface 42 GP4020 GPS Baseband Processor Design Manual W h en t he S equ en cer a s ser t s CW O RD_ EN, t he C ont r ol W or d is sh if t ed out a t SDO p ri or t o any d at a t o be wri tt en fr om the FIFO.
6: BSIO Interface GP4020 GPS Baseband Processor Design Manual 43 SHIFT CLOCKS rx_clk tx_clk shift_rx shift_tx sclkx2 RWPOL SSEL WRITE COUNTERS TXWORD WRSIZE shift_tx end_of_tx OPERATION sclk_int wfifo.
6: BSIO Interface 44 GP4020 GPS Baseband Processor Design Manual The S eque nc e r enables SCLK and the Slave Se l e ct Logic by means of SCLK_EN and ex t_sel r e spective l y.
6: BSIO Interface GP4020 GPS Baseband Processor Design Manual 45 Bit Mnemoni c Descr iption Reset Value R/W 10: 7 SCLKFR E Q SCLK Fr equenc y. Selec t th e fr equ enc y of SC LK , bet ween B_ CLK/ 512 to B_CL K/2 i n nine incre men ts.
6: BSIO Interface 46 GP4020 GPS Baseband Processor Design Manual Bit No . M nemoni c Des cript ion R eset Value R/W 9:0 RDSIZ E R ead S iz e. W he n writ t en c onfig ur es t he n umb er o f bytes / words to b e read in t he c urr ent op e r at ion.
6: BSIO Interface GP4020 GPS Baseband Processor Design Manual 47 6.9. 5 BSIO Status Regis ter - B S IO_S T A T - Memory Offse t - 0x0030 Bit No . M nemoni c Des crip ti on Res et Value R/W 31: 8 Reserved All = 0 R 7O P C O M P Op erati on C om pl ete: S et onc e c urr ent op e r ati on h as comp l eted.
6: BSIO Interface 48 GP4020 GPS Baseband Processor Design Manual 6.9. 7 BSIO Read /Writ e B uf fer Register - RWBUF - Memory O ff se t - 0x0038 Bit No . M nemoni c Descri pt ion Res et Value R/W 31: 0 R W BUF F 32-bit R ead / W rite b uf fer, f o r wor d t o b e s ent and r ec eived .
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 49 7 12 -C HANNEL CORRE LATOR (CORR) 7.1 I nt r od u ction The 12-Channe l Cor relator fo rms the GPS-spe c ific module of the GP4020 GPS Baseband Proce ssor.
7: 12-Ch annel Correl ator 50 GP4020 GPS Baseband Processor Design Manual TIMEBASE GENERATOR MEAS_I NT ACCUM_INT CLOCK GENERATOR SAMPLE L ATCH SIGN 0 / MAG0 SIGN 1 / MAG1 SAMPCLK M_CLK (from SC G) TRA.
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 51 7.1. 3 Raw-T imemark Gen erato r The R aw Tim e mark ge nerator ge nerates two esse nti a l s ignals: 1) CK100kHz .
7: 12-Ch annel Correl ator 52 GP4020 GPS Baseband Processor Design Manual operations to the code and carrier DC O’s are 32-bit data transfe rs, in w hich the High 1 6- b it word mu st be wr i tte n imm e diate l y before t he low 16-bit wo rd.
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 53 The ind ividual sub–b locks i n the tr a cking mod ul e s are : 7.2. 1 Carrier DCO Th e Car r i er DCO , whi c h i s cl ock .
7: 12-Ch annel Correl ator 54 GP4020 GPS Baseband Processor Design Manual output is 2.046 MHz , t o give a ch i p rate of 1.023 MHz and is se t by l oad i ng the 25 -bit registe r CHx_CODE_DCO _I NCR . It i s p rogrammed w ith a re solution o f 8 5·14949 m Hz whe n used w i th a GP2015 /GP2010 f ront end.
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 55 7.2. 5 Carrier Mixers The C arrier Mixe rs multiply the digital i nput signal by the Carrie r DC O digi t al loca l osc i lla t o r t o ge nerate a signa l at baseband. B oth the I and Q Ca rrier DC O phase s are directed to the appro priate m ixe rs.
7: 12-Ch annel Correl ator 56 GP4020 GPS Baseband Processor Design Manual 2) Pro ce ss p se udo -ran ge s to g ive the na vig atio n so lu tio n an d fo rm at i t in a fo rm su ita b le fo r th e u se r. In orde r for a Naviga t ion S olut i on to be achieve d, all o f the pse udo-range s mus t h ave e x act ly the same clock error.
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 57 the re ceived sig nals the refore, a local l y gene rated code must be chose n to pre cise l y match the spre adi n g co de type , ra te, a nd pha se .
7: 12-Ch annel Correl ator 58 GP4020 GPS Baseband Processor Design Manual CHX_CODE_I NCR_L O / _H I r e gi ste r s t o st ee r t he Code DCO and gradu all y br i ng the gold code phase t o the r ight value.
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 59 milliseconds, an im p roved first gue ss for l ocal time could include an allowance f o r t h i s de lay t o reduce the i tera tion time late r.
7: 12-Ch annel Correl ator 60 GP4020 GPS Baseband Processor Design Manual iv. Release the re l e vant CHx _RSTB bits of the RESET_CONTROL register t o make the channe l acti ve . W h en t he c od e cl oc k i s i nhi b it ed (t o sl ew t he co d e p has e) , t h e I nt eg r at e a nd Dum p m od ul e i s hel d at r eset .
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 61 For t he poll ed m e th od, t he ACCUM_STATUS_ A regist e r is always read fo llowin g every ACCUM_INT.
7: 12-Ch annel Correl ator 62 GP4020 GPS Baseband Processor Design Manual The A nal ogue delay t hrough the RF Front - e nd of the GPS re ceiver is se t by such param e ters as g roup delay in filt e r s. For the bandw i dths u sed for C/A code will be i n th e region of 1 to 2 µ s.
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 63 1. reading at TIC 0 : CHx_CARR_DCO _PHASE 0 = PH 0 2. re ading a t T IC 1 : CHx_CARR_DCO _PHASE 1 = PH 1 CHx_CARR_CYCLE 1 = K 1 + 1 3.
7: 12-Ch annel Correl ator 64 GP4020 GPS Baseband Processor Design Manual 7.5. 1 Write Cycl e T o Read Cycle Timin gs As de scribed pre viously, the inte rnal write cycle of the Corre lat o r take s 300ns . O n l y on ce the write cycle is co m plete will t he correlator addre ss decode rs swi t ch to de coding the current addre ss.
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 65 Addr ess Offs et Regist er D ir ect ion Functi on 0x1C 0 t o 0 x1D C ALL C ontr ol (s ee Tabl e 7.
7: 12-Ch annel Correl ator 66 GP4020 GPS Baseband Processor Design Manual 7.6. 2 T racking Chann el Data A ccumu lat io n Registers Each T racking cha nnel ha s the Data Ac cumulat ion registe rs as shown in Tabl e 7. 4 on pa ge 67 . Each addre ss has an inde pende nt r e ad and w rit e function.
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 67 Addr ess Offs et Regi ster Dir ect ion Fun ctio n CHx_ Accu mula te + 0x0 0 I_T RAC K READ Int egr ate and Du mp V al ues f o r I tr ac ki ng arm in corr el at or c han nel X.
7: 12-Ch annel Correl ator 68 GP4020 GPS Baseband Processor Design Manual The registers are list e d in alphabe t ica l o rder and no t in add ress o rder to allow e asy refe rence t o e ach sect ion. Un l es s ot h er wi s e st at ed t h e L SB is bi t 0 a n d t h e MS B is bi t 1 5 or as f ar u p t h e r egi st er a s t h er e i s dat a .
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 69 Bit No M nemoni c Des cript ion R eset Value R/W 14 DIS CIP 1 T he DISC IP 1 b it i n dic ates t he l ev el on th e DI SCI P i np ut pin at t h e ti me this r ead occ urs .
7: 12-Ch annel Correl ator 70 GP4020 GPS Baseband Processor Design Manual 7.6. 5 A CCUM_S T A T US_C Regi ster - Read Address offset 0x200 ACCUM_STATUS_ C i s a regi ster c on taini ng the state of twelv e st atus bit s sampled and latch ed on the active edge of e v e r y ACCUM_I NT (as f o r ACCUM_STATUS_A).
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 71 7.6. 7 CHx_CARRIER_CY CLE_CO UN T ER Reg ister - Offset <CHx_Con trol> + 0x 08 MULTI _CA RRI ER_CYCLE _COUNT ER Reg ister - Offse t (0x180 + 0x08) ALL _CARRIER_CYCL E_COUNT ER Register - Offset ( 0x1C0 + 0 x08) Bit No.
7: 12-Ch annel Correl ator 72 GP4020 GPS Baseband Processor Design Manual 7.6. 10 CHx_CARRIER_DCO _INCR_HI GH Register - Offset <CHx _Control> + 0x0C MULTI _CA RRI ER_DCO_I NCR_HIGH Regi ster - .
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 73 Bit No . M nemoni c Des cript ion R eset Value R/W 15: 10 Not us ed '0' when r ead 0 R 9:0 C H x _C ARRI ER _DCO _PH ASE [ 9:0] Bit s 9 :0 o f the 10- bit C arr ier DCO P h ase C ou nt.
7: 12-Ch annel Correl ator 74 GP4020 GPS Baseband Processor Design Manual 7.6. 14 CHx_CODE_DCO _INCR_L OW Re g ister - Offset <CH x_Contro l > + 0x18 MULTI _CODE_DCO _ I NCR_LOW Regist er - Of f.
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 75 7.6. 17 CHx_CODE_P HA SE Reg ister - Read Of fset <CHx_Con trol> + 0x0 4 CHx_ CODE_PHA SE_COUN T ER R egister - Write Of.
7: 12-Ch annel Correl ator 76 GP4020 GPS Baseband Processor Design Manual If a channel is inactive, a non-z ero sle w value shoul d be w ritt e n in t o CH x_CODE_S LE W be fore t he channel is r el eas ed . Th is wr it e w il l be a ct ed o n im m edi at el y th e r es et i s rel ea s ed.
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 77 Bit No . M nemoni c Des cript ion R eset Value R/W 15: 14 Not us ed '0' when r ead. - R 13: 8 CH x _ 20MS _EPOC H [5: 0] Ins t ant aneous val u e of the CH x_2 0M S_E POCH .
7: 12-Ch annel Correl ator 78 GP4020 GPS Baseband Processor Design Manual Tabl e 7.26 C ORR CHx _EP O CH_COUNT_LOAD Re g i ster 7.6. 22 CHx_I_T RACK Regi ster - Read Addr es s Offse t <CH x_Accu mu.
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 79 t he r egi st er st at e f or th e ti m e of t h e s eco nd c o de c hi p. Tabl e 7. 28 on page 79 show s the va lues re quired to select one of the 37 GPS, 19 WAAS or t he 8 INM ARSAT–GIC possib l e PRN (P seudo Rando m Noi se) patterns .
7: 12-Ch annel Correl ator 80 GP4020 GPS Baseband Processor Design Manual Bit No . M nemoni c Descr ipt ion Res et Value R/W 15 GP S_ NGL ON S e le c t mode o f C/A c o de ge nera tor. '0 ' = Ru n C/A c o de gene rator in GLO NAS S mode , to ge nera te the fix ed 511 -bit sequ enc e us ed b y all G LO NAS S S at ell it e s .
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 81 Bit No . M nemoni c Des cript ion R eset Value R/W 11 CH11_MISSE D_ MEAS_DAT A '1' = on e or more s ets o f m eas ur ement dat a h a ve b een m iss e d sinc e t he l a s t r ead f r om t his r egis t e r .
7: 12-Ch annel Correl ator 82 GP4020 GPS Baseband Processor Design Manual Bit No . M nemoni c Descri pt ion Res et Value R/W 15: 12 Not Use d -W 11 CH11 _SE LECT '1' = enab les t he Mu lti-c hann el wri te op er ati ons on C h annel 11. '0' = dis ables Mult i-c han n el writ e op er ati ons on C hann el 1 1.
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 83 7.6. 27 PROG _TIC_HIGH Regi ster - Wr ite Address Offset 0x 1B4 The PROG_TI C_H IGH a nd PR OG_TIC_L OW r e gister l ocat ions opera te in co njunction to set the pe riod of T IC.
7: 12-Ch annel Correl ator 84 GP4020 GPS Baseband Processor Design Manual Cycle, Co de S l e w or the Epoch counte rs. At the e nd of the rese t , the channe l enable re sets the code gene rator to a previously progra mm e d start phase.
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 85 7.6. 30 STAT US Register - Write Addr ess O ff s et 0x200 Thi s register allo ws the b it s on t he Accumulation Status r e gi sters ACCUM_ST ATUS_A, ACCUM_STATUS_B, and ACCUM_STATUS_C t o be l atched for readin g .
7: 12-Ch annel Correl ator 86 GP4020 GPS Baseband Processor Design Manual Bit No . M nemoni c Descri pt ion Res et Value R/W 0 CARRIER _MIX _DIS ABLE '1' = Dis a bl e Ca rr ier m i xe rs (N ote 1). '0' = E nabl e C arr ier m ixer s.
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 87 Bit No . M nemoni c Des cript ion R eset Value R/W 3 TM_TEST En abl e s Tr acki ng Modu l e T e s t mod e.
7: 12-Ch annel Correl ator 88 GP4020 GPS Baseband Processor Design Manual To get the SI G N and MAG cou nt co rr e ctly i n to the accumu lat o rs, bot h the carrier and code mixe rs m u st be m a de transparent .
7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 89 7.6. 33 TI MEMA RK_CO NT R O L Reg i ster - Write A ddress O ffset 0x1EC This register i s used to se t- up the cor relator par t of the 1PP S T im e mar k Gene rator (i.e. the R aw_Ti m e mark Ge ne rato r).
7: 12-Ch annel Correl ator 90 GP4020 GPS Baseband Processor Design Manual Thi s Page intenti onall y l ef t bl ank..
8: D MA Cont ro ller GP4020 GPS Baseband Processor Design Manual 91 8 DMA CONTROLLER (DMAC) The GP4020 co nt a ins a D MA con troller, wh ich ass ists the p rocessor to move la r ge blocks of da t a around a sys tem.
8: D MA Cont ro ller 92 GP4020 GPS Baseband Processor Design Manual 1. 1 . 4 ) C l ear to “0 ” t he R ecei v e I n t er ru pt E n abl e b it (bi t 4) t o di s abl e i nt er r upt s gen er a t ed wh en t h e U AR T rece ive re gi ste r is ful l . 1.
8: D MA Cont ro ller GP4020 GPS Baseband Processor Design Manual 93 3. 1.1 ) Set t o ”1” t he DMAC Ha r dware Request Stat us bit (bit 1), t o allow Hardwar e requests ( dr e q and dack ) f rom t he U AR T t o co nt ro l t he D MAC f u nct i on. 3.
8: D MA Cont ro ller 94 GP4020 GPS Baseband Processor Design Manual 3.4) Se t t he DMAC B ase T ransfer Coun t Register (BTR ) , to indicate to the DMAC how many transfers are required in the DM A opera tion be ing progra mm e d.
8: D MA Cont ro ller GP4020 GPS Baseband Processor Design Manual 95 8.1. 2 Set up exampl e of DMAC for a F l y-by t ra nsf er from UAR T RX to memory The follow ing ex am p l e shows t he se quence of.
8: D MA Cont ro ller 96 GP4020 GPS Baseband Processor Design Manual 3.1. 2) Clear t o “ 0” the DMA C Softwa re Re quest bit ( b it 2), to d i sable the So ft wa re DM A transfe r trigge ri ng .
8: D MA Cont ro ller GP4020 GPS Baseband Processor Design Manual 97 this nu m be r is the (numbe r of da ta by t e s - 1), of Packe t siz e "1" which are r e quired to be transferred fro m me mor y to the U ART 1 o r 2 tra ns mit po rt.
8: D MA Cont ro ller 98 GP4020 GPS Baseband Processor Design Manual 1.3) DMA C Channe l 2 can on l y re ceive D MAC har dware tri gge rs fro m UART 2, and no o t he r source. Conse quently, the tri gge r op ti ons liste d i n Table 8.1 do no t e xist for UA RT 2 D MAC F ly-by or dua l- addresse d transfe rs.
8: D MA Cont ro ller GP4020 GPS Baseband Processor Design Manual 99 2.1. 12) Clear to "0" t he Periphera l Location bit (bit 18 ), to indicate that the data buffer for a dual-addresse d tran sfe r is inte rna l to the DM AC . 2.2 ) Se t DM AC P ack et S iz e (b its [7:0 ]) o f the Pa cke t Siz e R e giste r (P SR) to z ero (i .
8: D MA Cont ro ller 100 GP4020 GPS Baseband Processor Design Manual 8.3. 2 Sof t w are T riggering Software Tr iggering of a DMAC channel i s the no rmal mode used in Dual-Addre ssed (Buffered) da ta transfe rs.
8: D MA Cont ro ller GP4020 GPS Baseband Processor Design Manual 101 8.4 Caution ary Notes 8.4. 1 Packet T ransfers in pl ace of Block T ra nsf ers For Both Single-addre ssed and Dual-add resse d transfers u si n g the G P 4020 D MA, it is N OT reco mm e nded to use DMA Block-transfe rs, but t o use Packe t transfers inste ad.
8: D MA Cont ro ller 102 GP4020 GPS Baseband Processor Design Manual Thi s Page intenti onall y l ef t bl ank..
9: GP IO I nter fac e GP4020 GPS Baseband Processor Design Manual 103 9 GENER AL PU RPOS E INPU T OUTPUT ( GPIO) IN TERFACE 9.1 I nt r od u ction A se t o f 8 ge neral purpose static inpu t output log.
9: GP IO I nter fac e 104 GP4020 GPS Baseband Processor Design Manual 1N F D T IO Figur e 9.2 G PIO Pad Cell C onfigur a tion The GPI O modu le m ust be read o r w ritten in 32 - b i t acce sse s, although o nly t he lower eight b i ts o f the B µ ILD data bus ( b_da t a [7: 0 ]) a re used.
9: GP IO I nter fac e GP4020 GPS Baseband Processor Design Manual 105 B_SI Z E[1: 0] D ata size B_E RR OR 00 8 - b i t Er r or, b us er r or as s er t ed 01 16- bit Err or, bus e rr or a s s ert ed 10 32- bit V alid, bus e rr or neg at ed 1 1 Re se rv e d Er ro r, bu s e rro r a sse rte d Table 9.
9: GP IO I nter fac e 106 GP4020 GPS Baseband Processor Design Manual 9.3. 2 GPIO I nput Register – GPIO _INPUT - M emo ry Offset 0x004 Re adabl e only, a w rite to t his addre ss wi l l p roduce a b_erro r .
10: I nterrupt C o ntroller GP4020 GPS Baseband Processor Design Manual 107 10 INT ERRUP T CO NTROLLER (INTC) The Interr upt Con tr o ller can manage up to 32 Interrupt source s. In the G P40 20, 18 interrupt source s a re pr e sent: 16 int e rnal sou r ce s, and 2 ex ternal sou rces.
10: I nterrupt C o ntroller 108 GP4020 GPS Baseband Processor Design Manual In the GP4020, the interrupt channe ls are a ll o cat e d as s hown i n Table 10.2 bel ow . I n each ca se t he appl ication soft ware for the GPS receiver will nee d t o configure t he i n t e rr up t channels a s shown.
11: Memo ry Periph eral Co n troll er GP4020 GPS Baseband Processor Design Manual 109 11 M EMORY PERI PHER AL CON T R OLL ER (MPC) 11.1 I nt r od u ction Th e Mem or y P er ip her a l C ont r ol l er ( MPC) i s t he i nter f a c e b et ween t h e B µ ILD bus and the e xte rnal bus sy ste m.
11: Memo ry Periph eral Co n troll er 110 GP4020 GPS Baseband Processor Design Manual The de f ault hard-w ired con fi gura tion at R ese t of MPC M e m ory A rea 1 (registe r addre ss 0xE000 8000) is.
11: Memo ry Periph eral Co n troll er GP4020 GPS Baseband Processor Design Manual 111 11.4 GP4020 M emory A rea 3 Con figuration GP4020 M e m ory A rea 3 is a special case whe re a nu mber of internal co mponents share resource s w ith a n Ex t e rnal ch ip se l e ct line – N SCS [2A].
11: Memo ry Periph eral Co n troll er 112 GP4020 GPS Baseband Processor Design Manual Esse nti al ly, this e quat e s to setting add ress 0x E000 8008 to a value of 0x 3303 306E. The M PC m ust be con fi g ured to address a 32-b it bus wh en ac cessing t he Are a 3 in ternal pe ripherals.
12: Peri pheral Con trol Logi c GP4020 GPS Baseband Processor Design Manual 113 12 P ERIPHERAL C ONTROL LOGIC (PCL ) 12.1 I nt r od u ction The Peripheral Contro l Logic (PCL) i s used t o contro l GP4020 c hip-wide functions.
12: Peri pheral Con trol Logi c 114 GP4020 GPS Baseband Processor Design Manual PLL DT1 UART_CLK BuIL D_CLK RF _PLL_LO CK RTC_CLK NSRESET POWER_GOOD EN_PO W_RST F_SL EEP SFT_RESET UART_CLK NRESET (TO .
12: Peri pheral Con trol Logi c GP4020 GPS Baseband Processor Design Manual 115 • WATCH_TM (or Watchdog Time - ou t) signal. Th is is a n in t e rnall y gene rat e d Re set signal co m es fro m the on- chip W atc hdog m o dul e .
12: Peri pheral Con trol Logi c 116 GP4020 GPS Baseband Processor Design Manual RF_PLL_LOCK NRESET UART_CLK 3 CYCLES Any Freq Figure 12.3 RF_PLL _LOCK Ha rdware Rese t Genera t ion POWER_GOOD NRESET UART_CLK 3 CYCLES Any Freq Fi gure 12.
12: Peri pheral Con trol Logi c GP4020 GPS Baseband Processor Design Manual 117 NSRESET NPOR_RESET NRESET RTC_CLK UART_CLK 3 CYCLES - 150ns 20MHz Any Freq RTC_CLK period = 30517ns.
12: Peri pheral Con trol Logi c 118 GP4020 GPS Baseband Processor Design Manual either WATCH_ TM or NSRESET signa l s. The refor e , a co mpl e t e GP4020 r e set can o nl y occur if an NSRESET or a W ATCH _TM e ve nt is introduce d.
12: Peri pheral Con trol Logi c GP4020 GPS Baseband Processor Design Manual 119 PLL_PD / PLL_SLEEP PLL_IN_SEL value change NRESET PLL_ENABLE RTC_CLK 6 RTC_CLK cycles = 183us <30.5us ....................... OR ........................ ..............
12: Peri pheral Con trol Logi c 120 GP4020 GPS Baseband Processor Design Manual MULTI_FNIO DISCIO CLK100KHz DISCOP_MUX BSIO_MUX[1:0] MFNIO_CFG[2:0] MULTI_FNIO_READ UART_CLK '0' '1'.
12: Peri pheral Con trol Logi c GP4020 GPS Baseband Processor Design Manual 121 GPIO output lin e number Altern ative sign al mult ipl ex Condi tion 0 BSIOC LK BS IO_ MUX[ 1: 0] = ' 1 0', '0 1', '11 ' SIGN 1 Not av aila b le in s tan dar d oper at ion UIM_TEST = '1' (i.
12: Peri pheral Con trol Logi c 122 GP4020 GPS Baseband Processor Design Manual A single Inte r rup t line, PER_ INT, is p roduce d from 3 Peripheral Control L ogic Inter rupt signals from the Real Time Clock (RTC_CM P_INT) , the 1PPS Tim e mark Gene r ator (TIC_INT ), and t he PO W ER_G O OD i npu t ( Pin 64 (100 -pi n package)) .
12: Peri pheral Con trol Logi c GP4020 GPS Baseband Processor Design Manual 123 Note: t he W ATCH _EN bit i n only e f fects W atchdog behavio ur due t o Firef l y rese t.
12: Peri pheral Con trol Logi c 124 GP4020 GPS Baseband Processor Design Manual 12.6. 2 RF In put and RF Front- e nd Pow er-Down A Powe r-down of an RF Front-e nd IC, alon g with d isabling the 40MHz .
12: Peri pheral Con trol Logi c GP4020 GPS Baseband Processor Design Manual 125 Ad dr e ss Off set Regi ster Dir ect ion Functi on Fun ctio n Bl oc k 0x00 0 RTC_P R E Rea d Rea l T ime C loc k Pr e-s .
12: Peri pheral Con trol Logi c 126 GP4020 GPS Baseband Processor Design Manual Bit No . M nemoni c Des cript ion R eset Value R/W 10 RF_S LEEP ' 1' = Disa ble 40 MH z lo w- lev el di ffe r .
12: Peri pheral Con trol Logi c GP4020 GPS Baseband Processor Design Manual 127 Note : For each change of va lue of PLL_ IN_SEL[1:0] or a t PLL wake-up, t he PLL will be disabled f or a wait period of approx. 18 3 µ s (6 * 32 kHz clock cycle s, de t e rmined by the Re al Time Clock bl ock).
12: Peri pheral Con trol Logi c 128 GP4020 GPS Baseband Processor Design Manual 12.7. 3 PCL Inp ut Read regist er - I P_READ - Memory Of fset 0x00E This Re ad-only re gi s t e r allows t he mos t rece nt stat e of a number o f GP4020 input s ignals t o be read.
12: Peri pheral Con trol Logi c GP4020 GPS Baseband Processor Design Manual 129 Bit No . M nemoni c D escr ipt ion Res et Value R/W 13 PO W _INT_EN En abl e PE R_INT I nt err upt s i gn al t o I nt erru pt C on tr oll er i n F ir efl y MF1, du e t o PO W _G D_IN T ( POW ER _GOO D (pin 64) g oing L ow.
12: Peri pheral Con trol Logi c 130 GP4020 GPS Baseband Processor Design Manual Bit No . M nemoni c D escr ipt ion Res et Value R/W 2 POW _RESET (See No te 2) '1' = Res e t du e t o PO W ER_ GOOD = Low, ha s occurr ed si nc e l a st CLR_RST or NSRESET cl ea r- event.
13: Real Ti me Clock GP4020 GPS Baseband Processor Design Manual 131 13 REAL TIME CL OCK (RTC) 13.1 I nt r od u ction Th e Rea l T im e Cl oc k ( RT C) i s u sed to pr o vi de a n i nc rem en t al ti m e i n di c at or.
13: Real Ti me Clock 132 GP4020 GPS Baseband Processor Design Manual crystal ne ed to be se t to e nsure that the t otal loop gain of t he oscillato r is h i gh e nough t o guar ant e e continuous oscillation unde r all conditions. Nor mall y t h is w i ll m e an tha t a loop gain of greater than 1 is ne eded.
13: Real Ti me Clock GP4020 GPS Baseband Processor Design Manual 133 Bit No . M nemoni c D escr ipt ion Res et Value R/W 15: 1 RT C_PRE [15: 1] Number o f RTC cl o c k c y cl e s a t s ampl e time, w i thin 1 s econd sinc e las t div ide r rese t/rol love r.
13: Real Ti me Clock 134 GP4020 GPS Baseband Processor Design Manual Bit No . M nemoni c D escr ipt ion Res et Value R/W 15: 8 RT C_SE C_T[ 7: 0] 8 MSBs of acc um ulat ed RT C s e c onds si nc e l ast 24- bit c ount er r e s et. Most Si gnif icant Bit = Bit 15 Note: Thi s data ONLY re set by writi ng ‘0’ to bit 0 of RTC_ PRE.
14: Syst em Clock Gen erator GP4020 GPS Baseband Processor Design Manual 135 14 SYSTEM CLOCK GENER AT OR (SCG ) 14.1 I nt r od u ction The S yste m Clo ck Gene r ator (SCG) is used to ge nerate two c lock si gnals fo r the GP4020: • The U ART_CLK w hich runs U ART2 continuously and produce s the B µ ILD C lock.
14: Syst em Clock Gen erator 136 GP4020 GPS Baseband Processor Design Manual 14.2 40MH z Low Level Di fferential I nput The 40M Hz l ow- l e vel diffe rential input can proce ss the 40MHz signal f r o m a RF Front -end chip. The signa l should have a DC bias o f less than ap pr ox .
14: Syst em Clock Gen erator GP4020 GPS Baseband Processor Design Manual 137 14.3 Pr ocesso r Cry stal Oscillator Th e Proce ssor Cry sta l Osc illa tor may ne ed to be us ed wi th an ex tern al cry sta l, to ge ne rate the c lock so ur ce fo r the UART_C LK signa l .
14: Syst em Clock Gen erator 138 GP4020 GPS Baseband Processor Design Manual Z o = Output I mpedance of oscil l ator at PRX_ OUT G m = T ran s co nd uct a n ce of os c il l at or R f = Fe edback Re si.
14: Syst em Clock Gen erator GP4020 GPS Baseband Processor Design Manual 139 TCXO 10uF Vcc To RF Front-end PLL Ref input Vcc GND 10.0MHz GP4020 PRX_IN PRX_OUT Vdd (NOT Vcc) 1M IC1 100nF 1nF 47nF 100 1V p-p IC1 = ANY 3.3V High-speed CMOS Inverter. 3.3V p-p 47nF ~0.
14: Syst em Clock Gen erator 140 GP4020 GPS Baseband Processor Design Manual Fig ure 14 .5 GP4 02 0 S y ste m C lock Ge ne rato r PL L Con figu ra tion The P LL can p rovide accu rate phase a li g nment be twee n a ge nerated clock a nd a refe rence clock withou t i ncu rri ng del a y s n orm al l y as s oci at ed wi t h bu ff er i n g.
14: Syst em Clock Gen erator GP4020 GPS Baseband Processor Design Manual 141 PI N DE S C RI PT I O N VC OD [1:0 ] PLL VCO O utput Fr equ enc y R ang e s elec ti on pin. Th is inp ut d e t er mines whic h o f t h e 4 f requ enc y r ang es ar e sele ct e d.
14: Syst em Clock Gen erator 142 GP4020 GPS Baseband Processor Design Manual If you i ntend t o change the fre quency of the P LL on the fly during tim e -critical co de-e xecution, care should be use d to e nsu re tha t the PLL is a llow e d to s tab ilis e be fo re al low ing th e c ode ex ec ution to con tin ue .
14: Syst em Clock Gen erator GP4020 GPS Baseband Processor Design Manual 143 UART _CLK O/ P Freq. (M Hz) I/P Freq. MH z PLL Mu l t Fact Prog. Div i d er sett ing DI V [4:0] Charge Pump sett ing CHP [4:0] PLL SYNC MO D E SYN CEN PLL O/ P VCO Freq. MH z VCO Freq.
14: Syst em Clock Gen erator 144 GP4020 GPS Baseband Processor Design Manual UART_CLK O/ P F r eq. (M Hz) POW_C NTL regi ster v alu e PLL_C NTL regi ster v alu e Comments 10. 0 0 x80 3C 0 x19 7F PLL byp a s s ed an d dis abl ed PLL _CNT L val ue = r e s et valu e 11.
14: Syst em Clock Gen erator GP4020 GPS Baseband Processor Design Manual 145 PLL Mu l t Factor Desir ed PLL outp ut fr eq ue ncy Prog. Div i d er Control DIV [4: 0] PLL SYNC MO D E SYNCE N Charge Pump sett ing CH P [4 :0 ] VCO Freq. Range VC OD [1:0 ] Wo rs t case sett lin g ti me .
14: Syst em Clock Gen erator 146 GP4020 GPS Baseband Processor Design Manual 5) Output fr e quency o f PLL; t he highe r the ou tput freque ncy, the m ore cur rent consu m e d: i. 240MHz = 6.2 m A; ii . 125MHz = 4.5 m A; iii. 60 MH z = 3. 4 mA ; i v. 30MHz = 2.
14: Syst em Clock Gen erator GP4020 GPS Baseband Processor Design Manual 147 Bit No . M nemoni c Des cript ion R eset Value R/W 7:6 B_C LK_S EL[ 1: 0] U ART _CLK di vid er b l ock s e l ect or .
14: Syst em Clock Gen erator 148 GP4020 GPS Baseband Processor Design Manual 14.6. 2 SCG PL L Co n trol Regist er - PLL _CN T L - M emo ry Offset 0x00A A write to this re gister sto res logic va l ue s which se t or rese t input control l i ne s to the PLL w ithin the Sys tem Clock Gene rat or.
15: 1PPS T imema rk Ge nerator GP4020 GPS Baseband Processor Design Manual 149 15 1PPS TI MEM A R K GENERATO R 15.1 I nt r od u ction The One Pulse Pe r Second (1PPS) T im e m ark G e nerator is nomin.
15: 1PPS T imema rk Ge nerator 150 GP4020 GPS Baseband Processor Design Manual TIC GENE RATOR (C ount down to Zero) Clock div ide by 7 LOAD ZE RO 1ms delay TIC ARM_TI MEMARK Modulo 7 Add TIC_ CORR[2 :.
15: 1PPS T imema rk Ge nerator GP4020 GPS Baseband Processor Design Manual 151 TIC ARM_TIMEMARK RAW TIMEMARK 0.0999999s 10 TIC Periods = 0.999999s Figure 15.2 Time mar k output using A RM_T IM EMARK si gn al, triggered f ro m software. The TIC pe riod can only be adj u sted i n steps of 175ns ( 7 / 40MHz = 175ns).
15: 1PPS T imema rk Ge nerator 152 GP4020 GPS Baseband Processor Design Manual TIMEMARK 1ms 1ms 1us delay 2us delay UTC 012 10 TIC Periods = 0.999999s TIC ARM_TIMEMARK RAW_TIMEMARK TIMEMARK DELAY SECONDS Figure 15.
15: 1PPS T imema rk Ge nerator GP4020 GPS Baseband Processor Design Manual 153 i v ) T h e va l u e of t he T I C per i od is a t a gi v en TI C. T h is c an b e c a l cul at ed pr eci s el y wit h r es pec t t o U TC i f th e Rec eiv er Cl oc k Of fs et i s kn o wn.
15: 1PPS T imema rk Ge nerator 154 GP4020 GPS Baseband Processor Design Manual TOT AL ma x. o sc il lato r dr ift e rro r = (a) + (b ). In pract ice, the drift is much l e ss than t h is unde r typical con ditions ≈ 10 to 20n s 5.
15: 1PPS T imema rk Ge nerator GP4020 GPS Baseband Processor Design Manual 155 15.4 Fine-r esolution Timemar k setting, usin g TIC perio d slewin g 15.
15: 1PPS T imema rk Ge nerator 156 GP4020 GPS Baseband Processor Design Manual TIC _INT _EN [1 :0] = ' 01' . In d i cates t hat the T I C per iod will a ut omatica lly be correct ed ind e pendent ly of G PS software e ach tim e the phase _counte r r e aches 7 , by m e ans o f the R ELOAD_T I C signal.
15: 1PPS T imema rk Ge nerator GP4020 GPS Baseband Processor Design Manual 157 TIC Event TIC _ CORR [2:0] Phase Off set Off set delay (ns) Ov er flow Next T IC Period ( µ s) Cumulated Ov erf l o w Ov erf l o w delay (ns) Tot a l Dela y (ns) 0 100 0 0 0 999 99.
15: 1PPS T imema rk Ge nerator 158 GP4020 GPS Baseband Processor Design Manual 15.4. 5 Ti memark setti ng example 3 - T IC period Slewi ng with +2. 5 pp m Receiver Clo ck Of fset For TIC period e rrors whi ch are la rger than +0.
15: 1PPS T imema rk Ge nerator GP4020 GPS Baseband Processor Design Manual 159 TIC Event TIC _ CORR [2:0] Phase Off set Off set delay (ns) Ov er flow Next T IC Period ( µ s) Cumulated Ov erf l o w Ov erf l o w de lay ( ns) Tot a l Dela y (ns) 5 001 5 1 25 0 999 99.
15: 1PPS T imema rk Ge nerator 160 GP4020 GPS Baseband Processor Design Manual 6) The Tim e mar k delay cou nter w ill continue counting down to 0, at which poin t the T I ME MARK output register will be cleared and the counte r will stop.
15: 1PPS T imema rk Ge nerator GP4020 GPS Baseband Processor Design Manual 161 15.5. 3 Ti memark setti ng example 6 - T imemark Delay Cou nter with +0.
15: 1PPS T imema rk Ge nerator 162 GP4020 GPS Baseband Processor Design Manual Tim ema rk Event ( s) TIC Event TIC Tim e (s ) R eq uir ed delay ( µ s) TI M _ D EL val ue TI M _ D EL _L O TI M _ D EL_ HI 0 0 0 0 40 000 0 x9C4 0 0 x40 1 10 0 .99 99965 3.
15: 1PPS T imema rk Ge nerator GP4020 GPS Baseband Processor Design Manual 163 Tim ema rk Event ( s) TIC Eve nt TIC Ti m e (s ) Re qui re d delay ( µ s) TI M _ D EL val ue TI M _ D EL _L O TI M _ D EL _H I 0 0 0 0 40 000 0 x9C4 0 0 x40 (TIC ADD) 1 9 0.
15: 1PPS T imema rk Ge nerator 164 GP4020 GPS Baseband Processor Design Manual 15 .7 1 PPS T imema rk G enera to r Reg isters The Tim e mar k Gene rat or use s four registers. These re gisters a r e addre ssabl e in t he same part of the m e m ory map as the Pe ripheral Con trol Log ic Block - Root address 0x 4010 1000.
15: 1PPS T imema rk Ge nerator GP4020 GPS Baseband Processor Design Manual 165 15.7.2 1PPS Timemar k Generat or TIC Re tention Re g ister - TIC_RE T - Me mory O ffset 0x01 2 This register combines con tr o l and m o nito r line s for the 1PPS Tim e mark Generator TIC period slewing logic, with an 8-bit data re tention registe r.
15: 1PPS T imema rk Ge nerator 166 GP4020 GPS Baseband Processor Design Manual 15.7.4 1PPS Timemar k Generat or Delay C ounter Reg ister (MSB) - TIM_DE L _HI - Me mory Offse t 0x016 This register sets.
16: Up -Integ ration Modul e GP4020 GPS Baseband Processor Design Manual 167 16 UP-INTE GRA TION MOD ULE (UIM ) The GP4020 conta ins the Firefly MF1 core , wi t h in whic h i s a Me m ory Pe ri phe ral Con troller (MPC) which contain s a module ca ll e d the Up In tegration M odule (UIM ).
16: Up -Integ ration Modul e 168 GP4020 GPS Baseband Processor Design Manual Thi s Page intenti onall y l ef t bl ank..
17: UART s GP4020 GPS Baseband Processor Design Manual 169 17 UNIVERSAL A S YNCHRONOUS RECEIVER TRANSMITTER (UART) 17.1 I nt r od u ction The GP4020 uses two U niversal Asy nchronous Rece i ver Trans .
17: UART s 170 GP4020 GPS Baseband Processor Design Manual W hi l st t h ese a r e th e sam e f r eq uen c y, t he B µ I LD_CLK can be d i sabled by us i ng the F_SLEEP facilit y (refer to Section 12. 5 "Interru pt and Wake-up l ogi c" on page 121 , for mo re in for ma tion ).
17: UART s GP4020 GPS Baseband Processor Design Manual 171 Baud Rate Require d Div i s io n Sel ect Value Reference Clock (MHz) Baud Rate Ratio Prog. BRR Value Progra mme d Baud Rate Baud Rate Error ( % ) 1200 8 2.6 56 25 13 7.346 3 5 137 12 03. 01 2 -0.
17: UART s 172 GP4020 GPS Baseband Processor Design Manual Baud Rate Require d Div i s io n Sel ect Value Reference Clock (MHz) Baud Rate Ratio Prog. BRR Value Progra mme d Baud Rate Baud Rate Error ( % ) 1200 8 3.1 25 16 1.7 604 2 16 2 1198. 23 6 0.1 47 2400 4 6.
17: UART s GP4020 GPS Baseband Processor Design Manual 173 Baud Rate Require d Div i s io n Sel ect Value Reference Clock (MHz) Baud Rate Ratio Prog. BRR Value Progra mme d Baud Rate Baud Rate Error ( % ) 1200 8 3.5 93 75 186. 174 48 18 6 1201. 12 - 0.
17: UART s 174 GP4020 GPS Baseband Processor Design Manual Baud Rate Require d Div i s io n Sel ect Value Reference Clock (MHz) Baud Rate Ratio Prog. BRR Value Progra mme d Baud Rate Baud Rate Error ( % ) 1200 8 4.3 75 22 6.8 645 8 22 7 1199. 28 7 0.0 59 2400 4 8.
17: UART s GP4020 GPS Baseband Processor Design Manual 175 Thi s Page intenti onally l ef t Bl ank.
18 : Wa tchdo g Timer 176 GP4020 GPS Baseband Processor Design Manual 18 WATCHD OG TIMER (WD OG) The func tion of the W atchdog Ti m er block [ W DOG] i s to dete ct hardware or run - ti m e sof t wa re errors. It pe rforms this function by r e quiring the proce ssor to wr ite to one of it s re gi sters periodically .
18 : Wa tchdo g Timer GP4020 GPS Baseband Processor Design Manual 177 UART_CLK PRIMARY DOWN-COUNTER 32BIT SECONDARY DOWN-COUNTER 8BIT DIV 16 = WATCH_INT RELOAD READ CONSTAT =0 =0 CLR START WATCH_EN START [7:0 ] BUILD BUS INTERFACE BUILD BUS CLR RESTART KEY 0XECD9F7BD WATCH_TM TEST [11: 0] Figure 18.
18 : Wa tchdo g Timer 178 GP4020 GPS Baseband Processor Design Manual To resta rt the w atchdog coun ter, a speci f ic 32 -bit va lue (=0x ECD9F7B D; the R ESTART key) m us t be prog ramm e d into the watchdog restart register .
18 : Wa tchdo g Timer GP4020 GPS Baseband Processor Design Manual 179 All W atchdog Re gist e rs are 32-bits w i de . 18.3. 1 Wa tchdo g C ontr ol / St atus R e giste r - CON S T A T - M e mory Offset 0x000 The control register is 32-b i ts w ide, with un use d bits de f ine d as ze r o.
18 : Wa tchdo g Timer 180 GP4020 GPS Baseband Processor Design Manual 18.3. 4 Watch dog Restart Register - REST A RT - Memory Offset 0x00C Bit No . M nemoni c D escri pt ion Reset Val ue R/W 31: 0 RESTAR T _ KEY Re sta rt Ke y .
19: Syst em A dd ress Map GP4020 GPS Baseband Processor Design Manual 181 19 A DDRESS M A PS 19.1 GP4020 S ystem A d dress M ap The GP4020 has the Addre ss Map a s show n in Tabl e 19.
19: Syst em A dd ress Map 182 GP4020 GPS Baseband Processor Design Manual a) G a te N SCS[2A] ex ternally w ith S ADD[19] t o p roduce a smal l e r ex ternal add ress s pace for NSCS[2A ], but without the r e f lect i on of t he internal l og ic once eve ry 0x2000.
19: Syst em A dd ress Map GP4020 GPS Baseband Processor Design Manual 183 19.2 GP4020 Firefly MF1 A d dress M ap The Firef l y MF 1 B µ ILD bus modules have the address map as shown in Tabl e 19.
19: Syst em A dd ress Map 184 GP4020 GPS Baseband Processor Design Manual Thi s page intentional ly left bl ank..
20: I nput / Output pin Charact eristi cs GP4020 GPS Baseband Processor Design Manual 185 20 INPUT / OU TPUT PIN CH A R ACTERISTICS The GP4020 E l e ctric a l Chara ct e ristics, whi ch are specific to the GP4020 devi ce are shown in the “ GP 4020 GPS Base band Proce ssor Data shee t” , DS51 34, ava ilable f rom Zarlink S e mi cond uctor.
20: I nput / Output pin Charact eristi cs 186 GP4020 GPS Baseband Processor Design Manual Pi n No . Pi n Na m e Pi n Typ e IP / O P Ce ll Typ e 5V Tol.
20: I nput / Output pin Charact eristi cs GP4020 GPS Baseband Processor Design Manual 187 Pi n No . Pi n Na m e Pi n Typ e IP / O P Ce ll Typ e 5V Tol.
20: I nput / Output pin Charact eristi cs 188 GP4020 GPS Baseband Processor Design Manual Input edge 0.1ns Inpu t e dge 1.5n s Switch ing De lay (n s) Load (fF) Load (fF) 50 100 25 0 50 0 10 00 50 10 0 25 0 500 1000 IP → D ↑ 0.29 0. 34 0.4 9 0.7 4 1.
20: I nput / Output pin Charact eristi cs GP4020 GPS Baseband Processor Design Manual 189 20.3. 1.2 Norm a l N ou tput s (3.3V ou tputs): CLA IO1HD01N, CL AIO1NR01N , CLAOP01N . Input edge 0.1ns Inpu t e dge 1.5n s Sw itc hin g De lay (ns) Load (pF) Load (pF) 10 20 40 80 150 10 20 40 80 150 D → OP ↑ 5.
20: I nput / Output pin Charact eristi cs 190 GP4020 GPS Baseband Processor Design Manual 20.3. 2.2 Norm a l N ou tput s : CLAI O 1HD03N , CLA OP03N . Input edge 0.1ns Inpu t e dge 1.5n s Switch ing De lay (n s) Load (pF) Load (pF) 10 20 40 80 150 10 20 40 80 15 0 D → OP ↑ 5.
20: I nput / Output pin Charact eristi cs GP4020 GPS Baseband Processor Design Manual 191 Para mete r Cell Type Mi n Typ Max Unit Conditi ons Input Leakage All IP -1 +1 µ A N o P ull Up /D own, VDD = 3. 6V Outp ut ( Tr ist at e) L eak ag e All OP 1 µ A N o Pull Up /D own, VD D = 3.
20: I nput / Output pin Charact eristi cs 192 GP4020 GPS Baseband Processor Design Manual Thi s Page intenti onall y l ef t bl ank..
21: T i m ing Characteri stics GP4020 GPS Baseband Processor Design Manual 193 2 1 T IM IN G CHA RA CTE R IS TI CS Th e t im i ng p a r am eter s i n thi s sec ti o n a ssum e a l o gi c s wi t chi n g p oi nt of 5 0% of VDD: All inpu ts assu m e rise and f all tim e s of nomina lly 2ns.
21: T i m ing Characteri stics 194 GP4020 GPS Baseband Processor Design Manual SDATA NSOE NSWE NSCS SADDR BuILD_CLK Taddrh Tncs Tnoe Taddr Tncsh Tdih Tnoeh Tdisu Figu re 2 1.
21: T i m ing Characteri stics GP4020 GPS Baseband Processor Design Manual 195 21.2 Mem ory Per ipheral C ontroller (M PC) E xternal R ead & Write tim ing pa rame te rs wi th SWa it Cont rol Me m .
21: T i m ing Characteri stics 196 GP4020 GPS Baseband Processor Design Manual For this ex am ple an edge trigge r e d packet t ra nsf e r (size = 2) i s shown . NOT E : W h en p er f orm i n g a DM A tr a ns f er , m e m o ry s i g nal s ar e a s p er th e MPC ti mi ng inf o rm at i on .
21: T i m ing Characteri stics GP4020 GPS Baseband Processor Design Manual 197 21.6 Sy stem Se rvices Modu le (SSM ) Broadcast Dia gnostic Tim ing Diagram s The S BDIAG l ines referred to here are the.
21: T i m ing Characteri stics 198 GP4020 GPS Baseband Processor Design Manual Parame ter M in M ax unit s Des cript ion an d note s T bsc l 15. 6 - ns T CK l ow p e r i od T bsc h 15. 6 - ns T CK hig h peri od Tbsis 5.0 - ns TDI,T MS s e t up t o [TCr] Tbsih 5.
GP4020 GPS Baseband Processor Design Manual Index - I INDEXES.
Index - I I GP4020 GPS Baseband Processor Design Manual Thi s page intentional ly left bl ank.
GP4020 GPS Baseband Processor Design Manual Index - I II Table of Figu re s Page Fig ure 1.1 GP 40 20 B loc k D iag ra m ............................................................................................... ....................... 2 Figure 1.
Index - IV GP4020 GPS Baseband Processor Design Manual Figure 12.10 Pe ri phe ral Cont r ol Log ic - Multiplex Logic .................................................................................... 120 Fig ure 12.1 1 Pe riphe ral C o nt rol L og ic - P e rip he ral In terru pt a nd W a ke -up con tro l log ic .
GP4020 GPS Baseband Processor Design Manual Index - V Thi s page intentional ly left bl ank.
Index - VI GP4020 GPS Baseband Processor Design Manual Table of D ata Tabl es Page Table 2 .1 GP4020 100-p in package dimens i on s ........................................................................ 1 3 Table 2 .2 G P4020 100-p in package Signa l Descript i ons .
GP4020 GPS Baseband Processor Design Manual Index - VI I Ta ble 7 .18 C OR R C Hx _C ODE _DC O_P HA SE Re giste r .............................................................74 Tabl e 7 .1 9 CORR CHx_CODE_DCO_PRESET_ PHASE Regis ter .................
Index - VI II GP4020 GPS Baseband Processor Design Manual Ta ble 12 .8 PC L PE R_ STA T R e gis te r ...................................................................................... 130 Ta ble 13 .1 Re al T ime Clo ck Re giste r M ap ...........
GP4020 GPS Baseband Processor Design Manual I ndex - IX Table 18 .1 W atchdog R egister M ap ......................................................................................... 178 Table 18 . 2 W atchdog C O NSTAT R egister .....................
Index - X GP4020 GPS Baseband Processor Design Manual Thi s page intentional ly left bl ank.
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