National SemiconductorメーカーDP8400の使用説明書/サービス説明書
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TL/F/5012 The DP8400 Family of Memory Interface Circuits AN-302 National Semiconductor Application Note 302 Charles Carinalli Mike Evans February 1986 The DP8400 Family of Memory Interface Circuits IN.
Indicates that there is a 3 k X pull-up resistor on these outputs when they are disabled. TL/F/5012 – 1 FIGURE 1. DP8409A Block Diagram TABLE II. DP8409A Mode Select Options Mode (RFSH ) M1 M0 Mode .
Drams may be 16k, 64k or 256k For 4 banks, can drive 16 data bits a 6 check bits for ECC. For 2 banks, can drive 32 data bits a 7 check bits for ECC. For 1 bank, can drive 64 data bits a 8 check bits for ECC. * These outputs may need damping resistors to prevent overshoot, undershoot at memories.
Refreshing The DP8409A also provdes hidden refresh capability while in one of the automatic access modes ( Figure 4 ). In this mode, it will automatically perform a refresh without the sys- tem being interrupted.
Two new devices are now available for this application. The DP84240 is pin and function compatible with the DM74S240. The DP84244 is likewise compatible with the DM74S244. However, this is where the similarity between the devices ends. Both the DP84240 and the DP84244 have been designed specifically to drive DRAM arrays.
TL/F/5012 – 8 FIGURE 7a. Typical Power Dissipation for DP84240 at V CC e 5.5V (All 8 drivers switching simultaneously) TL/F/5012 – 9 FIGURE 7b. Typical Power Dissipation for DP84244 at V CC e 5.5V (All 8 drivers switching simultaneously) The output stages of the DP84240 and the DP84244, al- though well matched, are relatively low impedance.
TABLE IV. Check Bit Overhead for Multiple Bit Error Detection and Single Bit Error Correction Number of Bits Number of Percentage in Memory Check Bits of Excess Data Word Required Memory 8 5 63% 16 6 .
TL/F/5012 – 11 FIGURE 9a. Normal Write Mode with DP8400 TL/F/5012 – 12 FIGURE 9b. Normal Read Mode Using the Error Monitoring Method with the DP8400 TL/F/5012 – 13 FIGURE 9c. Normal Read Mode Using the Always Correct Method with the DP8400 * C2, C3 generate odd parity TL/F/5012 – 14 FIGURE 10.
A key advantage of the DP8400 is that it has three error flags detailing the type of error occurrence. These are gen- erated using the syndrome word in the manner shown in Figure 11 .
After the complement correct cycle, the memory must be rewritten with the corrected data since the address now contains data that is complemented. Full error reporting is available from the DP8400 after the second read, the com- plement read, of memory.
MICROPROCESSOR INTERFACE CIRCUITS The major 8-bit, 16-bit and 32-bit microprocessors have dif- ferent control signal timing. There are also a number of speed options.
The DP8400 DRAM interface family provides complete solu- tions to memory support. This begins with the LSI functions such as the DP8400 expandable error checker/corrector and the DP8409A DRAM controller/driver. It continues with the DP84240 and the DP84244 high performance buffer/ drivers.
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AN-302 The DP8400 Family of Memory Interface Circuits LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION.
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