National SemiconductorメーカーDS90C3202の使用説明書/サービス説明書
ページ先へ移動 of 22
DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver General Description The DS90C3202 is a 3.3V single/dual FPD-Link 10-bit color receiver is designed to be used in Liquid Crystal Display TVs, LCD Monitors, Digital TVs, and Plasma Display Panel TVs.
Typical Application Diagram 20147102 FIGURE 2. LCD Panel Application Diagram Functional Description The DS90C3201 and DS90C3202 are a dual 10-bit color T ransmitter and Receiver FPD-Link chipset designed to transmit data at clocks speeds from 8 to 135 MHz.
Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply V oltage (V DD ) −0.3V to +4V L VCMOS/L VTTL Input V oltage −0.
Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units RECEIVER SUPPLY CURRENT ICCRW .
Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Condition/ Reference Min Typ Max Units CLHT LVCMOS/LVTTL Low-to.
Two-Wire Serial Communication Interface Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units f SC S2CLK Clock Frequency 400 kHz SC:LOW Clock Low Period R P = 4.7K Ω ,C L = 50pF 1.
AC Timing Diagrams (Continued) 20147103 FIGURE 2. “Worst Case” T est Pattern 20147104 FIGURE 3. Incremental T est Pattern 20147105 FIGURE 4. T ypical and Max ICC with Worse Case and Incremental Pattern 20147106 FIGURE 5. L VCMOS/L VTTL Output Load and T ransition Times DS90C3202 www .
AC Timing Diagrams (Continued) 20147107 FIGURE 6. Receiver Phase Lock Loop W ake-up Time 20147108 FIGURE 7. Powerdown Delay 20147109 FIGURE 8. Receiver Propagation Delay DS90C3202 www .
AC Timing Diagrams (Continued) 20147110 FIGURE 9. RFB: L VTTL Level Programmable Strobe Select 20147111 RITOL ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 11) + ISI (Inter-symbol interference) (Note 12) Cable Skew — typically 10 ps– 40 ps per foot, media dependent Please see National’s AN-1217 for more details.
AC Timing Diagrams (Continued) 20147113 RegisterAddress 29d/1dh bit [2:1] = 00b FIGURE 12. Receiver RSRC and RHRC Output Setup/Hold Time — PTO Enabled 20147114 FIGURE 13. Receiver RSRC and RHRC Output Setup/Hold Time Adjustment — PTO Disabled DS90C3202 www .
AC Timing Diagrams (Continued) 20147115 FIGURE 14. Receiver RSRC and RHRC Output Setup/Hold Time Adjustment — PTO Enabled DS90C3202 www .national.com 11.
AC Timing Diagrams (Continued) 20147116 FIGURE 15. L VDS Input Mapping DS90C3202 www .national.com 12.
AC Timing Diagrams (Continued) 20147117 FIGURE 16. Receiver RITOL Min and Max DS90C3202 www .national.com 13.
Pin Diagram DS90C3202 Receiver 20147118 DS90C3202 www .national.com 14.
DS90C3202 Pin Descriptions Pin No. Pin Name I/O Pin Type Description 1 S2DAT I/OP Digital Two-wire Serial Interface – Data 2 S2CLK I/P Digital Two-wire Serial Interface – Clock 3 VDDP1 VDD PLL Pow.
DS90C3202 Pin Descriptions (Continued) Pin No. Pin Name I/O Pin Type Description 46 VDD2 VDD LVTTL O/P PWR Power supply pin for LVTTL outputs and digital circuitry 47 RXEA0 O/P LVTTL O/P LVTTL level d.
DS90C3202 Pin Descriptions (Continued) Pin No. Pin Name I/O Pin Type Description 92 RXOA4 O/P LVTTL O/P LVTTL level data output 93 RXOA5 O/P LVTTL O/P LVTTL level data output 94 RXOA6 O/P LVTTL O/P LV.
Two-Wire Serial Communication Interface Description The DS90C3202 operates as a slave on the Serial Bus, so the S2CLK line is an input (no clock is generated by the DS90C3202) and the S2DA T line is bi-directional. DS90C3202 has a fixed 7bit slave address.
DS90C3202 Two-Wire Serial Interface Register Table Address R/W RESET Bit # Description Default Value 0d/0h R PWDN [7:0] Vender ID low byte[7:0] = 05h 0000_0101 1d/1h R PWDN [7:0] Vender ID high byte[1.
DS90C3202 Two-Wire Serial Interface Register Table (Continued) Address R/W RESET Bit # Description Default Value 26d/1ah R/W None [7] Reserved 0000_0000 [6:4] LVDS input skew control for RXE channel B.
DS90C3202 Two-Wire Serial Interface Register Table (Continued) Address R/W RESET Bit # Description Default Value 30d/1eh R/W None [7:5] Reserved 0000_0000 [4] I/O disable control for RXE channel A, 1:.
Physical Dimensions inches (millimeters) unless otherwise noted 128-Pin TQFP Package Order Number DS90C3202VS NS Package Number VJX128A National does not assume any responsibility for use of any circu.
デバイスNational Semiconductor DS90C3202の購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
National Semiconductor DS90C3202をまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはNational Semiconductor DS90C3202の技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。National Semiconductor DS90C3202の取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。National Semiconductor DS90C3202で得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
National Semiconductor DS90C3202を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はNational Semiconductor DS90C3202の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、National Semiconductor DS90C3202に関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちNational Semiconductor DS90C3202デバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
