NvidiaメーカーDG-04927-001_V01の使用説明書/サービス説明書
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Advance Information – Subject to Change NVIDIA CONFIDENTIAL January 2010 | D G-04927-001_v01 USER GUIDE T egra ™ 200 Series Developer Board.
2 Advance Information – Subject to Change DG-04927-001_v01 NVIDIA CONFIDENTIAL Document Change History Version Date Description v01 JAN 22, 2010 Initial Release.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 3 NVIDIA CONFIDENTIAL Table of Contents 1.0 INTROD UCTION ..........................................................................................
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 4 NVIDIA CONFIDENTIAL 4.6 Display ..................................................................................................................
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 5 NVIDIA CONFIDENTIAL 1.0 INTRODUCTION The Smartbook Development System is an example of a devel opment platform built around the Tegra ™ 200 Series De veloper Board.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 6 NVIDIA CONFIDENTIAL 2.0 DEVELOPER BO ARD OVERVIEW 2.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 7 NVIDIA CONFIDENTIAL Figure 2. Tegra 200 Seri es Developer Board (Top V iew) Debug Conn (J10) MM.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 8 NVIDIA CONFIDENTIAL 2.2 NVIDIA® Tegra™ 250 The NVIDIA Tegra 250 computer-on-a-c hip is suited for handheld a nd mobile applications . It’s primary purpose is to control all system peripherals and provide computi ng power.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 9 NVIDIA CONFIDENTIAL 2.5 LCD Interface The Smartbook Development System routes an 18-bit paral lel RGB interface from the Tegra 250 to a Texas Instrument s SN75LVDS83B LVDS Transmitter which goes to an LVDS panel connector (J7).
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 10 NVIDIA CONFIDENTIAL of the USB ports are brought to standard T ype A connectors (J6 – Dual host port connector and J25 – S ingle host port). The forth USB is routed to PCIe Mini-Card #1 (J28).
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 11 NVIDIA CONFIDENTIAL 2.12 User Interface Attach your USB keyboard and mouse to a ny of the available USB Type-A Host ports (J6, J25). 2.13 Miscellaneous Temperature Sensor On Semiconductor Model ADT7461AARMZ_RL 7 0.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 12 NVIDIA CONFIDENTIAL 3.0 SATELLITE BOARD HEADERS Two dual row 50-pin expansion hea ders enable the ability to connect a satellite board to the Tegra 200 Series D eveloper Board and are used to extend devel oper board functionalit y.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 13 NVIDIA CONFIDENTIAL 3.1 Satellite Board Headers All the interface connections bet ween a sa tellite board and the T egra 200 Series Deve loper Board ar e through two sets of Samtec FTS series 50-pin Micro Strips connectors.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 14 NVIDIA CONFIDENTIAL 3.2 I2C Map The I2C interface can be used to connect a touch screen, touch p ad and other devices. There are two options for the T ouch devic es.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 15 NVIDIA CONFIDENTIAL 4.0 CONNECTION EXAMPLES 4.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 16 NVIDIA CONFIDENTIAL 4.1.1 Major Components 4.1.1.1 PMU The Tegra 200 Series Dev eloper Board includes a multi-c h annel power management unit for embedded process ors (TI TPS658621).
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 17 NVIDIA CONFIDENTIAL 4.1.2 Power Supplies The Tegra 250 has 29 power rails (3 cores, 14 analog and 12 di gital I/O). Depending on system design, many of the rails can share a power supply, and some are not needed for al l designs .
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 18 NVIDIA CONFIDENTIAL 4.1.3 Power Sequencing The Power solution, including the PMU and any external suppli e s/logic, must be able to meet the Tegra 250 po wer sequence requirements.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 19 NVIDIA CONFIDENTIAL 4.1.4 Bypass Capacitor Recommendations Table 5 lists the basic recommend ations for bypass capacitors near the Tegra 250. In general, on e 0.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 20 NVIDIA CONFIDENTIAL 4.2 Clocks The Tegra 250 has a large nu mber of internal functional blocks supporting a broa d range of interf aces. Each of these has its own clocking requirements.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 21 NVIDIA CONFIDENTIAL Figure 9. Crystal Connection Example Table 6 Crystal and Circuit Requireme.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 22 NVIDIA CONFIDENTIAL 4.3 DRAM Memory Configurations Tegra 250 supports standard DDR2 SDRAM. Up to 1GB total memo ry, two chip selects and two Clock Enables are su pported.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 23 NVIDIA CONFIDENTIAL Table 7. DDR Pinout Signal Pin Signal Pin DDR_A0 A20 DDR_DM0 F19 DDR_A1 C2.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 24 NVIDIA CONFIDENTIAL 4.4 NAND The Tegra 250 GMI interface supports a bro ad range of devi ces including a variet y of NAND devices and config urations.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 25 NVIDIA CONFIDENTIAL 4.5.1 Force Recovery The Tegra 250 requires USB1 to be available as a Device for Force Recover y mode which is used to download ne w firmware.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 26 NVIDIA CONFIDENTIAL Table 8. ULPI Pinout Signal Pin Signal Pin ULPI_CLK M2 ULPI_DATA2 N4 ULPI_DIR M3 ULPI_DATA3 L3 ULPI_NXT M1 ULPI_DATA4 L4 ULPI_STP P3 ULPI_DATA5 L6 ULPI_DATA0 P4 ULPI_DATA6 P5 ULPI_DATA1 P6 ULPI_DATA7 N6 4.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 27 NVIDIA CONFIDENTIAL Table 9. PCIe Pinout Signal Pin Signal Pin PEX_CLK_OUT1_N AC4 PEX_L1_TXN A.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 28 NVIDIA CONFIDENTIAL Figure 16. Example LVDS Connections 10K Table 10.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 29 NVIDIA CONFIDENTIAL 4.6.2 HDMI HDMI_RSET on the Tegra 250 is tied to gro und through a 1K , 1% resistor DDC_SCL/SDA pins are 5V toler ant (no level shifter required).
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 30 NVIDIA CONFIDENTIAL 4.6.3 VGA (CRT) Out Figure 18. VGA Output Connection Example 4.6.3.1 Unused Pins Any unused VDAC pins (VDAC_R, VDAC _G, VDAC_B) can be left unconnected.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 31 NVIDIA CONFIDENTIAL 4.7 Camera The Tegra 200 Series Dev eloper Board supports a dual lane MI PI CSI connecti on. The Smartbook Development S ystem uses an OmniVision Camera modul e.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 32 NVIDIA CONFIDENTIAL 4.8 SD/SDIO/MMC The Tegra 250 has four SD/MMC controller s, capable of supporting a variety of dev ices and protocols including SD Mem ory, SDIO, eSD, MMC and eMMC.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 33 NVIDIA CONFIDENTIAL 4.8.2 eMMC Device Connections The SD/MMC interface can support a variety of flash mem ory devices.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 34 NVIDIA CONFIDENTIAL 4.8.3 SDIO Device Connections An SDIO controller is often used to interface to medium b and width peripherals such as a Wi-F i controller.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 35 NVIDIA CONFIDENTIAL 4.9 Miscellaneous 4.9.1 Thermal Diode (Temperature Sensor) Figure 23: Thermal Diode Connection Examp le 100K 100K 10K 10K Table 13.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 36 NVIDIA CONFIDENTIAL Figure 24. Debug Interface Connection DBG_RESET_N VDDIO_SYS 12 2 11 12 10 .
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 37 NVIDIA CONFIDENTIAL 4.9.4 Strapping Pins Straps must be stable from the rising edge of SYS_RESET_N until 12.5us afterward. Figure 26. Power-on Strapping Co nnections Table 14.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 38 NVIDIA CONFIDENTIAL 5.0 THERMAL 5.1 Major Component Thermal Specifications Most of the major components used in Tegra 200 ser ies Devel oper Board are listed in Table 39 a long with the temperature range they are able to operate across.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 39 NVIDIA CONFIDENTIAL Figure 27. Top View – Heat Generating and Therm al Sensitive Components Figure 28.
Tegra 200 Series Developer Board User Guide DG-04927-001_v01 Advance Information – Subject to Change 40 NVIDIA CONFIDENTIAL The Tegra 200 Series Dev eloper Board does not represent an ac tual layout for use in a Smartbook design.
Notice ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS, AND OTHER DOCUMENTS (TOGETHER AND SEPARATELY, “MATERIALS”) ARE BEING PROVIDED “AS IS.
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