Omega Vehicle SecurityメーカーDAQ-16の使用説明書/サービス説明書
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INTERFACE CARDS FOR PERSONAL COMPUTERS DAQ-16 Data Acquisition Adapter for 16-bit ISA compatible machines Users Manual OMEGA ENGINEERING, INC. TEL: (203) 359-1660 One Omega Drive FAX: (203) 359-7700 P.O. Box 4047 Toll free: 1-800-826-6342 Stamford, CT 06907-4047 E-mail: das@omega.
WARRANTY/DISCLAIMER OMEGA ENGI NEERING, INC. , w arrants this unit to be free of def ects in materials and w orkmanship for a perio d of 13 mont hs from the date of purchase. OMEGA w arranty adds an ad ditional one (1) month grace period to the normal one (1 ) year pr oduct w arr anty to co ver shipping and handling time.
OMEGAnet On-line Service: Internet e-mail: http://www.omega.com info@omega.com Servicing North America : USA : One Omega Drive, Box 4047 E-mail: info@omega.com ISO 9001 Certified Stamford, CT 06907-0047 Tel: (203) 359-1660 FAX: (203) 359-7700 Canada : 976 Bergar E-mail: info@omega.
United Kingdom : One Omega Drive, River Bend Technology Drive ISO 9002 Certified Northbank, Irlam, Manchester M44 5EX, England Tel: 44 (161) 777-6611 FAX: 44 (161) 777-6622 Toll Free in England: 0800-488-488 E-mail: info@omega.co.uk It is the policy of OM EGA to comply with al l worl dwide safety and EM C/EMI regulations that apply.
Declaration of Conf orm ity Manufacturer's Name: Omega Engineering Inc. Manufacturer's Address: One Omega Drive Stamford, CT 06907-0047 Application of Council Directive: 89/336/EEC Standards.
Table of Contents 28 4.2 Programming the 8254 Counter/Timer ............................ 27 4.1.8 8254 Control Word/Status Register ................................... 27 4.1.7 Multi-Function Timer Register ....................................... 27 4.
List of Figures and Tables 25 Table 4-1. DAQ-16 Address Map .............................................. 15 Table 2-3. Jumper J4 Configuration ............................................ 13 Table 2-2. A/D Conversion Format Examples ................
1. Introduction The DA Q-1 6 is a high s peed dat a ac quisit ion adap te r for IBM AT com pat ible mac hine s off eri ng ei ght d if fer ential anal og i nput channel s with 16- bit r esol ution, two anal og output channel s with 12-b it r esoluti on and four di gi tal i nput/output lines.
1.2 DAQ-16 Specifications DACK 5, 6 , 7 DRQ 5, 6 , 7 DMA Levels: IRQ 2, 3, 4. 5, 6, 7, 10, 11, 12, 14, 15 Interrupt Levels: 0000H - FFFFH I/O Address Range: ISA 16-bit Bus Interface: 491.
2. Circuit Board Description and Configuration The ba se addres s of t he DA Q-1 6 is sele ct ed using s witch es SW1 and SW 2. The op erat ing mo de of t he DAQ-16 is co nt rolled by jump ers J1 th rough J7 , while DMA an d interru pt sele ctions ar e set wi th jumper s J 8 throug h J 11.
Figures 2-1 and 2-2 show the configuration options for jumpers J7 and J6. J7 J7 J7 1 3 2 4 2 4 2 4 1 3 1 3 Ga i n = 1 Gai n = 1 0 Gai n = 1 00 Figure 2-1. Jumper J7 Configuration 10 vo l t ra ng e 1 2 3 4 5 6 J6 5 vo l t ra ng e 1 2 3 4 5 6 J6 2.5 vol t r ange 4 5 6 1 2 3 J6 Figure 2-2.
The final stage of the A/D converter circuit is the A/D converter IC . The co nverter must be co nfigur ed for u nipo lar o r bipolar inp ut vo ltages a nd for binary o r 2' s com plemen t dat a conversion. These options are selected using jumper J5 as shown in Figure 2-3 below.
+32,767 +32,767 +65,535 +65,535 +Vmax +16,384 0 +49,152 +32,768 +Vmax/2 0 -32,768 +32,768 0 0 -16,384 n/a +16,384 n/a -Vmax/2 -32,768 n/a 0 n/a -Vmax bipolar unipolar bipolar unipolar 2’s Complement 2’s Complement Binary Binary Voltage Table 2-2.
2.2 Digital to Analog Converters The di gi tal to an alog (D /A) se ction of the DA Q-16 consi sts of two i ndepe nden t 12-b it multi ply ing D /A converte rs, and tw o ind ependent two-stag e output ampl ifi ers.
5 6 7 8 1 2 3 4 J4 Channel 1 gain Channel 1 select Channel 0 select Channel 0 gain Figure 2-5. Jumper J4 Configuration Table 2-3 lists configuration options for jumper J4. connect 4-8 open 4-8 connect 2-6 open 2-6 Gain = 1 Gain = 2 connect 3-7 open 3-7 connect 1-5 open 1-5 Bipolar Unipolar Channel 1 Channel 0 Table 2-3.
2.4 Base Address The DAQ-16 uses 16 consec utiv e I/O address lo cation s in the range 0 t o 0FFFFH. Two six- positi on switches (SW1 and SW2) are used to select the base add ress. SW1 controls addres s lines A15 - A 10, and S W2 co nt rols A9 - A4. Addres s lines A3 - A0 are us ed internally by the DAQ-16 to select which register to access.
2.5 Clock Selection The D AQ-1 6 is e quipped wi th a progr ammab le cl ock ci rcui t to pr oduce d ata sampl in g rate s independ ent from the clock rate o f the host co mputer. An onboard 8254 programmabl e inte rval time r, wi th a 10 MHz clock input and ei ther tw o or thr ee cascad ed 16-b i t timer s, provi d es the sampl i n g r a te.
2.5.1 Internal Clock Sampling rates for the internal clock can be calculated using the following equation: t = 100ns * [N1*N2] or f = 10MHz / [N1*N2] wher e N1 is the low 1 6-b its of the clock di vid er and N2 is the high 1 6-b its of the clock divider.
Whe n co nfigured fo r a 48-bit div ider, the first s ampling p eriod will be slightly lo nger th an the other s because the fi rst cl ock per iod is r equi red to l oad the i ni tial val ue of the multi-function timer.
When the mul ti- functi on time r is use d as a pr e-d i vid er, the fr equency of the ex ternal cl ock input may be var ied fr om DC to 10 MHz as l ong as the hi gh porti on of the cl ock is at l east 30ns and the low porti on is at least 5 0ns.
2.7 Direct Memory Access Di rect Me mory Acce ss (D MA) tra nsfe rs provi de a way of transf er ri ng da ta fr om the DAQ- 16's A/D converter in to the computer's memor y w ithout usi ng the Ce ntral Processi ng Unit (CPU). DMA capa bility e nable s o ther syst em so ftware to be e xecut ed while data is being input from the DAQ-16.
2.8 Interrupts The DAQ-16 is capable of generating an interrupt from one of four sources: 1. End of conversion signal 2. DMA terminal count 3. Multi-function timer output 4. External interrupt input The i nterrupt source is softwar e selected through the D AQ-16 contr ol word r egi ster.
3. External Connections The DAQ-16 is equipped with a high density 62-pin connector as shown in Figure 3-1. 2 - CH1+ 4 - CH2 - 6 - CH 4+ 8 - CH5- 10 - CH7+ 12 - AOUT0 14 - DOUT0 6 - DOUT3 18 - EXT TRI.
CH0 -,CH0+ ,...,CH7-,C H7+ : Ana log inpu ts t o t he an alog to digit al c onv ert er. Am plitude and polar ity d epend upon jumper setting s. The i nput re sistance of these l ines i s 1.5K ohms typical. AOUT 0, A OUT1 : Ana log outputs from the d i gi tal to ana log conve rter s.
4. Register Description and Programming The DAQ-16 us es 16 consecu tive I/ O address lo cations in the range 0 to FFFFH. The card ut ilizes thes e addre ss es fo r the regist ers list ed in Table 4-1 . (* indicat es regis ters loca te d in 8254 counter).
DMAEN - enables / disables DMA. When set, logic 1, DMA transfers are enabled. DMAC T - e nable s t he m ulti-c hanne l DM A capa bility o f th e DAQ -16. When s et, logic 1 , a termi nal count on the acti ve DMA channe l cause s DMA tr ansfer s to beg in on the "stand -b y" ch ann el.
4.1.2 Start of Conversion Register The start of conversion register is 16-bit write only and performs two functions: 1. Wh en co nfigured for inte rnal triggerin g, writing a "0" to th is regist er generat es the software trigger, starting the data conversion process.
4.2 Programming the 8254 Counter/Timer This section provides programming information for the 8254 co unter/timer as i mplemented on the DAQ-16. For more details on the 8254, consult the Intel Micro-Processor and Peripheral Handbook. To program any of the counters contained in the 8254 counter/timer, three steps are required: 1.
Counter 1 - Clock rate register (high word) operating mode: 2 minimum count value: 2 configuration byte: 0 / 1 / 1 / 1 / 0 / 1 / 0 / 0 = 74H Example: Program the value 13A4H into the high word of the clock rate register.
DAQ-16 Users Manual Version 2.20 January 28, 1999 Part No. 940-0032-220.
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