RenesasメーカーHD49335NPの使用説明書/サービス説明書
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Rev.1.0, Fe b.12.2004, page 1 of 29 HD49335NP/HNP CDS/PGA & 10-bit A/D TG Conv erter REJ03F0 097-0100Z Rev.1.0 Feb.12.20 04 Descr iption The HD49335NP/ HNP i s a CMO S IC th at provides CDS- PGA a.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 2 of 29 Pin A rrangem ent 48 47 39 46 45 44 43 42 41 40 38 36 35 34 37 12 1 0 3 4 5 6 7 8 9 11 12 13 14 15 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 3 of 29 Pin De scription (cont.) Pin No . Sy mbol Description I/O A nalog(A ) or Digital (D) Remarks 30 XV1 V.CCD trans fer pulse out put-1 O D 2 m A/10 pF 31 XV2 V.CCD trans fer pulse out put-2 O D 2 m A/10 pF 32 XV3 V.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 4 of 29 Input/Out put Equivale nt Ci rcuit Pin Name Equiv alent Circuit D0 to D9, HD_in, VD_in, H1A, H2A, 1/2clk_o, 1/4clk_o, 4 1cont, SUB_SW, SUB_PD DIN DV .
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 5 of 29 Block Diagram 10bit ADC AV SS VRB VRM VRT CDS_in CDS BLKSH BLKC ADC_in SUB_SW SUB_PD STROB D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Reset DV SS 1 to 4 BLKFB CS .
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 6 of 29 Internal Functions Functional Descriptio n • CDS input CCD l ow-frequen cy noise is suppres sed by CDS (correl ated doubl e sampl ing). The sign al level is clamped at 14 LSB to 76 L SB by resist er during th e OB period.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 7 of 29 3. Auto matic Offset Calib ration Function a nd Black-Level Cla mp Data Settings The DAC DC voltage added to the output of the PG A amplifier is adjusted by auto matic offset calibration.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 8 of 29 6. ADC Digital Outpu t Control Functio n The ADC digital outpu t includes t he funct ions output en able, code conve rsion, an d test mode. Tables 3, 4 and 5 show t he out p ut f unct i o ns a nd the c ode s.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 9 of 29 7. Adjustment of Black-Level S/H Respon se Frequency Characteristics The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by ch anging the register se ttings, as sho wn i n t able 6 .
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 10 of 29 Timing Chart Figure 2 s hows the t iming chart when CDSIN and A DCIN input modes are used. 012 9 1 0 11 N+1 N+2 N+9 N+10 N+11 N CDS_in SP1 SP2 ADCLK.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 11 of 29 Detaile d Timing Spe cificat ions Detailed Timing Specifications w h en CDSIN Inp ut Mode is Used Figure 3 s hows the det ailed timin g specification s when th e CDSIN input mode is used, and ta ble 8 show s each timin g specification.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 12 of 29 Detailed Timing Specif ica tions at Pre-Blan kin g Figure 5 s hows the pre- blanking detailed t iming specificat ions.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 13 of 29 Dummy Clamp It adjusts the mis- clamp which occurs wh en taking the phot o under the hi ghli g ht co ndit io ns.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 14 of 29 Absolute Maximum Ratings (Ta = 25 ° C) Item Symbol Ratings Unit Power supply voltage V DD 4.1 V Analog input v oltage V IN –0.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 15 of 29 Electrical Ch aracte ristics (cont.) (Unless othewi de specified, Ta = 25°C, A V DD = 3.0 V, DV DD = 3.0 V, and R BIAS = 33 k Ω ) • Items for CDSIN In p ut Mode Item Symbol Min Typ Max Unit Test Conditions Remarks Consumpti on current (1) I DD1 — 84 96.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 16 of 29 Electrical Ch aracte ristics (cont.) (Unless othewi de specified, Ta = 25°C, A V DD = 3.0 V, DV DD = 3.0 V, and R BIAS = 33 k Ω ) • Items for A DCIN Input Mode Item Symbol Min Ty p Max Unit Test Conditions Remarks Consumpti on current (3) I DD3 — 32 38.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 17 of 29 Serial Interfa ce Specifications Timing Specifications SDATA STD2(Upper data) STD1(Lower data) address(address) SCK CS f SCK D9 D8 D11 D10 D13 D12 D.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 18 of 29 Explanati on of Serial D ata of CD S Part Serial data of CDS part are assign ed to a ddress H’F0 to H’F8.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 19 of 29 • Output m ode (D2 to D4 of address H’F1 and addres s H’F4 of D6) It is a test mode. Combinatio n details are table 3 to 5. Normally set to all 0. • SHA-fsel (D 8 to D9 of addres s H’F1) It is a LPF switching of SH amplifier.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 20 of 29 Address STD1[7:0] (L) STD2[15:8] (H) 11110100 D 4 D 3 D 2 D7 D6 D5 D1 D0 D12 D11 D10 D9 D8 Gray_test VD latch MON Gray code H12_Buff • MON (D0 to D2 of address H’F4) Select the pulse which output to p in MON (pin 60).
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 21 of 29 Ripple (pseudo outline made b y qua ntized error) occurres on the point which swithing the ADC output multiple b it in parallel. When switching the several of ADC outp ut at the same time, ripple (pseudo outline caused by miss quantization) occurs to the image.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 22 of 29 • Address H ’F5 sets t he DLL delay t ime and sel ects the 1/4 ph ase. Detail s are on t he next page. A nd D15 of address H’F8 can switch 2/3 divided mod e b ut ensure that this address data relative to va lid /invalid.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 23 of 29 (3) Setting meth od of DLL 28 14 0 1. 2. 3. 42 ∗ Default 56 10 H1 DLL step decides the how many divide the 1 cycle of sensor CLK. For reference, set 1 ns(when 2 ns DLL_current bit = 0, when 1 set to 1 ns) Can be set 16 to 64 steps by 4 steps.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 24 of 29 Operation Sequence at Pow er On V DD (1) Resistor transfer of TG part (2) DLL data transfer of CDS part (3) Reset=L of CDS part (4) Reset=H of CDS part (5) Other data of CDS part : Wait more than 6clk after release the hardware Reset and then transfer the necessary data to TG part.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 25 of 29 Timing Sp ecification s of High Speed Pulse two twh tr twl twl tf 50% 50% t H1DL 90% 10% 90% 10% H2 RG • H1, H2, RG waveform H1 tf twh tr Item H1/.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 26 of 29 Notice for Use 1. Careful handling is necessary to prevent dam a ge due to static electricity. 2. T his product ha s been dev eloped for con sumer appl ications , and should n ot be used in non-cons umer applicat ions.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 27 of 29 Example of Reco mmend ed Extern al Circuit • Slave mode Pin 57(Test1 = Low) 31 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 33 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 24 23 22 21 20 19 18 17 25 26 27 28 29 30 32 50 57 58 59 60 61 62 63 64 56 55 54 53 52 51 49 HD49335 1 µ 1 µ 0.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 28 of 29 • CDS single operating mode Pin 56(Test2 = Low) ∗ Pin 57 is "Don't care" in this mode.
HD49335N P/HNP Rev.1.0, Fe b.12.2004, page 29 of 29 Package Dimensions Package Code JEDEC JEITA Mass (reference value) TNP-64AV — — 0.14 g Unit: mm 1 9 0.20 ± 0.05 0.05 M 0.05 S S A-B C A B C 8.80 0.65 C0.50 Index 0.50 Part A ( φ 0.2) S Enlargement of Part A C0.
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