SamsungメーカーM471B1G73AH0の使用説明書/サービス説明書
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- 1 - M471B1G73AH0 Rev . 1.0, Jul. 2010 SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMA TION AND SPECIFICA TIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference pur poses only . All info rmation discussed herein is provided on an "AS IS" basis, without warra nties of any kind.
- 2 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 Rev ision History Revision No. History Draft Date Remark Editor 1.0 - First Release Jul. 2010 - S.
- 3 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 Table Of Contents 204pin Unbuffered SODIMM based on 4Gb A-die 1. DDR3 Unbuffered SODIMM Ordering Information .......................................... ....................................... ....
- 4 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 1. DDR3 Unbuff ered SODIMM Order ing Inf ormation NOTE : 1. "##" - F8/H9 2. F8 - 1066Mbps 7-7-7 & H9 - 1333Mbp s 9-9-9 - DDR3-1333(9-9-9) is backward compatib le to DDR3-1066(7-7-7) 2.
- 5 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 4. x64 DIMM Pin Configurations (F ront side/B ack Side) NOTE : 1. NC = No Connect, NU = Not Used, R FU = Reserved Future Use 2. TEST(pin 125) is reserved for bus analysi s probes and is NC on normal memory modul es.
- 6 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 5. Pin Descr iption NOTE: * The V DD and V DDQ pins are tied commo n to a si ngle po wer-plane on these designs.
- 7 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 6. Input /Output F uncti onal Description Symbol Ty p e Function CK0-CK1 CK0 -CK1 Input The system clock inputs. All address and command lines are sampled on the cross point of the rising edg e of CK and falling edge of CK.
- 8 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 7. F uncti on Block Diagram: 7.1 8GB, 1Gx64 Module (Popu lated as 2 ranks of x8 DDR3 SDRAMs) V7 V8 V5 S1 RAS CAS WE CK1 CK1 CKE1 ODT1 A[0:N] /BA[.
- 9 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 8. Abso lute Maximum Ratings 8.1 Abso lute Maximum DC Ratings NOTE : 1. S tresses greater th an those listed under “A bsolute Maximum Rating s” may cause p ermanent damage to the d evice.
- 10 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 10. AC & DC Input Measurement Levels 10.1 AC & DC Logic Input Leve ls for Single-ended Signals [ T abl e 1 ] Single-ended AC & DC in put levels for Command and Address NOTE : 1. For input o nly pins except RESET , V REF = V REFCA (DC) 2.
- 11 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 10.2 V REF T olerances. The dc-tolerance limits and ac-noise limits for the reference voltages V REFCA and V REFDQ are illustrate in Figure 1. It shows a valid reference voltage V REF (t) as a function of time.
- 12 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 10.3 AC and DC Logic Input Levels f or Diff erential Signals 10.3.1 Diff erential Signa ls Definition Figure 2. Definition of dif ferential ac-swing and "time above ac leve l" tDV AC 10.
- 13 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 10.3.3 Single-ended Requirements for Differential Signals Each individual component of a differential signal (CK, DQS, CK , DQS ) has also to comply with cert ain requirements for single-ended signals.
- 14 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 10.3.4 Different ial Input Cross Poi nt Voltage T o guarantee t ight setup and hold time s as well as output skew para meters wit h respect to clock and strobe, each cross point vo ltage of differential input signals (CK, CK and DQS, DQS ) must meet the requir ements in below table.
- 15 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 11. AC & DC Output Measurement Levels 11.1 Single Ended AC and DC Output Lev els [ T abl e 7 ] Single Ended AC and DC out put levels NOTE : 1.
- 16 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 11.4 Diff erential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V OLdiff (AC) and V OH- diff (AC) for differential signals as shown in below .
- 17 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 12. DIMM IDD specification definition Symbol Description IDD0 Operating One Bank Active-Precharge Cur rent CKE: High; External clock: On; tCK, n.
- 18 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 NOTE : 1) Burst Length: BL8 fixed by MRS: set MR0 A[1, 0]=00B 2) Output Buf fer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01 B; R TT_Nom enab.
- 19 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 13. IDD SPEC T ab le M471B1G73AH0 : 8 GB (1Gx64) Module NOTE : 1. DIMM IDD SPEC is calculated with consid ering de-actived rank(IDLE) is IDD2N.
- 20 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 14. Input /Output Capacitance 14.1 2Rx8 2G B SODIMM Parameter Symbol M471B1G73AH0 Unit s NOTE DDR3-1066 DDR3-1333 Min Max Min Max Input/output c.
- 21 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 15. E lectric al Char acteristics and AC timing (0 ° C<T CASE ≤ 95 ° C, V DDQ = 1.5V ± 0.
- 22 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 [ T abl e 14 ] DDR3-1066 Speed Bins Speed DDR3-1066 Units NOTE CL-nRCD-nRP 7 - 7 - 7 Parameter Symbol min max Internal read command to first data tAA 13.125 20 ns ACT to internal read or write delay time tRCD 13.
- 23 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 [ T abl e 15 ] DDR3-1333 Speed Bins Speed DDR3-1333 Units NOTE CL-nRCD-nRP 9 -9 - 9 Parameter Symbol min max Internal read command to first data tAA 13.5 (13.125) 8 20 ns ACT to internal read or write delay time tRCD 13.
- 24 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 [ T abl e 16 ] DDR3-1600 Speed Bins Speed DDR3-1600 Units NOTE CL-nRCD-nRP 11-11 -11 Parameter Symbol min max Internal read command to first data tAA 13.75 (13.125) 8 20 ns ACT to internal read or write delay time tRCD 13.
- 25 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 15.3.1 Speed Bin T able Notes Absolute S pecification (T OPER ; V DDQ = V DD = 1.5V +/- 0.075 V); NOTE : 1. The CL setting and CWL setting result in tCK(A VG).MIN and tCK(A VG).MAX requ irements.
- 26 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 16. T iming P arameters by Speed Gr ade [ T abl e 17 ] Timing Parameters by Speed Bin Speed DDR3-80 0 DDR3-1066 DDR3-1333 DDR3 -1600 Units NOTE .
- 27 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 [ Table 17 ] Timing Parame ters by Speed Bin (Cont.) Speed DDR3-800 DDR3-1066 DDR 3-1333 DDR3-1600 Units NOTE Parameter Symbol MIN MAX MIN MAX M.
- 28 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 [ T abl e 17 ] Timing Parameters by Speed Bin (Cont.) Speed DDR3-800 DDR3-1066 DDR3-1 333 DDR3-1600 Units NOTE Parameter Symbol MIN MAX MIN MAX .
- 29 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 16.1 Jitter Notes Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input cl ock under operation. Unit ’nCK’ r epresents one clock cycle of the input clock, counting the actual clock edges .
- 30 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 16.2 T iming P arameter Not es 1. Actual val ue dependant upo n measuremen t level defini tions which are TBD. 2. Commands requ iring a locked DL L are: READ (and RAP) an d synchronous ODT co mmands.
- 31 - Unbuffered SODIMM datasheet DDR3 SDRAM Rev . 1.0 17. Physical Dimensions : 17.1 512Mx8 based 1Gx64 Module (2 Ranks) - M471B1G73AH0 The used device is 512M x8 DDR3 SDRAM, FBGA. DDR3 SDRAM Part NO : K4B4G0846A - HC** * NOTE : T olerances on all dimensions ±0.
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