Texas InstrumentsメーカーSLVU013の使用説明書/サービス説明書
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IMPORT ANT NOTICE T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify , before placing orders, that information being relied on is current and complete.
Information About Cautions and Warnings iii Read This First Preface Read This First About This Manual This user ’ s guide describes techniques for designing synchronous buck converters using TI’s SL VP1 1 1 1–1 14 evaluation modules (EVM) and TPS56xx ripple regulator controllers.
T rademarks iv Related Documentation From T exas Instruments Synchronous Buck Converter Design Using TPS56xx Controllers in SL VP10x EVMs User ’s Guide (literature number SL VU007).
Running Title—Attribute Reference v Chapter Title—Attribute Reference Contents 1 Introduction 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Synchronous Buck Regulator Operation 1-2 .
Running Title—Attribute Reference vi Figures 1–1 Simplified Synchronous Buck Converter Schematic 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Simplified Hysteretic Controlled Output V oltage W aveform 1-3 . . . . . . .
Running Title—Attribute Reference vii Contents 3–27 SL VP1 13 Measured Start-Up (V IN ) W aveforms 3-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–28 SL VP1 13 Measured Load T ransient Waveforms 3-20 . . . . . . . . .
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1-1 Introduction Introduction The SL VP1 1 1/1 12/1 13/1 14 evaluation modules (EVMs) have been designed and tested using the TPS56xx hysteretic controllers. These boards are synchronous dc-dc buck converters with fixed output voltages of 3.3 V , 2.5 V , 1.
Synchronous Buck Regulator Operation 1-2 1.1 Synchronous Buck Regulator Operation The synchronous buck converter is a variation of the traditional buck converter . The main switching device is usually a power MOSFET and is driven in the same manner as in a traditional buck converter .
Hysteretic Control Operation 1-3 Introduction 1.2 Hysteretic Control Operation Hysteretic control, also called bang-bang control or ripple regulator control, maintains the output voltage within the hysteresis band centered about the internal reference voltage.
Design Strategy 1-4 1.3 Design Strategy The SL VP1 1 1–1 14 evaluation modules (EVMs) are optimized for 5-V main input voltage and 6-A output current. The EVMs need an additional low current 12-V (30 mA max) input voltage for the controller . TI’s application report, Providing a DSP Power Solution from 5 V or 3.
Design Specification Summary 1-5 Introduction 1.4 Design Specification Summary This section summarizes the design requirements of the EVM converters. Although every attempt was made to accurately desc.
Design Specification Summary 1-6 T able 1–2. EVM Converter Operating Specifications (Continued) Specification Min Ty p Max Units Output ripple || SL VP1 1 1 (3.3 V) SL VP1 12 (2.5 V) SL VP1 13 (1.8 V) SL VP1 14 (1.5 V) 66 50 36 30 mV p–p mV p–p mV p–p mV p–p Efficiency , 6 A load SL VP1 1 1 (3.
Schematic 1-7 Introduction 1.5 Schematic Figure 1–3 shows the EVM converter schematic diagram. The schematic diagrams for the other EVM converters are identical except for the controller IC used.
Bill of Materials 1-8 1.6 Bill of Materials T able 1–3 lists materials required for the SL VP1 1 1–1 14 EVMs. T able 1–3. SL VP1 1 1–1 14 EVMs Bill of Materials Ref Des Part Number Description MFG C1 10TP A33M Capacitor , POSCAP , 33 µ F , 10 V , 20% Sanyo C2 6TPB150M Capacitor , POSCAP , 150 µ F , 6.
Bill of Materials 1-9 Introduction T able 1–3. SL VP1 1 1–1 14 EVMs Bill of Materials (Continued) Ref Des Part Number Description MFG R7 Std Resistor , Chip, 1 k Ω , 1/16W , 5% R8 Std Resistor ,.
Board Layout 1-10 1.7 Board Layout Figures 1–4 through 1–7 show the board layouts for the SL VP1 1 1–1 14 evaluation modules. Figure 1–4. T op Assembly T op Assembly Figure 1–5. Bottom Assembly (T op View) Bottom Assembly (T op V iew) Figure 1–6.
Board Layout 1-1 1 Introduction Figure 1–7. Bottom Layer (T op VIew) Bottom Layer (T op View).
1-12.
2-1 Design Procedure Design Procedure The SL VP1 1 1–1 14 are dc-dc synchronous buck converter evaluation modules (EVMs) that provide a regulated output voltage at up to 6 A with a power input voltage range of 4.5 V to 6 V . A low power 12-V , 20-mA source is also required to power the TPS56xx controller .
TPS56xx Functions 2-2 2.1 TPS56xx Functions The functional block diagram of the TPS56xx family of controllers is given in Figure 2–1. The controller has the following main features: ± 1% reference over 0 ° C to125 ° C junction temperature range.
TPS56xx Functions 2-3 Design Procedure Figure 2–1. TPS56xx Functional Block Diagram INHIBIT OCP SLOWST IOUT BIAS DRV BOOT HIGHDR BOOTLO LOWDR DRVGND HISENSE IOUTLO LOSENSE PWRGD ANAGND CC V VREFB AGND2 VSENSE VHYST LODRV LOHIB _ + 2 V 10 V UVLO V CC 22 3 8 25 4 6 1 1 1 0 15 7 28 20 21 19 1 9 14 16 17 18 13 12 _ + Deglitch 100mV VOVP 1.
TPS56xx Functions 2-4 2.1.2 Inhibit The inhibit circuit is a comparator with a 2.1-V start voltage and a 100-mV hysteresis. When inhibit is low , the output drivers are low and the slowstart capacitor is discharged. When inhibit is above the start threshold, the short across the slowstart capacitor is released and normal operation begins.
TPS56xx Functions 2-5 Design Procedure R VREFB + 3.3 V 165 m A + 20 k W This value is used to determine the values of R10 and R14 that set the hysteresis level.
TPS56xx Functions 2-6 Note that V del is independent of the output voltage. T o calculate V del for this example design, use the component measurements given in Section 2.2.4.2. They are repeated here for convenience: L = 1.5 µ H ESR = 10 m Ω T del = 400 ns Now calculate V del : V del + 5 1.
TPS56xx Functions 2-7 Design Procedure 2.1.5 Noise Suppression Hysteretic regulators, by nature, have a fast response time to V O transients and are thus inherently noise sensitive due to the very high bandwidth of the controller . Noise suppression circuits were added to the TPS56xx to improve the noise immunity , as shown in Figure 2–2.
TPS56xx Functions 2-8 Figure 1–3). This arrangement improves efficiency over solutions having a separate current sensing resistor . The drain of the high-side MOSFET is connected to HISENSE (pin 19). The source of the high-side MOSFET is connected to LOSENSE (pin 20).
TPS56xx Functions 2-9 Design Procedure resistor-divider network is designed so that the voltage applied to OCP is 100 mV for the desired output current limit point. If the voltage on OCP exceeds 100 mV , a fault latch is set and the output drivers are turned off.
TPS56xx Functions 2-10 An alternate current sensing scheme is to insert a current sense resistor in series with the drain of Q1. Higher accuracy may be obtained at the expense of lower efficiency . 2.1.7 Overvoltage Protection If V O exceeds V ref by 15%, a fault latch is set and the output gate drivers are turned off.
TPS56xx Functions 2-1 1 Design Procedure Figure 2–4. Gate Driver Block Diagram Level Shifter/ Predriver M1 45 Ω M2 5 Ω BOOT HIGHDR C4 BOOTLO Highside Driver Predriver M3 45 Ω M4 5 Ω LOWDR DR.
TPS56xx Functions 2-12 Figure 2–5. I–V Characteristic Curve for Low-Side Gate Drivers Driver Output V oltage – 1 V/div Driver Sink Current – 0.5 A/div The high-side gate driver is a bootstrap configuration with an internally integrated Schottky bootstrap diode.
TPS56xx Functions 2-13 Design Procedure LOHIB (pin 1 1) is an inhibit input for the low-side MOSFET driver . This input has to be logic low before the low-side MOSFET is allowed to be turned on, i.e., a logic high on LOHIB prevents the low-side MOSFET driver from turning on the low-side MOSFET .
External Component Selection 2-14 2.2 External Component Selection This section shows the procedure used in designing and selecting the power stage components to meet the performance parameters shown in T able 1–2 for the example circuit shown in Figure 1–3.
External Component Selection 2-15 Design Procedure performance in response to fast load transients encountered when supplying power to current- and next-generation microprocessors. A secondary consideration is the switching frequency resulting from the output filter component values.
External Component Selection 2-16 for the particular application. In addition, the capacitor(s) must have an ample ripple current rating to handle the applied ripple current. This ripple current is dependent on the ripple current in the output inductance that is calculated in the next section.
External Component Selection 2-17 Design Procedure V L + L I TRAN t å L v V L I TRAN t Where: V L = the voltage applied across the output inductor , I TRAN = the magnitude of the load step, and ∆ t = the desired response time.
External Component Selection 2-18 Figure 2–6. Output Ripple V oltage Detail (a) Current waveform through output capacitor (b) Voltage waveform across ideal capacitor with initial value at beginning .
External Component Selection 2-19 Design Procedure Peak to peak value of the inductor current ∆ I is given by the following equation: I + V I –I o ǒ R DS ( on ) ) R L Ǔ –V O L D Ts (1) Whe.
External Component Selection 2-20 of power losses and additional voltage drops through non-ideal components. Equation (4) should be sufficiently accurate for the first frequency estimate at the beginning of a design. 2.2.5 Power MOSFET Selection The TPS56xx is designed to drive N-channel power MOSFET s in a synchronous rectifier configuration.
3-1 T est Results T est Results This chapter shows the test setups used, and the test results obtained, in designing the SL VP1 1 1–1 14 EVMS. T opic Page 3.1 T est Summary 3–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T est Summary 3-2 3.1 T est Summary The detailed test results and waveforms are presented in Figures 3–2 to 3–10 for the SL VP1 1 1, Figures 3–1 1 to 3–19 for the SL VP1 12, Figures 3–20 to 3–28 for the SL VP1 13 and Figures 3–29 to 3–37 for the SL VP1 14.
T est Summary 3-3 T est Results in a linear fashion. There is no discernable overshoot in the waveforms. In this application, output voltage rise time is set to approximately 9 mS with an external capacitor .
T est Summary 3-4 3.1.8 Conclusion The test results of the SL VP1 1 1/1 12/1 13/1 14 EVMs demonstrate the advantages of TPS56xx controllers to meet stringent supply requirements to power supplies, especially for powering DSPs and microprocessors. The power system designer has a good solution to optimize system for his particular application.
T est Setup 3-5 T est Results 3.2 T est Setup Follow these steps for initial power up of the SL VP1 12: 1) Connect an electronic load from V out to PwrGND (J1-15, -16, -17, -18 to J1-1 1, -12, -13, -14) adjusted to draw approximately 1 A at 2.5 V . The exact current is not critical; any nominal current is sufficient.
T est Setup 3-6 Figure 3–1. T est Setup 5V Power Supply + – Load + – 12-V Power Supply + –.
T est Results 3-7 T est Results 3.3 T est Results Figures 3–2 to 3–102 show test results for the SL VP1 1 1. Figure 3–2. SL VP1 1 1 Measured Load Regulation 3.295 3.29 3.285 01 23 4 5 6 – V 3.3 SL VP1 1 1 MEASURED LOAD REGULA TION 3.305 V O I O – A Vin = 5.
T est Results 3-8 Figure 3–4. SL VP1 1 1Measured Power Dissipation 1.5 1 0.5 0 01 2 3 4 5 6 Ploss – W 2 SL VP1 1 1 MEASURED POWER DISSIP A TION 2.5 Vin = 4.5 V Vin = 5 V Vin = 5.5 V I O – A Figure 3–5. SL VP1 1 1Measured Switching Frequency Vin = 4.
T est Results 3-9 T est Results Figure 3–6. SL VP1 1 1 Measured Switching W aveforms C3 Pk–Pk 50.8 mV C3 Frequency 130.088 kHz Low Signal Amplitude C4 Max 5.20 V C4 + Duty 70.4% V DS Q2 2 V/div V O 20 mV/div 2.5 µ s/div Figure 3–7. SL VP1 1 1Measured Start-Up (INHIBIT) Waveforms C3 Pk–Pk 3.
T est Results 3-10 Figure 3–8. SL VP1 1 1 Measured Start-Up (V CC ) Waveforms C3 Pk–Pk 3.36 V C3 Rise 7.300 ms Low Signal Amplitude C3 + Over 2.5% V O 2 V/div V CC (12 V) 5 V/div UVLO Threshold 2.5 ms/div Figure 3–9. SL VP1 1 1Measured Start-Up (V IN ) Waveforms C3 Pk–Pk 3.
T est Results 3-1 1 T est Results Figure 3–10. SL VP1 1 1 Measured Load T ransient Waveforms C3 Pk–Pk 208 mV C2 High 6.5 V V O 100 mV/div 6.5 A I O 5 A/div 2.5 µ s/div Figure 3–1 1. SL VP1 12 Measured Load Regulation 2.5 2.495 01 2 3 4 5 6 2.505 SL VP1 12 MEASURED LOAD REGULA TION 2.
T est Results 3-12 Figure 3–12. SL VP1 12 Measured Efficiency SL VP1 1 1 MEASURED EFFICIENCY Vin = 5.5 V Vin = 4.5 V Vin = 5 V 84 82 80 78 12 3 4 5 6 Eficiency – % 86 88 90 I O – A Figure 3–13. SL VP1 12 Measured Power Dissipation 01 2 3 4 5 6 I O – A Vin = 5.
T est Results 3-13 T est Results Figure 3–14. SL VP1 12 Measured Switching Frequency 225 200 175 150 0 1 234 5 6 Frequency – kHz 250 275 SL VP1 12 MEASURED SWITCHING FREQUENCY 300 Vin = 5.5 V Vin = 4.5 V Vin = 5 V I O – A Figure 3–15. SL VP1 12 Measured Switching Waveforms C3 Pk–Pk 43.
T est Results 3-14 Figure 3–16. SL VP1 12 Measured Start-Up (INHIBIT) Waveforms C3 Pk–Pk 2.64 V C3 Rise 7.885 ms C3 + Over 3.2% V O 1 V/div INHIBIT 1 V/div 2.5 m s/div Figure 3–17. SL VP1 12 Measured Start-Up (V CC ) Waveforms C3 Pk–Pk 2.56 V C3 Rise 7.
T est Results 3-15 T est Results Figure 3–18. SL VP1 12 Measured Start-Up (V IN ) Waveforms C3 Pk–Pk 2.60 V C3 Rise 7.635 ms C3 + Over 3.2% V O 1 V/div V IN (5 V) 1 V/div 2.5 m s/div Figure 3–19. SL VP1 12 Measured Load T ransient W aveforms C3 Pk–Pk 200 mV C2 High 7.
T est Results 3-16 Figure 3–20. SL VP1 13 Measured Load Regulation Vin = 5.5 V Vin = 4.5 V Vin = 5 V 1.8 1.7975 1.795 01 2 3 4 5 6 1.8025 SL VP1 13 MEASURED LOAD REGULA TION 1.805 I O – A – V V O Figure 3–21. SL VP1 13 Measured Efficiency 80 78 76 72 1 2 345 6 Efficiency – % 82 86 SL VP1 13 MEASURED EFFICIENCY 88 84 74 I O – A Vin = 5.
T est Results 3-17 T est Results Figure 3–22. SL VP1 13 Measured Power Dissipation 01 2 3 4 5 6 I O – A Vin = 5.5 V Vin = 4.5 V Ploss – W SL VP1 13 MEASURED POWER DISSIP A TION Vin = 5 V 1.5 1 0.5 0 2 2.5 Figure 3–23. SL VP1 13 Measured Switching Frequency 01 23 4 56 Frequency – kHz SL VP1 13 MEASURED SWITCHING FREQUENCY Vin = 5.
T est Results 3-18 Figure 3–24. SL VP1 13 Measured Switching Waveforms C3 Pk–Pk 34.8 mV C3 Frequency 285.52 kHz Low Signal Amplitude C5 Max 5.80 V V O 20 mV/div V DS Q2 2 V/div C4 + Duty 40.4% 1 µ s/div Figure 3–25. SL VP1 13 Measured Start-Up (INHIBIT) Waveforms C3 Pk–Pk 1.
T est Results 3-19 T est Results Figure 3–26. SL VP1 13 Measured Start-Up (V CC ) Waveforms C3 Pk–Pk 1.84 V C3 Rise 7.195 ms Low Signal Amplitude C3 + Over 2.3% V O 2 V/div V CC (12 V) 5 V/div 2.5 m s/div Figure 3–27. SL VP1 13 Measured Start-Up (V IN ) Waveforms C3 Pk–Pk 1.
T est Results 3-20 Figure 3–28. SL VP1 13 Measured Load T ransient W aveforms C3 Pk–Pk 1 12 mV C2 High 3.64 V V O 100 mV/div I O 5 A/div 3.6 A 25 µ s/div Figure 3–29. SL VP1 14 Measured Load Regulation Vin = 5.5 V Vin = 4.5 V Vin = 5 V 1.496 1.
T est Results 3-21 T est Results Figure 3–30. SL VP1 14 Measured Efficiency Vin = 5.5 V Vin = 4.5 V I O – A Vin = 5 V 77 73 69 65 12 3 4 5 6 Efficiency – % 81 83 SL VP1 14 MEASURED EFFICIENCY 85 79 75 71 67 Figure 3–31. SL VP1 14 Measured Power Dissipation Vin = 5.
T est Results 3-22 Figure 3–32. SL VP1 14 Measured Switching Frequency Frequency – kHz Vin = 5.5 V Vin = 4.5 V Vin = 5 V I O – A 325 300 250 200 01 2 34 5 6 350 375 SL VP1 14 MEASURED SWITCHING FREQUENCY 400 275 225 Figure 3–33. SL VP1 14 Measured Switching Waveforms C3 Pk–Pk 30.
T est Results 3-23 T est Results Figure 3–34. SL VP1 14 Measured Start-Up (INHIBIT) Waveforms C3 Pk–Pk 1.56 V C3 Rise 6.990 ms Low Signal Amplitude C3 + Over 2.8% V O 1 V/div INHIBIT 1 V/div 2.5 m s/div Figure 3–35. SL VP1 14 Measured Start-Up (V CC ) Waveforms C3 Pk–Pk 1.
T est Results 3-24 Figure 3–36. SL VP1 14 Measured Start-Up (V IN ) Waveforms C3 Pk–Pk 1.56 V C3 Rise 7.07 ms Low Signal Amplitude C3 + Over 2.7% V O 1 V/div V IN (5 V) 1 V/div 2.5 m s/div Figure 3–37. SL VP1 14 Measured Load T ransient W aveforms C3 Pk–Pk 108 mV C2 High 3.
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