Texas InstrumentsメーカーTMS320C6747 DSPの使用説明書/サービス説明書
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TMS320C6747 DSP Universal Serial Bus (USB) OHCI Host Controller User's Guide Literature Number: SPRUFM8 September 2008.
2 SPRUFM8 – September 2008 Submit Documentation Feedback.
Contents Preface ........................................................................................................................................ 6 1 Introduction ................................................................................
www.ti.com List of Figures 1 Relationships Between Virtual Address Physical Address ............................................................ 11 2 OHCI Revision Number Register (HCREVISION) ..........................................................
www.ti.com List of Tables 1 USB Host Controller Registers ........................................................................................... 12 2 OHCI Revision Number Register (HCREVISION) Field Descriptions ..................................
Preface SPRUFM8 – September 2008 Read This First About This Manual This document describes the universal serial bus OHCI host controller. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h.
1 Introduction 1.1 Purpose of the Peripheral User's Guide SPRUFM8 – September 2008 Universal Serial Bus OHCI Host Controller This document describes the universal serial bus OHCI host controller. The USB OHCI host controller (HC) is a single port controller that communicates with USB devices at the USB low-speed (1.
2 Architecture 2.1 USB1 Module Clock and Reset 2.1.1 Internal System Bus Clocks Needed by the USB1 Module 2.1.2 USB1 Module Local Bus Clock and Local Reset 2.1.3 USB1 Module Bus 48-MHz Reference Clock Architecture www.ti.com The USB1 module requires that several different clocks are present before it can be accessed: 1.
2.2 USB1 Module Open Host Controller Interface Functionality 2.2.1 OHCI Controller Overview 2.3 USB1 Module Differences From OHCI Specification for USB 2.3.1 Power Switching Output Pins Not Supported 2.3.2 Overcurrent Protection Input Pins Not Supported 2.
2.4 Implementation of OHCI Specification for USB 2.4.1 USB Host Controller Endpoint Descriptor (ED) List Head Pointers 2.4.2 OHCI USB Suspend State Architecture www.ti.com The OHCI Specification for USB provides a specific sequence of operations for the host controller driver to perform when setting up the host controller.
2.5 OHCI Interrupts 2.6 USB Host Controller Access to System Memory 2.7 Physical Addressing Processor physical address Processor virtual address Processor MMU 00000000h FFFFFFFFh www.ti.com Architecture The USB1 host controller can be controlled either by the ARM or the DSP.
3 Registers Registers www.ti.com Most of the host controller (HC) registers are OHCI operational registers, defined by the OHCI Specification for USB . Four additional registers not specified by the OHCI Specification for USB provide additional information about the USB host controller state.
3.1 OHCI Revision Number Register (HCREVISION) 3.2 HC Operating Mode Register (HCCONTROL) www.ti.com Registers The OHCI revision number register (HCREVISION) is shown in Figure 2 and described in Table 2 .
Registers www.ti.com Table 3. HC Operating Mode Register (HCCONTROL) Field Descriptions Bit Field Value Description 31-11 Reserved 0 Reserved 10 RWE 0-1 Remote wake-up enable. 9 RWC 0-1 Remote wake-up connected. 8 IR 0 Interrupt routing. The USB host controller does not provide an SMI interrupt.
3.3 HC Command and Status Register (HCCOMMANDSTATUS) www.ti.com Registers The HC command and status register (HCCOMMANDSTATUS) shows the current state of the host controller and accepts commands from the host controller driver. HCCOMMANDSTATUS is shown in Figure 4 and described in Table 4 .
3.4 HC Interrupt and Status Register (HCINTERRUPTSTATUS) Registers www.ti.com The HC interrupt and status register (HCINTERRUPTSTATUS) reports the status of the USB host controller internal interrupt sources. HCINTERRUPTSTATUS is shown in Figure 5 and described in Table 5 .
3.5 HC Interrupt Enable Register (HCINTERRUPTENABLE) www.ti.com Registers The HC interrupt enable register (HCINTERRUPTENABLE) enables various OHCI interrupt sources to generate interrupts to the level 2 interrupt controller. HCINTERRUPTENABLE is shown in Figure 6 and described in Table 6 .
3.6 HC Interrupt Disable Register (HCINTERRUPTDISABLE) Registers www.ti.com The HC interrupt disable register (HCINTERRUPTDISABLE) is used to clear bits in the HC interrupt enable register (HCINTERRUPTENABLE). HCINTERRUPTDISABLE is shown in Figure 7 and described in Table 7 .
3.7 HC HCAA Address Register (HCHCCA) 3.8 HC Current Periodic Register (HCPERIODCURRENTED) www.ti.com Registers The HC HCAA address register (HCHCCA) defines the physical address of the beginning of the HCCA. HCHCCA is shown in Figure 8 and described in Table 8 .
3.9 HC Head Control Register (HCCONTROLHEADED) Registers www.ti.com The HC head control register (HCCONTROLHEADED) defines the physical address of the head endpoint descriptor (ED) on the control ED list. HCCONTROLHEADED is shown in Figure 10 and described in Table 10 .
3.10 HC Current Control Register (HCCONTROLCURRENTED) www.ti.com Registers The HC current control register (HCCONTROLCURRENTED) defines the physical address of the next endpoint descriptor (ED) on the control ED list. HCCONTROLCURRENTED is shown in Figure 11 and described in Table 11 .
3.11 HC Head Bulk Register (HCBULKHEADED) 3.12 HC Current Bulk Register (HCBULKCURRENTED) Registers www.ti.com The HC head bulk register (HCBULKHEADED) defines the physical address of the head endpoint descriptor (ED) on the bulk ED list. HCBULKHEADED is shown in Figure 12 and described in Table 12 .
3.13 HC Head Done Register (HCDONEHEAD) 3.14 HC Frame Interval Register (HCFMINTERVAL) www.ti.com Registers The HC head done register (HCDONEHEAD) defines the physical address of the current head of the done TD queue. HCDONEHEAD is shown in Figure 14 and described in Table 14 .
3.15 HC Frame Remaining Register (HCFMREMAINING) 3.16 HC Frame Number Register (HCFMNUMBER) Registers www.ti.com The HC frame remaining register (HCFMREMAINING) reports the number of full-speed bit times remaining in the current frame. HCFMREMAINING is shown in Figure 16 and described in Table 16 .
3.17 HC Periodic Start Register (HCPERIODICSTART) www.ti.com Registers The HC periodic start register (HCPERIODICSTART) defines the position within the USB frame where endpoint descriptors (EDs) on the periodic list have priority over EDs on the bulk and control lists.
3.18 HC Low-Speed Threshold Register (HCLSTHRESHOLD) Registers www.ti.com The HC low-speed threshold register (HCLSTHRESHOLD) defines the latest time in a frame that the USB host controller can begin a low-speed packet. HCLSTHRESHOLD is shown in Figure 19 and described in Table 19 .
3.19 HC Root Hub A Register (HCRHDESCRIPTORA) www.ti.com Registers The HC root hub A register (HCRHDESCRIPTORA) defines several aspects of the USB host controller root hub functionality. HCRHDESCRIPTORA is shown in Figure 20 and described in Table 20 .
3.20 HC Root Hub B Register (HCRHDESCRIPTORB) Registers www.ti.com The HC root hub B register (HCRHDESCRIPTORB) defines several aspects of the USB host controller root hub functionality. HCRHDESCRIPTORB is shown in Figure 21 and described in Table 21 .
3.21 HC Root Hub Status Register (HCRHSTATUS) www.ti.com Registers The HC root hub status register (HCRHSTATUS) reports the USB host controller root hub status.
3.22 HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Registers www.ti.com The HC port 1 status and control register (HCRHPORTSTATUS1) reports and controls the state of USB host port 1. HCRHPORTSTATUS1 is shown in Figure 23 and described in Table 23 .
www.ti.com Registers Table 23. HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Field Descriptions (continued) Bit Field Value Description 8 PPS/SPP Port 1 port power status/set port power. The host controller driver can write a 1 to this bit to set the port 1 port power status bit; a write of 0 has no effect.
3.23 HC Port 2 Status and Control Register (HCRHPORTSTATUS2) Registers www.ti.com The HC port 2 status and control register (HCRHPORTSTATUS2) reports and controls the state of USB host port 2. HCRHPORTSTATUS2 is shown in Figure 24 and described in Table 24 .
www.ti.com Registers Table 24. HC Port 2 Status and Control Register (HCRHPORTSTATUS2) Field Descriptions (continued) Bit Field Value Description 8 PPS/SPP Port 2 port power status/set port power. This bit indicates, when read as 1, that the port 2 power is enabled.
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