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TMS320C674x/OMAP-L1x Processor Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRUFL5B April 2011.
2 SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated.
Preface ...................................................................................................................................... 10 1 Introduction ..........................................................................................
www.ti.com (C0RXIMAX-C2RXIMAX) ............................................................................................. 68 3.13 EMAC Control Module Interrupt Core Transmit Interrupts Per Millisecond Registers (C0TXIMAX-C2TXIMAX) .................
www.ti.com 5.31 Emulation Control Register (EMCONTROL) ...................................................................... 114 5.32 FIFO Control Register (FIFOCONTROL) ......................................................................... 114 5.
www.ti.com List of Figures 1 EMAC and MDIO Block Diagram ........................................................................................ 13 2 Ethernet Configuration—MII Connections ...........................................................
www.ti.com 47 Transmit Interrupt Mask Set Register (TXINTMASKSET) ........................................................... 92 48 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ..................................................... 93 49 MAC Input Vector Register (MACINVECTOR) .
www.ti.com List of Tables 1 EMAC and MDIO Signals for MII Interface ............................................................................. 15 2 EMAC and MDIO Signals for RMII Interface ...........................................................
www.ti.com 46 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ..................................... 92 47 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions ............................... 93 48 MAC Input Vector Register (MACINVECTOR) Field Descriptions .
Preface SPRUFL5B – April 2011 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the device.
www.ti.com Related Documentation From Texas Instruments SPRUGM7 — OMAP-L138 Applications Processor System Reference Guide. Describes the System-on-Chip (SoC) including the ARM subsystem, DSP subsyst.
User's Guide SPRUFL5B – April 2011 EMAC/MDIO Module 1 Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the device.
DMA Master 8KCPPI RAM Interrupt Combiner C0 C1 C2 ControlModule EMAC Module MDIO Module EMAC Interrupts MDIO Interrupts Interrupts EMACSubSystem RegisterBus DMA Bus MII/RMIIBus MDIOBus www.
Architecture www.ti.com 1.4 Industry Standard(s) Compliance Statement The EMAC peripheral conforms to the IEEE 802.3 standard, describing the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications.
MII_TXCLK MII_TXD[3−0] MII_TXEN MII_COL MII_CRS MII_RXCLK MII_RXD[3−0] MII_RXDV MII_RXER MDIO_CLK MDIO_D Physical layer device (PHY) System core Transformer 2.5 MHz or 25 MHz RJ−45 EMAC MDIO www.ti.com Architecture The individual EMAC and MDIO signals for the MII interface are summarized in Table 1 .
RMII_TXD[1-0] RMII_TXEN RMII_MHZ_50_CLK RMII_RXD[1-0] RMII_CRS_DV RMII_RXER MDIO_CLK MDIO_D MDIO EMAC Physical Layer Device (PHY) T ransformer 50MHz RJ-45 Architecture www.ti.com Table 1. EMAC and MDIO Signals for MII Interface (continued) Signal Type Description MDIO_CLK O Management data clock (MDIO_CLK).
Preamble SFD Destination Source Len Data 7 1 6 6 2 46−1500 4 FCS Number of bytes Legend: SFD=Start Frame Delimeter; FCS=Frame Check Sequence (CRC) www.ti.com Architecture 2.4 Ethernet Protocol Overview A brief overview of the Ethernet protocol is given in the following subsections.
Architecture www.ti.com 2.4.2 Ethernet ’s Multiple Access Protocol Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel -- when an EMAC port transmits a frame, all the adapters on the local network receive the frame.
SOP | EOP 60 0 60 pBuffer pNext Packet A 60 bytes 0 SOP Fragment 1 Packet B 512 1514 pBuffer pNext 512 bytes EOP 0 0 −−− Packet B Fragment 3 500 bytes 502 pBuffer −−− 500 pNext −−− pBuffer pNext Packet B Fragment 2 502 bytes SOP | EOP 0 1514 bytes Packet C 1514 pBuffer pNext (NULL) 1514 www.
Architecture www.ti.com 2.5.2 Transmit and Receive Descriptor Queues The EMAC module processes descriptors in linked lists as discussed in Section 2.5.1 . The lists used by the EMAC are maintained by the application software through the use of the head descriptor pointer registers (HDP).
www.ti.com Architecture 2.5.3 Transmit and Receive EMAC Interrupts The EMAC processes descriptors in linked list chains as discussed in Section 2.5.1 , using the linked list queue mechanism discussed in Section 2.5.2 . The EMAC synchronizes descriptor list processing through the use of interrupts to the software application.
Architecture www.ti.com Figure 7. Transmit Buffer Descriptor Format Word 0 31 0 Next Descriptor Pointer Word 1 31 0 Buffer Pointer Word 2 31 16 15 0 Buffer Offset Buffer Length Word 3 31 30 29 28 27 26 25 16 SOP EOP OWNER EOQ TDOWNCMPLT PASSCRC Reserved 15 0 Packet Length Example 1.
www.ti.com Architecture 2.5.4.1 Next Descriptor Pointer The next descriptor pointer points to the 32-bit word aligned memory address of the next buffer descriptor in the transmit queue. This pointer is used to create a linked list of buffer descriptors.
Architecture www.ti.com 2.5.4.7 End of Packet (EOP) Flag When set, this flag indicates that the descriptor points to a packet buffer that is last for a given packet. In the case of a single fragment packet, both the start of packet (SOP) and EOP flags are set.
www.ti.com Architecture 2.5.5 Receive Buffer Descriptor Format A receive (RX) buffer descriptor ( Figure 8 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive buffer descriptor described by a C structure.
Architecture www.ti.com Example 2. Receive Buffer Descriptor in C Structure Format /* // EMAC Descriptor // // The following is the format of a single buffer descriptor // on the EMAC.
www.ti.com Architecture 2.5.5.4 Buffer Length This 16-bit field is used for two purposes: • Before the descriptor is first placed on the receive queue by the application software, the buffer length field is first initialized by the software to have the physical size of the empty data buffer pointed to by the buffer pointer field.
Architecture www.ti.com 2.5.5.11 Pass CRC (PASSCRC) Flag This flag is set by the EMAC in the SOP buffer descriptor if the received packet includes the 4-byte CRC. This flag should be cleared by the software application before submitting the descriptor to the receive queue.
Arbiter and bus switches CPU DMA Controllers 8K byte descriptor memory Configuration registers Interrupt logic Interrupts to CPU EMAC interrupts MDIO interrupts Configuration bus T ransmit and Receive www.
Architecture www.ti.com 2.6.3 Interrupt Control Interrupt conditions generated by the EMAC and MDIO modules are combined into four interrupt signals that are routed to three independent interrupt cores in the EMAC control module; the interrupt cores then relay the interrupt signals to the CPU interrupt controller.
EMAC control module Control registers and logic PHY monitoring Peripheral clock MDIO clock generator USERINT MDIO interface polling PHY MDCLK MDIO LINKINT Configuration bus www.
Architecture www.ti.com 2.7.2 MDIO Module Operational Overview The MDIO module implements the 802.3 serial management interface to interrogate and control an Ethernet PHY, using a shared two-wired bus. It separately performs autodetection and records the current link status of up to 32 PHYs, polling all 32 MDIO addresses.
www.ti.com Architecture 2.7.2.1 Initializing the MDIO Module The following steps are performed by the application software or device driver to initialize the MDIO device: 1. Configure the PREAMBLE and CLKDIV bits in the MDIO control register (CONTROL).
Architecture www.ti.com 2.7.2.4 Example of MDIO Register Access Code The MDIO module uses the MDIO user access register (USERACCESS n ) to access the PHY control registers.
Clock and reset logic Receive DMA engine Interrupt controller Transmit DMA engine Control registers Configuration bus EMAC control module Configuration bus RAM State FIFO Receive FIFO Transmit MAC transmitter Statistics receiver MAC SYNC MII address Receive RMII www.
Architecture www.ti.com 2.8.1.4 Transmit DMA Engine The transmit DMA engine is the interface between the transmit FIFO and the CPU. It interfaces to the CPU through the bus arbiter in the EMAC control module. 2.8.1.5 Transmit FIFO The transmit FIFO consists of three cells of 64-bytes each and associated control logic.
www.ti.com Architecture The EMAC module operates independently of the CPU. It is configured and controlled by its register set mapped into device memory. Information about data packets is communicated by use of 16-byte descriptors that are placed in an 8K-byte block of RAM in the EMAC control module (CPPI buffer descriptor memory).
Architecture www.ti.com In either case, receive flow control prevents frame reception by issuing the flow control appropriate for the current mode of operation. Receive flow control prevents reception of frames on the EMAC until all of the triggering conditions clear, at which time frames may again be received by the EMAC.
www.ti.com Architecture 2.9.2 Data Transmission The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to the transmit clock rate. Transmission begins when there are TXCELLTHRESH cells of 64 bytes each, or a complete packet, in the FIFO.
Architecture www.ti.com 2.9.2.6 Transmit Flow Control Incoming pause frames are acted upon, when enabled, to prevent the EMAC from transmitting any further frames. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in the MAC control register (MACCONTROL) are set.
www.ti.com Architecture 2.10 Packet Receive Operation 2.10.1 Receive DMA Host Configuration To configure the receive DMA for operation the host must: • Initialize the receive addresses. • Initialize the receive channel n DMA head descriptor pointer registers (RX n HDP) to 0.
Architecture www.ti.com 2.10.4 Hardware Receive QOS Support Hardware receive quality of service (QOS) is supported, when enabled, by the Tag Protocol Identifier format and the associated Tag Control Information (TCI) format priority field. When the incoming frame length/type value is equal to 81.
www.ti.com Architecture 2.10.7 Receive Frame Classification Received frames are proper (good) frames, if they are between 64 bytes and the value in the receive maximum length register (RXMAXLEN) bytes in length (inclusive) and contain no code, align, or CRC errors.
Architecture www.ti.com Table 5. Receive Frame Treatment Summary Address Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN Receive Frame Treatment 0 0 X X X No frames transferred. 0 1 0 0 0 Proper frames transferred to promiscuous channel. 0 1 0 0 1 Proper/undersized data frames transferred to promiscuous channel.
www.ti.com Architecture 2.10.9 Receive Overrun The types of receive overrun are: • FIFO start of frame overrun (FIFO_SOF) • FIFO middle of frame overrun (FIFO_MOF) • DMA start of frame overrun (.
Architecture www.ti.com 2.11 Packet Transmit Operation The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed or round-robin as selected by the TXPTYPE bit in the MAC control register (MACCONTROL).
www.ti.com Architecture 2.12 Receive and Transmit Latency The transmit and receive FIFOs each contain three 64-byte cells. The EMAC begins transmission of a packet on the wire after TXCELLTHRESH (configurable through the FIFO control register) cells, or a complete packet, are available in the FIFO.
Architecture www.ti.com 2.14 Reset Considerations 2.14.1 Software Reset Considerations Peripheral clock and reset control is done through the Power and Sleep Controller (PSC) module included with the device.
www.ti.com Architecture 2.15 Initialization 2.15.1 Enabling the EMAC/MDIO Peripheral When the device is powered on, the EMAC peripheral may be in a disabled state. Before any EMAC specific initialization can take place, the EMAC needs to be enabled; otherwise, its registers cannot be written and the reads will all return a value of zero.
Architecture www.ti.com 2.15.4 EMAC Module Initialization The EMAC module is used to send and receive data packets over the network. This is done by maintaining up to eight transmit and receive descriptor queues. The EMAC module configuration must also be kept up-to-date based on PHY negotiation results returned from the MDIO module.
www.ti.com Architecture 2.16 Interrupt Support 2.16.1 EMAC Module Interrupt Events and Requests The EMAC module generates 26 interrupt events: • TXPEND n : Transmit packet completion interrupt for t.
Architecture www.ti.com When the EMAC completes a packet reception, the EMAC issues an interrupt to the CPU by writing the packet's last buffer descriptor address to the appropriate channel queue's receive completion pointer located in the state RAM block.
www.ti.com Architecture The receive host error conditions are: • Ownership bit not set in input buffer • Zero buffer pointer The application software must acknowledge the EMAC control module after receiving host error interrupts by writing the appropriate C n MISC key to the EMAC End-Of-Interrupt Vector (MACEOIVECTOR).
Architecture www.ti.com 2.16.2.2 User Access Completion Interrupt When the GO bit in one of the MDIO register USERACCESS0 transitions from 1 to 0 (indicating completion of a user access) and the corre.
www.ti.com Architecture 2.17 Power Management Each of the three main components of the EMAC peripheral can independently be placed in reduced-power modes to conserve power during periods of low activity. The power management of the EMAC peripheral is controlled by the processor Power and Sleep Controller (PSC).
EMAC Control Module Registers www.ti.com 3 EMAC Control Module Registers Table 8 lists the memory-mapped registers for the EMAC control module. See your device-specific data manual for the memory address of these registers.
www.ti.com EMAC Control Module Registers Table 8. EMAC Control Module Registers (continued) Offset Acronym Register Description Section 70h C0RXIMAX EMAC Control Module Interrupt Core 0 Receive Interrupts Per Section 3.12 Millisecond Register 74h C0TXIMAX EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Section 3.
EMAC Control Module Registers www.ti.com 3.2 EMAC Control Module Software Reset Register (SOFTRESET) The EMAC Control Module Software Reset Register (SOFTRESET) is shown in Figure 13 and described in Table 10 .
www.ti.com EMAC Control Module Registers 3.3 EMAC Control Module Interrupt Control Register (INTCONTROL) The EMAC control module interrupt control register (INTCONTROL) is shown in Figure 14 and described in Table 11 . The settings in the INTCONTROL register are used in conjunction with the CnRXIMAX and CnTXIMAX registers.
EMAC Control Module Registers www.ti.com 3.4 EMAC Control Module Interrupt Core Receive Threshold Interrupt Enable Registers (C0RXTHRESHEN-C2RXTHRESHEN) The EMAC control module interrupt core 0-2 receive threshold interrupt enable register (C n RXTHRESHEN) is shown in Figure 15 and described in Table 12 .
www.ti.com EMAC Control Module Registers 3.5 EMAC Control Module Interrupt Core Receive Interrupt Enable Registers (C0RXEN-C2RXEN) The EMAC control module interrupt core 0-2 receive interrupt enable register (C n RXEN) is shown in Figure 16 and described in Table 13 Figure 16.
EMAC Control Module Registers www.ti.com 3.6 EMAC Control Module Interrupt Core Transmit Interrupt Enable Registers (C0TXEN-C2TXEN) The EMAC control module interrupt core 0-2 transmit interrupt enable register (C n TXEN) is shown in Figure 17 and described in Table 14 Figure 17.
www.ti.com EMAC Control Module Registers 3.7 EMAC Control Module Interrupt Core Miscellaneous Interrupt Enable Registers (C0MISCEN-C2MISCEN) The EMAC control module interrupt core 0-2 miscellaneous interrupt enable register (C n MISCEN) is shown in Figure 18 and described in Table 15 Figure 18.
EMAC Control Module Registers www.ti.com 3.8 EMAC Control Module Interrupt Core Receive Threshold Interrupt Status Registers (C0RXTHRESHSTAT-C2RXTHRESHSTAT) The EMAC control module interrupt core 0-2 receive threshold interrupt status register (C n RXTHRESHSTAT) is shown in Figure 19 and described in Table 16 Figure 19.
www.ti.com EMAC Control Module Registers 3.9 EMAC Control Module Interrupt Core Receive Interrupt Status Registers (C0RXSTAT-C2RXSTAT) The EMAC control module interrupt core 0-2 receive interrupt status register (C n RXSTAT) is shown in Figure 20 and described in Table 17 Figure 20.
EMAC Control Module Registers www.ti.com 3.10 EMAC Control Module Interrupt Core Transmit Interrupt Status Registers (C0TXSTAT-C2TXSTAT) The EMAC control module interrupt core 0-2 transmit interrupt status register (C n TXSTAT) is shown in Figure 21 and described in Table 18 Figure 21.
www.ti.com EMAC Control Module Registers 3.11 EMAC Control Module Interrupt Core Miscellaneous Interrupt Status Registers (C0MISCSTAT-C2MISCSTAT) The EMAC control module interrupt core 0-2 miscellaneous interrupt status register (C n MISCSTAT) is shown in Figure 22 and described in Table 19 Figure 22.
EMAC Control Module Registers www.ti.com 3.12 EMAC Control Module Interrupt Core Receive Interrupts Per Millisecond Registers (C0RXIMAX-C2RXIMAX) The EMAC control module interrupt core 0-2 receive interrupts per millisecond register (C n RXIMAX) is shown in Figure 23 and described in Table 20 Figure 23.
www.ti.com EMAC Control Module Registers 3.13 EMAC Control Module Interrupt Core Transmit Interrupts Per Millisecond Registers (C0TXIMAX-C2TXIMAX) The EMAC control module interrupt core 0-2 transmit interrupts per millisecond register (C n TXIMAX) is shown in Figure 24 and described in Table 21 Figure 24.
MDIO Registers www.ti.com 4 MDIO Registers Table 22 lists the memory-mapped registers for the MDIO module. See your device-specific data manual for the memory address of these registers. Table 22. Management Data Input/Output (MDIO) Registers Offset Acronym Register Description Section 0h REVID MDIO Revision ID Register Section 4.
www.ti.com MDIO Registers 4.2 MDIO Control Register (CONTROL) The MDIO control register (CONTROL) is shown in Figure 26 and described in Table 24 . Figure 26.
MDIO Registers www.ti.com 4.3 PHY Acknowledge Status Register (ALIVE) The PHY acknowledge status register (ALIVE) is shown in Figure 27 and described in Table 25 . Figure 27. PHY Acknowledge Status Register (ALIVE) 31 0 ALIVE R/W1C-0 LEGEND: R/W = Read/Write; W1C = Write 1 to clear (writing a 0 has no effect); - n = value after reset Table 25.
www.ti.com MDIO Registers 4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 29 and described in Table 27 .
MDIO Registers www.ti.com 4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 30 and described in Table 28 .
www.ti.com MDIO Registers 4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 31 and described in Table 29 .
MDIO Registers www.ti.com 4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in Figure 32 and described in Table 30 .
www.ti.com MDIO Registers 4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 33 and described in Table 31 .
MDIO Registers www.ti.com 4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 34 and described in Table 32 .
www.ti.com MDIO Registers 4.11 MDIO User Access Register 0 (USERACCESS0) The MDIO user access register 0 (USERACCESS0) is shown in Figure 35 and described in Table 33 .
MDIO Registers www.ti.com 4.12 MDIO User PHY Select Register 0 (USERPHYSEL0) The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 36 and described in Table 34 .
www.ti.com MDIO Registers 4.13 MDIO User Access Register 1 (USERACCESS1) The MDIO user access register 1 (USERACCESS1) is shown in Figure 37 and described in Table 35 .
MDIO Registers www.ti.com 4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 38 and described in Table 36 .
www.ti.com EMAC Module Registers 5 EMAC Module Registers Table 37 lists the memory-mapped registers for the EMAC. See your device-specific data manual for the memory address of these registers. Table 37. Ethernet Media Access Controller (EMAC) Registers Offset Acronym Register Description Section 0h TXREVID Transmit Revision ID Register Section 5.
EMAC Module Registers www.ti.com Table 37. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description Section 164h MACSTATUS MAC Status Register Section 5.30 168h EMCONTROL Emulation Control Register Section 5.31 16Ch FIFOCONTROL FIFO Control Register Section 5.
www.ti.com EMAC Module Registers Table 37. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description Section 67Ch RX7CP Receive Channel 7 Completion Pointer Register Section 5.49 Network Statistics Registers 200h RXGOODFRAMES Good Receive Frames Register Section 5.
EMAC Module Registers www.ti.com 5.1 Transmit Revision ID Register (TXREVID) The transmit revision ID register (TXREVID) is shown in Figure 39 and described in Table 38 . Figure 39. Transmit Revision ID Register (TXREVID) 31 0 TXREV R-4EC0 020Dh LEGEND: R = Read only; - n = value after reset Table 38.
www.ti.com EMAC Module Registers 5.3 Transmit Teardown Register (TXTEARDOWN) The transmit teardown register (TXTEARDOWN) is shown in Figure 41 and described in Table 40 .
EMAC Module Registers www.ti.com 5.4 Receive Revision ID Register (RXREVID) The receive revision ID register (RXREVID) is shown in Figure 42 and described in Table 41 . Figure 42. Receive Revision ID Register (RXREVID) 31 0 RXREV R-4EC0 020Dh LEGEND: R = Read only; - n = value after reset Table 41.
www.ti.com EMAC Module Registers 5.6 Receive Teardown Register (RXTEARDOWN) The receive teardown register (RXTEARDOWN) is shown in Figure 44 and described in Table 43 . Figure 44. Receive Teardown Register (RXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved RXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 43.
EMAC Module Registers www.ti.com 5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 45 and described in Table 44 .
www.ti.com EMAC Module Registers 5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in Figure 46 and described in Table 45 .
EMAC Module Registers www.ti.com 5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 47 and described in Table 46 .
www.ti.com EMAC Module Registers 5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure 48 and described in Table 47 .
EMAC Module Registers www.ti.com 5.11 MAC Input Vector Register (MACINVECTOR) The MAC input vector register (MACINVECTOR) is shown in Figure 49 and described in Table 48 .
www.ti.com EMAC Module Registers 5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR) The MAC end of interrupt vector register (MACEOIVECTOR) is shown in Figure 50 and described in Table 49 .
EMAC Module Registers www.ti.com 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in Figure 51 and described in Table 50 .
www.ti.com EMAC Module Registers 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in Figure 52 and described in Table 51 .
EMAC Module Registers www.ti.com 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 53 and described in Table 52 .
www.ti.com EMAC Module Registers 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 54 and described in Table 53 .
EMAC Module Registers www.ti.com 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 55 and described in Table 54 .
www.ti.com EMAC Module Registers 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 57 and described in Table 56 .
EMAC Module Registers www.ti.com 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 59 and described in Table 58 . Figure 59.
www.ti.com EMAC Module Registers Table 58. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field Value Description 22 RXCEFEN Receive copy error frames enable bit. Enables frames containing errors to be transferred to memory.
EMAC Module Registers www.ti.com Table 58. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field Value Description 2-0 RXMULTCH 0-7h Re.
www.ti.com EMAC Module Registers 5.22 Receive Unicast Enable Set Register (RXUNICASTSET) The receive unicast enable set register (RXUNICASTSET) is shown in Figure 60 and described in Table 59 .
EMAC Module Registers www.ti.com 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 61 and described in Table 60 .
www.ti.com EMAC Module Registers 5.24 Receive Maximum Length Register (RXMAXLEN) The receive maximum length register (RXMAXLEN) is shown in Figure 62 and described in Table 61 . Figure 62. Receive Maximum Length Register (RXMAXLEN) 31 16 Reserved R-0 15 0 RXMAXLEN R/W-5EEh LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 61.
EMAC Module Registers www.ti.com 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 64 and described in Table 63 .
www.ti.com EMAC Module Registers 5.28 Receive Channel Free Buffer Count Registers (RX0FREEBUFFER-RX7FREEBUFFER) The receive channel 0-7 free buffer count register (RX n FREEBUFFER) is shown in Figure 66 and described in Table 65 .
EMAC Module Registers www.ti.com 5.29 MAC Control Register (MACCONTROL) The MAC control register (MACCONTROL) is shown in Figure 67 and described in Table 66 .
www.ti.com EMAC Module Registers Table 66. MAC Control Register (MACCONTROL) Field Descriptions (continued) Bit Field Value Description 4 TXFLOWEN Transmit flow control enable bit. This bit determines if incoming pause frames are acted upon in full-duplex mode.
EMAC Module Registers www.ti.com 5.30 MAC Status Register (MACSTATUS) The MAC status register (MACSTATUS) is shown in Figure 68 and described in Table 67 .
www.ti.com EMAC Module Registers Table 67. MAC Status Register (MACSTATUS) Field Descriptions (continued) Bit Field Value Description 15-12 RXERRCODE 0-Fh Receive host error code. These bits indicate that EMAC detected receive DMA related host errors.
EMAC Module Registers www.ti.com 5.31 Emulation Control Register (EMCONTROL) The emulation control register (EMCONTROL) is shown in Figure 69 and described in Table 68 .
www.ti.com EMAC Module Registers 5.33 MAC Configuration Register (MACCONFIG) The MAC configuration register (MACCONFIG) is shown in Figure 71 and described in Table 70 .
EMAC Module Registers www.ti.com 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 73 and described in Table 72 .
www.ti.com EMAC Module Registers 5.37 MAC Hash Address Register 1 (MACHASH1) The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address.
EMAC Module Registers www.ti.com 5.39 Back Off Test Register (BOFFTEST) The back off test register (BOFFTEST) is shown in Figure 77 and described in Table 76 .
www.ti.com EMAC Module Registers 5.41 Receive Pause Timer Register (RXPAUSE) The receive pause timer register (RXPAUSE) is shown in Figure 79 and described in Table 78 . Figure 79. Receive Pause Timer Register (RXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; - n = value after reset Table 78.
EMAC Module Registers www.ti.com 5.43 MAC Address Low Bytes Register (MACADDRLO) The MAC address low bytes register used in address matching (MACADDRLO), is shown in Figure 81 and described in Table 80 .
www.ti.com EMAC Module Registers 5.44 MAC Address High Bytes Register (MACADDRHI) The MAC address high bytes register (MACADDRHI) is shown in Figure 82 and described in Table 81 .
EMAC Module Registers www.ti.com 5.46 Transmit Channel DMA Head Descriptor Pointer Registers (TX0HDP-TX7HDP) The transmit channel 0-7 DMA head descriptor pointer register (TX n HDP) is shown in Figure 84 and described in Table 83 .
www.ti.com EMAC Module Registers 5.48 Transmit Channel Completion Pointer Registers (TX0CP-TX7CP) The transmit channel 0-7 completion pointer register (TX n CP) is shown in Figure 86 and described in Table 85 .
EMAC Module Registers www.ti.com 5.50 Network Statistics Registers The EMAC has a set of statistics that record events associated with frame traffic. The statistics values are cleared to zero 38 clocks after the rising edge of reset.
www.ti.com EMAC Module Registers 5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES) The total number of IEEE 802.3X pause frames received by the EMAC (whether acted upon or not). A pause frame is defined as having all of the following: • Contained any unicast, broadcast, or multicast address • Contained the length/type field value 88.
EMAC Module Registers www.ti.com 5.50.7 Receive Oversized Frames Register (RXOVERSIZED) The total number of oversized frames received on the EMAC. An oversized frame is defined as having all of the fo.
www.ti.com EMAC Module Registers To determine the number of receive frames discarded by the EMAC for any reason, sum the following statistics (promiscuous mode disabled): • Receive fragments • Rec.
EMAC Module Registers www.ti.com 5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES) The total number of good broadcast frames transmitted on the EMAC.
www.ti.com EMAC Module Registers 5.50.20 Transmit Single Collision Frames Register (TXSINGLECOLL) The total number of frames transmitted on the EMAC that experienced exactly one collision.
EMAC Module Registers www.ti.com 5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) The total number of frames on the EMAC that experienced carrier loss.
www.ti.com EMAC Module Registers 5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511) The total number of 256-byte to 511-byte frames received and transmitted on the EMAC.
EMAC Module Registers www.ti.com 5.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS) The total number of frames received on the EMAC that had either a FIFO or DMA start of frame (SOF) overrun.
www.ti.com Appendix A Glossary Broadcast MAC Address— A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the first byte is odd, qualifying it as a group address; however, its value is reserved for broadcast.
Appendix A www.ti.com Multicast MAC Address— A class of MAC address that sends a packet to potentially more than one recipient. A group address is specified by setting the LSB of the first MAC address byte to 1. Thus, 01h-02h-03h-04h-05h-06h is a valid multicast address.
www.ti.com Appendix B Revision History Table 88 lists the changes made since the previous version of this document. Table 88. Document Revision History Reference Additions/Modifications/Deletions Figure 2 Changed figure. Section 2.5.2 Changed first paragraph.
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