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TMS320DM36x Digital Media System-on-Chip (DMSoC) Ethernet Media Access Controller (EMAC) User's Guide Literature Number: SPRUFI5B March 2009 – Revised December 2010.
2 SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback © 2009–2010, Texas Instruments Incorporated.
Preface ...................................................................................................................................... 10 1 Introduction ..........................................................................................
www.ti.com 4.1 MDIO Version Register (VERSION) ................................................................................. 70 4.2 MDIO Control Register (CONTROL) ................................................................................ 71 4.
www.ti.com 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) .............................................. 115 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) .............................................. 115 5.37 MAC Hash Address Register 1 (MACHASH1) .
www.ti.com List of Figures 1 EMAC and MDIO Block Diagram ........................................................................................ 14 2 Ethernet Configuration MII Connections .............................................................
www.ti.com 48 Transmit Interrupt Mask Set Register (TXINTMASKSET) ........................................................... 92 49 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ..................................................... 93 50 MAC Input Vector Register (MACINVECTOR) .
www.ti.com List of Tables 1 EMAC and MDIO Signals for MII Interface ............................................................................. 17 2 Ethernet Frame Description .........................................................................
www.ti.com 46 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ..................................... 92 47 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions ............................... 93 48 MAC Input Vector Register (MACINVECTOR) Field Descriptions .
Preface SPRUFI5B – March 2009 – Revised December 2010 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the TMS320DM36x Digital Media System-on-Chip (DMSoC).
www.ti.com Related Documentation From Texas Instruments SPRUFH2 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Asynchronous Receiver/Transmitter (UART) Users Guide This document describes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC).
Related Documentation From Texas Instruments www.ti.com SPRUFI5 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Ethernet Media Access Controller (EMAC) User's Guide This document describes the operation of the ethernet media access controller interface in the TMS320DM36x Digital Media System-on-Chip (DMSoC).
User's Guide SPRUFI5B – March 2009 – Revised December 2010 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 1 Introduction This document provides a functional descr.
Configurationbus DMA memory transfercontroller Peripheralbus EMACcontrolmodule EMACmodule MDIOmodule MIIbus MDIObus EMAC/MDIO interrupts ARMinterrupt controller 4 Introduction www.ti.com • Emulation support • Loopback mode 1.
www.ti.com Architecture The EMAC and MDIO interrupts are combined within the control module, so only the control module interrupt needs to be monitored by the application software or device driver. The EMAC control module combines the EMAC and MDIO interrupts and generates 4 separate interrupts to the ARM through the ARM interrupt controller.
EMAC_TX_CLK EMAC_TXD(3-0) EMAC_TX_EN EMAC_COL EMAC_CRS EMAC_RX_CLK EMAC_RXD(3-0) EMAC_RX_DV MRXER MDCLK MDIO Physical layer device (PHY) System core T ransformer 2.
www.ti.com Architecture Table 1. EMAC and MDIO Signals for MII Interface Signal Type Description EMAC_TX_CLK I Transmit clock (EMAC_TX_CLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations. The EMAC_TXD and EMAC_TX_EN signals are tied to this clock.
Preamble SFD Destination Source Len Data 7 1 6 6 2 46−1500 4 FCS Number of bytes Legend: SFD=Start Frame Delimeter; FCS=Frame Check Sequence (CRC) Architecture www.ti.com 2.5 Ethernet Protocol Overview Ethernet provides an unreliable, connection-less service to a networking application.
www.ti.com Architecture 2.5.2 Ethernet ’s Multiple Access Protocol Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel, as a result, when an EMAC port transmits a frame, all the adapters on the local network receive the frame.
SOP | EOP 60 0 60 pBuf fer pNext Packet A 60 bytes 0 SOP Fragment 1 Packet B 512 1514 pBuf fer pNext 512 bytes EOP 0 0 −−− Packet B Fragment 3 500 bytes 502 pBuf fer −−− 500 pNext −−− pBuf fer pNext Packet B Fragment 2 502 bytes SOP | EOP 0 1514 bytes Packet C 1514 pBuf fer pNext (NULL) 1514 Architecture www.
www.ti.com Architecture 2.6.2 Transmit and Receive Descriptor Queues The EMAC module processes descriptors in linked list chains as discussed in Section 2.6.1 . The lists controlled by the EMAC are maintained by the application software through the use of the head descriptor pointer registers (HDP).
Architecture www.ti.com 2.6.3 Transmit and Receive EMAC Interrupts The EMAC processes descriptors in linked list chains as discussed in Section 2.6.1 , using the linked list queue mechanism discussed in Section 2.6.2 . The EMAC synchronizes descriptor list processing through the use of interrupts to the software application.
www.ti.com Architecture 2.6.4 Transmit Buffer Descriptor Format A transmit (TX) buffer descriptor ( Figure 6 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer descriptor described by a C structure.
Architecture www.ti.com 2.6.4.1 Next Descriptor Pointer The next descriptor pointer points to the 32-bit word aligned memory address of the next buffer descriptor in the transmit queue. This pointer is used to create a linked list of buffer descriptors.
www.ti.com Architecture 2.6.4.7 End of Packet (EOP) Flag When set, this flag indicates that the descriptor points to a packet buffer that is last for a given packet. In the case of a single fragment packet, both the start of packet (SOP) and EOP flags are set.
Architecture www.ti.com 2.6.5 Receive Buffer Descriptor Format A receive (RX) buffer descriptor ( Figure 7 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive buffer descriptor described by a C structure.
www.ti.com Architecture Example 2. Receive Buffer Descriptor in C Structure Format /* // EMAC Descriptor // // The following is the format of a single buffer descriptor // on the EMAC.
Architecture www.ti.com 2.6.5.4 Buffer Length This 16-bit field is used for two purposes: • Before the descriptor is first placed on the receive queue by the application software, the buffer length field is first initialized by the software to have the physical size of the empty data buffer pointed to by the buffer pointer field.
www.ti.com Architecture 2.6.5.11 Pass CRC (PASSCRC) Flag This flag is set by the EMAC in the SOP buffer descriptor if the received packet includes the 4-byte CRC. This flag should be cleared by the software application before submitting the descriptor to the receive queue.
Arbiter and bus switches CPU DMA Controllers 8K byte descriptor memory Configuration registers Interrupt control and pacing logic EMAC interrupts MDIO interrupts Configuration bus T ransmit and Receive 4 interrupts to ARM Architecture www.
www.ti.com Architecture 2.7.3 Interrupt Control The EMAC control module combines multiple interrupt conditions generated by the EMAC and MDIO modules into four separate interrupt signals that are mapped to a CPU interrupt via the CPU interrupt controller.
Architecture www.ti.com 2.7.3.3 Receive Threshold Pulse Interrupt The EMAC control module receives the eight individual receive threshold interrupts originating from the EMAC module, one for each of the eight channels, and combines them into a single receive threshold pulse interrupt to the CPU.
EMAC control module Control registers and logic PHY monitoring Peripheral clock MDIO clock generator USERINT MDIO interface polling PHY MDCLK MDIO LINKINT Configuration bus www.ti.com Architecture 2.8 MDIO Module The MDIO module is used to manage up to 32 physical layer (PHY) devices connected to the Ethernet Media Access Controller (EMAC).
Architecture www.ti.com 2.8.1.3 Active PHY Monitoring Once a PHY candidate has been selected for use, the MDIO module transparently monitors its link state by reading the MDIO PHY link status register (LINK). Link change events are stored on the MDIO device and can optionally interrupt the CPU.
www.ti.com Architecture 2.8.2.1 Initializing the MDIO Module The following steps are performed by the application software or device driver to initialize the MDIO device: 1. Configure the PREAMBLE and CLKDIV bits in the MDIO control register (CONTROL).
Architecture www.ti.com 2.8.2.4 Example of MDIO Register Access Code The MDIO module uses the MDIO user access register (USERACCESS n ) to access the PHY control registers.
Clock and reset logic Receive DMA engine Interrupt controller Transmit DMA engine Control registers Configuration bus EMAC control module Configuration bus RAM State FIFO Receive FIFO Transmit MAC transmitter Statistics receiver MAC SYNC www.ti.com Architecture 2.
Architecture www.ti.com 2.9.1.3 MAC Receiver The MAC receiver detects and processes incoming network frames, de-frames them, and puts them into the receive FIFO.
www.ti.com Architecture 2.9.2 EMAC Module Operational Overview After reset, initialization, and configuration, the application software running on the host may initiate transmit operations. Transmit operations are initiated by host writes to the appropriate transmit channel head descriptor pointer contained in the state RAM block.
Architecture www.ti.com 2.10 Media Independent Interface (MII) The following sections discuss the operation of the Media Independent Interface (MII) in 10 Mbps and 100 Mbps mode. An IEEE 802.3 compliant Ethernet MAC controls the interface. 2.10.1 Data Reception 2.
www.ti.com Architecture 2.10.1.3.1 Collision-Based Receive Buffer Flow Control Collision-based receive buffer flow control provides a means of preventing frame reception when the EMAC is operating in half-duplex mode (the FULLDUPLEX bit is cleared in MACCONTROL).
Architecture www.ti.com 2.10.2 Data Transmission The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to the transmit clock rate. Transmission begins when there are TXCELLTHRESH cells of 64 bytes each, or a complete packet, in the FIFO.
www.ti.com Architecture 2.10.2.6 Transmit Flow Control Incoming pause frames are acted upon, when enabled, to prevent the EMAC from transmitting any further frames. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in the MAC control register (MACCONTROL) are set.
Architecture www.ti.com 2.11 Packet Receive Operation 2.11.1 Receive DMA Host Configuration To configure the receive DMA for operation the host must: • Initialize the receive addresses. • Initialize the receive channel n DMA head descriptor pointer registers (RX n HDP) to 0.
www.ti.com Architecture 2.11.3 Receive Address Matching The receive address block can store up to 32 addresses to be filtered or matched. Before enabling packet reception, all the address RAM locations should be initialized, including locations to be unused.
Architecture www.ti.com 2.11.5 Host Free Buffer Tracking The host must track free buffers for each enabled channel (including unicast, multicast, broadcast, and promiscuous), if receive QOS or receive flow control is used. Disabled channel free buffer values are do not cares.
www.ti.com Architecture • If the frame length is 1522, there are 1518 bytes transferred to memory. The last byte is the last data byte. 2.11.8 Promiscuous Receive Mode When the promiscuous receive m.
Architecture www.ti.com Table 4. Receive Frame Treatment Summary (continued) Address Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN Receive Frame Treatment 1 X 1 1 0 Proper/oversize/jabber/code/align/CRC data and control frames transferred to address match channel.
www.ti.com Architecture 2.12 Packet Transmit Operation The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed or round-robin as selected by the TXPTYPE bit in the MAC control register (MACCONTROL).
Architecture www.ti.com Receive overrun is prevented if the receive memory cell latency is less than the time required to transmit a 64-byte cell on the wire (0.512 ms in 1 Gbps mode, 5.12 ms in 100 Mbps mode, or 51.2ms in 10 Mbps mode). The latency time includes any required buffer descriptor reads for the cell data.
www.ti.com Architecture 2.15.2 Hardware Reset Considerations When a hardware reset occurs, the EMAC peripheral has its register values reset and all the components return to their default state. After the hardware reset, the EMAC needs to be initialized before being able to resume its data transmission, as described in Section 2.
Architecture www.ti.com Example 4. EMAC Control Module Initialization Code Uint32 tmpval ; /* Disable all the EMAC/MDIO interrupts in the control module */ EmacControlRegs->CONTROL.C_RX_EN = 0; EmacControlRegs->CONTROL.C_TX_EN = 0; EmacControlRegs->CONTROL.
www.ti.com Architecture 2.16.3 MDIO Module Initialization The MDIO module is used to initially configure and monitor one or more external PHY devices. Other than initializing the software state machine (details on this state machine can be found in the IEEE 802.
Architecture www.ti.com 2.16.4 EMAC Module Initialization The EMAC module is used to send and receive data packets over the network. This is done by maintaining up to eight transmit and receive descriptor queues. The EMAC module configuration must also be kept up-to-date based on PHY negotiation results returned from the MDIO module.
EMACcore MDIOcore RXTHRESHOLDPEND(0..7) Receivethresholdinterrupt RXPEND(0..7) Receiveinterrupt TXPEND(0..7) T ransmitinterrupt ST A TPEND HOSTPEND MDIO_USER Miscellaneousinterrupt MDIO_LINKINT Interruptcontrolandpacinglogic www.
Architecture www.ti.com Each of the eight transmit channel interrupts may be individually enabled by setting the corresponding bit in the transmit interrupt mask set register (TXINTMASKSET) to 1.
www.ti.com Architecture 2.17.1.4 Statistics Interrupt The statistics level interrupt (STATPEND) is issued when any statistics value is greater than or equal to 8000 0000h, if enabled by setting the STATMASK bit in the MAC interrupt mask set register (MACINTMASKSET) to 1.
Architecture www.ti.com 2.17.2 MDIO Module Interrupt Events and Requests The MDIO module generates two interrupt events: • LINKINT: Serial interface link change interrupt. Indicates a change in the state of the PHY link • USERINT: Serial interface user command event complete interrupt 2.
www.ti.com Architecture 2.18 Power Management Each of the three main components of the EMAC peripheral can independently be placed in reduced-power modes to conserve power during periods of low activity. The power management of the EMAC peripheral is controlled by the processor Power and Sleep Controller (PSC).
EMAC Control Module Registers www.ti.com 3 EMAC Control Module Registers Table 7 lists the memory-mapped registers for the EMAC control module. See the device-specific data manual for the memory address of these registers.
www.ti.com EMAC Control Module Registers 3.2 EMAC Control Module Software Reset Register (CMSOFTRESET) The software reset register (CMSOFTRESET) is shown in Figure 13 and described in Table 9 .
EMAC Control Module Registers www.ti.com 3.4 EMAC Control Module Interrupt Control Register (CMINTCTRL) The interrupt control register (CMINTCTRL) is shown in Figure 15 and described in Table 11 .
www.ti.com EMAC Control Module Registers 3.5 EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN) The receive threshold interrupt enable register (CMRXTHRESHINTEN) is shown in Figure 16 and described in Table 12 . Figure 16.
EMAC Control Module Registers www.ti.com 3.7 EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) The transmit interrupt enable register (CMTXINTEN) is shown in Figure 18 and described in Table 14 .
www.ti.com EMAC Control Module Registers 3.8 EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) The miscellaneous interrupt enable register (CMMISCINTEN) is shown in Figure 19 and described in Table 15 .
EMAC Control Module Registers www.ti.com 3.9 EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT) The receive threshold interrupt status register (CMRXTHRESHINTSTAT) is shown in Figure 20 and described in Table 16 . Figure 20.
www.ti.com EMAC Control Module Registers 3.11 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) The transmit interrupt status register (CMTXINTSTAT) is shown in Figure 22 and described in Table 18 .
EMAC Control Module Registers www.ti.com 3.12 EMAC Control Module Miscellaneous Interrupt Status Register (EWMISCSTAT) The miscellaneous interrupt status register (EWMISCSTAT) is shown in Figure 23 and described in Table 19 .
www.ti.com EMAC Control Module Registers 3.13 EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX) The receive interrupts per millisecond register (CMRXINTMAX) is shown in Figure 24 and described in Table 20 .
MDIO Registers www.ti.com 4 MDIO Registers Table 22 lists the memory-mapped registers for the MDIO module. See the device-specific data manual for the memory address of these registers. Table 22. Management Data Input/Output (MDIO) Registers Offset Acronym Register Description Section 0h VERSION MDIO Version Register Section 4.
www.ti.com MDIO Registers 4.2 MDIO Control Register (CONTROL) The MDIO control register (CONTROL) is shown in Figure 27 and described in Table 24 . Figure 27.
MDIO Registers www.ti.com 4.3 PHY Acknowledge Status Register (ALIVE) The PHY acknowledge status register (ALIVE) is shown in Figure 28 and described in Table 25 .
www.ti.com MDIO Registers 4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 30 and described in Table 27 .
MDIO Registers www.ti.com 4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 31 and described in Table 28 .
www.ti.com MDIO Registers 4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 32 and described in Table 29 .
MDIO Registers www.ti.com 4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in Figure 33 and described in Table 30 .
www.ti.com MDIO Registers 4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 34 and described in Table 31 .
MDIO Registers www.ti.com 4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 35 and described in Table 32 .
www.ti.com MDIO Registers 4.11 MDIO User Access Register 0 (USERACCESS0) The MDIO user access register 0 (USERACCESS0) is shown in Figure 36 and described in Table 33 .
MDIO Registers www.ti.com 4.12 MDIO User PHY Select Register 0 (USERPHYSEL0) The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 37 and described in Table 34 .
www.ti.com MDIO Registers 4.13 MDIO User Access Register 1 (USERACCESS1) The MDIO user access register 1 (USERACCESS1) is shown in Figure 38 and described in Table 35 .
MDIO Registers www.ti.com 4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 39 and described in Table 36 .
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5 Ethernet Media Access Controller (EMAC) Registers Table 37 lists the memory-mapped registers for the EMAC. See the device-specific data manual for the memory address of these registers. Table 37.
Ethernet Media Access Controller (EMAC) Registers www.ti.com Table 37. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description Section 164h MACSTATUS MAC Status Register Section 5.30 168h EMCONTROL Emulation Control Register Section 5.
www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 37. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description Section 67Ch RX7CP Receive Channel 7 Completion Pointer Register Section 5.49 Network Statistics Registers 200h RXGOODFRAMES Good Receive Frames Register Section 5.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.1 Transmit Identification and Version Register (TXIDVER) The transmit identification and version register (TXIDVER) is shown in Figure 40 and described in Table 38 .
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.3 Transmit Teardown Register (TXTEARDOWN) The transmit teardown register (TXTEARDOWN) is shown in Figure 42 and described in Table 40 .
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.4 Receive Identification and Version Register (RXIDVER) The receive identification and version register (RXIDVER) is shown in Figure 43 and described in Table 41 .
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.5 Receive Control Register (RXCONTROL) The receive control register (RXCONTROL) is shown in Figure 44 and described in Table 42 .
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 46 and described in Table 44 . Figure 46.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in Figure 47 and described in Table 45 . Figure 47.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 48 and described in Table 46 .
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure 49 and described in Table 47 .
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.11 MAC Input Vector Register (MACINVECTOR) The MAC input vector register (MACINVECTOR) is shown in Figure 50 and described in Table 48 .
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in Figure 52 and described in Table 50 .
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in Figure 53 and described in Table 51 . Figure 53.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 54 and described in Table 52 .
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 55 and described in Table 53 .
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 56 and described in Table 54 .
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 58 and described in Table 56 .
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 60 and described in Table 58 .
Ethernet Media Access Controller (EMAC) Registers www.ti.com Table 58. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field Value Description 22 RXCEFEN Receive copy error frames enable bit.
www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 58. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field Value Desc.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.22 Receive Unicast Enable Set Register (RXUNICASTSET) The receive unicast enable set register (RXUNICASTSET) is shown in Figure 61 and described in Table 59 .
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 62 and described in Table 60 .
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.24 Receive Maximum Length Register (RXMAXLEN) The receive maximum length register (RXMAXLEN) is shown in Figure 63 and described in Table 61 .
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 65 and described in Table 63 .
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.28 Receive Channel 0-7 Free Buffer Count Register (RX n FREEBUFFER) The receive channel 0-7 free buffer count register (RX n FREEBUFFER) is shown in Figure 67 and described in Table 65 . Figure 67.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.29 MAC Control Register (MACCONTROL) The MAC control register (MACCONTROL) is shown in Figure 68 and described in Table 66 .
Ethernet Media Access Controller (EMAC) Registers www.ti.com Table 66. MAC Control Register (MACCONTROL) Field Descriptions (continued) Bit Field Value Description 4 TXFLOWEN Transmit flow control enable bit. This bit determines if incoming pause frames are acted upon in full-duplex mode.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.30 MAC Status Register (MACSTATUS) The MAC status register (MACSTATUS) is shown in Figure 69 and described in Table 67 .
Ethernet Media Access Controller (EMAC) Registers www.ti.com Table 67. MAC Status Register (MACSTATUS) Field Descriptions (continued) Bit Field Value Description 10-8 RXERRCH 0-3h Receive host error channel. These bits indicate which receive channel the host error occurred on.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.31 Emulation Control Register (EMCONTROL) The emulation control register (EMCONTROL) is shown in Figure 70 and described in Table 68 .
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.33 MAC Configuration Register (MACCONFIG) The MAC configuration register (MACCONFIG) is shown in Figure 72 and described in Table 70 .
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 74 and described in Table 72 .
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.37 MAC Hash Address Register 1 (MACHASH1) The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.39 Back Off Test Register (BOFFTEST) The back off test register (BOFFTEST) is shown in Figure 78 and described in Table 76 .
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.41 Receive Pause Timer Register (RXPAUSE) The receive pause timer register (RXPAUSE) is shown in Figure 80 and described in Table 78 . Figure 80. Receive Pause Timer Register (RXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; - n = value after reset Table 78.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.43 MAC Address Low Bytes Register (MACADDRLO) The MAC address low bytes register used in address matching (MACADDRLO), is shown in Figure 82 and described in Table 80 .
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.44 MAC Address High Bytes Register (MACADDRHI) The MAC address high bytes register (MACADDRHI) is shown in Figure 83 and described in Table 81 .
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TX n HDP) The transmit channel 0-7 DMA head descriptor pointer register (TX n HDP) is shown in Figure 85 and described in Table 83 .
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.48 Transmit Channel 0-7 Completion Pointer Register (TX n CP) The transmit channel 0-7 completion pointer register (TX n CP) is shown in Figure 87 and described in Table 85 .
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.50 Network Statistics Registers The EMAC has a set of statistics that record events associated with frame traffic. The statistics values are cleared to zero 38 clocks after the rising edge of reset.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES) The total number of IEEE 802.3X pause frames received by the EMAC (whether acted upon or not).
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.50.8 Receive Jabber Frames Register (RXJABBER) The total number of jabber frames received on the EMAC.
Ethernet Media Access Controller (EMAC) Registers www.ti.com This may not be an exact count because the receive overruns statistic is independent of the other statistics, so if an overrun occurs at the same time as one of the other discard reasons, then the above sum double-counts that frame.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.50.17 Pause Transmit Frames Register (TXPAUSEFRAMES) The total number of IEEE 802.3X pause frames transmitted by the EMAC. Pause frames cannot underrun or contain a CRC error because they are created in the transmitting MAC, so these error conditions have no effect on this statistic.
Ethernet Media Access Controller (EMAC) Registers www.ti.com CRC errors have no effect on this statistic. 5.50.22 Transmit Excessive Collision Frames Register (TXEXCESSIVECOLL) The total number of frames when transmission was abandoned due to excessive collisions.
www.ti.com Ethernet Media Access Controller (EMAC) Registers • Was exactly 64-bytes long. (If the frame was being transmitted and experienced carrier loss that resulted in a frame of this size being transmitted, then the frame is recorded in this statistic).
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.50.33 Network Octet Frames Register (NETOCTETS) The total number of bytes of frame data received and transmitted on the EMAC.
www.ti.com Appendix A Glossary Broadcast MAC Address— A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the first byte is odd, qualifying it as a group address; however, its value is reserved for broadcast.
Appendix A www.ti.com Multicast MAC Address— A class of MAC address that sends a packet to potentially more than one recipient. A group address is specified by setting the LSB of the first MAC address byte to 1. Thus, 01h-02h-03h-04h-05h-06h is a valid multicast address.
www.ti.com Appendix B Revision History Table 88 lists the changes made since the previous version of this document. Table 88. Document Revision History Reference Additions/Modifications/Deletions Section 1.
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デバイスTexas Instruments TMS320DM36Xの購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
Texas Instruments TMS320DM36Xをまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはTexas Instruments TMS320DM36Xの技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Texas Instruments TMS320DM36Xの取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Texas Instruments TMS320DM36Xで得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Texas Instruments TMS320DM36Xを既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はTexas Instruments TMS320DM36Xの不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Texas Instruments TMS320DM36Xに関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちTexas Instruments TMS320DM36Xデバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
