ToshibaメーカーTLCS-900の使用説明書/サービス説明書
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Data Book 32bit Micro controller TLCS-900/H1 series TMP92CZ26AXBG Rev0.2 09/Dec./2005 TENT A TIVE It’ s first version technical data sheet. Since this revision 0.2 is still under working, there may be some mistakes in it. When you will start to design, please order the latest one.
T able of Content s TLCS-900/H1 Devices TMP92CZ26A 1. Outline and Featur es ･････････････ ･･･････････････ ････････････ 92CZ26A-1 2. Pin Assignment and Pin Functions ･･････ ･･･････････････ ･･･････ 92CZ26A-6 2.
3.12 8 bit timers (TMRA) ･･ ･･････････････ ･･･････････････ ･･･ 92CZ26 A-266 3.13 16 bit timer (TMRB) ･･･････ ･･･････････････ ････････････ 92CZ26A-294 3.
TMP92CZ26A 92CZ26A-1 CMOS 32-Bit Micro controllers TMP92CZ26AXBG 1. Outline and Features TMP92CZ26A is high-speed advanced 32-bit micro-c ontroller developed for controlling equipment which processes mass data. TMP92CZ26AXBG is housed in a 228-pin BGA package.
TMP92CZ26A 92CZ26A-2 (4) External memory expansion • Expandable up to 3.1G bytes (shared progr am/data area) • Can simultaneously su pport 8/16-bit width external data bus …… Dynamic data bus .
TMP92CZ26A 92CZ26A-3 (17) T ouch screen interface • Built-in Switch of Low-resistor , and available to delete external compon ents for shift change row/column (18) Watch dog timer (19) Melody/alarm .
TMP92CZ26A 92CZ26A-4 (28) Stand-by function • Three Halt modes : IDLE2 (programmable), IDLE1, STOP • Each pin status programma ble for stand-by mode • Built-in power supply management circuits (PMC) for leak current prov ision (29) Clock controller • Built-in two blocks of clock doubler (PLL).
TMP92CZ26A 92CZ26A-5 Figure 1.1 Block Diagram of TMP92CZ26A (PY)P97 IX IY IZ SP L H E D C B A W XSP XIZ XIY XIX XHL XDE XBC XW A 900/H1 CPU F SR 32bit P C 288KB RAM SERIAL I/O SIO0 ( RXD0 ) P91 (TXD0).
TMP92CZ26A 92CZ26A-6 2. Pin Assignment and Pin Functions The assignment of input/output pins for TMP92C Z26A, their na mes and functions are as follows; 2.
TMP92CZ26A 92CZ26A-7 T able 2.1.1 Pin number and the name Ball No. Pin name Ball No. Pin name Ball No. Pin name Ball No. Pin name A1 Dummy1 D9 P73,EA24 J15 PT5,LD13 P15 PK4,LHSYNC A2 PG2,AN2, MX D10 P.
TMP92CZ26A 92CZ26A-8 2.2 Pin names and Functions The names of the input/output pins an d their func tions ar e described below . T able 2.2.1 Pin names and functions (1/6 ) Pin name Number of Pins I/O Functions D0 to D7 8 I/O Data: Data bus D0 to D7. P10 to P17 D8 to D15 8 I/O I/O Port 1: I/O port.
TMP92CZ26A 92CZ26A-9 T able 2.2.1 Pin names and functions (2/6 ) Pin name Number of Pins I/O Functions P86 CSZD CE 0 ND 1 Output Output Output Port 86 : Output port. Expanded address ZD : Outputs “Low” when add ress is within specified address area.
TMP92CZ26A 92CZ26A-10 T able 2.2.1 Pin names and functions (3/6 ) Pin name Number of Pins I/O Functions PF0 I2S0CKO 1 I/O Output Port F0: I/O port. Outputs clock of I2S0. PF1 I2S0DO 1 I/O Output Port F1: I/O port. Outputs data of I2S0. PF2 I2S0WS 1 I/O Output Port F2: I/O port.
TMP92CZ26A 92CZ26A-1 1 T able 2.2.1 Pin names and functions (4/6 ) Pin name Number of Pins I/O Functions PK0 LCP0 1 Output Output Port K0: Output port. Signal for LCD driver . PK1 LLOAD 1 Output Output Port K1: Output port. Signal for LCD driver .: Data load signal PK2 LFR 1 Output Output Port K2: Output port.
TMP92CZ26A 92CZ26A-12 T able 2.2.1 Pin names and functions (5/6 ) Pin name Number of Pins I/O Functions PR3 SPCLK 1 I/O Output Port R3: I/ O port. Clock output pin of SD card. PT0 to PT7 LD8 to LD15 8 I/O Output Port T0 to T7: I/O port. Data bus for LCD driver: LD8 to LD15.
TMP92CZ26A 92CZ26A-13 T able 2.2.1 Pin names and functions (6/6 ) Pin name Number of Pins I/O Functions D+, D- 2 I/O Data pin connected to USB. In case USB is not used, connect both pins to pull-up(DVCC3A) or pull-down resistor for protect current flows it.
TMP92CZ26A 92CZ26A-14 3. Operation This section describes the basic com ponents, functi ons and operation of the T MP92 CZ26A. 3.1 CPU The TMP92CZ26A contains an advanced high -speed 32 -bit CPU (900/H1 CPU) 3.1.1 CPU Outline 900/H1 CPU is high-sp eed and high-perform anc e CPU based on 900/L1 CPU.
TMP92CZ26A 92CZ26A-15 3.1.2 Reset Operation When resetting the TMP92CZ26A microcontroller , ensure that the power supply voltage is within the operatin g voltage range, and that the internal hig h-frequency osci llator has stabilized. Then hold the RESET input Low for at least 20 system clocks (3 2µs at X1=10MHz).
TMP92CZ26A 92CZ26A-16 Figure 3.1.1 TMP92CZ26 A Reset timing chart f sys A 23 ∼ 0 DATA-IN D0 ∼ 15 D0 ∼ 15 Sampling (After reset is released, it is started from 1 wait read cycle) : High-Z Sampling RESET RD WRxx SRWR 0FFFF00H DATA-IN DATA-OUT CS0,1, 3 CS2 SRxxB SRxxB f SYS × (15.
TMP92CZ26A 92CZ26A-17 This LSI has the restriction for the order of supplying power . Be sure to supply external 3.3V power with 1.5V power is supplied. Note1: Inernal 1.5 V and External 3.3V po wer supply can be set to ON/ OFF at the same time. However, ext ernal pin may become unstable condition momentary.
TMP92CZ26A 92CZ26A-18 3.1.3 Setting of AM0 and AM1 Set AM1 and AM0 pins as Table 3.1.2 shows according to syst em usage. T able 3.1.2 Operation Mode Setup T able Mode Setup input pin RESET AM1 AM0 DBG.
TMP92CZ26A 92CZ26A-19 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP92 CZ2 6A. Figure 3.2.1 Memory Map Note1: Don’t use specified 64kbyte area of above 16M byte when using debug mode. This is because the area is reserved for control in the debug mode.
TMP92CZ26A 92CZ26A-20 3.3 Clock Function and S tandby Function TMP92CZ26A contains (1) clock gear , (2) clock doubler (PLL), (3) standb y controlle r and (4) noise-re ducing circuit. Th ey are used f or low-power , lo w-noise syste ms. This chapter is organized as follows: 3.
TMP92CZ26A 92CZ26A-21 The clock operating modes are as follows: (a) PLL-OFF Mode (X1, X2 pins only), (b) PLL-ON Mode (X1, X2, and PLL). Figure 3.3.1 shows a transition figure.
TMP92CZ26A 92CZ26A-22 3.3.1 Block diagram of system clock Clock gear SYSCR 0<PRC K> fs f OSCH Low frequency Oscillator circuit XT1 XT2 SYSCR0<XTEN > Warming up timer (High/Low frequency os.
TMP92CZ26A 92CZ26A-23 TMP92CZ26A has two PLL circuits: one is fo r CPU (PLL0) and the other for USB (PLL1). Each PLL can be con trolled in dependently . Frequency of external osc illat or is 6 to 10MHz. Don’t conn ec t oscill at or m ore than 10 MH z.
TMP92CZ26A 92CZ26A-24 3.3.2 SFR 7 6 5 4 3 2 1 0 bit Symbol XTEN USBCLK1 USBCLK0 WUEF PRCK Read/write R/W R/W R/W R/W R/W After Reset 1 0 0 0 0 Function Low -frequency oscillator circui t (fs) 0: Stop .
TMP92CZ26A 92CZ26A-25 7 6 5 4 3 2 1 0 Bit symbol PROTECT − EXTIN DRVOSCH DRVOSCL Read/Write R R/W R/W R/W R/W After reset 0 0 0 1 1 Function Protect flag 0: OFF 1: ON Always write “0”.
TMP92CZ26A 92CZ26A-26 7 6 5 4 3 2 1 0 bit symbol FCSEL LUPFG Read/Write R/W R After reset 0 0 Function Select fc-clock 0 : f OSCH 1 : f PLL Lock-up timer Status flag 0 : not end 1 : end Note: Be carefull that logic of PLL CR0<LUPFG> is different from 900/L1’s DFM.
TMP92CZ26A 92CZ26A-27 3.3.3 System clock controller The system clock controller gene rates the system clock signal (f SYS ) for the CPU core and internal I/O. SYSCR0<XEN> and S YSCR0<XTEN> control enab ling and disabli ng of each oscil lator .
TMP92CZ26A 92CZ26A-28 3.3.4 Clock doubler (PLL) PLL0 outputs the f PLL clock signal, which is 12 or 16 times as fa st as f OSCH . That is, the low-speed frequenc y oscillator can be used as extern al oscillator, ev en though the intern al clock is high-frequency.
TMP92CZ26A 92CZ26A-29 The following is a setting exampl e fo r PLL0-starting and PLL0-stopping. (Example-1) PLL0-starting PLLCR0 EQU 10E8H PLLCR1 EQU 10E9H LD (PLLCR1),1XXXXXXXXB ; Enables PLL0 operation and starts lock-up . LUP: BIT 5,(PLLCR0) ; JR Z,LUP ; Detects end of lock-up LD (PLLCR0 ), X1XXXXXXB ; Changes fc from 10 MHz to 60 MHz.
TMP92CZ26A 92CZ26A-30 Limitation point on the use of PLL0 1. If you stop PLL operation during using PLL0 , you should execute following setting in the same order . LD (PLLCR0),X0XXXXXXB ; Change the clock f PLL to f OS CH LD (PLLCR1),0XXXXXXXB ; S top PLL0 X: Don't care 2.
TMP92CZ26A 92CZ26A-31 3.3.5 Noise reduction circuits Noise reduction c ircuits a re built in, allowin g im p lementation o f the f ollowing features. (1) Reduced drivability for high-f requ ency oscil.
TMP92CZ26A 92CZ26A-32 (2) Reduced drivabi lity for low-fr equency osci llator circuit (Purpose) Reduces noise and p ow er for oscillator when a r esonator is used.
TMP92CZ26A 92CZ26A-33 (4) Runaway prov ision with SFR protect i on register (Purpose) Provision in runaway of program by noise mixin g. W rit e operation t o specified SFR is prohib ited so that prov .
TMP92CZ26A 92CZ26A-34 3.3.6 S tandby controller (1) Halt Modes and Port Drive-register When the HAL T instruction is e xecuted, th e operating mod e switches to IDLE2, IDLE1 or STOP Mode, depending on the cont ents of the SYSCR 2<HAL TM1 to 0 > register and each pin-status is se t according to PxDR-register .
TMP92CZ26A 92CZ26A-35 The operati o n of e ach of the differ ent Halt Modes i s describ ed in T able 3.3.3. T able 3.3.3 I/O operation during Halt Mo des Halt Mode IDLE2 IDLE1 STOP SYSCR2 <HAL TM1:.
TMP92CZ26A 92CZ26A-36 T able 3.3.4 Source of Halt state cl earance and Halt clearan ce operation S tatus of Received Interrupt Interrupt Enabled (interrupt level) ≥ (interrupt mask) Interrupt Disabl.
TMP92CZ26A 92CZ26A-37 (Example - releas ing IDLE1 Mode) An INT0 interrupt clears the Halt stat e when the devic e is in IDLE1 Mode. Address 8200H LD (PCFC), 02H ; Sets PC1 to INT0 interru pt. 8203H LD (IIMC0), 00H ; Select INT0 interrupt rising edge. 8206H LD (INTE0), 06H ; Sets INT0 interrupt level to 6.
TMP92CZ26A 92CZ26A-38 (3) Operation a. IDLE2 Mode In IDLE2 Mode, on ly specific internal I/O op erations, as designa ted by the IDLE2 Setting Reg iste r , can take place. Instruction execut ion by the CPU stops. Figure 3.3.8 il lustrates an example of the timin g for clearance o f the IDLE2 Mode Halt state by an interrupt.
TMP92CZ26A 92CZ26A-39 c. STOP Mode When STOP Mode is selected, al l internal circuits stop, inc luding the in ternal oscillator. After STOP Mode has been cleared system clock outp ut starts when the w arm-up time has elapsed, in orde r to al low oscillation to st abi lize.
TMP92CZ26A 92CZ26A-40 T able 3.3.6 Input Buf fer S tate T able Input Buffer S tate In HAL T mode (IDLE2/1/STOP) When the CPU is operating <PxDR>=1 <PxDR>=0 Port Name Input Function Name Du.
TMP92CZ26A 92CZ26A-41 T able 3.3.7 Output buf fer S tate T able (1/ 2) Output Buffer S tate In HAL T mo de (IDLE2/1 /STOP) When the CPU is operating <PxDR>=1 <PxDR>=0 Port Name Output Func.
TMP92CZ26A 92CZ26A-42 T able 3.3.8 Output buf fer state table (2/2) Output Buffer S tate In HAL T mode (IDLE2/1/STOP) When the CPU is operating <PxDR>=1 <PxDR>=0 Port Name Output Function .
TMP92CZ26A 92CZ26A-43 3.4 Boot ROM The TMP92CZ26A contains boot ROM for download ing a user program, and supports two kinds of do wnloading methods. 3.4.1 Operation Modes The TMP92CZ26A has two operation modes: MUL TI mode and BOOT mode. The operation mod e is selected according to the AM1 and AM0 pin leve ls when RESET is asserted.
TMP92CZ26A 92CZ26A-44 3.4.2 Hardware S pecifications of Internal Boot ROM (1) Memory map Figure 3.4.1 shows a memory map of BOOT mode. The boot ROM inc orporated in the TM P92CZ26A is an 8-Kbyte ROM area mapped to addresses 3FE000H to 3FFFFFH. In MUL TI mode, the boot ROM is not mapped and the above area is map ped as an external area.
TMP92CZ26A 92CZ26A-45 3.4.3 Outline of Boot Operation The method for download ing a user program can be select ed from two types: from UART , or via USB.
TMP92CZ26A 92CZ26A-46 Figure 3.4.3 How the Boot Program Uses Internal RAM Work Area for Boot Program (4 Kbytes) Download Area for User Program (282 Kbytes) Stack Area for Boot Program (2 Kbytes) 00200.
TMP92CZ26A 92CZ26A-47 (1) Port settings T able 3.4.3 shows th e port settings by the boot pro gram. When desig ning your application system, pl ease a lso re fer to T able 3.
TMP92CZ26A 92CZ26A-48 T able 3.4.4 Recommended Pin Connections Recommended Pin Connections for Each Download Method Port Name Function Name I/O UART USB P90 TXD0 Output No special setting is needed for booting via USB. UART P91 RXD0 Input Connect to the level shifter.
TMP92CZ26A 92CZ26A-49 (2) I/O register s ettings T able 3.4.5 shows the I/O regist ers th at are set by the boot program. After the boot se quence, if ex ecution moves to an application syst em program without a reset being asserted, the settings of these I/O registers must be taken into account.
TMP92CZ26A 92CZ26A-50 3.4.4 Downloading a User Program via UAR T (1) Connection example Figure 3.4.4 shows an example of con nec tions for download ing a user program via UART (using a 16-bit NOR Flash memory device as program me mory).
TMP92CZ26A 92CZ26A-51 (3) UART data transfer format T able 3.4.6 to T able 3.4.1 1 show the support ed frequencies, data transfer format, baud rate modification command, oper atio n command, and version managemen t information, respective ly . Please also ref er to th e description of b oot program operat ion later in this sec tion.
TMP92CZ26A 92CZ26A-52 T able 3.4.8 Baud Rate Modification Co mmand Baud Rate (bps) 9600 19200 38400 57600 115200 Modification Command 28H 18H 07H 06H 03H Note 1: If f OSCH (oscillation frequency) is 10.0 MHz, 5760 0 and 115200 bps are not supported. Note 2: If f OSCH (oscillation frequency) is 6.
TMP92CZ26A 92CZ26A-53 the baud rate is not changed, the initial baud rat e data (28H: 9600 bps) must be sent. Baud rate modification b e comes effective a fter the echo back transmission is completed.
TMP92CZ26A 92CZ26A-54 b) Error codes The boot program uses the error codes shown in T able 3.4.12 to notify the PC of its processing status. T able 3.4.
TMP92CZ26A 92CZ26A-55 d) No tes on Inte l Hex fo rmat (bi nary) 1. After receiving the checksum of a record, the boot pr ogram waits for the star t mark (3AH for “:”) of the next record . If data other than 3AH is received between records, it is ignored.
TMP92CZ26A 92CZ26A-56 e) User program recei v e error If either of the f ollowing error c onditions occ urs while a us er program is b eing received, the boo t pro gra m stops operati on.
TMP92CZ26A 92CZ26A-57 (5) Others a) Handshake function Although the CTS pin is available in the TMP 92CZ26A, the boot pr ogram does not use it for transfer control. b) RS-232C connector The RS-232C connector must not be connected or disconnected while the boot program is running.
TMP92CZ26A 92CZ26A-58 3.4.5 Downloading a User Program via USB (1) Connection example Figure 3.4.5 shows an example of con nec tions for download ing a user program via USB (using a 16-bit NOR Flash memory device as program memory). Note 1: The value of pull-up and pull-down resistors are rec ommended values.
TMP92CZ26A 92CZ26A-59 The following shows an overview of th e USB communicat i on flow . Figure 3.4.6 Overall Flowchart Host (PC) Connection Recognition Send GET_DISCRIPTOR Send DESCRIPTOR information.
TMP92CZ26A 92CZ26A-60 T able 3.4.15 V endor Requ est Co mmands Command Name V alue of bRequest Operation Notes Microcontroller information command 00H Send microcontroller information Microcontroller information data is sent by bulk IN transfer after the setup stage is completed.
TMP92CZ26A 92CZ26A-61 T able 3.4.17 S tandard Request Comma nds S tandard Request Response Method GET_STATUS Automatic response by hardware CLEAR_FEATURE Automatic response by hard ware SET_FEATURE Au.
TMP92CZ26A 92CZ26A-62 ConfigrationDescriptor Field Name V alue Meaning bLength 09H 9 bytes bDescriptorType 02H Configuration descriptor wTotalLength 0020H T ota l length (32 bytes) which each descriptor of both configuration descriptor , interface and endpoint is added.
TMP92CZ26A 92CZ26A-63 T able 3.4.19 Information Returned for th e Microcontroller Information Comm and Microcontroller Information ASCII Code TMP92CZ26A 54H, 4DH, 50H, 39H, 32H, 43H, 5AH, 32H, 36H,20H, 20H, 20 H, 20H, 20H, 20H T able 3.
TMP92CZ26A 92CZ26A-64 (3) Description of the USB boot program opera tion The boot program l oads a user pr ogram in Intel H ex format se nt from the P C into the internal RAM. Wh en the user pr ogram has be en loaded succ essful ly , the user program starts executing from th e first address receiv ed.
TMP92CZ26A 92CZ26A-65 b. Notes on the user program format (binary) 1. After rec eiving the ch ecksum of a reco rd, the boot program waits for the start mark (3AH for “:”) of the next record . If data other than 3AH is received between records, it is ignored.
TMP92CZ26A 92CZ26A-66 (4) Others a) USB connector The USB connector must not be con nected or disconnected whi le the boot program is running. b) Software on the PC T o download a user program via USB, a USB device driver and special application soft war e are needed on th e P C.
TMP92CZ26A 92CZ26A-67 3.5 Interrupts Interrupts are controlled by the CPU Interrupt Ma sk Regist er <IFF2 to 0> (bits 12 to 14 of the Status Regist er) an d by the built-in interrupt control ler.
TMP92CZ26A 92CZ26A-68 Figure 3.5.1 Interrupt processing Sequence Interrupt processing Interrupt vector calue “V” read interrupt request F/F clear Interrupt specified by DMA start v ector ? PUSH PC.
TMP92CZ26A 92CZ26A-69 3.5.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it us ually performs the following sequence of operations. How ever , in the cas e of softwar e in terrupts and illegal instruction int errupts generated by the CPU, the CPU sk ips steps (1) and (3), and exec utes only steps (2), (4), and (5).
TMP92CZ26A 92CZ26A-70 T able 3.5.1 TMP92CZ26A Interrupt V ect ors and Micro DMA/HDMA S tart V ectors Default Priority T ype Interrupt Source and Source of Micro DMA Request Ve c t o r V alue Address R.
TMP92CZ26A 92CZ26A-71 Default Priority T ype Interrupt Source and Source of Micro DMA Request Ve c t o r V alue Address Refe r to V ector Micro DMA /HDMA S tart Ve c t o r 51 INTADHP: AD most priority.
TMP92CZ26A 92CZ26A-72 3.5.2 Micro DMA processing In addition to general-p urpose interrupt proc essing, the TMP92CZ26 A also includes a micro DMA function and HDMA function. This section explains about Micro DMA function. For the HDMA function, please refer 3.
TMP92CZ26A 92CZ26A-73 If micro DMA requ ests are set simultaneously for more than one channel, priority is not based on the interru pt priority level but on th e channel number: The low er the channel number , the higher the priority (Channel 0 thus has the highest priority an d channel 7 the lowest).
TMP92CZ26A 92CZ26A-74 (2) Soft start function T h e T M P 9 2 C Z 2 6 A c a n i n i t i a t e m i c r o D M A / H D M A e i t h e r w i t h a n i n t e r r u p t o r b y using the micro DM A /HDMA soft start func tion, in wh ich micro DMA or HDMA is initiated by a W rite cyc le which writes to the regis ter DMAR.
TMP92CZ26A 92CZ26A-75 (4) Detailed des cription of the transf er m ode register 0 0 0 Mode DMAM0 to 7 DMAMn[4:0] Mode Descrip tion Execution T ime 0 0 0 z z Destination IN C mode (DMADn +) ← (DMASn).
TMP92CZ26A 92CZ26A-76 3.5.3 Interrupt Controller Operation The block diagram in Figure 3.5.3 shows the int errupt circuits. The left-h and side of the diagram shows the interrupt controller ci rcuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit.
TMP92CZ26A 92CZ26A-77 Interrupt request signal to CPU IFF ＝ 7 then 0 Micro DMA/H DMA start vector setting regist er INTTC4/INTDM A4 INTTC5/INTDM A5 INTTC6 INTTC7 V = E0H V = E4H V = E8H V = ECH Soft.
TMP92CZ26A 92CZ26A-78 (1) Interrupt priority settin g registers Symbol Name Addres s 7 6 5 4 3 2 1 0 − INT0 − − − − I0C I0M2 I0M1 I0M0 R R/W R R/W INTE0 INT0 enable F0H Always write “0”.
TMP92CZ26A 92CZ26A-79 Symbol Nam e Address 7 6 5 4 3 2 1 0 INTTB01 (TMRB0) INTTB00 (TMRB0) ITB01C ITB01M2 ITB 01M1 ITB01M0 I TB00C IT B00M2 ITB00M1 ITB00M0 R R/W R R/W INTETB0 INTTB00 & INTTB01 en.
TMP92CZ26A 92CZ26A-80 Symbol Name Address 7 6 5 4 3 2 1 0 − INTLCD − − − − ILCD1C ILCDM2 ILCDM1 ILCDM0 R R/W INTELCD INTLCD enable EAH Always write “0”.
TMP92CZ26A 92CZ26A-81 Symbol Name Address 7 6 5 4 3 2 1 0 INTTC1/INTDMA1 INTTC0/INTDMA0 ITC1C /IDMA1C ITC1M2 /IDMA1M2 ITC1M1 /IDMA1M1 ITC1M0 /IDMA1M0 ITC0C /IDMA0C ITC0M2 /IDMA0M2 ITC0M1 /IDMA0M1 ITC0.
TMP92CZ26A 92CZ26A-82 (2) External interrupt contro l Symbol Name Address 7 6 5 4 3 2 1 0 I5EDGE I4EDGE I3EDGE I2EDGE I1EDGE I0EDGE I0LE − W W W W W W R/W R/W 0 0 0 0 0 0 0 0 IIMC0 Interrupt input m.
TMP92CZ26A 92CZ26A-83 (3) SIO receive interrupt control Note: When using the micro DMA transfer end interrupt, al ways write “1”. INTRX0 edge enable 0 Edge detect INTRX0 1 “H” level INTRX0 Sym.
TMP92CZ26A 92CZ26A-84 (4) Interrupt request flag clear register The interrup t request flag is clear ed by wr iting the appr opriate micro D MA /HDMA start vector , as given in T able 3.5.1 to the register INTCLR. For example, to cl ear the interrupt flag INT0, perform the following re gister operation after execution of the DI i n stru ction.
TMP92CZ26A 92CZ26A-85 Symbol Name Address 7 6 5 4 3 2 1 0 DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 R/W 0 0 0 0 0 0 DMA0V DMA0 start vector 100H DMA0 start vector DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DM.
TMP92CZ26A 92CZ26A-86 (7) Specification of a micro DM A burst Specifying the micro DMA burst function caus es micro DMA transfer , once started, to continue until th e value in the transfer count er re gister reaches “0”.
TMP92CZ26A 92CZ26A-87 (8) Notes The instruction executi on unit and the bus interface unit in this CPU operate independentl y . T herefor e, if imm ediat ely befor e an interru pt is generat ed, the C.
TMP92CZ26A 92CZ26A-88 3.6 DMAC (DMA Controller) The TMP92CZ26A incorporates a DMA controller (DMAC) havin g six channels. This D MAC can realize data transfer fast er than the m icro DMA function by th e 900/H1 CPU .
TMP92CZ26A 92CZ26A-89 3.6.1 Block Diagram Figure 3.6.1 shows an overall block diagram for the DMAC. Note: “n” denotes a channel number. Micro DMA has eight c hannels (0 to 7) and DMA has six channels (0 to 5).
TMP92CZ26A 92CZ26A-90 3.6.2 SFRs The DMAC has the follo wing SFRs. These regist ers are connected to the CPU via a 1 6-bit data bus. (1) HDMASn (DMA Transfer Source Address Setting Register) The HDMASn register is used to set the DMA tr ansfer source addr ess.
TMP92CZ26A 92CZ26A-91 (2) HDMADn (DMA Transfer Destination Address Sett ing Register) The HDMADn regist er is used to set the DM A transfer destin ation address. When th e destination address is upd ated by D MA ex ecution, HDMADn is also updated. HDMAD0 to HDMAD5 have th e same configuration.
TMP92CZ26A 92CZ26A-92 (3) HDMACAn (DM A Transf er C ount A Setting Regist er) The HDMACAn re gister is used to s et the number o f times a DMA tran sfer is to be performed by one DMA requ est. HDMACAn contains 16 bits and can specify up to 65536 transfers (0001H = one transfer, FFFFH = 65535 transfers, 0000H = 65536 transfers).
TMP92CZ26A 92CZ26A-93 (4) HDMACBn (DM A Transf er C ount B Setting Regist er) The HDMACBn register is used t o set the num ber of t imes a D MA r equest is to be m ade. HDMACBn contains 16 bits and can specify up to 65536 requ ests (0001H = one requ est, FFFFH = 65535 requests, 0000H = 65536 requests).
TMP92CZ26A 92CZ26A-94 (5) HDMAMn (DMA Transfer Mode Setting Registe r) The HDMAMn regist er i s used to set the DMA tra nsfer mode. HDMAM0 to HDMAM5 have th e same configuration.
TMP92CZ26A 92CZ26A-95 (6) HDMAE (DMA Operation Enable Reg ister) The HDMAE regist er is used to enabl e or disable the DM AC operati on. Bits 0 to 5 correspond to channels 0 to 5.
TMP92CZ26A 92CZ26A-96 3.6.3 DMAC Operation Description (1) Overall flowchart Figure 3.6.9 shows a flowchart for DMAC operation wh en an interrupt (DMA) is requested.
TMP92CZ26A 92CZ26A-97 ZZ12H 1234H 400001H 400000H 800000H D15 ∼ D0 SRLLB SRLUB SRWR RD A23 ∼ A0 1 CS busak busrq int_xx SDCLK DMAC/read DMAC/write CPU execution c y cle Undefined after interrupt r.
TMP92CZ26A 92CZ26A-98 3.6.4 Setting Example This section explains how to set the D MAC usin g a n example. (1) Transferring music data from inte rnal RAM to I2S by DMA transfer The 32 Kbytes of data stored in the int ernal RAM at addr esses 2000H to 9FFFH shall be transferred to FIFO-RAM via I2S.
TMP92CZ26A 92CZ26A-99 3.6.5 Note 1. In case of using S/W start with HDMA, tr ansmission start is to set to "1" DMAR register. However DMAR register can't be us ed to confirm flag of transmission end. DMAR register reset to "0" when HDMA release bus occupation once with HDMATR function.
TMP92CZ26A 92CZ26A-100 3.6.6 Considerations for Usi ng More Than One Bus Master In the TM P92CZ26A, t he LCD con troller, SDRAM cont roller , and DMA con troller may act as the bus master apart from the CPU. Theref ore, care must be exercised to enable each of these functions to operate sm oothly.
TMP92CZ26A 92CZ26A-101 Sample 1) Calculation example for CPU + HDMA Conditions: CPU operation speed (f SYS ) : 60 MHz I2S sampling frequency : 48 KHz (60 MHz/25/50 = 48 KHz) I2S data transfer bit leng.
TMP92CZ26A 92CZ26A-102 (2) CPU + LDMA The LCD controll er performs DMA t ransfer (LDMA) after issuing a bus requ est to the CPU and getting a bus acknowledgem ent. If LDMA is not p erformed pro perly, the LC D display funct ion cannot work properly. Therefore, LDM A must have higher prior ity than the CPU.
TMP92CZ26A 92CZ26A-103 Sample2) Calculation examp les for CPU + LDMA Conditions 1: CPU operation speed (f SYS ) : 60 MHz Display RAM : Internal RAM Display size : QVGA (320seg × 240com) Display quali.
TMP92CZ26A 92CZ26A-104 (3) CPU + LDMA + ARDMA The SDRAM controller o wns the bus not only when SDRAM is used as the LCD displa y RAM but also when SDRAM is used as work, data, or stack area. The SDRAM controller occupies the bus (ARD M A) while it refr eshes SD RAM data by th e aut o refresh function.
TMP92CZ26A 92CZ26A-105 Sample3) Calculation examp le for CPU + LDMA + ARDMA Conditions: CPU operating speed(f SYS ) : 60 MHz Display RAM : 16-bit external SDRAM Display size : QVGA (320seg × 240com) Display quality : 65536 colors (TFT) Refresh rate : 70 Hz (incl uding 20 clocks of dummy cycles) SDRAM auto refresh : Every 936 states (15.
TMP92CZ26A 92CZ26A-106 (4) CPU + LDMA + ARDMA + HDMA This is a case in which all the bus masters are active at th e sa me time. Since the LCD displ ay function can not work properly i f the LCD controll er cannot perform LDMA pr operly, the priorities amon g the four bus masters shoul d be set in the order of LDM A > ARDMA > HDMA > C PU.
TMP92CZ26A 92CZ26A-107 Sample 4) Calculation examp le for CPU + LDMA + ARD M A + HDMA Conditions: CPU operation speed (f SYS ) : 60 MHz Display RAM : QVGA (320seg × 240com) Display quality : 65536 colors (TFT) Refresh rate : 70 Hz (incl uding 20 clocks of dummy cycles) SDRAM Auto Refresh : Ever y 936 states (15.
TMP92CZ26A 92CZ26A-108 HDMATR Register 7 6 5 4 3 2 1 0 bit Symbol DMATE DMATR6 DMATR5 DMATR4 DMATR3 DMATR2 DMATR1 DMATR0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Timer operation 0: Disable .
TMP92CZ26A 92CZ26A-109 Sample 5) Calculation examp le when using CPU + LCDC + SDRAMC + HDMA at same time (Worst case) Conditions: CPU operation speed (f SYS ) : 80MHz Display RAM : Internal RAM Displa.
TMP92CZ26A 92CZ26A-1 10 3.7 Function of port s TMP92CZ26A has I/O port pins t hat are shown in T able 3.7.1 in addition to funct ioning as general-purpose I/O p orts, these pins are also used by int ernal CPU and I/O funct ions. T able 3.7.2 lists I/O registers and their specificat ions.
TMP92CZ26A 92CZ26A-1 1 1 T able 3.7.1 Port Functions (2/3) Port Name Pin Name Number of Pins I/O R I/O Setting Pin Name for built-in function PJ0 1 Output − (Fixed) SDRAS , SRLLB PJ1 1 Output − (F.
TMP92CZ26A 92CZ26A-1 12 T able 3.7.1 Port Functions (3/3) Port Name Pin Name Number of Pins I/O R I/O Setting Pin Name for built-in function PZ0 1 I/O − bit EI_PODDATA PZ1 1 I/O − bit EI_SYNCLK PZ.
TMP92CZ26A 92CZ26A-1 13 T able 3.7.2 I/O Port and Specification s (1/4) X: Don’t care I/O register Port Pin name Specification Pn PnCR PnFC PnFC2 Input port X 0 Output port X 1 0 Port 1 P10 toP17 D8.
TMP92CZ26A 92CZ26A-1 14 T able3.7.2 I I/O Port and Specification s (2/4) X: Don’t care I/O register Port Pin name Specification Pn PnCR PnFC PnFC2 P90, P92 Input port X 0 0 None P91 Input port, RXD0.
TMP92CZ26A 92CZ26A-1 15 T able3.7.2 I/O Port and Specification s (3/4) X: Don’t care I/O register Port Pin name Specification Pn PnCR PnFC PnFC2 Input port PG0 to PG5 AN0 to AN5 Input 0 PG3 ADTRG In.
TMP92CZ26A 92CZ26A-1 16 T able 3.7.2 I/O Port and Specification s (4/4) X: Don’t care I/O register Port Pin name Specification Pn PnCR PnFC PnFC2 PR0 to PR3 Input port X 0 0 PR0 to PR3 Output port X.
TMP92CZ26A 92CZ26A-1 17 3.7.1 Port 1 (P10 to P17) Port1 is an 8-bit general-purpose I/O port. Bits c an be ind ividually set as either inputs or outputs by control register P1 CR and functi on re gister P1FC. In addition to functioning as a gen eral-purpose I/O port, port1 can als o function as a data bus (D8 to D15).
TMP92CZ26A 92CZ26A-1 18 Port 1 register 7 6 5 4 3 2 1 0 bit Symbol P17 P16 P15 P14 P13 P12 P11 P10 Read/Write R/W After reset Data from external port (Output latch register is cleared to “0”) Port.
TMP92CZ26A 92CZ26A-1 19 3.7.2 Port 4 (P40 to P47) Port4 is an 8-bit general-purpose Output ports. In addition to functi oning as a general-purpose Output port, port 4 can also function as an address bus (A0 to A7). Each bit can be set individually for function.
TMP92CZ26A 92CZ26A-120 Port 4 register 7 6 5 4 3 2 1 0 bit Symbol P47 P46 P45 P44 P43 P42 P41 P40 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Port 4 Function register 7 6 5 4 3 2 1 0 bit Symbol P47F P4.
TMP92CZ26A 92CZ26A-121 3.7.3 Port 5 (P50 to P57) Port5 is an 8-bit general-purpose Output ports. In addition to functi oning as a general-purpose I/O port, port5 can also function as an address bus (A8 to A15). Each bit can be set individually for function.
TMP92CZ26A 92CZ26A-122 Port 5 register 7 6 5 4 3 2 1 0 bit Symbol P57 P56 P55 P54 P53 P52 P51 P50 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Port 5 Function register 7 6 5 4 3 2 1 0 bit Symbol P57F P5.
TMP92CZ26A 92CZ26A-123 3.7.4 Port 6 (P60 to P67) Port6 is an 8-bit general-purpose I/O ports. Bits can be ind ividually set as either inputs or outputs and function by control r egister P6CR and funct i on register P6FC. In addition to function ing as a general-purp ose I/ O port, port6 can also function as an address bus (A16 to A23).
TMP92CZ26A 92CZ26A-124 Port 6 register 7 6 5 4 3 2 1 0 bit Symbol P67 P66 P65 P64 P63 P62 P61 P60 Read/Write R/W After reset Data from external port (Output latch register is cleared to “0”) Port .
TMP92CZ26A 92CZ26A-125 3.7.5 Port 7 (P70 to P76) Port7 is a 7-bit general-purpose I/O port (P 70 is used for output only). Bits can be individually set as either inputs or outputs by contr ol register P7CR and function register P7FC.
TMP92CZ26A 92CZ26A-126 Figure 3.7.10 Port7 Read data P7 register S 1 0 Selecto r P7CR register P7FC register S 0 1 Selecto r P73 (EA24) P74 (EA25) EA24, EA25 Selector P7 register Port read data P7CR r.
TMP92CZ26A 92CZ26A-127 Port 7 register 7 6 5 4 3 2 1 0 bit Symbol P76 P75 P74 P73 P72 P71 P70 Read/Write R/W After reset Data from extern al port (Output latch register is set to “1”) Data from ex.
TMP92CZ26A 92CZ26A-128 3.7.6 Port 8 (P80 to P87) Port 80 to 87 are 8-bit output por ts. Resetting sets output latch of P82 to “0” and out put latches of P80 to P81, P83 to P87 to “1”. But if it is started at boot mode (AM [1:0] = “1 1”), output latch of P82 is set to “1”.
TMP92CZ26A 92CZ26A-129 Port 8 register 7 6 5 4 3 2 1 0 bit Symbol P87 P86 P85 P84 P83 P82 P81 P80 Read/Write R/W After rese t 1 1 1 1 1 0 (Note3) 1 1 Port 8 Function register 7 6 5 4 3 2 1 0 bit Symbo.
TMP92CZ26A 92CZ26A-130 3.7.7 Port 9 (P90 to P92, P96, P97) P90 to P92 are 3-bit general- purpos e I/O port. I/O can be set on bit basis using the contro l register . Rese ttin g sets P90 to P92 to input port and all bits of output latch to” 1”. P96 to P97 are 2-bit general-purpose input p ort.
TMP92CZ26A 92CZ26A-131 Figure 3.7.15 P91, 92 Figure 3.7.16 Port 96,97 Internal data bus Selector A B S Selector A B S P91(RXD0) P92(SCLK0, 0 CTS ) SCLK0 output P9 read Direction control ( on bit basis.
TMP92CZ26A 92CZ26A-132 Port 9 register 7 6 5 4 3 2 1 0 bit Symbol P97 P96 P92 P91 P90 Read/Write R R/W After reset Data from extern al port Data from external port (Output latch register is set to “.
TMP92CZ26A 92CZ26A-133 3.7.8 Port A (P A0 to P A7) P or t A0 t o A 7 ar e 8 - b it g en e ra l -p u r p os e in p u t ports with pull-up resist or . In addition to functioning as gen eral-purpose I/O ports, port A 0 t o A 7 ca n a l s o K ey - o n wa ke - u p f un c t io n as Keyboard interfac e.
TMP92CZ26A 92CZ26A-134 Port A register 7 6 5 4 3 2 1 0 b i t S y m b o l PA 7 PA 6 PA 5 PA 4 PA 3 PA 2 PA 1 PA 0 Read/Write R After reset Data from external port Port A Function register 7 6 5 4 3 2 1.
TMP92CZ26A 92CZ26A-135 3.7.9 Port C (PC0 to PC7) PC0 to PC7 are 8-bit general-purp ose I/O port. Each bit can be set indiv idually for input or output. Resetting sets Port C to an input port. It also sets all bits of the output latc h register to “1”.
TMP92CZ26A 92CZ26A-136 (2) PC1 (INT1, T A0IN), PC3 (INT3, T A2IN) Figure 3.7.21 Port C1,C3 PC1 (INT1,TA0IN) PC3 (INT3, TA2IN) Internal data bus Direction control Reset PCCR write PCwrite PC read Funct.
TMP92CZ26A 92CZ26A-137 (3) PC4 (EA26), PC5 (E A27), PC6 (EA28) Figure 3.7.22 Port C4, C5, C6 (4) PC7 (KO8) Figure 3.7.23 Port C7 Reset Selector A B S PC7(KO8) PC read Direction control PCCR write Func.
TMP92CZ26A 92CZ26A-138 Port C register 7 6 5 4 3 2 1 0 bit Symbol PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Read/Write R/W After reset Data from external port (Output latch register is set to “1”) Port C co.
TMP92CZ26A 92CZ26A-139 3.7.10 Port F (PF0 to PF5, PF7) Port F0 to F5 are 6-bit gene ral-purpose I/O ports. Resetting sets PF0 to PF5 to be input ports. It also sets all bits of the outpu t latch register to “ 1”. In addition to functioning as general-purpose I/O p ort pins, PF0 to P F5 can also function as the ou tput for I 2 S0, I 2 S1.
TMP92CZ26A 92CZ26A-140 Figure 3.7.25 Port F0, F3 Figure 3.7.26 Port F1, F2, F4, F5 Internal data bus Selector A B S Selector A B S PF0 (I2S0CKO) PF3 (I2S1CKO) I2S0CKO output I2S1CKO /X1D4 outpu t PF r.
TMP92CZ26A 92CZ26A-141 (2) Port F7 (SDCLK), Port F7 is general-purpose output port. In addition to functioning as general-purp ose output port, PF7 can also function as the SDCLK output.
TMP92CZ26A 92CZ26A-142 Port F register 7 6 5 4 3 2 1 0 bit Symbol PF7 PF5 PF4 PF3 PF2 PF1 PF0 Read/Write R/W R/W After reset 1 Data from external port (Output latch register is set to “1”) Port F .
TMP92CZ26A 92CZ26A-143 3.7.11 Port G (PG0 to PG5) PG0 to PG5 are 6-bit input port and can also be used as the analog input pins for the internal AD converter . PG3 can also be used as ADTRG pin for the AD converter . PG2, PG3 can also be used as MX, MY pin for T ouch screen interface.
TMP92CZ26A 92CZ26A-144 Port G register 7 6 5 4 3 2 1 0 Bit Symbol PG5 PG4 PG3 PG2 PG1 PG0 Read/Write R After reset Data from external port Note: Selection of the input channel of AD converter and ADTRG input mode register is enabled by setting AD converter .
TMP92CZ26A 92CZ26A-145 3.7.12 Port J (PJ0 to PJ7) PJ0 to PJ4 and PJ7 are 6 -bit output port. Resetting sets th e output latch PJ to “1”, an d they output “1”.
TMP92CZ26A 92CZ26A-146 Figure 3.7.32 Port J5,J6 Internal data bus Selector A B S Selector A B S PJ5 (NDALE), PJ6 (NDCLE) NDALE, NDCLE output P J read Direction control PJCR write Function control S Ou.
TMP92CZ26A 92CZ26A-147 Port J register 7 6 5 4 3 2 1 0 bit Symbol PJ7 PJ6 PJ 5 PJ4 PJ3 PJ2 PJ1 PJ0 Read/Write R/W After reset 1 Data from exte rnal port (Output latch register is set to “1”) 1 1 1.
TMP92CZ26A 92CZ26A-148 3.7.13 Port K (PK0 to PK7) PK0 to PK7 are 8-bit output ports. Resetting se ts the ou tput latch PK to “0”, and PK0 to PK7 pins output “0”. In addit ion to functi oning as output port function, Port K also function as output pins for LCD controll er (LCP0, LHSYNC, LLOAD, LFR, L VSYNC, and LGOE0 to LGOE2).
TMP92CZ26A 92CZ26A-149 Port K register 7 6 5 4 3 2 1 0 bit Symbol PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Port K function register 7 6 5 4 3 2 1 0 bit Symbol PK7F PK.
TMP92CZ26A 92CZ26A-150 3.7.14 Port L (PL0 to PL7) PL0 to PL7 are 8-bit output ports. Resetting se ts the output latch PL to “0”, and PL0 to PL7 pins output “0”. In addit ion to functioning as a gener al-purpose output port, P ort L can also function as a data bus for LCD contro ller (LD0 to LD7).
TMP92CZ26A 92CZ26A-151 Port L register 7 6 5 4 3 2 1 0 bit Symbol PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Port L function register 7 6 5 4 3 2 1 0 bit Symbol PL7F PL.
TMP92CZ26A 92CZ26A-152 3.7.15 Port M (PM1, PM2, PM7) PM1, PM2 and PM7 are 3-b it output ports. Resetting s ets the output latch P M to “1”, and PM1, PM2 and PM7 pins output “1”.
TMP92CZ26A 92CZ26A-153 Figure 3.7.39 Port M2 Figure 3.7.40 Port M7 PWE Reset S Output latch PM write PM read Function control (on bit basis) PMFC write S A Y Selector B PM7 (PWE) Internal data bus MLD.
TMP92CZ26A 92CZ26A-154 Port M register 7 6 5 4 3 2 1 0 bit Symbol PM7 PM2 PM1 Read/Write R/W R/W After reset 1 1 1 Port M function register 7 6 5 4 3 2 1 0 bit Symbol PM7F PM2F PM1F Read/Write W W Aft.
TMP92CZ26A 92CZ26A-155 3.7.16 Port N (PN0 to PN7) PN0 to PN7 are 8-bit general-purpose I/O port. Eac h bit can be set ind ividu ally f or input or output. Resetting s ets Port N to an input port. In a ddition to functionin g as a general-purpose I/O port, Port N can also func tion as interfa ce pin for key -boar d (KO0 to KO7).
TMP92CZ26A 92CZ26A-156 Port N register 7 6 5 4 3 2 1 0 bit Symbol PN7 PN6 PN5 PN4 PN3 PN2 PN1 PN0 Read/Write R/W After reset Data from external port (Output latch register is set to “1”) Port N co.
TMP92CZ26A 92CZ26A-157 3.7.17 Port P (PP1 to PP7) Port P1 to P5 are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output.
TMP92CZ26A 92CZ26A-158 Figure 3.7.45 Port P3 Figure 3.7.46 Port P4,P5 PP4 (INT6,TB0IN0) PP5 (INT7, TB1IN0) Internal data bus Direction control (on bit basis) Reset PPCR write PP write PP read Function.
TMP92CZ26A 92CZ26A-159 Figure 3.7.47 Port P6, P7 Selector A B S PP6 (TB0OUT0) PP7 (TB1OUT0) TB0OUT0 output TB1OUT0 output Function control (on bit basis) R Output latch PP write Reset PPFC write Inter.
TMP92CZ26A 92CZ26A-160 Port P register 7 6 5 4 3 2 1 0 bit Symbol PP7 PP6 PP5 PP4 PP3 PP2 PP1 Read/Write R/W After reset 0 0 Data from external port (Output latch register is cleared to “0”) Port .
TMP92CZ26A 92CZ26A-161 3.7.18 Port R (R0 to R3) Port R0 to R3 are 4-bit general-purpose I/O ports. Each bit can be set individually for input or output.
TMP92CZ26A 92CZ26A-162 Figure 3.7.50 Port R1 to R3 Selector A B S PR1(SPDO), PR2( SPCS ), PR3(SPCLK) PR read Direction control ( on bit basis ) PRCR write Function control (on bit basis) PRFC write R .
TMP92CZ26A 92CZ26A-163 Port R register 7 6 5 4 3 2 1 0 bit Symbol PR3 PR2 PR1 PR0 Read/Write R/W After reset Data from external port (Output latch register is cleared to “0”) Port R control regist.
TMP92CZ26A 92CZ26A-164 3.7.19 Port T (PT0 to PT7) Port T0 to T7 are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output.
TMP92CZ26A 92CZ26A-165 Port T register 7 6 5 4 3 2 1 0 bit Symbol PT7 PT6 PT 5 PT4 PT3 PT2 PT1 PT0 Read/Write R/W After reset Data from external port (Output latch register is cleared to “0”) Port.
TMP92CZ26A 92CZ26A-166 3.7.20 Port U (PU0 to PU7) Port U0 to U7 are 8-bit gene ral-purpose I/O ports. Each bi t can be set individually for input or output.
TMP92CZ26A 92CZ26A-167 Figure 3.7.55 Port U5 Selector A B S Selector A B S PU5 (LD21) PU read Direction control (on bit basis) PUCR wirte Function control ( on bit basis ) PUFC write R Output latch PU.
TMP92CZ26A 92CZ26A-168 Port U register 7 6 5 4 3 2 1 0 Bit Symbol PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 Read/Write R/W After reset Data from external port (Output latch register is cleared to “0”) Port .
TMP92CZ26A 92CZ26A-169 3.7.21 Port V (PV0 to PV4, PV6 , PV7) Port V0 to V2, V6 and V7 are 5-bit genera l-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port V0 to V2, V6 and V7 to input port and output latch to “0”.
TMP92CZ26A 92CZ26A-170 Figure 3.7.58 Port V3, V4 Figure 3.7.59 Port V6, V7 Selector A B S Selector A B S PV6(SDA) PV7(SCL) PV read Direction control (on bit basis) PVCR write Function control (on bit .
TMP92CZ26A 92CZ26A-171 Port V register 7 6 5 4 3 2 1 0 bit Symbol PV7 PV6 PV4 PV3 PV2 PV1 PV0 Read/Write R/W R/W After reset Data from external port (Output latch register is cleared to “0”) Data .
TMP92CZ26A 92CZ26A-172 3.7.22 Port W (PW0 to PW7) Port W0 to W7 are 8-bit general-purpose I/O ports. Each bit can be set in dividually for input or output. Resetting sets port W0 to W7 to input port and output latch t o “0”. Above settin g is used th e control reg ist er PWCR and function r egister PWFC .
TMP92CZ26A 92CZ26A-173 Port W register 7 6 5 4 3 2 1 0 bit Symbol PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0 Read/Write R/W After reset Data from external port (Output latch register is cleared to “0”) Port .
TMP92CZ26A 92CZ26A-174 3.7.23 Port X (PX4, PX5 and PX7) Port X5 and X7 are 2-bit gen eral-purpose I/O ports. Each bit can be set in dividually for input or output.
TMP92CZ26A 92CZ26A-175 Figure 3.7.64 Port X5, X7 Selector A B S PX5 (X1USB) PX7 PX read Direction control ( on bit basis ) PXCR write Function control (on bit basis) PXFC write R Output latch PX write.
TMP92CZ26A 92CZ26A-176 Port X register 7 6 5 4 3 2 1 0 bit Symbol PX7 PX5 PX4 Read/Write R/W R/W After reset Data from external port (Output latch register is cleared to “0”) Port W control regist.
TMP92CZ26A 92CZ26A-177 3.7.24 Port Z (PZ0 to PZ7) Port Z0 to Z7 are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output.
TMP92CZ26A 92CZ26A-178 Figure 3.7.67 Port Z6 to Z7 Selector A B S PZ6(EO_MCUDATA) PZ7(EO_MCUREQ) PZ read Direction control (on bit basis) PZCR write R Output latch PZ write Reset Internal data bus Sel.
TMP92CZ26A 92CZ26A-179 Port Z register 7 6 5 4 3 2 1 0 bit Symbol PZ7 PZ6 PZ 5 PZ4 PZ3 PZ2 PZ1 PZ0 Read/Write R/W After reset Data from external port (Output latch register is cleared to “0”) Port.
TMP92CZ26A 92CZ26A-180 3.8 Memory Controller (MEMC) 3.8.1 Functions TMP92CZ26A has a memory contro ller with a variable 4-block addr ess area that controls as follows. (1) 4-block address area support Specifies a start address and a bl ock size for 4-block address area (block 0 to 3).
TMP92CZ26A 92CZ26A-181 3.8.2 Control register and O peration after reset release This section describes the regist ers to contro l the memory con troller, the state after re set release and nece ssary settings. (1) Control Register The control re gi sters of the memor y co ntro ll er are as follows and Table 3.
TMP92CZ26A 92CZ26A-182 Table 3.8.1 Control register 7 6 5 4 3 2 1 0 Bit symbol B0WW3 B0WW2 B0WW1 B0WW0 B0WR3 B0WR2 B0WR1 B0WR0 Read/Write R/W After Reset 0 0 1 0 0 0 1 0 Bit Symbol B0E B0REC B0OM1 B0O.
TMP92CZ26A 92CZ26A-183 Table 3.8.2 Control register 7 6 5 4 3 2 1 0 Bit Symbol BEXWW3 BEXWW2 BEXWW1 BEXWW0 BEXWR3 BEXWR2 BEXWR1 BEXWR0 Read/Write R/W BEXCSL (0159H) After Reset 0 0 1 0 0 0 1 0 Bit Sym.
TMP92CZ26A 92CZ26A-184 (2) Operation after releasing reset The data bus width at starting is determined depen ding on state of AM1/AM0 pins after releasing reset. Then, the extern al memory access as follows; Note: A memory to be used to start afte r releasing reset is either N OR-Flash or Masked-ROM.
TMP92CZ26A 92CZ26A-185 3.8.3 Basic functions and register setting In this section, setting of the block address ar ea, the con necting m emory and the num ber of waits out of the mem ory controller’s functions ar e described.
TMP92CZ26A 92CZ26A-186 (b) Memory address mask registers Figure 3.8.3 shows the memory address mask regi sters. MAMR0 to MAMR3 are used to set the size of the CS0 t o CS3 areas by specifying a m ask for each bit of the start address s et in MAMR0 to M AMR3.
TMP92CZ26A 92CZ26A-187 (c) Setting memory start add r esses and address areas An example of specifyin g a 64-Kbyte a ddress area startin g from 010000H us ing the CS0 areas i describes. Set 01H in MSAR0<S23 :16> (Correspon ding to the up per 8 bits of the star t address).
TMP92CZ26A 92CZ26A-188 Table 3.8.3 Valid Area Sizes for Each CS Area Size (Byte) CS area 256 512 32 K 64 K 128 K 256 K 512 K 1 M 2 M 4 M 8 M CS0 ○ ○ ○ ○ Δ Δ Δ Δ Δ CS1 ○ ○ ○ Δ Δ Δ.
TMP92CZ26A 92CZ26A-189 (2) Connection Mem ory Spec ificat ion Setting BnCSH<BnO M1:0> specifies the mem ory type to be c onnected with the b lock address areas.
TMP92CZ26A 92CZ26A-190 CPU Dat a Operand Data Si ze ( bi t) Operand St art Address Bus wid th of Mem ory (bit ) C PU Address D31 to D24 D 23 to D16 D15 to D8 D7 to D0 4n + 0 8/ 16/32 4n + 0 xxxxx xxxx.
TMP92CZ26A 92CZ26A-191 (4) Wait control The external bus cycle c o mpletes for two stat es m i nimum(25 ns at f SYS = 80 MHz). Setting the Bn CSL<BnWW3:0> specifies th e number of wa its in the write cycle, and BnCSL<BnWR3:0> spec ifies the number of waits in the read cy cle.
TMP92CZ26A 92CZ26A-192 (5) Recove ry (Data h old) cyc le contr ol S o m e m e m o r y h a v e a n A C s p e c i f i c a t i o n a b o u t d a t a h o l d t i m e f r o m CE or OE for read cycle and a data confliction problem m ay occur.
TMP92CZ26A 92CZ26A-193 (6) Adjust Function for the timing of con tr ol signal This function can change the timing of CSn , CSZx , CSXx , R / W , RD , WRxx , SRWR and SRxxB signals and adjust the timing accord in g to the set-up/hold tim e of the memories.
TMP92CZ26A 92CZ26A-194 RDTMGCR0/1<BnTCRS1:0> 00 TCRS = 0.5 × f SYS (Default) 01 TCRS = 1.5 × f SYS 10 TCRS = 2.5 × f SYS 11 TCRS = 3.5 × f SYS TCRS:The dela y from (CSn) to (RD,SRxxB). Note: TW cycle is inserted by setting BnCSL register . If it is set to 0-Wait, TW cycle is not inserted.
TMP92CZ26A 92CZ26A-195 (7) Basic bus timing (a) External re ad/write cycle (0 waits) (b) External read/write cycle (1 wait) CSn WRxx RD , SRxxB A 23 to A0 In p ut Output Read Write SDCLK (60 MHz) D15 .
TMP92CZ26A 92CZ26A-196 (c) External read bus cycle (1 wait + TAC: 1f SYS + TCRS: 1.5f SYS + TCRH: 1f SYS ) External write bus cycle (1 wait + TAC: 1f SYS + TCWS/H: 1.
TMP92CZ26A 92CZ26A-197 (e) External read/write cycle (4 waits + WAIT pin input mode) (f) External read bus cycle (4 waits + WAIT pin input mode + TAC: 1f SYS + TCRS: 1.5f SYS + TCRH: 1f SYS ) External write bus cycle (4 waits + WAIT pin input mode + TAC: 1f SYS + TCWS/H: 1.
TMP92CZ26A 92CZ26A-198 (8) Connect ing to ex ternal memory Figure 3.8.4 shows an example of ho w to connect external 1 6-bit SRAM and 16 -bit NOR flash to the TMP92C Z26A.
TMP92CZ26A 92CZ26A-199 3.8.4 ROM Page mode Access Control This section describes ROM page mode accessing and how to se t registers. ROM page mode is set by PMEMCR. (1) Operation and how to set the registers TMP92CZ26A supports ROM access with the pa ge mode.
TMP92CZ26A 92CZ26A-200 3.8.5 Internal Boot ROM Control This section describes about bu ilt -in boot ROM. For the specification of S/W in b oot ROM, refer t o the sect ion 3.4 boot ROM. (1) BOOT mode BOOT mode is started by following AM 1 and AM0 pins condition with reset .
TMP92CZ26A 92CZ26A-201 (4) Disap pearing boot ROM After boot sequence in BOOT mode, an appl ication system prog ram m ay continue to run without reset asserting. In this cas e, an ex ternal memory which is map ped 3FE000H to 3FFFFFH address can not be accessed because of boot ROM is assigned.
TMP92CZ26A 92CZ26A-202 3.8.6 Cautions (1) Note the timing betw een CS and RD If the load capacitance of the RD (Read signal) is greater than that of the CS (Chip select signal), it is possible th at an unintended read cycle occu rs due to a dela y in the read signal.
TMP92CZ26A 92CZ26A-203 (2) Note the NAND flash area setting Figure 3.8.8 shows a memory map for NAND flash. And since CS3 area is recommended to assi gn address from 00000 0H to 3FFFFFH, this case is explained. In this case, “NAND flash” and CS3 area ar e overlapped.
TMP92CZ26A 92CZ26A-204 3.9 External Memory Ex tension Function (MMU) This is MMU function which can expand program/ data area to 3. 1G bytes by having 4-type local area.
TMP92CZ26A 92CZ26A-205 0000 00H : Internal area : Overlapped with CO M MO N -Area a nd disabled s etting as LOCAL-area. 4000 00H 8000 00H C0 00 00 H FFFF0 0H FFFFFFH Ad d re ss me mo ry map LOC A L-Z .
TMP92CZ26A 92CZ26A-206 000000H SDCS or 1 CS 128MB or *64MB CSXA to CSXB , EA24 to 28 512MB × 2=1024MB Interna l-I/O a nd Internal RAM LOCAL-X LOCAL-Y LOCAL-Z CSZA to CSZD , EA24 to 28 512MB × 4=2048.
TMP92CZ26A 92CZ26A-207 000000H : Inte rn a l a re a : Overlapped wi th COM M ON -Area and di sabled set ti ng as LOCAL-area. 400000H 800000H C00000H FFFF00H FFFFFFH A dd re s s me mor y ma p LOC AL-Z .
TMP92CZ26A 92CZ26A-208 3.9.2 Control register There are 24-r egisters for MMU. They ar e prepared for 8 -purpose using (as P rogram, read-data, write-data and LCDC-disp lay-data, source-data for odd/even number channel DMA, destination-data for odd/even number channel DM A), and 3-loc al area (LOCAL -X, Y and Z).
TMP92CZ26A 92CZ26A-209 3.9.2.1 Program bank register The bank number use d as program memor y is set to these reg isters. In certain bank, ca nnot diverg e dire ct ly to di ffe ren t b an k of same lo cal area. T o change program bank number in the same local area is disable.
TMP92CZ26A 92CZ26A-210 3.9.2.2 LCD display bank register The bank page used as LCD display m emor y is set to these reg isters. Since the bank re gister for CPU and LCDC are p repared independen tly , th e bank page for CPU (Program, Read-data, write-data) can change d uring L CD display on.
TMP92CZ26A 92CZ26A-21 1 3.9.2.3 Read-data bank regi ster The bank number use d as read-data memory is set t o these registers. The following is an example which read dat a bank register of LOCAL -X is set to “1”. When “ldw wa, (xix)” instruction is exec uted, the bank beco mes effective at onl y read data (operan d) f or xix address.
TMP92CZ26A 92CZ26A-212 3.9.2.4 Write-data ba nk register The bank number used as write data memory is set to thes e registers. The follow ing is an example whi c h data b ank register of L OCAL-X is set to “ 1”. Wh en “ldw (xix), wa” instruction is extended, the bank b ec omes effecti ve at onl y cycle for xix addr ess.
TMP92CZ26A 92CZ26A-213 3.9.2.5 DMA-function bank register In addition to functioning as read/wr ite functi on of CPU, this LSI can also function wh ich transfer data at high-speed b y internal DM AC becoming bus master .
TMP92CZ26A 92CZ26A-214 LOCAL-X register for even-group DMA source 7 6 5 4 3 2 1 0 bit Symbol X7 X6 X5 X4 X3 X2 X1 X0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Set BANK number for LOCAL-X (“0” is disabled because of over lapped with Common-area.
TMP92CZ26A 92CZ26A-215 LOCAL-X register for even-group DMA destination 7 6 5 4 3 2 1 0 bit Symbol X7 X6 X5 X4 X3 X2 X1 X0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Set BANK number for LOCAL-X (“0” is disabled because of over lapped with Common-area.
TMP92CZ26A 92CZ26A-216 LOCAL-X register for odd-group DMA source 7 6 5 4 3 2 1 0 bit Symbol X7 X6 X5 X4 X3 X2 X1 X0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Set BANK number for LOCAL-X (“0” is disabled because of over lapped with Common-area.
TMP92CZ26A 92CZ26A-217 LOCAL-X register for odd-group DMA destination 7 6 5 4 3 2 1 0 bit Symbol X7 X6 X5 X4 X3 X2 X1 X0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Set BANK number for LOCAL-X (“0” is disabled because of over lapped with Common-area.
TMP92CZ26A 92CZ26A-218 3.9.3 Setting example This is in case of using like followin g condition. No. Used as Memo ry Setting MMU-area Logical address Physical address (a) Main Routine COMMON-Z C00000H.
TMP92CZ26A 92CZ26A-219 (b) Sub routine (Bank -0 in LOCAL-Y) Logical address Physical address No Instruction Comment 16 org 4000 00H ; 400000H 000000H 17 ldw (localwy),8001H ; Bank1 in LOCAL-Y is set t.
TMP92CZ26A 92CZ26A-220 3.10 SDRAM Controller (SDRAMC) The TMP92CZ 26A incorpora tes an SDRA M contro ller (SDRA MC) for ac cessing SD RAM that can be used as data memory , program memory , or display memory .
TMP92CZ26A 92CZ26A-221 3.10.1 Control Registers The SDRAMC has the fol lo win g control registers. SDRAM Access Control Register 7 6 5 4 3 2 1 0 Bit symbol SRDS – SMUXW1 SMUXW0 SPRE SMAC Read/Write .
TMP92CZ26A 92CZ26A-222 SDRAM Command Register 7 6 5 4 3 2 1 0 Bit symbol SCMM2 SCMM1 SCMM0 Read/Write R/W After reset 0 0 0 Function Command issue (Note 1) (Note 2) 000: Don’t care 001: Initialization sequence a. Precharge All command b. Eight Auto Refresh commands c.
TMP92CZ26A 92CZ26A-223 3.10.2 Operation Description (1) Memory access control The SDRAMC is enabled by setting SDACR<S MAC> to “1”. When one of the bus mast ers (CPU, LCDC, DMA C) generates a cycl e to acc ess the SDRAM address area, the SDRAMC out p uts SDRAM control signals.
TMP92CZ26A 92CZ26A-224 (b) Address multip lex function In access cycles, the A0 to A15 pins output low/column m ultiplexed addresses. The multiplex width is set by SDAC R<SMUXW1:0>. T able3.10.2 shows the relationship between the multiplex width and low/ column addresses.
TMP92CZ26A 92CZ26A-225 Figure3.10.2 1-Word Read Cycle T iming Figure3.10.3 Full-Page Read Cycle Timing SDCLK SDCKE SDLUDQM SDLLDQM SDCS SDR AS SDC AS SDW E A10 A15-A0 D15-D0 RA Bank Active RA CA (n) C.
TMP92CZ26A 92CZ26A-226 Figure3.10.4 Single Write Cycle Timing Figure3.10.5 Burst W rite Cycle T iming SDCLK SDCKE SDLUDQM SDLLDQM A10 A15-A0 D15-D 0 RA Bank Active RA CA (n) CA (n+2) D (n+2) Wr ite tR.
TMP92CZ26A 92CZ26A-227 (2) Execution of instructions on SDRA M The CPU can execu te instructions th at are stored in the SDRAM. H owever , the following operations cannot be performed.
TMP92CZ26A 92CZ26A-228 (d) Precharge c o mmand (e) Read cycle (f) W rite cyc le COMMAND PRECHARGE SDCLK Next Command NOP NOP NOP TRP *TRP=2CLK (SDCISR <ST RP>= “1”) SDCLK COMMAND NOP ACTIVE .
TMP92CZ26A 92CZ26A-229 (4) Read data shift function If the AC specific ations of the SDRA M cannot be satisfie d when data is read fr om the SDRAM, the read data can be latched in a port circuit so that the CPU can read the data in the next state. When this read data shift functi on is used, the read cycle req uires additio nal one state.
TMP92CZ26A 92CZ26A-230 (c) Full-page read, the rea d data shift function enabled (SD ACR<SRDS> = “1”, <SRDSCK> = “0”) (5) Read/W rite commands The Read/W rite comma nds to be used in 1-word rea d/single writ e mode can be specified by using SDACR<SPRE>.
TMP92CZ26A 92CZ26A-231 (6) Refresh control The TMP92CZ26 A suppor ts two kinds of refresh comm ands: Au to Refresh and Self Refr esh. (a) Auto Refresh When SDRCR<SRC> is set to “1”, the Auto Re fresh command is automatical ly issued at intervals specified by SD RCR<SRS2:0>.
TMP92CZ26A 92CZ26A-232 (b) Self Refresh The Self Refresh Entry c ommand is issued by setting SD CMM<SCMM2:0> to “10 1”. Figure3.10.7 shows the Self R efresh cycle tim ing. O nce Self Refr esh is started, the SDRAM is refreshed internally wit hout th e need to issue the Auto Refresh command.
TMP92CZ26A 92CZ26A-233 The Self Refr esh state can be exit ed by the Self R efresh Exit com mand. The Self R efresh Exit command is exec uted when SDCM M<SCMM2:0> is set to “1 10”. It is also executed automaticall y in synchronization w ith HAL T mode release.
TMP92CZ26A 92CZ26A-234 (7) SDRAM initializ ati on sequenc e After reset releas e, the followin g sequence o f commands can be executed to initialize the SDRAM. 1. Precharge All comm and 2. Eight Auto Refresh commands 3. Mode Register Set co mmand The above com mands are issued by setting SDCMM<S CMM2:0> to “001 ”.
TMP92CZ26A 92CZ26A-235 (8) Connection example Figure3.10.10 shows an example of connectio ns between th e TMP92CZ26A and SDRAM. T able3.10.4 Pin Connections SDRAM Pin Name Data Bus Width 16 bits 92CZ2.
TMP92CZ26A 92CZ26A-236 3.10.3 An Example of Calculating HDMA T ransfer T i me The followin g shows an example of calculating th e HDMA transfer tim e when SDRAM is used as the transfer source.
TMP92CZ26A 92CZ26A-237 3.10.4 Considerations for Using the SDRAMC This section describes the points that must be taken into account when using the SDRAMC. Please carefull y rea d the following t o ensure proper use of th e S DRAMC. 1) W AIT access When SDRAM is used, the fo llowing restriction appli es to memory access to other than the SDRAM.
TMP92CZ26A 92CZ26A-238 3.11 NAND Flash Controller (NDFC) 3.11.1 Features The NAND Flash Contro ller (NDFC) is provi ded with dedicated pins for conn ecting with NAND Flash memory . The NDFC also has an ECC calculati on function for error c orrection and s upports two types of ECC calculation met hods.
TMP92CZ26A 92CZ26A-239 3.11.1 Block Diagram Figure 3.1 1.1 Block Diag ram for NAND Flash Control l er ND _ CE* ND _ RE * ND _ ALE ND _ CLE ND WE * ND _ RB * DA T A_IN[15:0] NAND Flash Controller Ch an.
TMP92CZ26A 92CZ26A-240 3.11.2 Operation Description 3.11.2.1 Accessing NAND Flash Memory The NDFC accesses data on NAND Flash me mory indirectly through its internal registers.
TMP92CZ26A 92CZ26A-241 The NDRE and NDWE signals are exp lained next. W rite an d read operations to and from the NAND Flash are perfor med through the ND0FDTR register . The actual write operati on completes not when the ND0FDTR re gister is writ ten to but when the data is written to the external NA ND Flash.
TMP92CZ26A 92CZ26A-242 3.11.3 ECC Control NAND Flash memory device s may inh erently include error bits. It is therefore necessary to implement t he err or correction proc essing using ECC (Err or Correction Co de). Figure 3.1 1.4 shows a basic flowchart for ECC control.
TMP92CZ26A 92CZ26A-243 3.11.3.1 Differences between Ha mm ing Codes and Reed -Solomon Codes The NDFC includes an ECC generator suppo rt ing NAND Flash memo ry devices of SLC (or 2LC: two states) typ e and MLC (or 4LC: four st ates) type.
TMP92CZ26A 92CZ26A-244 3.11.3.2 Error Correction Methods Hamming ECC • The ECC generator generates 44 bits of ECC for a page containing 512 bytes of valid data. The error correction process must be performed in units of 256 b y tes (22 bits of ECC).
TMP92CZ26A 92CZ26A-245 Reed-Sol omon ECC • The ECC gene rator generates 80 bits of ECC for u p to 518 bytes of valid data. If the NAND Flash to be used has a large-capacity page size (e.g. 2048 byte s), the error correction process must be repeated several times to cover the entire page.
TMP92CZ26A 92CZ26A-246 3.11.4 Description of Registers NAND Flash Control 0 Registe r 7 6 5 4 3 2 1 0 bit Symbol WE ALE CLE CE0 CE1 ECCE BUS Y ECCRST Read/Write R/W R/W R/W R/W R/W R/W R W After reset.
TMP92CZ26A 92CZ26A-247 (c) <ECCE> The <ECCE> bit is used for b oth Hamming and Re ed -Solomon cod es. This bit is used to enable or disabl e the ECC generator. T o reset the ECC in the ECC generator (to set <ECCRST> to “1”), the ECC ge nerator must be enable d (<ECCE> = “1”).
TMP92CZ26A 92CZ26A-248 (i) <RSECCL> The <RSECCL> bit is used on ly for Reed-Sol omon codes. When using Ha mming codes, this bit should be set to “0”. The Reed-So lomon proces sing unit is compris ed of two el ements: an ECC g enerator and an ECC calculat or.
TMP92CZ26A 92CZ26A-249 NAND Flash Control 1 Register 7 6 5 4 3 2 1 0 bit Symbol INTERDY INTRSC BUSW ECCS SYSCKE Read/Write R/W R/W R/W R/W R/W After reset 0 0 0 0 0 Function Ready interrupt 0: Disable.
TMP92CZ26A 92CZ26A-250 This bit is used t o enab le or d isable t h e in terrupt t o b e gen erate d wh en the c alcu lat ion of error address and error b it pos ition has ended. The interrupt is enabled when th is bit is set to “1” and disabled when “0”.
TMP92CZ26A 92CZ26A-251 NAND Flash Data Registe r 0 7 6 5 4 3 2 1 0 bit Symbol D7 D6 D5 D4 D3 D2 D1 D0 Read/Write R/W After reset Undefined Undefined Undefined U ndefined Undefined Undefi ned Undefined.
TMP92CZ26A 92CZ26A-252 T able 3.1 1.3 How to Access the NAND Flash Data Registe r Writ e Access Data Size Example of instruct ion 8-bit NAND Flas h 16-bit NAND Flash 1-byte access ld (0x1FF0),a Suppor.
TMP92CZ26A 92CZ26A-253 NAND Flash ECC Register 0 7 6 5 4 3 2 1 0 bit Symbol ECCD7 ECCD6 ECCD5 ECCD4 ECCD3 ECCD2 ECCD1 ECCD0 Read/Write R After reset 0 0 0 0 0 0 0 0 Function NAND Flash EC C Register (.
TMP92CZ26A 92CZ26A-254 The NAND Flash ECC regist er is used to re ad ECC generated by the ECC generator . After valid data has been written to or r e a d f r o m t h e N A N D F l a s h , s e t t i n g NDFMCR0<ECCE> to “0” causes the correspon ding ECC to be set in this registe r .
TMP92CZ26A 92CZ26A-255 NAND Flash Reed-Solomo n Calculation Result Address Regi ster 7 6 5 4 3 2 1 0 bit Symbol RS0A7 RS0A6 RS0A5 RS0A4 RS0A3 RS0A2 RS0A1 RS0A0 Read/Write R After reset 0 0 0 0 0 0 0 0.
TMP92CZ26A 92CZ26A-256 If error is found at only one address, the error address is stored in the NDRSCA0 register . If error is found at two addresses, the NDRS CA0 and NDRSCA1 register s are used to store the error addresses. In this manner , up to four error addres ses can be stor ed in the NDRSCA0 to NDRSCA 3 reg isters.
TMP92CZ26A 92CZ26A-257 3.11.5 An Example of Accessing NAND Flash of SLC T ype 1. Initialization ; ; ***** Initialize NDFC ***** ; Conditions: 8-bit bus, CE0, SLC, 512 (5 28) b ytes/page, Hamming codes ; ld (ndfmcr1),0001h ; 8-bit bus, Hamming ECC, SYSCK-ON ld (ndfmcr0),2000h ; SPL W1:0=0, SPHW1:0=2 2.
TMP92CZ26A 92CZ26A-258 Executing pa ge pr ogram ; ***** Set auto page program***** ; ldw (ndfmcr0),20B0h ; WE enable, CLE enable l d ( ndfdtr0),1 0h ; Aut o page prog ram command ldw (ndfmcr0),2010h ; WE disable, CLE disable ; ; W ait setup time (from Busy to Ready) ; 1.
TMP92CZ26A 92CZ26A-259 3. Read Reading vali d data ; ***** Read val id data**** * ; ldw (ndfmcr0),2010h ; CE0 enable ldw (ndfmcr0),20B0h ; WE enable, CLE enable ld (ndfdtr0),00h ; Read command ldw (ndfmcr0),20D0h ; ALE enable ld (ndfdtr0),xxh ; Address write (3 or 4 times) ; ; W ait setup time (from Busy to Ready) ; 1.
TMP92CZ26A 92CZ26A-260 4. ID Read The ID read routine is as fo ll ows: ldw (ndfmcr0),20B0h ; WE Enable, CLE enable ld (ndfdtr0),90h ; W rite ID read command ldw (ndfmcr0),20D0h ; ALE enable, CLE disa .
TMP92CZ26A 92CZ26A-261 3.11.6 An Example of Accessing NAND Flash of MLC T ype (When the valid dat a is processed as 518byte) 1. Initialization ; ; ***** Initialize NDFC ***** ; Conditions: 16-bit bus,.
TMP92CZ26A 92CZ26A-262 W riting ECC to NAND Flash ; ***** W rit e dummy data & ECC ***** ; ldw (ndfmcr0),5088h ; ECC circuit disable, data write mode ldw (ndfdtr0),xxxxh ; Redundancy area data wri.
TMP92CZ26A 92CZ26A-263 3. Read (including ECC data read) Reading vali d data ; ***** Read val id data**** * ; ldw (ndfmcr0),5008h ; CE1 enable ldw (ndfmcr0),50A8h ; WE enable, CLE enable ldw (ndfdtr0).
TMP92CZ26A 92CZ26A-264 4. ID Read The ID read routine is as fo ll ows: ldw (ndfmcr0),50A8h ; WE enable, CLE enable ldw (ndfdtr0),0090h ; W rite ID read command ldw (ndfmcr0),50C8h ; ALE enable, CLE di.
TMP92CZ26A 92CZ26A-265 3.11.7 An Example of Connections with NAND Flash Note 1: A rese t set s the NDRE and NDWE pins as input ports, so pu ll-up resistors are needed. Note 2: The pull-up resi st or value for the NDR/B pin must be set appropriately accord ing to the NAND Flash memory to be used an d the capacity of the boa rd (typical : 2 K Ω ).
TMP92CZ26A 92CZ26A-266 3.12 8 Bit Timer (TMRA) The TMP92C Z26A feature s 8 channel ( TMRA0 to TMRA 7) built-i n 8-bit ti mers. These timers are paired into 4 modules: TMRA01, TMRA23, TMRA45 and TMRA67. Each module consists of 2 chan nels and can operat e in any of the fol l owing 4 opera ting m odes.
TMP92CZ26A 92CZ26A-267 3.12.1 Block Diagram Figure 3.12.1 TMRA01 Block Diagram φ T1 φ T16 φ T256 8-bit comparator (CP1) 8-bit up counter (CP0) 8-bit up counter (UC0) 2 n Over flow 8-bit up counter .
TMP92CZ26A 92CZ26A-268 Figure 3.12.2 TMRA23 Block Diagram φ T1 φ T16 φ T256 8-bit comparator (CP3) 8-bit comparator (CP2) 8-bit up counter (UC2) 2 n Over flow 8-bit up comparator (UC3) Timer flip-f.
TMP92CZ26A 92CZ26A-269 Figure 3.12.3 TMRA45 Block Diagram φ T1 φ T16 φ T256 8-bit comparator (CP5) 8-bit comparator (CP4) 8-bit up counter (UC4) 2 n Over flow 8-bit up comparator (UC5) Timer flip-f.
TMP92CZ26A 92CZ26A-270 Figure 3.12.4 TMRA67 Block Diagram φ T1 φ T16 φ T256 8-bit comparator (CP7) 8-bit comparator (CP6) 8-bit up counter (UC6) 2 n Over flow 8-bit up comparator (UC7) Timer flip-f.
TMP92CZ26A 92CZ26A-271 3.12.2 Operation of Each Circuit (1) Prescaler A 9-bit prescal er generates the input clock to TMRA01.The cl ock φ T0 is selected using the prescaler c lock s election regis ter SYS CR0<PRCK>. The prescaler operati on can be controlled using TA01RUN<TA 0PRUN> in the timer control register.
TMP92CZ26A 92CZ26A-272 (3) Timer registers (TA0 RE G and TA 1REG) These are 8-bit registers, which can be used to set a tim e interval. When the value set in the timer re gister TA0 REG or TA1 REG ma tches th e v alue in the c or respond ing up counter, the comparator match detect si gnal goes active.
TMP92CZ26A 92CZ26A-273 (4) Comparator (CP0, CP 1) The compara tor compares the va lue in an up counter with th e value set in a timer register. If they match, the up c ounter is cleared to 0 and an interrupt sign al (INTTA0 or INTTA1) is generated. If tim er flip-flop inversi on is enabled, the timer fl ip-flop is inverted at the same time .
TMP92CZ26A 92CZ26A-274 3.12.3 SFR TMRA01 RUN Register 7 6 5 4 3 2 1 0 Bit symbol TA0RDE I2TA01 TA01PRUN TA1RUN TA0RUN Read/Write R/W R/W After Reset 0 0 0 0 0 TMRA01 prescaler Up counter (UC1) Up coun.
TMP92CZ26A 92CZ26A-275 TMRA45 RUN Register 7 6 5 4 3 2 1 0 Bit symbol TA4RDE I2TA45 TA45PRUN TA5RUN TA4RUN Read/Write R/W R/W After Reset 0 0 0 0 0 TMRA45 prescaler Up counter (UC5) Up counter (UC4) F.
TMP92CZ26A 92CZ26A-276 TMRA01 Mode Register 7 6 5 4 3 2 1 0 Bit symbol TA01M1 TA01M0 PWM01 PWM 00 TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Operation mode 00:.
TMP92CZ26A 92CZ26A-277 TMRA23 Mode Register 7 6 5 4 3 2 1 0 Bit symbol TA23M1 TA23M0 PWM21 PWM 20 TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Operation mode 00:.
TMP92CZ26A 92CZ26A-278 TMRA45 Mode Register 7 6 5 4 3 2 1 0 Bit symbol TA45M1 TA45M0 PWM41 PWM 40 TA5CLK1 TA5CLK0 TA4CLK1 TA4CLK0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Operation mode 00:.
TMP92CZ26A 92CZ26A-279 TMRA67 Mode Register 7 6 5 4 3 2 1 0 Bit symbol TA67M1 TA67M0 PWM61 PWM 60 TA7CLK1 TA7CLK0 TA6CLK1 TA6CLK0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Operation mode 00:.
TMP92CZ26A 92CZ26A-280 TMRA1 Flip-Flop Control Register 7 6 5 4 3 2 1 0 Bit symbol TA1FFC1 TA1FFC0 TA1FFIE TA1FFIS Read/Write R/W R/W After reset 1 1 0 0 Function 00: Invert TA1FF 01: Set TA1FF 10: Cl.
TMP92CZ26A 92CZ26A-281 TMRA3 Flip-Flop Control Register 7 6 5 4 3 2 1 0 Bit symbol TA3FFC1 TA3FFC0 TA3FFIE TA3FFIS Read/Write R/W R/W After reset 1 1 0 0 Function 00: Invert TA3FF 01: Set TA3FF 10: Cl.
TMP92CZ26A 92CZ26A-282 TMRA5 Flip-Flop Control Register 7 6 5 4 3 2 1 0 Bit symbol TA5FFC1 TA5FFC0 TA5FFIE TA5FFIS Read/Write R/W R/W After reset 1 1 0 0 Function 00: Invert TA5FF 01: Set TA5FF 10: Cl.
TMP92CZ26A 92CZ26A-283 TMRA7 Flip-Flop Control Register 7 6 5 4 3 2 1 0 Bit symbol TA7FFC1 TA7FFC0 TA7FFIE TA7FFIS Read/Write R/W R/W After reset 1 1 0 0 Function 00: Invert TA7FF 01: Set TA7FF 10: Cl.
TMP92CZ26A 92CZ26A-284 Timer Registers 7 6 5 4 3 2 1 0 bit Symbol − − − − − − − − Read/Write W After reset 0 0 0 0 0 0 0 0 bit Symbol − − − − − − − − Read/Write W After.
TMP92CZ26A 92CZ26A-285 3.12.4 Operation in Each Mode (1) 8-b it tim er mode Both TMRA0 and TMRA1 can be used independent l y as 8-b it interval timers.
TMP92CZ26A 92CZ26A-286 b. Generating a 50% duty ratio square wave puls e The state of the t imer flip-fl op (TA1FF) is in verted at constant int ervals and its status output via the tim er output pin (TA1O UT).
TMP92CZ26A 92CZ26A-287 c. Making TMRA1 count up on the match signal fr om the TMRA0 comparator Select 8-bit timer mode and set the comp arator output from TMRA0 t o be the input clock to TMRA1.
TMP92CZ26A 92CZ26A-288 The comparator match sign al is output from TMRA0 each time the up counte r UC0 matches TA0REG, though the up count er UC0 is not be clear ed. In the case of the T MRA1 comparat or, the match det ect signal is output on each comparator puls e on which the values in the up count er UC1 and TA1REG m atch.
TMP92CZ26A 92CZ26A-289 In this mode a programmable square wave is generated b y inverting the timer output each time the 8 -bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0RE G must be smaller than th e va lue set in TA1REG.
TMP92CZ26A 92CZ26A-290 Example: T o generate 1/4 duty 31.25 kHz pulses (at f C = 50 MHz) * Clock state Clcok gear : 1/1 Prescaler of clock gear : 1/2 Calculate the value which should be set in the timer register. To obtain a frequency of 31.25 kHz, the pulse cycle t should be: t = 1/31.
TMP92CZ26A 92CZ26A-291 (4) 8-bit PWM (Pulse width m odulation) outp ut mode This mode is only valid fo r TMRA0. In this mode, a PWM pulse with th e maximum resolution of 8 bits can b e outp ut. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (Shar ed with PM1).
TMP92CZ26A 92CZ26A-292 In this mode the value of the regist er buffer will be shifted int o TA0REG if 2 n overflow is det ecte d wh en the TA0R E G double buffer is enab led. Use of the double buffer facilitates th e handling of low dut y ratio waves.
TMP92CZ26A 92CZ26A-293 Table 3.12.3 PWM Cycle PWM cycle TAxxMOD<PWMx1:0> 2 6 (x64) 2 7 (x128) 2 8 (x256) TAxxMOD<TAxCLK1:0> TAxxMOD<TA xCLK1:0> TAxxMOD<TAxCLK1:0> Clock gear se.
TMP92CZ26A 92CZ26A-294 3.13 16 bit timer / Event counter (TMRB) The TMP92CZ26A inc orporates two multi functional 16-bit tim er/event counter (TMR B0, TMRB1) which have the following operation mode s:.
TMP92CZ26A 92CZ26A-295 3.13.1 Block diagram Figure 3.13.1 Block diagram of TMRB0 Internal data bus Slelector 16-bit comparator (CP10) TB0MOD<TB0CLK1:0> φ T1 φ T4 φ T16 Timer flip-flop control.
TMP92CZ26A 92CZ26A-296 Figure 3.13.2 Block diagram of TMRB1 Internal data bus Slelector 16-bit comparator (CP12) TB1MOD<TB1CLK1:0> φ T1 φ T4 φ T16 Timer flip-flop control TB1FF0 TB1OUT0 Match.
TMP92CZ26A 92CZ26A-297 3.13.2 Operation (1) Prescaler The 5-bit prescaler generates the source cloc k for TMRB0. The prescaler clock ( φ T0) is selected by the reg ister SYSCR0<PRC K> of clock gear. This prescaler can be started or stopped using TB0RUN<T B0RUN>.
TMP92CZ26A 92CZ26A-298 (3) Timer registers (T B0RG0H/L, TB0RG1H/L) These two 1 6-bit register s are used to set the inter val time. Wh en the value in the up counter UC10 matches the value set in this tim er register, the comparator match detect signal will go active.
TMP92CZ26A 92CZ26A-299 TB0RG0H/L and the regist er buffer 10 both have th e same memory addresses (1188H and 1189 H) allocated to them. If <TB0RDE> = “0”, the value is wr itten to both the timer register and th e register buff er 10. If <TB0RDE> = “1 ”, the value is written to the register buffer 10 only.
TMP92CZ26A 92CZ26A-300 (4) Capture reg isters (TB0CP0H/L, TB0CP1H/L) These 16-bit reg isters ar e used to latch the va lues in the up cou n ter (U C10). Data in the capture registers shoul d be read all 16 bits. For exam ple, using a 2-byte data load instruction or two 1- byte da ta load instr uctions.
TMP92CZ26A 92CZ26A-301 (6) Comparat ors (CP10, CP1 1) CP10 and CP11 are 16-bit compar ators which compare the va lue in the up counter UC10 with the value set in TB0RG0H/L or TB0RG1H/L respectively, in order to detect a match. If a match is detected, the comparator generates an interrupt (IN TTB00 or INTTB01 respectively).
TMP92CZ26A 92CZ26A-302 3.13.3 SFR TMRB0 RUN Register 7 6 5 4 3 2 1 0 Bit symbol TB0RDE − I2TB0 TB0PRUN TB0RUN Read/Write R/W R/W R/W R/W R/W After Reset 0 0 0 0 0 TMRB0 prescaler Up counter (UC10) F.
TMP92CZ26A 92CZ26A-303 TMRB0 Mode Register 7 6 5 4 3 2 1 0 Bit symbol − − TB0CP0I TB0CPM1 TB0CPM0 TB0CLE TB0CLK1 TB0CLK0 Read/Write R/W W * R/W After Reset 0 0 1 0 0 0 0 0 Function Always write “0”.
TMP92CZ26A 92CZ26A-304 TMRB1 Mode Register 7 6 5 4 3 2 1 0 Bit symbol − − TB1CP0I TB1CPM1 TB1CPM0 TB1CLE TB1CLK1 TB1CLK0 Read/Write R/W W * R/W After Reset 0 0 1 0 0 0 0 0 Function Always write “0”.
TMP92CZ26A 92CZ26A-305 TMRB0 Flip-Flop Control Register 7 6 5 4 3 2 1 0 Bit symbol − − TB0C1T1 TB0C0T1 TB0E1T1 TB0 E0T1 TB0FF0C1 TB0FF0C0 Read/Write W * R/W W* After Reset 1 1 0 0 0 0 1 1 TB0FF0 inversion trigger 0: Disable trigger 1: Enable trigger Function Always write “11” *Always read as “11”.
TMP92CZ26A 92CZ26A-306 TMRB1 Flip-Flop Control Register 7 6 5 4 3 2 1 0 Bit symbol − − TB1C1T1 TB1C0T1 TB1E1T1 TB1 E0T1 TB1FF0C1 TB1FF0C0 Read/Write W * R/W W * After Reset 1 1 0 0 0 0 1 1 TB1FF0 inversion trigger 0: Disable trigger 1: Enable trigger Function Always write “11” *Always read as “11”.
TMP92CZ26A 92CZ26A-307 7 6 5 4 3 2 1 0 bit Symbol − − − − − − − − Read/Write W After reset 0 0 0 0 0 0 0 0 bit Symbol − − − − − − − − Read/Write W After reset 0 0 0 0 0.
TMP92CZ26A 92CZ26A-308 3.13.4 Operation in Each Mode (1) 16 bit timer mod e Generating interrupts at fixed intervals In this example, the interrupt INTTB01 is se t to be gen erated at fixed intervals. The interval time is set in th e timer register TB0RG1H/ L.
TMP92CZ26A 92CZ26A-309 (3) 16-bit progr ammable pulse generation (PPG) output mode Square wave puls es can be generat ed at any fr equency and dut y ratio.
TMP92CZ26A 92CZ26A-310 The following block diagr am illustrates this m ode. Figure 3.13.11 Block Diagram of 16-Bit Mode The following ex ample shows how to s et 16-bit PPG outp ut mode: 7 6 5 4 3210 TB0RUN ← 0 0 X X – – X 0 Disable the TB0RG0 double buffer and stop TMR B0.
TMP92CZ26A 92CZ26A-311 (4) Applic ation examples of captur e funct ion Used capture functi on, they can be applied in m a ny ways, for exam ple; 1. One-shot pulse output from externa l trig ger pulse 2. Frequency measurement 3. Pulse width measurement 1.
TMP92CZ26A 92CZ26A-312 Example: To output 2m s one-shot pu lse with 3ms dela y to the external trigger pulse to TB0IN0pin *Clock state System clock : f SYS Prescaler clock : f SYS /4 Main setting Free.
TMP92CZ26A 92CZ26A-313 Figure 3.13.13 One-shot Pu lse Output (without delay) 2. Frequency measurement The frequenc y of the external cl ock can be measure d in this mode. The cl ock is input through the TB0IN 0 pin, and its freq uency is measured b y the 8 bit timers TMRA01 and the 16 bit timer/event c ount er (TMRB0).
TMP92CZ26A 92CZ26A-314 3. Pulse width measurement This mode allows measu ring the H level wid th of an external pulse. Wh ile keeping the 16 bit timer/event counte r cou nting (free-runn ing) with the internal clock input, th e external puls e is input through the TB 0IN0 pin.
TMP92CZ26A 92CZ26A-315 3.14 Serial Channels (SIO) TMP92CZ26A includes 1 se rial I/O ch annel (SIO0 ). For both cha nnels eithe r UART mode (Asynchronous transmission ) or I/O interface mode (Synchrono us transmi ssion) can be selected. And, SIO0 includes data modulator th at supports the IrDA 1.
TMP92CZ26A 92CZ26A-316 3.14.1 Block Diagram Figure 3.14.2 Block Diagram Selector φ T0 φ T2 φ T8 φ T32 SC0MOD0 <SC1:0> Receive buffer 1 (Shift register) RXDCLK SC0MOD0 <CTSE> Prescaler .
TMP92CZ26A 92CZ26A-317 3.14.2 Operation of Each Circuit (1) Prescaler There is a 6-bit prescaler for gen erating a clock to SIO0. The prescaler can be run by selecting the baud rate generator as the seri al tra nsfer clock. Table 3.14.1 shows prescaler clock r eso lution into th e baud rate generator.
TMP92CZ26A 92CZ26A-318 (2) Baud rate generator The baud rate generator is the circuit whic h generates transm issi on/receiv ing clock and determines the trans fer rat e of the serial channels. The input clock to the baud rate generator, φ T0, φ T2, φ T8 or φ T32, is generated by the 6-bit prescaler which is shared by the ti mers.
TMP92CZ26A 92CZ26A-319 • I nteger divider (N divider) For example, when the source clock fr equency (f c ) is 19.6608 MHz, the input clock is φ T2, the frequency div ider N (BR0CR<BR0S3:0>) = 8, and BR0CR<BR0 ADD E> = 0, the ba ud rate in UART Mode is as follows: *Clock state System clock : 1/1 Prescaler clock : 1/2 Baud Rate = = 19.
TMP92CZ26A 92CZ26A-320 Table 3.14.2 Transfer Rate Selection (When baud rate generator is used and BR0 CR<BR0ADDE> = 0) f SYS [MHz] Input Clock Frequency Divider N φ T0 (f SYS /4) φ T2 ( f SYS /16) φ T8 (f SYS /64) φ T32 (f SYS /256) 7.3728 1 115.
TMP92CZ26A 92CZ26A-321 (3) Serial clock ge neration circuit This circuit generates the basic clock for transmitting and rec eiving data. • In I/O Interface Mode In SCLK Output Mode with the setting SC0CR<IOC> = 0, the basic clock is generated by divid ing the output of the baud rate gen erator by 2, as described previously.
TMP92CZ26A 92CZ26A-322 (6) The R ece iv ing Buffers To prevent Overrun err ors, the Receiving Buffers are arrange d in a double-buffer structure. Received d ata is stored on e bit at a time in R eceiving B uffer 1 (which is a shif t register).
TMP92CZ26A 92CZ26A-323 (8) Transmission controller • In I/O Interface Mode In SCLK Output Mode with the setting S C0CR<IOC> = 0, the da ta in the Transmission Buffer is output one bit at a ti m e to the TXD0 pin on the rising edge or falling of the shift clock which is output on the SCLK0 pin, according to the SC0CR<SCLKS> setting.
TMP92CZ26A 92CZ26A-324 Handshake function Serial Channels 0 has a 0 CTS pin. Use of this pin allows data can be sent in units of one frame; t hus, Overrun err ors can be avoided. The handshake f unctions is enabled or disabled by the SC0 M OD <CTSE> setting.
TMP92CZ26A 92CZ26A-325 (9) Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU f orm the least signif icant bit (LSB) in order. When a ll the bits are shifted out, the transmission buffer bec omes empty and generates an INTTX0 interrupt.
TMP92CZ26A 92CZ26A-326 2. Parity error <PERR> The parity generated for the d ata shifte d into rece iving buffer 2 (SC 0BUF) is compared wi th the parity bit rec eived via the RXD pin. If th ey are not equa l, a parity error is generated. Note: The parity error flag is cleared every time it is read.
TMP92CZ26A 92CZ26A-327 (12) Timing generation a. In UART Mode Receiving Mode 9-Bit (Note) 8-Bit + Parity (Note) 8-Bit, 7-Bit + Parity, 7-Bit Interrupt timing Center of last bit (bit 8) Center of last .
TMP92CZ26A 92CZ26A-328 3.14.3 SFR 7 6 5 4 3 2 1 0 Bit symbo l TB8 CTSE RXE W U SM1 SM0 SC1 SC0 Read/W rite R/W Afte r Reset 0 0 0 0 0 0 0 0 Function Transf er data b it 8 Hand s hak e 0: CTS disabl e .
TMP92CZ26A 92CZ26A-329 7 6 5 4 3 2 1 0 bi t S ymbol RB8 EVEN PE OERR PERR FERR SCLKS IOC R ead/W r it e R R/W R (c l ear ed t o 0 wh en r ead) R/W Af ter R e s et U ndefi n ed 0 0 0 0 0 0 0 Funct i on.
TMP92CZ26A 92CZ26A-330 7 6 5 4 3 2 1 0 Bit sy mbol − BR0ADDE BR0CK1 BR0CK0 BR0S3 B R0S2 B R0S1 BR0S0 Read/Write R/W After Reset 0 0 0 0 0 0 0 0 Function Alway s write “0” + (16 − K)/16 divisio.
TMP92CZ26A 92CZ26A-331 7 6 5 4 3 2 1 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 (Transmission) SC0BUF (1200H) 7 6 5 4 3 2 1 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 (Receiving) Note: Prohibit read modify write for SC0BU F.
TMP92CZ26A 92CZ26A-332 3.14.4 Operation in each mode (1) Mode 0 (I/O Interfac e M ode) This mode allows an increas e in the number of I/O pins available for transmitti ng data to or receiving data from an external shift register.
TMP92CZ26A 92CZ26A-333 a. Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writ es the data to the Transmission Buffer. When all data is output, INTES0 <ITX0C> will be set to generate the INTTX0 interrupt.
TMP92CZ26A 92CZ26A-334 b. Receiving In SCLK Output Mode the synchron ous clock is output on the SCLK0 pin and the data is shifted to Receiving Buf fer 1. This is initiated when th e R eceive Interrupt flag INTES0<IRX0C> is cleared as the received da ta is read.
TMP92CZ26A 92CZ26A-335 c. Transmission and Receiving (Fu ll Duplex Mod e ) When Full Dupl ex M ode i s used, set th e Rec eive Interrupt L evel to 0 and s et enable the level of tr ansmit interrupt(1 to 6). En sure that the pr ogram which tr ansmits the interrupt reads the receiving buffer b efore setting the next tran smit data.
TMP92CZ26A 92CZ26A-336 (2) Mode 1 (7-bit UART Mod e ) 7-Bit UART Mod e is selected by sett ing the Serial Chan nel Mode Register SC0MOD0<SM1:0> field to 01.
TMP92CZ26A 92CZ26A-337 Main routine 7 6543210 P9CR ← X XX XX − 0 − Set P91 to function as the RXD0 pin. P9FC ← − − XXX − X − SC0MOD0 ← − − 1 − 1 0 0 1 Enable receiving in 8-bit UART mode. SC0CR ← − 01 − − − − − Add odd parity.
TMP92CZ26A 92CZ26A-338 Protocol 1. Select 9-Bit UART Mode on th e master and slave c ontrollers. 2. Set the SC0MOD0<WU> bit on each slave co ntro ller to 1 to enabl e data receiving. 3. The master controller tra nsmits data one frame at a time. Each frame includ es an 8-bit select code which ident ifies a slave co ntroller.
TMP92CZ26A 92CZ26A-339 Setting exam ple: To link two slave controllers seri ally with the m aster controller us ing the internal clock f IO as the transfer cloc k.
TMP92CZ26A 92CZ26A-340 3.14.5 Support for IrDA SIO0 includes support for the IrDA 1.0 in fr ared data communication specification. Figure 3.14.8 shows the bl ock di agram.
TMP92CZ26A 92CZ26A-341 (3) Data format The data format is fixe d as fo llows: • Data length: 8-bit • Parity bits: none • Stop bits: 1bit (4) SFR Figure 3.14.21 shows the control regis ter SIRCR. Set the data SIRCR during SIO0 is stopping. The follo win g example de scribes h ow to set this register: 1) SIO setting ; Set the SIO to UART Mode.
TMP92CZ26A 92CZ26A-342 (5) Notes 1. Baud rate for IrDA When IrDA is operated, set 01 to SC0MOD0<SC1:0> to generate baud-rate. The setting exce pt abov e ( TA0T RG, f IO and SCLK0-input) ca nnot be used. 2. The pulse width for transmission The IrDA 1.
TMP92CZ26A 92CZ26A-343 7 6 5 4 3 2 1 0 Bit symbol PLSEL RXSEL TXEN RXEN SIR WD3 SI RWD2 SIRWD1 S IRWD0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Select transm it pulse widt h 0: 3/16 1: 1/16.
TMP92CZ26A 92CZ26A-344 3.15 Serial Bus Interface (SBI) The TMP92CZ26A has a 1-channel serial bus interface which an I 2 C bus mode. This circuit supports only I 2 C bus mode (Multi maste r). The serial bus interface is connect ed to an ex ternal device through PV6 (SDA) and PV7 (SCL) in the I 2 C bus mode.
TMP92CZ26A 92CZ26A-345 3.15.2 Serial Bus Interface (SBI) Control The following re gisters are used to c ontrol the serial b us interface and monitor the operation status.
TMP92CZ26A 92CZ26A-346 3.15.4 I 2 C Bus Mode Control Register The following regist ers are used to co ntrol and monitor the operation status when us ing the serial bus inter fac e (SBI) in the I 2 C bus m od e.
TMP92CZ26A 92CZ26A-347 Serial Bus Interface Control Register 1 7 6 5 4 3 2 1 0 Bit symbol BC2 BC1 BC0 ACK − SCK2 SCK1 SCK0/ SWRMON Read/Write R/W R/W R R/W R/W After Reset 0 0 0 0 1 0 0 0/1 (Note2) Function Number of transferred bits (Note 1) Acknowle dge mode specification 0: Not generate 1: Generate Always read as “1”.
TMP92CZ26A 92CZ26A-348 Serial Bus Interface Control Register 1 7 6 5 4 3 2 1 0 Bit symbol MST TRX BB PIN SBIM1 SBIM0 SWRST1 SWRST0 SBICR2 (1243H) Read/Write W W (Note 1) W (Note 1) After reset 0 0 0 1.
TMP92CZ26A 92CZ26A-349 Serial Bus Interface Status Register 7 6 5 4 3 2 1 0 Bit symbol MST TRX BB PIN AL AAS AD0 LRB SBISR (1243H) Read/Write R After reset 0 0 0 1 0 0 0 0 Prohibit Read-modif y-write .
TMP92CZ26A 92CZ26A-350 Serial Bus Interface Baud Rate Register 0 7 6 5 4 3 2 1 0 Bit symbol − I2SBI − − − − − − Read/Write W R/W R R/W After reset 0 0 1 1 1 1 1 0 SBIBR0 (1244H) Prohibit Read-modify -write Function Always read “0” IDLE2 0: Stop 1: Run Always read as “1” Always write “0”.
TMP92CZ26A 92CZ26A-351 3.15.5 Control in I 2 C Bus Mode (1) Acknowledg e Mode Specificat ion When slave address is matched or detecting GENERAL CALL, and set the SBICR1<ACK> to “ 1”, TMP92CZ26 A operates in th e acknowledge m ode.
TMP92CZ26A 92CZ26A-352 b. Clock synchronization In the I 2 C bus mode, in order to wir ed-AND a bus, a master device which pulls down a clock line to low -level, in the first place, in validate a c lock pulse of a nother master device which gen erates a high-level clock pu lse.
TMP92CZ26A 92CZ26A-353 (6) Transmitter/Receiv er sel e ction Set the SBICR2<TRX> to “1 ” for operating the TMP92 CZ26A as a transmitter. Clear the <TRX> to “0” fo r operation as a receiv er.
TMP92CZ26A 92CZ26A-354 (8) Interrupt service requests and interrupt cancellation When a serial bus interface interrupt re quest (IN TSBI) occurs, the SBICR2 <PIN> is cleared to “0”. During the time that th e SBI CR2< P IN> is “0”, the SCL lin e is pulled down to the Low level.
TMP92CZ26A 92CZ26A-355 lost and SBISR<AL> is set to “1”. When SBISR<AL> is set to “1”, SBISR<MST, TRX> are cleared to “00” and the mode is switched to Slave Rec eiver Mode. Thus, clock out put is stopped in data transfer a fter setting <AL>=“1”.
TMP92CZ26A 92CZ26A-356 (14) Software Res et function The software Reset fu nction is used to init ialize th e SBI circuit, when SBI is rocked by external noises, etc. An internal Res et signal pulse can be generated b y setting SBICR2<SW RST1:0> to “10” and “01”.
TMP92CZ26A 92CZ26A-357 3.15.6 Data Transfer in I 2 C Bus Mode (1) Device initi a lization Set the SBICR1<ACK, SCK2:0>, Set SBI BR1 to “1” and clear bits 7 to 5 and 3 in the SBICR1 to “0”. Set a slave address <SA6:0> and the <ALS> (<ALS> = “0” when an addr essing format) to the I2CAR.
TMP92CZ26A 92CZ26A-358 b. Slave Mode z In the Slave Mode, the start cond ition and the slav e address are received. After the start condition is receiv ed from the master device, while eight clocks are output from the SCL pin, the slave ad dress and the direction bit that are ou tput from the master dev ice ar e received.
TMP92CZ26A 92CZ26A-359 (3) 1-word Data Transfer Check the <MST> by the INTSBI interrupt process after the 1- word data transfer is completed, and det ermine wheth er the mode is a master or sl a ve. a. If <MST> = “1” (Master Mode) Check the <TRX> and determine whether the mode is a transmitter or receiver.
TMP92CZ26A 92CZ26A-360 When the < TRX > is “0” (Receiver mode) When the next transmitted data is ot her than 8 bits, set <BC2:0> <ACK> and read the received data from SBIDBR to rele ase the SCL line (data which i s read immediately after a slave address is sent is undefined).
TMP92CZ26A 92CZ26A-361 Example: In case receive dat a N times INTSBI interrupt (After transmitting dat a) 7 6 5 4 3 2 1 0 SBICR1 ← X X X X X X X X Set the bit number of receive data and ACK. Reg. ← SBIDBR Load the dummy data. End of interrupt INTSBI interrupt (Receive data of 1st to (N − 2) th) 7 6 5 4 3 2 1 0 Reg.
TMP92CZ26A 92CZ26A-362 b. If <MST> = 0 (Slave Mode) In the slave mode the T MP92CZ26A opera tes either in norm al slave mode or in slave mode after losing ar bitra tion.
TMP92CZ26A 92CZ26A-363 T able 3.15.2 Operation in t he slave mode <TRX> <AL> <AAS> <AD0> Conditions Process 1 1 0 The TMP92CZ26A loses arbitration when transmitting a slave address and receives a slave address for which the value of the direction bit sent from another master is “1”.
TMP92CZ26A 92CZ26A-364 (4) Stop condition generati on When SBISR<BB> = “1”, the sequence for gen erating a stop condition start by writing “1” to SBIC R2<MST, TRX, PIN> and “0” to SBICR2< BB>. Do not modify t he contents of SBICR2<MST, TRX, PIN, BB> un til a stop condition has been generated on the bus.
TMP92CZ26A 92CZ26A-365 (5) Restart Restart is used durin g data transfer between a master device a nd a slave device to change the data transfer dir ection. The following description expla ins how to restart when the TMP92 CZ26A is in Master Mode. Clear SBICR2<MST , TRX, and BB> to 0 an d set SBICR2<PIN> to 1 to release the bus.
TMP92CZ26A 92CZ26A-366 3.16 USB Controller 3.16.1 Outline This USB controller (UDC) is design e d for va rious serial links to construct USB system. The outline is as fol lows: (1) Com pliant with USB rev1.1 (2) Full-speed: 1 2 Mbps (Not supported low-speed (1.
TMP92CZ26A 92CZ26A-367 3.16.1.1 System Configuration The USB controller (UDC ) is consisted of followin g 3 blocks. 1. 900/H1 CPU I/F 2. UDC core block (DPLL, SIE, IFM and PW M), request controller , descriptor RAM and 4 endpoint FIFO 3. USB transceiver About above “1.
TMP92CZ26A 92CZ26A-368 3.16.1.2 Example If using USB controller in TMP92C Z26 A, above setting is needed . 1) Pull-up of D + pin ・ In the USB standard, in Full Speed connection, D + pin must be set to pull-up. And this pull-up is needed ON/OFF control b y S/W .
TMP92CZ26A 92CZ26A-369 3.16.2 900/H1 CPU I/F The 900/H1 CPU I/F is a bridge between 900/H1 CPU and U DC and it mainly works following ope rati ons. • INTUSB (interrupt fr om UDC) gener atio n • A b r i d g e f o r S F R • USB clock control (48 MHz) 3.
TMP92CZ26A 92CZ26A-370 3.16.2.2 USBCR1 Register This register is used to set USB clock ena bles, transceiver enab le etc. 7 6 5 4 3 2 1 0 bit Symbol TRNS_USE WAKEUP SPEED USBCLKE Read/Write R/W R/W R/W R/W After reset 0 0 1 0 Function • TRNS_USE (Bit7) 0: Disable USB transceiver 1: Enable USB transceiver Set to “1” for TMP92CZ26A.
TMP92CZ26A 92CZ26A-371 Mask registe r Writing “0” to flag registe r Flag registe r Interrupt source (Set by rising edge) AB C D 3.16.2.3 USBINTFRn, MRn Register These SFRs control to generat e INTUSB (only one interru pt to CPU) becaus e the UDC outputs 23 interrupt source.
TMP92CZ26A 92CZ26A-372 7 6 5 4 3 2 1 0 bit Symbol INT _URST_STR INT_URS T_END INT_SU S INT_RESUME INT_CLKSTO P INT_C LKON Read/Write R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 Function When read .
TMP92CZ26A 92CZ26A-373 7 6 5 4 3 2 1 0 bit Symbol EP1_FULL_A EP1_Empty_A EP1_FULL_B EP1_Empty_B EP2_FULL_A EP2_Empty_A EP2_FULL_B EP2_Em pty_B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 .
TMP92CZ26A 92CZ26A-374 7 6 5 4 3 2 1 0 bit Symbol INT_SETUP INT_ EP0 INT_STAS INT_STASN INT_EP1N INT_EP2N INT_EP3N Read/Write R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 Function When read 0: Not generate i nterrupt 1: Generate inter rupt When write 0: Clear flag 1: − Note: Above interrupt can release Halt state from ID LE2 mode.
TMP92CZ26A 92CZ26A-375 • INT_ST ASN (Bit4) This is a flag for INT_ST ASN (change host status stag e - int errupt). This is set to “1” when the US B host change to status stage at the Control read transfer type. This interrupt is needed if data length is less than wLength (specified by the host).
TMP92CZ26A 92CZ26A-376 7 6 5 4 3 2 1 0 bit Symbol MSK_URST_STR MSK_URST_END MSK_SUS MSK_RESUME MSK_CLKSTOP MSK_CLKON Read/Write R/W R/W R/W R/W R/W R/W After reset 1 1 1 1 1 1 Function 0: Be not masked 1: Be masked • MSK_URST_STR (Bit7) This is a mask register fo r USBINTFR1<INT_URST_STR>.
TMP92CZ26A 92CZ26A-377 7 6 5 4 3 2 1 0 bit Symbol EP1_MSK_FA EP1_MSK_E A EP1_MSK_FB EP1_MSK_EB EP2_MSK_FA EP2_MSK_EA EP2_MSK_FB EP2_MSK_EB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 1 1 1 .
TMP92CZ26A 92CZ26A-378 7 6 5 4 3 2 1 0 bit Symbol MSK_SE TUP MSK_EP0 MSK_STAS MSK_STASN MSK_EP 1N MSK_EP2N MSK_EP3N Read/Write R/W R/W R/W R/W R/W R/W R/W After reset 1 1 1 1 1 1 1 Function 0: Be not masked 1: Be masked • MSK_SETUP (Bit7) This is a mask register for USBINTFR4<INT_SETUP>.
TMP92CZ26A 92CZ26A-379 3.16.3 UDC CORE 3.16.3.1 SFRs The UDC CORE has followi ng SFRs to control UDC and USB transceive r . a) FIFO Endpoint 0 to 3 FIFO register b) Device request bmRequestType regist.
TMP92CZ26A 92CZ26A-380 Figure 3.16.3 UDC CORE SFRs (1/3) Address Read/W rite SFR Symbol 0500H R/W Descriptor RAM0 0501H R/W Descriptor RAM1 0502H R/W Descriptor RAM2 0503H R/W Descriptor RAM3 067DH R/.
TMP92CZ26A 92CZ26A-381 Figure 3.16.4 UDC CORE SFRs (2/3) Address Read/W rite SFR Symbol 07A9H R EP1_SIZE_H_A 07AAH R EP2_SIZE_H_A 07ABH R EP3_SIZE_H_A *07ACH R EP4_SIZE_H_A *07ADH R EP5_SIZE_H_A *07AE.
TMP92CZ26A 92CZ26A-382 Figure 3.16.5 UDC CORE SFRs (3/3) Address Read/W rite SFR Symbol 07E0H R/W Port_Status 07E1H R FRAME_L 07E2H R FRAME_H 07E3H R ADDRESS *07E4H – Reserved *07E5H – Reserved 07E6H R/W USBREADY *07E7H – Reserved 07E8H W Set Descriptor STALL Note: “*” is not used at TMP92CZ26A.
TMP92CZ26A 92CZ26A-383 3.16.3.2 EPx_FIFO Register (x: 0 to 3) This register is prepared for each endp oint independent ly . This is the window regist er from or to FI F O RA M. In the auto bus enumer ation, the request contr oller in UDC set m ode, which is defined at endpoint descriptor for each endpoi nt automatica lly .
TMP92CZ26A 92CZ26A-384 3.16.3.3 bmRequestT ype Register This register shows the bm Re questT ype field of de vic e request. 7 6 5 4 3 2 1 0 bit Symbol DI RECTION REQ_TYPE1 REQ_TYPE0 RECIPIENT4 RE CIPI.
TMP92CZ26A 92CZ26A-385 3.16.3.5 wV alue Register There are 2 reg isters; the wV alue_L register and wV alue_H register . wV alue_L shows the lower -byte of wV alue field of device request and w V alue_H register shows upper byte.
TMP92CZ26A 92CZ26A-386 3.16.3.8 Setup Received Register This register informs for the UDC that an application program rec ognized INT_SETUP interrupt. 7 6 5 4 3 2 1 0 bit Symbol D7 D6 D5 D4 D3 D2 D1 D.
TMP92CZ26A 92CZ26A-387 3.16.3.10 S tandard Request Register This register shows the standar d request that is execut ing n ow . A bit which is set to “1” shows pr esen t executing request.
TMP92CZ26A 92CZ26A-388 3.16.3.12 DA T ASET Register This register shows whethe r FIFO has data or not. The application program can be ch ecked it by acc essing this regist er that whether FIFO has data or not.
TMP92CZ26A 92CZ26A-389 Note1: In the receiving mode, if bits that A-packet and B-packet of applicable endpoint are “1”, rea d data that packet-number should be received, after checking DATASIZE<PACKET_ACTIVE>. Note2: In the transmitting mode, if the both A and B bits are not “1”, it means that there are space in FIFO.
TMP92CZ26A 92CZ26A-390 3.16.3.13 EPx_ST A TUS Register (x: 0 to 7) These registers are status registers f or each endpo int. The <SUSPEND> is comm on for all endpoi nt.
TMP92CZ26A 92CZ26A-391 ST A TUS [2:0] (Bit4 to bit2) These bits show status of endpoint of UDC. The status show wheth er transfer it or not, or show result o f transfer . . These are depending on transfer typ e. (For the Isochron ous tran sfer type, refer 3.
TMP92CZ26A 92CZ26A-392 FIFO_DISABLE (Bit1) 0: FIFO enabled 1: FIFO disabled This bit symbol shows FIFO status except EP0. If the FIFO is set to disabled, th e UDC transmits NA K handshake forcibly f or th e all transfer . Disabled or enabled is se t by COMMAND register .
TMP92CZ26A 92CZ26A-393 3.16.3.14 EPx_SIZE Register (x: 0 to 7) These registers have f ol lo win g function. a) In the receiving, show ing data number for 1 pack et which was received correctly . b) In the transmitting, it shows payload size . But it shows length value when short packet is transferred.
TMP92CZ26A 92CZ26A-394 7 6 5 4 3 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Read/Write R R R After reset 0 0 0 7 6 5 4 3 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Read/Write R R R After reset.
TMP92CZ26A 92CZ26A-395 7 6 5 4 3 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Read/Write R R R After reset 0 0 0 7 6 5 4 3 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Read/Write R R R After reset.
TMP92CZ26A 92CZ26A-396 7 6 5 4 3 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Read/Write R R R After reset 0 0 0 7 6 5 4 3 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Read/Write R R R After reset.
TMP92CZ26A 92CZ26A-397 3.16.3.15 FRAME Register This register shows frame number which is issued with SOF token from the host and is used for Isochronous transfer t yp e.
TMP92CZ26A 92CZ26A-398 3.16.3.17 EOP Register This register is used wh e n a dataphas e o f contr ol t ransf er typ e term inat e or when a short packet is transmitti ng o f bulk -I N, interrupt-IN.
TMP92CZ26A 92CZ26A-399 3.16.3.18 Port S tatus Register This register is used when a requ est of printer class is received. In case of request of GET_PORT _ST A TUS, the UDC opera tes automatically by using this data.
TMP92CZ26A 92CZ26A-400 3.16.3.20 Request Mode Register This register set answer for Class Request either answer aut omatically in Hardware or control in software. Each bit mean kind of request. When this register is set applicable bit to “0”, answer is execut ed automatic ally by hardware.
TMP92CZ26A 92CZ26A-401 3.16.3.21 COMMAND Register This register sets COMMAND at each endpoin t. This reg ister can be set sel ection of endpoint in bit6 to bit4 and ki nd of COMMAND in bit3 to bit0.
TMP92CZ26A 92CZ26A-402 1000: FIFO_E NABLE This COMMAND set FIFO of applicable endpoint to enable (EP1 to EP3). If FIFO is set to disable by FIFO_DISABLE COMMAND, this command is used for release disable condition. If dur ing receiving packet, this bec omes valid from next token.
TMP92CZ26A 92CZ26A-403 3.16.3.22 INT_Control Register INT_ST ASN interrupt is disabled an d enabled by value that is written to this register . This is initialized t o disable by exte rnal reset.
TMP92CZ26A 92CZ26A-404 3.16.3.24 EPx_MODE Register (x: 1 to 3) This register sets transfer mo de of endpoint (EP1 to EP3). If transaction of SET_CONFIG and SET_ INTERF ACE are set to software control, this control must use appo inted config or interfac e.
TMP92CZ26A 92CZ26A-405 3.16.3.25 EPx_SINGLE Register This register sets mode of FIFO in each endpoint (SINGLE/DUAL). 7 6 5 4 3 2 1 0 bit Symbol EP3_SELECT EP2_SELECT EP1_SELECT EP3_SINGLE EP2_SINGLE EP1_SINGLE Read/Write R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 Note: Endpoint 3 support only SINGLE mode at TMP92CZ26A.
TMP92CZ26A 92CZ26A-406 3.16.3.27 USBREADY Register This register informs finishing wr iting data to descript or R AM on UDC. After assigned data to descript or RAM, write “0” to bit0. 7 6 5 4 3 2 1 0 bit Symbol USBREADY Read/Write R/W After reset 0 USBREADY ( Bit0) 0: Writing to descriptor RAM was finished.
TMP92CZ26A 92CZ26A-407 3.16.3.28 Set Descriptor ST ALL Register This register sets whether returns ST ALL automatica lly in data stage or status stage for Set Descript or Request. 7 6 5 4 3 2 1 0 bit Symbol S_D_STALL Read/Write W After reset 0 Bit0: S_D_ST ALL 0: Soft ware control (Default) 1: Automatically STALL 3.
TMP92CZ26A 92CZ26A-408 3.16.4 Descriptor RAM This area stores descriptor that is defin ed in USB. Device, Config, Interface, Endpoin t and String descriptor must set to RAM by using followi ng format. Note 1: If St ring Descriptor is supported, set S tringx Len gth area to size0.
TMP92CZ26A 92CZ26A-409 Descriptor RAM setting example: Address Data Description Description Device Descriptor 500H 12H bLength 501H 01H bDescriptorType Device Descriptor 502H 00H bcdUSB (L) USB Spec 1.
TMP92CZ26A 92CZ26A-410 Address Dat a Description Description Interface0 Descriptor AlternateSetting1 52BH 09H bLength 52CH 04H bDescriptorType Interface Descrip tor 52DH 00H bInterfaceNumber 52EH 01H .
TMP92CZ26A 92CZ26A-41 1 Address DA T A Description Description Endpoint3 Descriptor 559H 07H bLength 55AH 05H bDescriptorType Endpoint Descriptor 55BH 83H bEndpointAddress IN 55CH 03H bmAttributes Int.
TMP92CZ26A 92CZ26A-412 3.16.5 Device Request 3.16.5.1 S tandard request UDC support automatically answ er in standard request. ( 1) GET_ST A TUS Request This request returns status that is ap pointed of receive side, a utomat ically .
TMP92CZ26A 92CZ26A-413 (2) CLEAR_ FEA TURE re quest This request clears or disables particular function. bmRequestT ype bRequest wV alue wIndex wLength Data 00000000B 00000001B 00000010B CLEAR_ FEATURE Feature selector 0 Interface endpoint 0 None • Receptio n side devi ce Feature selector: 1 Present remote wakeup setting is disabled.
TMP92CZ26A 92CZ26A-414 (4) SET_ADDRESS request This request set device address. Foll owin g request answer by using this devic e address. Answer of request is used pr esent device address until statu s stage of this request finish normally .
TMP92CZ26A 92CZ26A-415 (6) SET_DESCRIPTOR request This request sets or enab les particular functi on. bmRequestT ype bRequest wV alue wIndex wLength Data 00000000B SET_ Descriptor Descriptor type and Descriptor index 0 or Language ID Descriptor length Descriptor Automatically answer of t his request does not supp ort.
TMP92CZ26A 92CZ26A-416 (9) GET_INTERF ACE request This request returns Alter nateS etting value that is set by a ppointed interfac e. bmRequestT ype bRequest wV alue wIndex wLength Data 10000001B GET_ INTERFACE 0 Interface 1 Alternate setting If there is not appoint ed inter face, it become to ST ALL state.
TMP92CZ26A 92CZ26A-417 3.16.5.2 Printer Class Request UDC does not support “Autom at ic answer” of pr int er class request. T ransaction for Class request is the sam e as vendor request; answering to INT_SETUP interrupt. 3.16.5.3 V endor request (Class request) UDC doesn’ t support “Automat ic answer” of V endor request.
TMP92CZ26A 92CZ26A-418 (b) Control write/request There is no dataphase bmRequestT ype bRequest wV alue w Index wLength Data 010000xxB Vendor peculiar Vendor peculiar Vendor peculiar 0 None When INT_SETUP is received, judge contents of rec eiving request by bmRequestT ype, bRequ est, wV alue, wInde x, wLength regist ers.
TMP92CZ26A 92CZ26A-419 Below is control fl ow in UDC watch fro m appl ication. Figure 3.16.6 Control Flow in UDC W atch from Application Note 1: There is not special case in this flow such as overlap receive SETUP packet. Please refer to chaptor 4.5.2.
TMP92CZ26A 92CZ26A-420 3.16.6 T ransfer mode and Protocol T ransaction UDC perform automat ically in hard ware as f o llows; • Receive pack et • Judge address endpoint t r ansf er m ode • Error .
TMP92CZ26A 92CZ26A-421 (2) T ransfer mode UDC support transfer mode in FULL speed. • FULL speed device Control transfer type Interrupt transfer type Bulk transfer type Isochronous transfer type Following is explan at ion of UDC oper ati on in each transfer mo de.
TMP92CZ26A 92CZ26A-422 (a-1) T ransmission bulk mode Below is transaction format of bu lk transfer du ring transmi tting. • T oken: IN • Data: DA T A0/DA T A1, NAK, ST ALL • Handshake: ACK Control flow Below is control-flow wh en UDC receive IN t oken.
TMP92CZ26A 92CZ26A-423 Figure 3.16.7 Control Flow in UDC (B ulk transfer type (trans mission)/Interrupt transf er type (transmission)) IDLE Receive IN token Confirm Handshake answer • Confirm STATU .
TMP92CZ26A 92CZ26A-424 (a-2) Rece iving bulk mode Below is transaction format rece iv ing bulk transfer type. It ha s to fo llow below . • To k e n : O U T • Data: DA T A0/DA T A1 • Handshake: ACK, NAK, ST ALL Control flow Below is control-flow wh en UDC receive IN t oken.
TMP92CZ26A 92CZ26A-425 Figure 3.16.8 Control Flow in UDC (Bulk transfer type (Receiving)) IDLE Receive OUT token Confirm Status • Confirm STATUS register (status) • Confirm FIFO’s condition OK O.
TMP92CZ26A 92CZ26A-426 (b) Interrupt tra nsfer t ype Interrupt transfer type use transac tion format same with transmission bulk transfer . When transmission by using toggle bit, hardware setting and answer in UDC are same with transmission bulk transfer .
TMP92CZ26A 92CZ26A-427 (c) Control transfer type Control transfer type is conf igured in below thre e stages. • Setup stage • Data stage • Status stage Data stage is skipped sometimes. Each stage is conf igured in one or p lural transaction. UDC ex ecutes each transaction while manag ing of three stag es in hardware.
TMP92CZ26A 92CZ26A-428 3. Data packet is received. Device request of 8 b ytes from SIE in UDC is tr ansferred to below request register . • bmRequestT ype regist er • bmRequest register • wV alue register • wIndex register • wLength register 4.
TMP92CZ26A 92CZ26A-429 Figure 3.16.9 Control Flow in UDC (Set up st age) IDLE Receive SETUP token Confirm Status • Confirmation STATUS register (Status) Confirm DATA PID • DATA0 • Time out OK OK.
TMP92CZ26A 92CZ26A-430 (c-2) Data stage Data stage is configured b y one or plural transac tion base on tog gle sequence. T ransaction is same with format transm ission or re cei vin g bulk transaction. However , below is difference . • T oggle bit start from “1” by SETUP stage.
TMP92CZ26A 92CZ26A-431 4. If ACK handshake from host is rece ived, • Set ST A TU to READY . • Assert INT_ST A TUS interrupt. It finishes normally by above transaction. If it is time out without receivin g ACK from host, • Set ST A TUS register to TX_ERR and state return IDLE.
TMP92CZ26A 92CZ26A-432 (c-4) Stage manag ement UDC manages each stage of control transfer by hardware. Each stage is changed by receiving token from USB host, or CPU acces ses register . Each stage in control transfer ty pe has to process co mbinatio n so ft war e.
TMP92CZ26A 92CZ26A-433 Stage change condition of control r ead transfer type 1. Receive SET UP toke n from host • Start setup stage in UDC. • Receive data in request normally and judge. And assert INT_S ETUP interr upt to ex ternal. • Change data stage into the UDC.
TMP92CZ26A 92CZ26A-434 Stage change condit ion of control writ e transfer type 1. Receive SET UP toke n from host. • Start setup stage in UDC. • Receive data in request normally and judge. And assert INT_S ETUP interr upt to ex ternal. • Change data stage in UDC.
TMP92CZ26A 92CZ26A-435 Stage change cond it ion of control writ e (no data stag e) trans fer type 1. Receiv e SETUP token from host • Start setup stage in UDC. • Receive data in request normally and judge. And assert INT_S ETUP interr upt to ex ternal.
TMP92CZ26A 92CZ26A-436 (d) Isochronous transfer type Isochronous transfer type is guarant eed transfer by data number that is limited every each frame. However , this transfer don’ t retry when error occurs. Therefore, Isochronous transfer type transfer only 2 phases (t oken, data) and it do esn’ t use handshake phase.
TMP92CZ26A 92CZ26A-437 5. Below is transaction when SOF toke n from h ost is received. • Change the packet A ’ s FIFO from X Condition to Y Condition. An d clear data. • Change the packet B f rom Y Condition to X Condition. • Set frame number to fram e register .
TMP92CZ26A 92CZ26A-438 Figure 3.16.13 Control Flow in UDC (I sochronous tra nsfer type (T ransmission)) IDLE Receive IN token Confirm Status • Confirm STATUS register (status ) Generate DATA PID •.
TMP92CZ26A 92CZ26A-439 (d-2) Isochronous rec ei vi n g mode Isochronous transfer type form at i n re ceiving is belo w transaction format. • To k e n : O U T • Data: DA T A0 Control flow Isochronous transfer type is frame management. And data that is written to FIFO by OUT token is received to CPU in next frame.
TMP92CZ26A 92CZ26A-440 In renewed frame, Packet A ’ s FIFO interchange packet B’ s FIFO, and transaction is used same flow . I f SO F t o k en is n o t re ce i v ed by e r r or a n d s o o n, t h is d a ta is lo s t be ca u s e o f frame is not renewed.
TMP92CZ26A 92CZ26A-441 Figure 3.16.14 Control Flow in UDC (I sochronou s tra nsfer type (Receiving)) IDLE Receive OUT token Confirm Status Confirming ST A TUS register (status) Confirm DATA PID • Ti.
TMP92CZ26A 92CZ26A-442 3.16.7 Bus Interface and Access to FIFO (1) CPU bus interface UDC prepares two ty pes of FIFO acc ess, single packet and dual pack et. In single packet mode, FIFO capacity tha t is implemented by hardware is used as big FIFO. In dual packet mode, FIFO capacity that is divi ded into tw o is used as two FIFOs.
TMP92CZ26A 92CZ26A-443 (a) Single packet m ode This is data sequence of sing le packet mode whe n CPU bus interface is used. Figure 3.16.15 is receiving sequence. Figure 3.16 .16 is transmitting sequence. Main of this chapter is access to FIFO. Data sequence with USB host refer to chapter 5.
TMP92CZ26A 92CZ26A-444 Below is transmitting sequen ce in single packet mode. Figure 3.16.16 T ransmitting Sequence in Single Packet Mode Transmitting number < payload • WR of transmitting number.
TMP92CZ26A 92CZ26A-445 (b) Dual packet m ode In dual packet mode, FIFO is divided into A and B packet, it is controlled according to priority in hardwar e. It ca n be performed at once, transmittin g and receiving data to USB ho st and exchanges to exter nal of UDC.
TMP92CZ26A 92CZ26A-446 When it writes data to FIFO in transmitting, confirm condition of two packets, and consider the or der of priority . When tr ansfer data number is set, set to w hich packet A an d packet B, judge by P ACKET_ACTIVE bit. Packet that bit is set to 0 is bit that transfer now .
TMP92CZ26A 92CZ26A-447 (c) Issuance of NULL packet If t ra n sm i tt in g NU L L pa ck e t, by i np u t L p u ls e fr om E Px _ EO PB s ig n al , d a ta o f 0 length is set to FIFO, and it can be transferred NULL packet to IN tok en. But if it set NULL data to FIFO, it is valid only case of SET signal is L level condition (case o f FIFO is empty).
TMP92CZ26A 92CZ26A-448 3.16.8 USB Device answer USB controller (UDC) sets vari ous register and initializat ion in UDC in detecting o f hardware reset, detectin g of US B bus reset, and enumeration answer . Below is explain ing a bout each conditio n.
TMP92CZ26A 92CZ26A-449 ISO transfer mode Below is transfer conditi on of fram e before one. Recei vin g SOF renews this. OUT (RX) IN (TX) Initial READY READY Not transfer READY FULL Finish normally DATAIN READY Detect in error RXERR TXERR T ransfer mode of except ISO transfer This is result previous transfer .
TMP92CZ26A 92CZ26A-450 3.16.9 Power Management USB controller (UDC) can be sw itche d from optional resume condition (turn on the power supply condition) to suspend (Suspen s ion ) condit ion, and it can be returned from suspends condition to turn on the power supply conditio n.
TMP92CZ26A 92CZ26A-451 (4) Low power consumption by control of CLK input si gna l When UDC switches to s uspend condition, it stops CLK and switches to low power consumption condition. But as system, th is function enable s besides low power consumption by stopping source of CLK th at is supplied from external.
TMP92CZ26A 92CZ26A-452 3.16.10 Supplement (1) External access flow to USB communication a) Normally movement b) Stage error SETUP DATA0 ACK IN NAK DATA1 DATA0 DATA1 INT_SETUP INT_ ENDPOINT0 INT_STATUS.
TMP92CZ26A 92CZ26A-453 (2) Register beginning value Register Name Beginning V alue OUTSIDE Reset Beginning V alue USB_RESET Register Name Beginning V alue OUTSIDE Reset Beginning V alue USB_RESET bmRe.
TMP92CZ26A 92CZ26A-454 (3) USB control flow chart (a) T ransaction for standard r equ est (Outline flowchart (Example)) USB interrupt Call USBINT0 function Judge Interrupt SETUP transaction ENDPOINT 0.
TMP92CZ26A 92CZ26A-455 (b) Condition change Initialization transaction Turn on power supply Waiting USB interrupt condition Request transaction condition Receive USB token Transmit Request error/ S T .
TMP92CZ26A 92CZ26A-456 (c) Device request and variou s request jud gment Start Get request data Judge Request End Standard request CLEAR_FEATURE SET_FEATURE GET_STATUS SET_ADDRESS SET_CONFIGURATION GE.
TMP92CZ26A 92CZ26A-457 (c-1) CLEAR_FEA TURE re quest transaction Start End Is request right ？ Finish transaction Error transaction No Yes Judge Recipient Device Disable remote wakeup setting Endpoin.
TMP92CZ26A 92CZ26A-458 (c-2) SET_FEA TURE request transaction Start End Is request right? Finish transaction Error transaction No Yes Judge Recipient Device Enable remote wakeup setting Endpoint Set s.
TMP92CZ26A 92CZ26A-459 (c-3) GET_ST A TUS request tra nsaction Start End Is request right? Finish transaction Error transaction No Yes Judge Recipient Interface Set 0 x 0 0 data of 2 bytes Endpoint Se.
TMP92CZ26A 92CZ26A-460 (c-4) SET_CONFIGRA TION request transaction Start End Is request right ？ Finish transaction Error transaction No Yes Is EP0 stall ？ Is assignment value valid ？ Is state va.
TMP92CZ26A 92CZ26A-461 (c-5) GET_CONFIGRA TION request transaction Set present configuraion value Start End Is request right? Finish transaction Error transaction No Is state valid? No Yes Yes.
TMP92CZ26A 92CZ26A-462 (c-6) SET_INTERF ACE request transaction Start End Is request right? Finish transaction Error transaction No Yes Is EP0 stall? Is assignment value valid? Is state valid? Set each endpoint to assignmented configuration value.
TMP92CZ26A 92CZ26A-463 (c-7) SYNCH_FRAME requ est transaction Start End Is request right? Finish transaction Error transaction No Yes Is EP0 stall? Is assignment value valid? Is state valid? Set altrenate setting value to present transmitting data.
TMP92CZ26A 92CZ26A-464 (c-8) SYNCH_FRAME requ est transaction (c-9) SET_DESCRIPTOR request transaction Start End Is request right? Finish transaction Error t ransaction No Yes Start End Is request rig.
TMP92CZ26A 92CZ26A-465 (c-10) GET_DESCRIPTOR request transac tion Start End Is request right? Write information to FIFO[EP0_fifowrite ( )] Error transaction No Yes Is EP0 stall? Is assignment value valid? Is state valid? No No No Yes Yes Yes Stri ng Set string descriptor information.
TMP92CZ26A 92CZ26A-466 (c-1 1) Data read transaction to FIFO by EP0 Start End Is request right? No Yes Stage information = data stage STATUS_NAK interrupt enable Data read from FIFO All data number re.
TMP92CZ26A 92CZ26A-467 (c-12) Data write transaction to FIFO by EP0 Start End Is request right? No Yes Stage information = data stage STATUS_NAK interrupt enable Set data size to SIZE register All dat.
TMP92CZ26A 92CZ26A-468 (c-13) Beginning setting tran saction of microcontr oller (c-14) Begining setting transact ion of UDC Start Set Stack point Clear vRAM USB farm initialization[USB_INIT] Interrup.
TMP92CZ26A 92CZ26A-469 (c-15) Beginning transaction of USB farm changing number (c-16) Set DEVICE_ID data t o DEVICE_ID of UD C Start End Renew stage information Renew current information Renew support information Invalid EP except EP0 Various flag Intialization Start End Set DEVICE_ID data to DEVICE_ID_RAM area.
TMP92CZ26A 92CZ26A-470 (c-17) Descriptor data set transaction (c-18) USB interrupt transaction Start End Set descriptor data to DESC_RAM area. Start Judge Interrupt Read INT register End Judge Request.
TMP92CZ26A 92CZ26A-471 (c-19) Dummy function for not using maska ble interrupts. • T ransaction per form s no thing, theref ore outline f l ow is skipping. (c-20) Request judgm ent transaction. If transaction result is error , it puts ST ALL command.
TMP92CZ26A 92CZ26A-472 (c-22) Perform endpoint 0 transaction in except for SETUP stage. (c-23) Status stage interrupt transaction Start End Judge Stage Others Error transaction Status stage Finish nor.
TMP92CZ26A 92CZ26A-473 (c-24) ST A TUS_NAK interrupt transaction (c-25) This transaction is n o transaction by US B transaction per form in interrupts.
TMP92CZ26A 92CZ26A-474 (c-26) Getting descriptor inform ation (reration of stan dard request) Start End Is config within su pp ort? No Yes Get device information on descriptor Interface is within support in config present.
TMP92CZ26A 92CZ26A-475 3.16.11 Points to Note and Restrictions 1. Limitation of writin g to COMMAND r egister in special tim ing W he n “ S T A LL ” c o m ma n d i s i s su e d , E N D PO I N T status might be shift to “INV ALID”. T o avoid this problem, keep th e below routine.
TMP92CZ26A 92CZ26A-476 3. When generating toggle er ror of devic e controller a. UDC operation If USB host fail to receive ACK transmitte d from UDC in OUT transfer , USB host transmits the same data to UDC again.
TMP92CZ26A 92CZ26A-477 3.17 SPIC (SPI Controller) SPIC is a Serial Peripheral Interface Cont roller that supports only master mode. It can be connected to SD card, MMC (Multi Media Card) etc.
TMP92CZ26A 92CZ26A-478 3.17.1 Block diagram It shows block diagram and conn ect ion to SD card in Figure 3.17.1. Note1: SPCLK, SPCS , SPDO and SPDI pins are set to input port (Port PR3, PR2, PR1, PR0) by reset. These signals are needed pull-up resister to fix voltage leve l, could you adjust resist ance value for your final set.
TMP92CZ26A 92CZ26A-479 3.17.2 SFR SFR of SPIC are as follow s. T hese are a co nnected to CPU with 16 bit dat a bus. (1) SPIMD(SPI Mode setting register) SPIMD register is for ope r ati on m od e or clock etc.
TMP92CZ26A 92CZ26A-480 (c) <DOSTAT> Set the status of SPDO pin when data comm unication is not o perating (aft er transmitting or during receiving). Please don't change the setting of this re gist er when trans mitting/recei ving is in operation.
TMP92CZ26A 92CZ26A-481 (h) <SWRST> This bit is for Softwar e reset of transmit/rec eive FIFO point er. Write SPICT<TXE> to “0” at <XEN>="1", and stop transmitting. Af ter that, by writing <SWRST> to “1”, the read/write pointer of tr ans mit/receive F IFO are initializ ed.
TMP92CZ26A 92CZ26A-482 (2) SPICT(SPI Control Register) SPICT register is for data length or C RC etc. SPICT Register 7 6 5 4 3 2 1 0 bit Symbol CEN SPCS_B UNIT16 TXMOD TXE FDPXE RXMOD RXE Read/Write R.
TMP92CZ26A 92CZ26A-483 The process that calc ulating CRC16 of tr ansmits data and sending CRC ne xt to transmit data is explained as follows. (1) Set SPICT <CRC 16_7_B> to select CRC7 or CRC 16 and <CRCRX_TX_B> to se lect calculating data.
TMP92CZ26A 92CZ26A-484 (d) <CEN> Select enable/disable of th e pin for SD card or MMC. When the card isn’t insert ed or no-power su pp ly to DVcc, penetrat ed current is flowed because SPDI pin bec omes floating. In addition, current is flowed to th e card because SPCS , SPCLK and SPDO pin outp ut “1”.
TMP92CZ26A 92CZ26A-485 (k) <RXE> In UNIT receive mode, recei ves onl y 1 UNIT data b y writing “1”. When reading rec eive data register (S PIRD) with t he condition “1”, rec eives one tim e additionally. In sequential mod e, receiving is kept sequ entially until F IFO becomes fu ll by writing “1”.
TMP92CZ26A 92CZ26A-486 Difference points betw een UNIT transmission a nd Sequential transmission UNIT transmit mode ca n be select ed by writing SPICT < T X M OD>= “0”.
TMP92CZ26A 92CZ26A-487 Difference points be tw een UNIT receive and S equential rec ei ve UNIT receive is the mode that receiv ing only 1 UNIT data. U NIT receive mode can be selected by writing SPICT <RXMOD>= “0”. The receive F IFO is invalid in the UNIT receive mode.
TMP92CZ26A 92CZ26A-488 Transmit/Receive When transmitting or r eceiving, write <FDP X E>= “1” Writing <FDPXE>= “ 1” first, and SPICT<RXE>= “1” and keep waitin g state for start ing UNIT receiving. When writing SPICT<RXE>= “1”after <ALGNEN>= “1”, receiving does not start right away.
TMP92CZ26A 92CZ26A-489 (3) Interrupt In INTC (interrupt c ontroller), interrupt is di vided roughly into 2 kinds; transmit interrupt (INTSPITX) and rec e iv e i nterrupt (INTSPIRX ). Besides in this SPI circuit, t here are 4 kinds of interrupts; 2 transmit interrupts 2 rec eive int errupts.
TMP92CZ26A 92CZ26A-490 (3-1) SPIST (SPI Status Reg ister ) SPIST shows 4 statuses. SPIST Register 7 6 5 4 3 2 1 0 bit Symbol TEMP TEND REND Read/Write R R After reset 1 1 0 Function Transmit FIFO Stat.
TMP92CZ26A 92CZ26A-491 (3-2) SPIIE(SPI Interrupt Enable Register ) SPIIE register is for enable 4 i nterr upts. SPIIE Register 7 6 5 4 3 2 1 0 bit Symbol TEMPIE RFULIE TENDIE RENDIE Read/Write R/W Aft.
TMP92CZ26A 92CZ26A-492 (4) SPICR (SPI CRC Regist er) CRC result of Transmit/Receive data is set to SPICR register. SPICR Register 7 6 5 4 3 2 1 0 bit Symbol CRCD7 CRCD6 CRCD5 CRCD4 CRCD3 CRCD2 CRCD1 C.
TMP92CZ26A 92CZ26A-493 (5) SPITD (SPI Transmit Data Register) SPITD0, SPITD1 registers are for writing transmit ted d ata. SPITD0 Register 7 6 5 4 3 2 1 0 bit Symbol TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1.
TMP92CZ26A 92CZ26A-494 (6) SPIRD (SPI Receiv e Dat a Register) SPIRD0, SPIRD1 registers are for reading received data. SPIRD0 Register 7 6 5 4 3 2 1 0 bit Symbol RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD.
TMP92CZ26A 92CZ26A-495 • Note of FIFO buffer There are followin g not es in this SPIC. 1) Transmit ・ Data is overwritten if write data with cond ition transmit FIF O buffer is FULL. Interrupt and transmission are not executed nor mally becau se write-po inter in FIFO becomes abnormal c ondition.
TMP92CZ26A 92CZ26A-496 3.18 I 2 S (Inter-IC Sound) The TMP92CZ26A incorpora tes serial output circ uitry that is compliant with the I 2 S format. This function enables the TMP92CZ26A to be used for digital audio system s by connecting an LSI for audio output such as a DA converter.
TMP92CZ26A 92CZ26A-497 3.18.1 Block Diagram The I 2 S unit contains two channels: channel 0 and ch annel 1. Each channel can be controlled and made to outpu t indepe ndently .
TMP92CZ26A 92CZ26A-498 3.18.2 SFRs The I 2 S unit is provided with the follow ing registers. These reg isters are connected to the CPU via a 32-bit data bus. The transmission buffers I2S0BUF and I 2S1BUF must be ac cessed using 4-byte load instruc t ions.
TMP92CZ26A 92CZ26A-499 I2S1 Control Register 7 6 5 4 3 2 1 0 bit Symbol TXE1 *CNTE1 DIR1 BIT1 DTFMT11 DTFM T10 S YSCKE1 Read/Write R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 Function Transm.
TMP92CZ26A 92CZ26A-500 3.18.3 Description of Operation (1) Settings the transfer clock gen erator and Word Select signal In the I 2 S unit, the clock frequencie s for the I2SnCKO and I2SnWS signals are generated using the system clock ( f SYS ) as a source clock.
TMP92CZ26A 92CZ26A-501 Figure 3.18.4 Output Format LSB MSB LSB MSB LSB MSB I2SnWS LSB MSB LSB MSB LSB Valid data Valid Data Valid Data Valid Data MSB LSB MSB LSB MSB Left justify I2SnDO Stereo Valid D.
TMP92CZ26A 92CZ26A-502 (2) Setting example for the clock generat o r (8-bit count er/6-bit counter) The clock generator gene rates the reference clock for setting th e data transfer speed and sampli ng freque ncy.
TMP92CZ26A 92CZ26A-503 Note 1: The value to be s et in I2SnC<WSn5:0> must be 16 or larger (18 or larger for I2S tra nsfer) when the data length is 8 bits and 32 or larger (34 or larger for I2S transfer) when the data length is 16 bits. Note 2: It is recommended that the value to be set in I2SnC<WSn5:0> be an even number.
TMP92CZ26A 92CZ26A-504 The following shows how written data is output under various conditions. When I2SnCTL<WLVLn> = 0 When I2SnCTL<WLVLn> = 1 Note: In case of using monaural setting, and change ri ght / left: I2SnCTL<WLVLn>, data output order change off 1'st data and 2'nd data.
TMP92CZ26A 92CZ26A-505 3.18.4 Detailed Description of Operation (1) Connection example Figure 3.18.5 shows an example of conn ections between the TMP92CZ26 A and an external LSI (DA converter) using ch annel 0. Note: After reset, PF0 to PF2 are placed in a high-impedance st ate.
TMP92CZ26A 92CZ26A-506 Figure 3.18.6 Timing Diagrams (I2S FMT/Stereo/16bi t/MSB first) (3) Considerations for using t he I 2 S unit 1) INTI2Sn generation timing Every 4bytes data trance from FIF O buffer to shift register per one tim e. An INTI2Sn interrupt is generated under two co nditions.
TMP92CZ26A 92CZ26A-507 immediately. At the same time, the read and write pointers of the FIFO, the data in the output shift r egister and th e clock gener ator are all cl eared. (How ever, when I2SnCTL<CNTEn>=1, the clock generator is no t cleared.
TMP92CZ26A 92CZ26A-508 3.19 LCD Controller (LCDC) The TMP92CZ26A incorporates an LCD contro ller (LCDC) for controlling an LCD driver LSI (LCD module).
TMP92CZ26A 92CZ26A-509 3.19.1 LCDC Features according to LCD Driver T ype T able 3.19.1 LCDC Features according to LCD Driver T ype (This table assumes the connection with a TOSHIBA-made LCD driver .
TMP92CZ26A 92CZ26A-510 3.19.2 SFRs LCDMODE0 Register 7 6 5 4 3 2 1 0 bit Symbol RAMTYPE1 RAMTYPE0 SCPW1 SCPW0 MODE3 MODE2 MODE1 MODE0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 1 1 0 0.
TMP92CZ26A 92CZ26A-51 1 LCD Control 0 Register 7 6 5 4 3 2 1 0 bit Symbol PIPE ALL0 FRM ON – DLS LCP0OC START Read/Write R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 Function PIP function 0.
TMP92CZ26A 92CZ26A-512 LCD LHSYNC Pulse Register 7 6 5 4 3 2 1 0 bit Symbol LH7 LH6 LH5 LH4 LH3 LH2 LH1 LH0 Read/Write W After reset 0 0 0 0 0 0 0 0 Function LHSYNC period (bits 7–0) 7 6 5 4 3 2 1 0.
TMP92CZ26A 92CZ26A-513 7 6 5 4 3 2 1 0 bit Symbol HSD6 HSD5 HSD4 HSD3 HSD2 HSD1 HSD0 Read/Write W After reset 0 0 0 0 0 0 0 Function LHSYNC delay (bits 6-0) 7 6 5 4 3 2 1 0 bit Symbol PDT LDD6 LDD5 LD.
TMP92CZ26A 92CZ26A-514 7 6 5 4 3 2 1 0 bit Symbol HSW7 HSW6 HSW5 HSW4 HSW3 HSW2 HSW1 HSW0 Read/Write W After reset 0 0 0 0 0 0 0 0 Function LHSYNC width (bits 7-0) 7 6 5 4 3 2 1 0 bit Symbol LDW7 LDW6.
TMP92CZ26A 92CZ26A-515 LCD Main Area S tart Address Register 7 6 5 4 3 2 1 0 bit Symbol LMSA7 LMSA6 LMSA5 LMSA4 LMSA3 LMSA2 LMSA1 Read/Write R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 Funct.
TMP92CZ26A 92CZ26A-516 LCD Sub Area H OT Point Register (X-dir) 7 6 5 4 3 2 1 0 bit Symbol SAHX7 SAHX6 SAHX5 SAHX4 SAHX3 SAHX2 SAHX1 SAHX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 .
TMP92CZ26A 92CZ26A-517 3.19.3 Description of Operation 3.19.3.1 Outline After the required settings such as the operation mod e, display data memory address, color mode, and LCD size are specified, the start register is set to start the LCDC operation.
TMP92CZ26A 92CZ26A-518 3.19.3.3 Basic Operation The following diagram shows the basic timi ngs of the wavefo rms gene rated by the LCDC and adjustable elements.
TMP92CZ26A 92CZ26A-519 3.19.3.4 Reference Clock LCP0 LCP0 is used as the reference cl oc k for all the signals in the LCDC. This section explains how to set the fr equency (period) of the LCP0 signal. The LCP0 clock sp eed (LD bus transfer spe ed) is determined by selecting TFT or STN and setting LCDMODE0<SCPW1:0> and LCDMODE1<SWPW2>.
TMP92CZ26A 92CZ26A-520 LCP0 Setting Range T abl e Conditions f SYS : 60 MHz Display size (color) : up to 320 × 320 Display size (monoc hrome/grayscale) : up to 640 × 480 Note: This table shows the range of LCP0 settings t hat can be made under the conditions shown above.
TMP92CZ26A 92CZ26A-521 Example 1: When f SYS = 10 MHz, STN mode, LCDMODE0<SCPW1:0> = 01 Internal referenc e clock LCP0 = f SYS / 8 = 10 MHz / 8 = 1.25 [MHz] LCP0 period = 1 / 1.25 [MHz] = 0. 8 [ μ S] Example 2: when f SYS = 60 MHz, TFT mode, LCDMODE0<SCPW1:0> = 1 1 Internal reference clock LCP0 = f SYS / 16 = 60 MHz / 16 = 3.
TMP92CZ26A 92CZ26A-522 LCDCTL0 <LCP0OC> is used to control the output timing of the LCP0 signal. When <LCP0OC>=0, the LCP0 signal is alwa ys output.
TMP92CZ26A 92CZ26A-523 3.19.3.5 Refresh Rat e The period of the horizontal synch ronization signal LHSYNC is defined as the product of the value set in LCDHSP<LH15:0> and the LCP0 clock p eriod.
TMP92CZ26A 92CZ26A-524 • Insertion of dummy clocks The above is a conceptual diagram showin g the data (LD23-0), shift clock (LCP0), horizontal synchronization signal (LHSYN C), and vertical synchroni zation signal (L VSYNC) on the LCD panel.
TMP92CZ26A 92CZ26A-525 • Setting method The front dummy LHSYNC (vertical front po rch) not accompanied by valid data in the total of LHSYNC p eriod in the L VSYNC period is d efined by the value set in LCDPR VSP<PL V6:0>.
TMP92CZ26A 92CZ26A-526 3.19.3.6 Signal Settings The above diagram shows the typical timings of the signals controlled by the LCDC. This section explains how to c ontrol each of these signals.
TMP92CZ26A 92CZ26A-527 1. L VSYNC Signal The period of the vertical synchronization signal L VSYNC indicates the time for each scr een upda te ( re fres h ra te) . Th e L V SYN C pe riod is de fin ed a s an int egr al mu lti ple of the period of the h orizontal synchronization signal LHSYNC.
TMP92CZ26A 92CZ26A-528 2. LHSYNC Signal The period of the horizontal synchronizati on signal LHSYNC corresponds to one line of display . The LHSYNC period is defined as an integral multiple of the reference clock signal LCP0. The LHSYNC period is defined as the prod uct of the value set in LC DHSP<LH15:0 > and the LCP0 clock period .
TMP92CZ26A 92CZ26A-529 The enable width of the LHSYNC si gnal is set using LCDHSW<HSW8:0>. It can be specified in a range of 1 to 512 pulses of the LCP0 clock.
TMP92CZ26A 92CZ26A-530 As shown in the diagram below , delay time of 0 to 127 pulses of the LCP0 clock can be inserted in the LHSYNC signal. Delay time = <HSD6:0> LCDHSDL Y Register 7 6 5 4 3 2 .
TMP92CZ26A 92CZ26A-531 3. LLOAD Signal The LLOAD signal is used to control the timing for th e LCD driver to r eceive display data. The period of the L LOA D signal synchro nizes to on e line of display . It is defined as an integral multiple of the reference clock LCP0.
TMP92CZ26A 92CZ26A-532 The number of pulses in the front dummy LHSY NC (verti cal front porch) is spe cified by LCDPR VSP<PL V6:0>. This delay time can be set in a range of 0 to 1 27 pulses of the LCP0 clock.
TMP92CZ26A 92CZ26A-533 The enable width of the LLOAD signal is specified using LCDLDW<LDW9:0>. It can be set in a range of 0 to 1024 pulses of the LCP0 clock. The actual enable width is determined depending on the LCDLDDL Y<PDT> setting, as shown below .
TMP92CZ26A 92CZ26A-534 As shown in the diagram below , delay time of 0 to 127 pulses of the LCP0 clock can be inserted in the LLOAD signal. Delay time = <LDD6:0> Note: The delay time for the LLOAD signal is cont rolled based on LCDLDDL Y<PDT>=1.
TMP92CZ26A 92CZ26A-535 4. LGOE0 to LGOE2 Signals The LCDC has three signals (LGOE0 to LG OE2) that can be controlled like the LHSYNC signal. For these signals, the enable w idth, delay time, and phase timing can be adjusted as shown below .
TMP92CZ26A 92CZ26A-536 7 6 5 4 3 2 1 0 bit Symbol OE0D6 OE0D5 OE 0D4 OE0D3 OE0D2 OE0D1 OE0D0 Read/Write W After reset 0 0 0 0 0 0 0 Function OE0 delay (bits 6-0) 7 6 5 4 3 2 1 0 bit Symbol OE1D6 OE1D5.
TMP92CZ26A 92CZ26A-537 LCD Control 2 Register 7 6 5 4 3 2 1 0 bit Symbol LGOE2P LG OE1P LGOE0P Read/Write R/W R/W R/W After reset 0 0 0 Function LGOE2 phase 0: Rising 1: Falling LGOE1 phase 0: Rising .
TMP92CZ26A 92CZ26A-538 5. LFR Signal The LFR (frame) signal is used to co ntrol the direction of bias the LCD driver app lies on liquid crystal cells. W ith small screens in monochrome mode, the polarity of the LFR signal is normally inverted in synchroniza tion with each screen display .
TMP92CZ26A 92CZ26A-539 When LCDCTL0<FRMON>=1 and LCDCTL0<DLS >=1, frame output is inverted at intervals set in LCDDVM0<FML3:0> and the LFR signal is inverted at intervals of “LCP0 × M”. The “M” value is specified in LCDDVM0<FMP7:4>.
TMP92CZ26A 92CZ26A-540 LCD Control 0 Register 7 6 5 4 3 2 1 0 bit Symbol PIPE ALL0 FRM ON – DLS LCP0OC START Read/Write R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 Function PIP function 0:.
TMP92CZ26A 92CZ26A-541 6. LD Bus The data to be transferred to the LCD driv er is output via a dedicated bus (LD23 to LD0). The output format can be s elected according to the inpu t method of the LCD driver to be used.
TMP92CZ26A 92CZ26A-542 • Memory Map Image and Data Output in Each Display Mode STN monochrome (1-pixel display data = 1-bit memory data) Display Memory LD Bus Output 8-bit type LD0 0 → 8 … LD1 1.
TMP92CZ26A 92CZ26A-543 STN 16-grayscale (1-pixel display data = 4-bit memory data) Display Memory LD Bus Output 8-bit type LD0 3-0 → 35-32 … LD1 7-4 → 39-36 … LD2 1 1-8 → 43-40 … LD3 15-12 → 47-44 … LD4 19-16 → 51-48 … LD5 23-20 → 55-52 … LD6 27-24 → 59-56 … LD7 31-28 → 63-60 … Figure 3.
TMP92CZ26A 92CZ26A-544 STN 64-grayscale (1-pixel display data = 6-bit memory data) Display Memory LD Bus Output 8-bit type LD0 5-0 → 53-48 LD1 1 1-6 → 59-54 LD2 17-12 → 65-60 LD3 23-18 → 71-66 LD4 29-24 → 77-72 LD5 35-30 → 83-78 LD6 41-36 → 89-84 LD7 47-42 → 95-90 Figure 3.
TMP92CZ26A 92CZ26A-545 STN 256-color (1-pixel display data = 8-bit memo ry data (R: 3 bits, G: 3 bit s, B: 2 bits)) Display Memory LD Bus Output 8-bit type LD0 2-0(R0) → 23-22(B2) … LD1 5-3(G0) .
TMP92CZ26A 92CZ26A-546 STN 4096-color (12 bpp: R: 4 bits, G: 4 bits, B: 4 bits) Display Memory LD Bus Output 8-bit type LD0 3-0(R0) → 35-32(B2) … LD1 7-4(G0) → 39-36(R3) … LD2 1 1-8(B0) → 43.
TMP92CZ26A 92CZ26A-547 TFT 256-color (1-pixel display data = 8-bit memo ry dat a (R: 3 bits, G: 3 bits, B: 2 bits) Display Memory 12bit (TFT) LD0 0(R0) → 12(R1) … LD1 1(R0) → 13(R1) … LD2 2(R0.
TMP92CZ26A 92CZ26A-548 TFT 4096-color (1-pixel display data = 12-bit memo ry data (R: 4 bits, G: 4 bit s, B: 4 bit s) Display Memory 12-bit TFT LD0 0(R0) → 12(R1) … LD1 1(R0) → 13(R1) … LD2 2(.
TMP92CZ26A 92CZ26A-549 TFT 65536-color (16 bpp: R: 5 bits, G: 6 bit s, B: 5 bits) Display Memory 16-bit TFT LD0 0(R0) → 16(R1) … LD1 1(R0) → 17(R1) … LD2 2(R0) → 18(R1) … LD3 3(R0) → 19(.
TMP92CZ26A 92CZ26A-550 TFT 262144-/16777216-color (24 bpp: R: 8 bits, G: 8 bits, B: 8 bit s) Display Memory 24-bit TFT 18-bit TFT LD18 0(R0) → 24(R1) … LD19 1(R0) → 25(R1) … LD0 2(R0) → 26(R.
TMP92CZ26A 92CZ26A-551 7. LDIV Signal The <LDINV> and <AUTOINV> bits of the LCDMODE1 register are used to control the LDIV signal as well as data output. The LDIV signal indicates the inversion of all the LD bus signals. When LCDMODE1<LDINV>=1, all display data is forcefully inverted and the LDIV signal is also driven high.
TMP92CZ26A 92CZ26A-552 3.19.4 Interrupt Function The LCDC has two types of inte rrupts. One is generated synchronous with the LL OAD signal and the other is generate d synchronous with the LLOAD signal that is output immediately after the L VSYNC signal.
TMP92CZ26A 92CZ26A-553 3.19.5 S pecial Functions 3.19.5.1 PIP (Picture in Picture) Function The TMP92CZ26A includes a PIP (Picture in Picture) function that allows a different screen to be disp layed over the screen currently being displayed on the LCD.
TMP92CZ26A 92CZ26A-554 The table be low shows the HOT point locations that can be specified. *VRAM Access HOT_Point( Y_dir) HOT_Point(X_dir) 16bit In units of 16 dots Monochrome display 32bit In units.
TMP92CZ26A 92CZ26A-555 LCD Main Area S tart Address Register 7 6 5 4 3 2 1 0 bit Symbol LMSA7 LMSA6 LMSA5 LMSA4 LMSA3 LMSA2 LMSA1 Read/Write R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 Funct.
TMP92CZ26A 92CZ26A-556 LCD Sub Area H OT Point Register (X-dir) 7 6 5 4 3 2 1 0 bit Symbol SAH7 SAH6 SAH5 SAH4 SAH3 SAH2 SAH1 SAH0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 .
TMP92CZ26A 92CZ26A-557 LCD Sub Area Display Common S ize Register 7 6 5 4 3 2 1 0 bit Symbol SAC7 SAC6 SAC5 SAC4 SAC3 SAC2 SAC1 SAC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 .
TMP92CZ26A 92CZ26A-558 3.19.5.2 Display Data Rotation Function When display RAM data is output to th e LCD driver (LCDD), the data output direction can be automatically rotated by ha rd ware to meet the specifications of the LCDD (or LCD module) to be used.
TMP92CZ26A 92CZ26A-559 the need to rewrite the display RAM data. 2. 90-Degree Rotation Function Display RAM Image (QVGA 320 × 24 0) QVGA (320 × 240) Portrait-type QVGA (240 × 320) (when this function is used) The display RAM image above shows typical data of QVGA size (320 segments × 240 commons: landscape type).
TMP92CZ26A 92CZ26A-560 3. Setting Method The <LDC2:0> bits in the LCDMODE1 register are used to set the display data rotation function. LCDMODE1 Register 7 6 5 4 3 2 1 0 bit Symbol LDC2 LDC1 LDC.
TMP92CZ26A 92CZ26A-561 3.19.5.3 Considerations for Using the LCDC 1 ． If the operation mode is changed while the LCDC is operating, a maximum of one frame may not be displayed properly . Although this degree of disturbance does not normally pose any pro blem (e .
TMP92CZ26A 92CZ26A-562 3.19.6 Setting Example • STN COM001 COM240 SEG001 SEG240 240C O M × 240SEG LCD ( M onochr om e Panel ) O24 0 O001 O001 O240 LCP0 LHSYN C LFR LD7 ∼ LD0 SCP LP FR /D S P O F .
TMP92CZ26A 92CZ26A-563 • TFT G1 G16 2 SA1 SB1 SC1 SA80 SB80 SC80 160SEG × 3 ( RGB) × 162CO M LCD G16 2 G1 SA1 SB1 SC1 SA80 SB80 SC80 LCP0 LLOAD LFR LD23~LD 0 CPH LOAD D I/O DO/I DB5-0 DC5-0 U/D VD.
TMP92CZ26A 92CZ26A-564 3.20 Touch Screen Interface (TSI) The TMP92CZ26A has an interface for 4-te rmina l resistor network touch-screen. This interface supports t wo procedures: an X/ Y position m easu rement and touch det ection.
TMP92CZ26A 92CZ26A-565 3.20.2 Touch Screen Interface (TSI) Control Register TSI control register 7 6 5 4 3 2 1 0 bit Symbol TSI7 INGE PTST TWIEN PYEN PXEN MYEN MXEN Read/Write R/W R/W R R/W R/W R/W R/.
TMP92CZ26A 92CZ26A-566 3.20.3 Touch detection procedure A Touch detection procedure shows procedure until a pen is touched by the screen and it is detected.
TMP92CZ26A 92CZ26A-567 Figure 3.20.4 Timing diagram of de-bounce circuit INT4 Reset the counter for de-bounce time P96/INT4 pin Start the counter for de-bounce time de-bounce time de-bounce time INT4 is generated by matching counter and specified de-bounce time.
TMP92CZ26A 92CZ26A-568 3.20.4 X/Y position measuring procedure In the INT4 routine, e x ecute an X/Y p osition measuring pr ocedure like b elow. <X position measur ement> At first, set both SPX, SMX-switches to ON, and set SPY, SMY-switches to OFF.
TMP92CZ26A 92CZ26A-569 3.20.5 Flow chart for TSI Figure 3.20.6 Flow chart for TSI Following pages exp lain each circuit conditio n of (a), (b) and (c) i n abo ve flow chart.
TMP92CZ26A 92CZ26A-570 (a) Main routine (condition of wait ing INT4 interrupt ) (p9fc)<P96F>, <P97F>= “1” : Set P96 to int4/PX, set P97 to P Y (inte34) : Set interrupt level of INT4 (t.
TMP92CZ26A 92CZ26A-571 (b) X position m easurement (S tart AD c onversion) (tsicr0)=c5h : Set SMX, SPX to ON. Set the input gate of P97, P96 to OFF. (admod1)=b0h : Set to AN3.
TMP92CZ26A 92CZ26A-572 (c) Y position m easurement(Start AD c onversion) (tsicr0)=cah : Set SMX, SPX to ON. Set the input gate of P97, P9 6 to OFF. (admod1)=a0h : Set to AN2.
TMP92CZ26A 92CZ26A-573 3.20.6 Note 1. De-bounce circuit The system clock of CPU is used in de-bou nce circuit. Therefor e, de-bounce circuit is not operated when cl ock is not supplied to CPU (IDL E1, STOP mode or PCM m ode). And, an interrupt which through the de-bounce circuit is n ot generated.
TMP92CZ26A 92CZ26A-574 3.21 Real time clock (RTC) 3.21.1 Function description for R TC 1) Clock function (hou r , min ute, second) 2) Calendar fun ction (month and day , day of the week, and leap year.
TMP92CZ26A 92CZ26A-575 3.21.3 Control registers T able 3.21.1 P AGE 0 (Tim er fun ction) registers Symbol A ddress Bit7 Bit6 Bit5 Bit4 Bit3 Bi t2 Bit1 Bit0 Function Read/Write SECR 1320H 40 sec 20 sec.
TMP92CZ26A 92CZ26A-576 3.21.4 Detailed explanation of control register RTC is not initia lized by reset. Ther efore, all registers m ust be initia lized at the beginning of the pr ogram.
TMP92CZ26A 92CZ26A-577 (2) Minute column register (for P AGE0/1) 7 6 5 4 3 2 1 0 Bit symbol MI6 MI5 MI4 MI3 MI2 MI1 MI0 MINR (1321H) Read/Write R/W After reset Undefined Function "0" is read.
TMP92CZ26A 92CZ26A-578 (3) Hour column register (for P AGE0/1) 1. In case of 24-hour clock mode (MONTHR<MO0>= “1”) 7 6 5 4 3 2 1 0 Bit symbol HO5 HO4 HO3 HO2 HO1 HO0 HOURR (1322H) Read/Write R/W After reset Undefined Function "0" is read.
TMP92CZ26A 92CZ26A-579 (4) Day of the week column register (f or P AGE0/1) 7 6 5 4 3 2 1 0 Bit sy mbol WE2 WE1 WE0 DAYR (1323H) Read/Write R/W After reset Undefined Function "0" is read.
TMP92CZ26A 92CZ26A-580 (6) Month column register (for P A GE0 only) 7 6 5 4 3 2 1 0 Bit symbol MO4 MO4 MO2 MO1 MO0 MONTHR (1325H) Read/Write R/W After reset Undefined Function "0" is read.
TMP92CZ26A 92CZ26A-581 (8) Y ear column register (for P AGE0 only) 7 6 5 4 3 2 1 0 Bit symbol YE7 YE6 YE5 YE4 YE3 YE2 YE1 Y E0 YEARR (1326H) Read/Write R/W After reset Undefined Function 80 Years 40 Y.
TMP92CZ26A 92CZ26A-582 (10) P AGE register (for P AGE0/1) 7 6 5 4 3 2 1 0 Bit symbol INTENA ADJUST ENATMR ENAALM PAGE PAGER (1327H) Read/Write R/W W R/W R/W After reset 0 Undefined Undefined Undefined Read-modify write instruction are prohibited Function (Note) Interrupt 1: Enable 0: Disable “0” is read.
TMP92CZ26A 92CZ26A-583 3.21.5 Operational description (1) Reading timer data There is the case, which reads wr ong data when carry of the inside coun ter happens during the opera tion which cloc k data reads. Therefor e please read two time s with the following wa y for re ading correct data.
TMP92CZ26A 92CZ26A-584 (2) T iming of INTRTC and Clock data When time is read by interrupt, read cl ock data within 0.5s(s) aft er generating interrupt.
TMP92CZ26A 92CZ26A-585 (3) W riting time r data When there is carry on the wa y of write op eration, expecting data can not be wrote exactly . Th er efore, in ord er to write in data exactly please fo llow the below w ay . 1. Resetting a div id er In RTC inside, th ere are 15-stage dividers, which gener ates 1Hz clock from 32,768 KHz.
TMP92CZ26A 92CZ26A-586 2. Disabling the timer Carry of a timer is prohibit ed when write “0” to P AGER<ENA TMR> and can prevent malfunction by 1s Carry hold circuit. Durin g a timer prohibited, 1s Carry hold circuit holds one sec. carry signal, which is generated from divider .
TMP92CZ26A 92CZ26A-587 3.21.6 Explanation of the interrupt signal and alarm signal Can use alarm functi on by setting of register of P AGE1 a nd output either of three signals from ALARM pin as follows by write “1” t o P AGER<P AGE>. INTRTC outputs 1shot puls e when the falling edg e is detected.
TMP92CZ26A 92CZ26A-588 (2) When output clock of 1Hz RTC outputs clock of 1Hz to ALARM pin by setting up P AGER<ENAALM>= “0”, RESTR<DIS1HZ>= “0”, <DIS16H Z>= “1”. And RTC generates INTRC in terrupt by falling edge of th e clock.
TMP92CZ26A 92CZ26A-589 3.22 Melody / Alarm generator (MLD) TMP92CZ26A contain s melody fu nction a nd alar m function, both of which are output from the MLDALM pin. Five kind of fixed cycles interrupt is genera te by using 15bit c ounter , which is used for alarm generator .
TMP92CZ26A 92CZ26A-590 3.22.1 Block Diagram Figure 3.22.1MLD Block Di agram MELFH, MELFL register Comparator (CP0) 12bit counter (UC0) F/F [Melody Generator] Edge detectior A LMINT <IALM4E:0E> 1.
TMP92CZ26A 92CZ26A-591 3.22.2 Control registers ALM register 7 6 5 4 3 2 1 0 bit Symbol AL8 AL7 AL6 AL5 AL4 AL3 AL2 AL1 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Setting alarm pattern MELALM.
TMP92CZ26A 92CZ26A-592 3.22.3 Operational Description 3.22.3.1 Melody generator The Melody function generates signals of any frequency (4Hz-5461Hz) based on low-speed clock (32.768KHz) and outputs the signa ls from th e MLD ALM pin. By connecting a loud speaker ou tsid e, Melody tone can easily sound.
TMP92CZ26A 92CZ26A-593 3.22.3.2 Alarm generator The Alarm function generates eight kinds of alarm waveform ha ving a mod ulation frequency 4096Hz determined by the low-spee d clock (32.7 68 KHz). And this waveform is reversible by setti ng a value to a registe r .
TMP92CZ26A 92CZ26A-594 Example: W aveform of alarm pattern for each sett i ng value: not invert) 500 ms 1 A L3 pattern (once) 250 ms A L8 pattern (Once) Modulation frequency (4096 Hz) A L1 pattern (Continuous output) 31.25 ms 1 秒 1 2 8 1 A L2 pattern (8 times/1 sec) 62.
TMP92CZ26A 92CZ26A-595 3.23 Analog-Digital Converter (ADC) This LSI has a 6-channel, multip lexed-input, 10 -bit successiv e-approxim atio n Analog-Digital converter (ADC). Figure 3.23.1 shows a block diagram of the AD converter . The 6-analog input channels (AN0-AN5) ca n be used as general-purpose inputs.
TMP92CZ26A 92CZ26A-596 3.23.1 Control register The AD converter has 6-mode control registers (ADMOD0, ADMOD1 , ADMOD2, ADMOD3, ADMOD4 and AD MOD5) and 6-convers ion result high/low regist er pairs (ADREG0H/L ∼ ADREG 5H/L). The results of hig h - priority AD c onv ersion are st ored in the ADREGSPH/L.
TMP92CZ26A 92CZ26A-597 AD Mode Control Register 1 (Normal co nversion cont rol) 7 6 5 4 3 2 1 0 bit Symbol DACON ADCH2 ADCH1 ADCH0 LAT ITM REPEAT SCAN Read/Write R/W After reset 0 0 0 0 0 0 0 0 Functi.
TMP92CZ26A 92CZ26A-598 AD Mode Control Register 2 (High- priori ty conversion control) 7 6 5 4 3 2 1 0 bit Symbol HEOS HBUSY HADS HHTRGE HTSEL1 HTSEL0 Read/Write R R R/W After reset 0 0 0 0 0 0 Functi.
TMP92CZ26A 92CZ26A-599 AD Mode Control Register 4 (A D Monito r functio n control) 7 6 5 4 3 2 1 0 bit Symbol CMEN1 CMEN0 CMP1C CMP0C IRQEN1 IRQEN0 CMPINT1 CMPINT0 Read/Write R/W R/W R/W R R After res.
TMP92CZ26A 92CZ26A-600 AD Conversion Result Registe r 0 Lo w 7 6 5 4 3 2 1 0 bit Symbol ADR01 ADR00 OVR0 ADR0RF Read/Write R R R After reset 0 0 0 0 Function Store Lower 2 bits of AN0 AD conversion re.
TMP92CZ26A 92CZ26A-601 AD Conversion Result Registe r 2 Lo w 7 6 5 4 3 2 1 0 bit Symbol ADR21 ADR20 OVR2 ADR2RF Read/Write R R R After reset 0 0 0 0 Function Store Lower 2 bits of AN2 AD conversion re.
TMP92CZ26A 92CZ26A-602 AD Conversion Result Registe r 4 Lo w 7 6 5 4 3 2 1 0 bit Symbol ADR41 ADR40 OVR4 ADR4RF Read/Write R R R After reset 0 0 0 0 Function Store Lower 2 bits of AN4 AD conversion re.
TMP92CZ26A 92CZ26A-603 High-priority AD Conversion Result Re gister SP Low 7 6 5 4 3 2 1 0 bit Symbol ADRSP1 ADRSP0 OVSRP ADRSPRF Read/Write R R R After reset 0 0 0 0 Function Store Lower 2 bits of an.
TMP92CZ26A 92CZ26A-604 AD Conversion Result Co mp are Criterion Registe r 0 Low 7 6 5 4 3 2 1 0 bit Symbol ADR21 ADR20 Read/Write R/W After reset 0 0 Function Store Lower 2 bits of an AD conversion re.
TMP92CZ26A 92CZ26A-605 AD Conversion Clock Setting Re gister 7 6 5 4 3 2 1 0 bit Symbol − ADCLK2 ADCLK1 ADCLK0 Read/Write R/W R/W R/W R/W After reset 0 0 0 0 Function Always write “0” Select clo.
TMP92CZ26A 92CZ26A-606 3.23.2 Operation 3.23.2.1 Analog Reference V oltag es The VREFH and V R EFL pins pr ovide the an al og referenc e voltages f or th e ADC.
TMP92CZ26A 92CZ26A-607 3.23.2.3 S tarting an AD Conversion The ADC supports two types of A D conversion: normal AD con version and high-priorit y AD conversion. The ADC initiates a normal AD conversio n by software when the ADMOD0<ADS > is set to “1”.
TMP92CZ26A 92CZ26A-608 3.23.2.4 AD Conversion Modes and AD Conversion-End Inte rrupts The ADC sup ports the follow ing four conversio n modes. For a n ormal AD convers ion, ADMOD0<1:0> sel ect one of the f our conversion modes. For a high-pr iority AD conversion, the ADC only supports Channel Fixed Single Conv e rsion mode.
TMP92CZ26A 92CZ26A-609 If ADMOD1<ITM> is set to “1”, the AD C generates an interr upt after every four conversions. Th e results of convers ions are sequentiall y stored in the ADREG0H/L to ADREG3H/L regist ers, in that order . The ADMOD0<EOS> i s s e t to “1” when the ADC stores the resu lts in the ADREG3 H/L.
TMP92CZ26A 92CZ26A-610 Interrupt Generation T iming and Flag Setting in Each AD Conversion Mode ADMOD1 Conversion mode Interrupt Generation T iming EOS set timing (Note) ITM REPEA T SCAN Channel Fixed.
TMP92CZ26A 92CZ26A-61 1 3.23.2.5 High-Priority Conversion Mode The ADC ca n perform a high-priorit y AD conv ersion while it is perform ing a normal AD conversion sequenc e. A high-priority AD con version can be started at soft ware by setting the ADMOD 2<HADS> to “1”.
TMP92CZ26A 92CZ26A-612 3.23.2.8 S toring and Reading the AD Conversion Result Conversion results are stored into AD conversion result high/ low register (ADREG0H/L to ADREG5H/L). In Channel Fixed Repeat Conversi on mode, conversion results are stored into the ADREG0H/L to ADREG3H/L sequentially .
TMP92CZ26A 92CZ26A-613 T able 3.23.1 Relationship s between Analog Input Channel s and A D Conversion Re sult Re gisters AD Conversion Result Re giste rs Analog Input Channel (Port G) Conversion Modes.
TMP92CZ26A 92CZ26A-614 Setting example: 1. Convert the analog input voltage on the AN3 pin and write the result to memory address 2800H using the AD interrupt(INTAD) processing routine. Main routine 7 6 5 4 3 2 1 0 INTEAD ← 1 1 0 0 − − − − Enable INTAD and set it to interrupt level 4.
TMP92CZ26A 92CZ26A-615 3.24 Watchdog Timer (Runaway detection timer) The TMP92CZ26A contains a watchdog timer of r unaway detecting. The watchdog timer (WDT ) is used to return the CPU to the normal stat e when it detects that the CPU has started to malfunction (runaway) due to causes such as noise.
TMP92CZ26A 92CZ26A-616 3.24.2 Operation The watchdog timer generates an INT WD interrupt when the detection tim e set in the WDMOD<WDTP1:0> has elaps ed. The watchdog timer must be clear ed “0” in software before an INTWD interrupt will b e generated.
TMP92CZ26A 92CZ26A-617 3.24.3 Control Registers The watchdog timer (WDT) is contr olled by two control regist er s WDMOD and WDCR. (1) W atchdog timer mode registers (WD MOD ) 1.
TMP92CZ26A 92CZ26A-618 7 6 5 4 3 2 1 0 Bit symbol WDTE WDTP1 WDTP0 I2WDT RESCR − WDMOD (1300H) Read/Write R/W R/W After reset 1 0 0 0 0 0 Function WDT control 1: Enable Select detecting time 00: 2 1.
TMP92CZ26A 92CZ26A-619 3.25 Power Management Circuit (PMC) The TMP92CZ26A incorporates a power mana gement circuit (PMC) for managing power supply in standby state as protective measures against leak current in fine-process products. The following six power supply rai ls are available.
TMP92CZ26A 92CZ26A-620 3.25.1 SFR 7 6 5 4 3 2 1 0 bit symbol PCM_ON − WUTM1 WUTM0 Read/Write R/W W R/W R/W After system reset 0 0 0 0 After hot reset Data retained − Data retained Data retained Function Power Cut Mode 0: Disable 1: Enable Alw ays write “0” Always read as “0” Warm-up time 00: 29 (15.
TMP92CZ26A 92CZ26A-621 3.25.2 Detailed Description of Operation This section explains th e procedures for ent ering and exit ing the Power Cut Mo de. • Entering the Power Cut Mode When to enter the Power Cut Mode, the CPU n eeds to be operating in the in ternal RAM.
TMP92CZ26A 92CZ26A-622 1. Prepare to shift P ower Cut Mode (1) Set the warm-up time: PMCCTL<WUTM1:0> After wake-up interruption, int ernal wake-up timer count setting register value:<WUTM1:0>, and after about 77 us, external PWE termin al change from low level to high level.
TMP92CZ26A 92CZ26A-623 • Exiting the Pow er Cut Mode The Power Cut Mode can be exited by external or internal interruption. (It inhibits to exit the Power Cut Mode by reset when D VCC1A is cu t off. Reset must be a sserted afte r supplying power to DVCC1A and wait ing for its voltage t o fully stabilize.
TMP92CZ26A 92CZ26A-624 3.25.3 Detailed Description of T iming Internal HOT _RESET assert to dead ci rcuit only. (DVCC1A &DVCC1C circuit) 1. If it is set PMCCTL<PCM_O N>=“1”, shift the Pow er Cut Mode, howeve r , it spen ds 3-clock times maximum (around 92 μ S) to shift from normal mode to Power Cut Mode.
TMP92CZ26A 92CZ26A-625 Figure3.25.2 Example External Circuitry for Usin g the PMC Figure3.25.2 shows an example of exte rnal circuitry for using th e PMC. In normal mode, the power management pin (P WE) outputs “1” and power is supplied t o all the blocks in the TMP92C Z26A.
TMP92CZ26A 92CZ26A-626 3.25.4 Notes of Power sequence • Power ON/Power OFF Se quence (Initi al Power ON/Complete Power OFF) In the pow er ON sequen ce (initia l power ON), po wer must be supplied to internal circuits first and then to external circuits, as show n below .
TMP92CZ26A 92CZ26A-627 3.25.5 Setting Example Condition: Wake-up trigger=INT4(TSI) org 002000h ld (syscr0),40h ; Enable low frequency clock ldw (wdmod),0b100h ; Disable WDT ldw (admod0),0000h ; ldw (a.
TMP92CZ26A 92CZ26A-628 3.26 Multiply and Accumulate Calculation Unit (MAC) The TMP92CZ2 6A includes a multip ly-accumula te unit (MAC) capable of 32-b it × 32-bit + 64-bit arithmetic opera ti ons at high speed.
TMP92CZ26A 92CZ26A-629 3.26.1.2 Data Registers The data registers are arr anged as shown below . Data Registers Bits<63:56> Bits<55:48> Bit s<47:40> Bits<39:32> Bits<31:24&g.
TMP92CZ26A 92CZ26A-630 3.26.2 Description of Operation (1) Calculation mode The MAC has the f ollowing three types of calculatio n mode. The calculation m ode to be used is specified in MA CCR<MOPMD1:0> . MACCR<MSM D> is used to select unsigned or signed mode.
TMP92CZ26A 92CZ26A-631 (d) Sign mode Both multiply-accumulate and multiply-subtrac t operations can be executed in unsigned or signed mode. In signed mode, the MACMA , MACMB, and M ACOR registers beco.
TMP92CZ26A 92CZ26A-632 3.26.3 Operation Examples (1) Unsigned m ultip ly-accumulat e operation The following shows a setting example for calc ula ting “33333333 + 11 111111 × 22222222”: ld (MACCR), 0x08 ; Unsigned multiply-accumulate mode Start calculation by write to MACMB.
TMP92CZ26A 92CZ26A-633 3.27 Debug Mode The TMP92CZ26A includes a debug suppor t unit (DSU) for en abling on-board debugging. The DSU has 9 debug pins for interfa cing with an external em ulator via a DSU connector to b e mounted on the tar get board and a DSU con necting cable.
TMP92CZ26A 92CZ26A-634 (3) Limitations in debug mode Debug mode has the following limitat ions: 1) T arget reset While debuggin g is being perform ed, the system reset ( RESET pin) of the target (microcontroller) must not be used to reset th e controller and microcontroller .
TMP92CZ26A 92CZ26A-635 2) Pins In debug mode, a total of 9 pins (PZ0 to PZ7 in Port Z and PU7 in Port U) are used to connect the TMP92CZ2 6 A with an emulator via a DSU probe for c ommunicating with the controller . For this reason, these 9 pins cannot be debugged.
TMP92CZ26A 92CZ26A-636 Port U Register 7 6 5 4 3 2 1 0 Bit Symbol PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 Read/Write R/W After reset External pin data (Output latch is reset to “0”.
TMP92CZ26A 92CZ26A-637 3) Boot function In this LSI, we support boot function, howeve r , this boot function is not available in debug mode. (It is inhibit to set DBGE =“0”, AM0 = “1” and AM1 = “1” at the same time.
TMP92CZ26A 92CZ26A-638 5) Data bus occupancy The TMP92C Z26A incl udes three control lers (LCD co ntroller , SDRA M contro ller and DMAC) that function as bus masters apart fr om the CPU.
TMP92CZ26A 92CZ26A-639 Figure 3.27.2 Example of Data Bus Oc cu pancy T iming in Debug Mode Figure 3.27.2 shows an example of dat a bus occupancy tim ing in deb ug mode.
TMP92CZ26A 92CZ26A-640 4. Electrical Characteristics (T ent ative) 4.1 Maximum Ratings Symbol Contents Rating Unit DVCC3A DVCC3B -0.3 to 3.9 DVCC1A DVCC1B DVCC1C -0.3 to 3.0 AVCC Power Supply Voltage -0.3 to 3.9 V V IN Input Voltage -0.3 ∼ DVCC3A/3B+0.
TMP92CZ26A 92CZ26A-641 4.2 DC Electrical Characteristics Symbol Parameter Min T yp. Max Unit Condition DVCC 3A General I/O Power Supply Voltage (DVCC=AVCC) (DVSSCOM=AVSS=0V) 3.0 3.3 3.6 V DVCC 1A Internal Power A DVCC 1B Internal Power B DVCC 1C High CLK oscillator and PLL Pow er 1.
TMP92CZ26A 92CZ26A-642 Symbol Parameter Min T yp. Max Unit Condition VIH0 Input High Voltage for D0 to D7 P10 to P17 (D8 to 15), P60 to P67 P71 to P76, P90 PC4 to PC7, PF0 to PF5 PG0 to PG5, PJ5 to PJ6 PN0 to PN7, PP1 to PP2 PR0 to PR3, PT0 to PT7 PU0 to PU7, PX5, PX7 0.
TMP92CZ26A 92CZ26A-643 Symbol Parameter Min T yp. Max Unit Condition VOL1 Output Low Voltage1 P90 to P92, PC0 to PC3, PC7 PF0 to PF5 , PK1 to PK7 PM1 to PM2, PM7 PN0 to PN7, PP1 to P P7 PV0 to PV7 , PW0 to P W7, PX5, PX 7 IOL = 0.5mA, 3.0 ≦ DVCC3A VOL2 Output Low Voltage2 Except VOL1 output pin – – 0.
TMP92CZ26A 92CZ26A-644 Symbol Parameter Min T yp. Max Unit Condition − 15 30 DVCC3A,3B = 3.6V NORMAL (note2) 45 60 DVCC1A,1B,1C = 1.6V − 0.5 1 DVCC3A,3B = 3.6V IDLE2 28 45 PLL_ON f SYS =80MHz DVCC1A,1B,1C = 1.6V − 12 23 DVCC3A,3B = 3.6V NORMAL (note2) 34 45 DVCC1A,1B,1C = 1.
TMP92CZ26A 92CZ26A-645 4.3 AC Characteristics The Following all AC regulation is the measurement resu lt in following co ndition, if unless otherwise noted. AC measuring c ondition • Clock of top column i n above t able shows sy stem clock frequency , and “T” shows system clock period [ ns].
TMP92CZ26A 92CZ26A-646 Write cycle Va r i a b l e No. Parameter Symbol Min Max 80MHz 60MHz Unit t DW 1.0T − 10.0 − 6.6 16-1 D0 ~ D15 valid → WR xx rising at 0 waits t DW 1.0T − 6.0 6.5 − t DW4 3.0T − 10.0 − 39.8 16-2 D0 ~ D15 valid → WR xx rising at 2 waits/4 waits t DW6 5.
TMP92CZ26A 92CZ26A-647 (1) Read cycle (0 wait s) Note1: The phase relation between X1 i nput signal and the other signals is undefined. Note2: The above timing chart show an exam ple of basic bus timing . The CSn , R/ W , RD , WRxx , SRxxB , SRWR pins timing can be adjusted by memo ry controller timing adjust function.
TMP92CZ26A 92CZ26A-648 (2) Write cycle (0 waits) Note1: The phase relation between X1 i nput signal and the other signals is undefined. Note2: The above timing chart show an exam ple of basic bus timing . The CSn , R/ W, RD , WRxx , SRxxB , SRWR pins timing can be adjus ted by memory controlle r timing adjust function.
TMP92CZ26A 92CZ26A-649 (3) Read cycle (1 wait) (4) Writ e cycle (1 wait) SDCLK Data in p ut t RR3 t AD3 t RD3 WAIT A0~A23 CSn RD D0~D15 R/ W SDCLK Data out p ut t WW3 t DW3 WAIT A0~A23 CSn WRxx D0~D15.
TMP92CZ26A 92CZ26A-650 4.3.2 Page ROM Read Cycle (1) 3-2- 2-2 mo de Va r i a b l e Parameter Symbol Min Max 80 MHz 60 MHz Unit 1 System clock period ( = T) t CYC 12.5 266.6 12.5 16.6 2 A0, A1 → D0 ~ D15 input t AD2 2.0T − 18 7 15.2 3 A2 ~ A23 → D0 ~ D15 input t AD3 3.
TMP92CZ26A 92CZ26A-651 4.3.3 SDRAM controller AC Characteristics Variable Parameter Symbol Min Max 80 MHz 60 MHz Unit <STRC[2:0]>= 000 T 12.5 16.6 1 Ref/Active to ref/active command period <STRC[2: 0]>=110 t RC 7T 87.5 116.2 <STRC[2:0]>= 000 2T 12210 25.
TMP92CZ26A 92CZ26A-652 (1) SDRAM read timing (1Word length read mode, <SP RE>=1) Column Row SDCLK SDxxDQM SDCS SDRAS SDCAS A 0~A9 D0~D15 SDWE A 10 A 11~A15 t CH t CL t CK t RCD t RAS t RP t CMS .
TMP92CZ26A 92CZ26A-653 (2) SDRAM write timing (Single write mode, <SPRE>=1 ) SDCLK SDxxDQM SDCS SDRAS SDCAS D0~D15 SDWE t CH t CL t CK t WR t RCD t RP t CMS t RRD t CMS t CMH t RAS Data output t.
TMP92CZ26A 92CZ26A-654 (3) SDRAM burst read timing (S tart burst cycle) Column Row SDCLK SDxxDQM SDCS SDRAS SDCAS A 0~A9 D0~D15 SDWE A 10 A 11~A15 t CK t RCD t CMS t CMH t CMH t AH t AS Row Row Data i.
TMP92CZ26A 92CZ26A-655 (4) SDRAM burst read timing (End burst timing) SDCLK SDxxDQM SDCS SDRAS SDCAS D0~D15 SDWE t CK t RP t CMS t CMH Data input t CMH t CMS t CMS Column t AC Data input t OH t OH t C.
TMP92CZ26A 92CZ26A-656 (5) SDRAM initializes timing 220 SDCLK SDxxDQM SDCS SDRAS SDCAS A 0~A9 SDWE t CK t RC t CMS t CMH t CMS t CMH t CMH t CMS A 10 A 11~A15 t AS t AH t CMH t CMS 0.
TMP92CZ26A 92CZ26A-657 (6) SDRAM refreshes timing (7) SDRAM self refresh timing SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE t CK t RC t CMH t CMS SDCLK SDCKE SDCS SDRAS SDCAS SDWE t C K t RC t CMH t CMS t CKS.
TMP92CZ26A 92CZ26A-658 4.3.4 NAND Flash Controller AC Characteristics Va r i a b l e No. Symbol Parameter Min Max 80 MHz (n=3) (m=3) 60 MHz (n=3) (m=3) Unit 1 t NC Access cycle (2 + n + m ) T 100 132 2 t RP NDRE low level width (1.5 + n) T − 12 45 63 3 t REA NDRE data access time (1.
TMP92CZ26A 92CZ26A-659 4.3.5 Serial channel timing (1) SCLK input mode (I/O interface mode) Va r i a b l e Parameter Symbol Min Max 80 MHz 60 MHz Unit SCLK cycle t SCY 16T 200 266 Output data → SCLK rising/ falling t OSS t SCY /2 − 4T − 30 20 36.
TMP92CZ26A 92CZ26A-660 4.3.6 T imer input pulse (T A0IN, T A2IN, TB0IN0, TB1IN0) Va r i a b l e Parameter Symbol Min Max 80 MHz 60 MHz Unit Clock cycle t VCK 8T+100 200 234 Low level pulse width t VCKL 4T + 40 90 107 High level pulse width t VCKH 4T + 40 90 107 ns 4.
TMP92CZ26A 92CZ26A-661 4.3.9 LCD Controller Va r i a b l e Parameter Symbol Min Max 80 MHz (n=0) 60 MHz (n=0) Unit LCP0 clock period t CW 2T(n+1 ) 25 33.3 LCP0 high width (Include phase inversion) t CWH T(n+1) − 5 7.5 11.6 LCP0 low width (Include phase inversion) t CW L T(n+1) − 5 7.
TMP92CZ26A 92CZ26A-662 4.3.10 I 2 S T iming Variable Parameter Symbol Min Max 80 MHz 60 MHz Unit I2SCKO clock period t CR t IC 100 100 I2SCKO high width t HB 0.5 t CR − 15 35 35 I2SCKO low width t LB 0.5 t CR − 15 35 35 I2SDO, I2SWS setup time t SD 0.
TMP92CZ26A 92CZ26A-663 4.3.11 SPI Controller Va r i a b l e Parameter Symbol Min Max 80MHz 60 MHz Unit SPCLK frequency ( = 1/S) f PP 20 20 15 MHz SPCLK rising time t r 6 6 6 SPCLK falling time t f 6 6 6 SPCL K low widt h t WL 0.5S − 6 19 28 SPCLK high width t WH 0.
TMP92CZ26A 92CZ26A-664 4.4 AD Conversion Characteristics Parameter Symbol Condition Min T yp. Max Unit Analog reference voltage ( + ) VREFH AVCC − 0.
TMP92CZ26A 92CZ26A-665 5. T able of S pecial function registers (S FRs) The SFRs include the I/O ports and periph eral control reg isters allocated to t he 8-Kbyte address space from 000000H to 001FF0H.
TMP92CZ26A 92CZ26A-666 T able 5.1 I/O Register Address Map [1] Port (1/2) Address Name Address Name Address Name Address Name 0000H 0010H P4 0020H P8 0030H PC 1H 1H 1H P8FC2 1H 2H 2H 2H 2H PCCR 3H 3H .
TMP92CZ26A 92CZ26A-667 [1] Port (2/2) Address Name Address Name Address Name Address Name 0080H 0090H PGDR 00A0H PT 00B0H PX 1H P1DR 1H 1H 1H 2H 2H 2H PTCR 2H PXCR 3H 3H PJDR 3H PTFC 3H PXFC 4H P4DR 4.
TMP92CZ26A 92CZ26A-668 [2] INTC Address Name Address Name Address Name Address Name 00D0H INTE12 00E0H INTESBIADM 00F0H INTE0 0100H DMA0V 1H INTE34 1H INTESPI 1H INTETC01 /INTEDMA01 1H DMA1V 2H INTE56.
TMP92CZ26A 92CZ26A-669 [5] SDRAMC Address Name 0250H SDACR 1H SDCISR 2H SDRCR 3H SDCMM 4H SDBLS 5H 6H 7H 8H 9H AH BH CH DH EH FH [6] LCDC [7] PMC Address Name Address Name Address Name Address Name 02.
TMP92CZ26A 92CZ26A-670 [8] USBC (1/2) Address Name Address Name Address Name Address Name 0500H Descriptor 0780H ENDPOINT0 0790H EP0_STATUS 07A0H to RAM 1H ENDPOIN T1 1H EP1_STATUS 1H EP1_SIZE_L_B 067.
TMP92CZ26A 92CZ26A-671 [8] USBC (2/2) Address Name Address Name 07E0H Port Status 07F0H USBINTFR1 1H FRAME_L 1H USBINTFR2 2H FRAME_H 2H USBINTFR3 3H ADDRESS 3H USBINTFR4 4H 4H USBINTMR1 5H 5H USBINTMR.
TMP92CZ26A 92CZ26A-672 [9] SPIC Address Name Address Name 0820H SPIMD 0830H SPITD0 1H SPIMD 1H SPITD0 2H SPICT 2H SPITD1 3H SPICT 3H SPITD1 4H SPIST 4H SPIRD0 5H SPIST 5H SPIRD0 6H SPICR 6H SPIRD1 7H .
TMP92CZ26A 92CZ26A-673 [1 1] NAND-Flash controller Address Name Address Name Address Name 08C0H NDFMCR0 08D0H NDRSCA0 1FF0H NDFDTR0 1H NDFMCR0 1H NDRSCA0 1H NDFD TR0 2H NDFMCR1 2H NDRSCD0 2H NDFDTR1 3.
TMP92CZ26A 92CZ26A-674 [12] DMAC Address Name Address Name Address Name Address Name 0900H HDMAS0 0910H HDMAS1 0920H HDMAS2 0930H HDMAS3 1H HDMAS0 1H HDMAS1 1H HDMAS2 1H HDMAS3 2H HDMAS0 2H HDMAS1 2H .
TMP92CZ26A 92CZ26A-675 [13] CGEAR, PLL [14] 8-bit timer Address Name Address Name Address Name 10E0H SYSCR0 1100H TA01RUN 1110H TA45RUN 1H SYSCR1 1H 1H 2H SYSCR2 2H TA0REG 2H TA4REG 3H EMCCR0 3H TA1RE.
TMP92CZ26A 92CZ26A-676 [18] 10-bit ADC [19] WDT Address Name Address Name Address Name 12A0H ADREG0L 12B0H ADREGSPL 1300H WDMOD 1H ADREG0H 1H ADREGSPH 1H WDCR 2H ADREG1L 2H Reserved 2H 3H ADREG1H 3H R.
TMP92CZ26A 92CZ26A-677 [22] I 2 S [23] MAC Address Name Address Name Address Name Address Name 1800H I2S0BUF 1810H I2S1BUF 1BE0H MACMA 1BF0H 1H 1H 1H MACMA 1H 2H 2H 2H MACMA 2H 3H 3H 3H MACMA 3H 4H 4H.
TMP92CZ26A 92CZ26A-678 (1) I/O ports (1/1 1) Symbol Name Address 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 R/W P1 PORT1 0004H Data from external port (Output latch register is cleared to “0”.
TMP92CZ26A 92CZ26A-679 (1) I/O ports (2/1 1) Symbol Name Address 7 6 5 4 3 2 1 0 PR3 PR2 PR1 PR0 R/W PR PORTR 0064H Data from external port (Output latch register is cleared to “0”) PT7 PT6 PT5 PT.
TMP92CZ26A 92CZ26A-680 (1) I/O ports (3/1 1) Symbol Name Address 7 6 5 4 3 2 1 0 P17C P16C P15C P14C P13C P12C P11C P10C W 0 0 0 0 0 0 0 0 P1CR PORT1 control register 0006H (Prohibit RMW) 0: Input 1:O.
TMP92CZ26A 92CZ26A-681 (1) I/O ports (4/1 1) Symbol Name Address 7 6 5 4 3 2 1 0 P87F P86F P85F P84F P83F P82F P81F P80F W 0 0 0 0 0 0 0 0 P8FC PORT8 function register 0023H (Prohibit RMW) 0: Port 1: .
TMP92CZ26A 92CZ26A-682 (1) I/O ports (5/1 1) Symbol Name Address 7 6 5 4 3 2 1 0 PA7F PA6F PA5F PA4F PA3F PA2F PA1F PA0F W 0 0 0 0 0 0 0 0 PAFC PORTA function register 002BH (Prohibit RMW) 0: Key-in d.
TMP92CZ26A 92CZ26A-683 (1) I/O ports (6/1 1) Symbol Name Address 7 6 5 4 3 2 1 0 PG3F W 0 PGFC PORTG function register 0043H (Prohibit RMW) 0:Input port, AN3 1: ADTRG PJ6C PJ5C W 0 0 PJCR PORTJ contro.
TMP92CZ26A 92CZ26A-684 (1) I/O ports (7/1 1) Symbol Name Address 7 6 5 4 3 2 1 0 PN7C PN6C PN5C PN4C PN3C PN2C PN1C PN0C W 0 0 0 0 0 0 0 0 PNCR PORTN control register 005EH (Prohibit RMW) 0: Input 1: .
TMP92CZ26A 92CZ26A-685 (1) I/O ports (8/1 1) Symbol Name Address 7 6 5 4 3 2 1 0 PU7C PU6C PU5C PU4C PU3C PU2C PU1C PU0C W 0 0 0 0 0 0 0 0 PUCR PORTU control register 00A6H (Prohibit RMW) 0: Input 1: .
TMP92CZ26A 92CZ26A-686 (1) I/O ports (9/1 1) Symbol Name Address 7 6 5 4 3 2 1 0 P17D P16D P15D P14D P13D P12D P11D P10D R/W 1 1 1 1 1 1 1 1 P1DR PORT1 drive register 0081H Input/Output buffer drive r.
TMP92CZ26A 92CZ26A-687 (1) I/O ports (10/1 1) Symbol Name Address 7 6 5 4 3 2 1 0 PG3D PG2D R/W 1 1 PGDR PORTG drive register 0090H Input/Output buffer drive register for standby mode PJ7D PJ6D PJ5D P.
TMP92CZ26A 92CZ26A-688 (1) I/O ports (1 1/1 1) Symbol Name Address 7 6 5 4 3 2 1 0 PW7D PW6D PW5D PW4D PW3D PW2D PW1D PW0D R/W 1 1 1 1 1 1 1 1 PWDR PORTW drive register 009EH Input/Output buffer drive.
TMP92CZ26A 92CZ26A-689 (2) Interrupt control (1/4) Symbol Name Address 7 6 5 4 3 2 1 0 − INT0 − − − − I0C I0M2 I0M1 I0M0 − − R R/W INTE0 INT0 enable 00F0H Always write “0” 0 0 0 0 IN.
TMP92CZ26A 92CZ26A-690 (2) Interrupt control (2/4) Symbol Name Address 7 6 5 4 3 2 1 0 − INTUSB − − − − IUSBC IUSBM2 IUSBM1 IUSBM0 − − R R/W INTEUSB INTUSB enable 00E3H Always write “0.
TMP92CZ26A 92CZ26A-691 (2) Interrupt control (3/4) Symbol Name Address 7 6 5 4 3 2 1 0 INTTC1/INTDMA1 INTTC0/INT DMA0 ITC1C /IDMA1C ITC1M2 /IDMA1M2 ITC1M1 /IDMA1M1 ITC1M0 /IDMA1M0 ITC0C /IDMA0C ITC0M2.
TMP92CZ26A 92CZ26A-692 (2) Interrupt control (4/4) Symbol Name Address 7 6 5 4 3 2 1 0 DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 R/W 0 0 0 0 0 0 DMA0V DMA0 start vector 0100H DMA0 start vector DMA1V5 .
TMP92CZ26A 92CZ26A-693 (3) Memory controller (1/4) Symbol Name Address 7 6 5 4 3 2 1 0 B0WW3 B0WW2 B0WW1 B0WW0 B0WR 3 B0WR2 B0WR1 B0WR0 R/W 0 0 1 0 0 0 1 0 Write waits Read w aits 0001: 0 waits 0101: .
TMP92CZ26A 92CZ26A-694 (3) Memory controller (2/4) Symbol Name Address 7 6 5 4 3 2 1 0 B3WW3 B3WW2 B3WW1 B3WW0 B3WR 3 B3WR2 B3WR1 B3WR0 R/W 0 0 1 0 0 0 1 0 Write waits Read waits 0001: 0 waits 0101: 2.
TMP92CZ26A 92CZ26A-695 (3) Memory controller (3/4) Symbol Name Address 7 6 5 4 3 2 1 0 M0V20 M0V19 M0V18 M0V17 M0V16 M0V15 M0V14-9 M0V8 R/W 1 1 1 1 1 1 1 1 MAMR0 Memory address mask register 0 0142H 0.
TMP92CZ26A 92CZ26A-696 (3) Memory controller (4/4) Symbol Name Address 7 6 5 4 3 2 1 0 OPGE OPWR1 OPWR0 PR1 P R0 R/W 0 0 0 1 0 PMEMCR Page ROM control register 0166H ROM page access 0: Disable 1: Enab.
TMP92CZ26A 92CZ26A-697 (4) TSI Symbol Name Address 7 6 5 4 3 2 1 0 TSI7 INGE PTST TWIEN PYEN PXEN MYEN MXEN R/W R/W R R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 TSICR0 TSI control register0 01F0H 0: Disable .
TMP92CZ26A 92CZ26A-698 (5) SDRAM controller Symbol Name Address 7 6 5 4 3 2 1 0 SRDS − SMUXW1 SMUXW0 SPRE SMAC R/W R/W 1 0 0 0 0 0 SDACR SDRAM access control register 0250H Read data shift function .
TMP92CZ26A 92CZ26A-699 (6) LCD controller (1/6) Symbol Name Address 7 6 5 4 3 2 1 0 RAMTYPE1 RAMTYPE0 SCPW1 SCPW 0 MODE3 MODE2 MODE1 MODE0 R/W 0 0 1 1 0 0 0 0 LD bus transfer speed Mode setting SCPW2=.
TMP92CZ26A 92CZ26A-700 (6) LCD controller (2/6) Symbol Name Address 7 6 5 4 3 2 1 0 LCP0P LHSP LVSP LLDP LVSW1 LVSW0 R/W R/W R/W R/W R/W R/W 1 0 1 0 0 0 LCDCTL1 LCD control1 register 0286H LCP0 phase .
TMP92CZ26A 92CZ26A-701 (6) LCD controller (3/6) Symbol Name Address 7 6 5 4 3 2 1 0 OE0D6 OE0D5 OE0D4 OE0D3 OE0D2 OE0D1 OE0D0 W 0 0 0 0 0 0 0 LCDO0DLY LGOE0 Delay register 0291H OE0 delay (bits 6-0) O.
TMP92CZ26A 92CZ26A-702 (6) LCD controller (4/6) Symbol Name Address 7 6 5 4 3 2 1 0 LMSA7 LMSA6 LMSA5 LMSA4 LMSA3 LMSA2 LMSA1 R/W 0 0 0 0 0 0 0 LSAML Start address register LCD main-L 02A0H LCD main a.
TMP92CZ26A 92CZ26A-703 (7) PMC Symbol Name Address 7 6 5 4 3 2 1 0 PCM_ON − WUTM1 WUTM0 02A0H R/W W R/W R/W After system reset 0 0 0 0 After Ho t reset Data retained − Data retained Data retained PMCCTL PMC Control Register Power Cut Mode 0: Disable 1: Enable Always write “0” Always read as “0” Warm-up time 00: 29 (15.
TMP92CZ26A 92CZ26A-704 (8) USB controller (1/6) Symbol Name Address 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W Descriptor RAM0 Descriptor RAM 0 register 0500H Undefined Undefined Undefi ned Undefined.
TMP92CZ26A 92CZ26A-705 (8) USB control ler (2/6) Symbol Name Address 7 6 5 4 3 2 1 0 TOGGLE SUSPEND STATUS[2] STATUS[1] STATUS[0] FIFO_DISABLE STAGE_ERR R EP0_STATUS Endpoint 0 status register 0790H 0.
TMP92CZ26A 92CZ26A-706 (8) USB control ler (3/6) Symbol Name Address 7 6 5 4 3 2 1 0 DATASIZE9 DATASIZE8 DATASIZE7 R EP1_SIZE_ H_B Endpoint 1 size register High B 07B1H 0 0 0 DATASIZE9 DATASIZE8 DATAS.
TMP92CZ26A 92CZ26A-707 (8) USB control ler (4/6) Symbol Name Address 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 W SetupReceiv ed SetupRecei- ved register 07C8H 0 0 0 0 0 0 0 0 REMOTEWAKEUP ALTE RNATE[1] .
TMP92CZ26A 92CZ26A-708 (8) USB control ler (5/6) Symbol Name Address 7 6 5 4 3 2 1 0 Reserved7 Reserved6 PaperError Select NotError Reserved2 Reserved1 Reserved0 W Port Status Port status register 07E.
TMP92CZ26A 92CZ26A-709 (8) USB control ler (6/6) Symbol Name Address 7 6 5 4 3 2 1 0 MSK_URST_STR MSK_UR ST_END MSK_SUS MSK_RESUME MSK_CLKSTOP MSK_CLKON R/W 1 1 1 1 1 1 USBINTMR1 USB interrupt mask re.
TMP92CZ26A 92CZ26A-710 (9) SPIC (1/2) Symbol Name Address 7 6 5 4 3 2 1 0 SWRST XEN CLKSEL2 CLKSEL1 CLKSEL0 W R/W R/W 0 0 1 0 0 0820H (Prohibit RMW) Software reset 0: don’t care 1: Reset SYSCK 0: di.
TMP92CZ26A 92CZ26A-71 1 (9) SPIC (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 CRCD7 CRCD6 CRCD5 CRCD4 CRCD3 CRCD2 CRCD1 CRCD0 R 0 0 0 0 0 0 0 0 0826H CRC result register [7:0] CRCD15 CRCD14 CRCD13 CRCD12.
TMP92CZ26A 92CZ26A-712 (10) MMU (1/8) Symbol Name Address 7 6 5 4 3 2 1 0 X7 X6 X5 X4 X3 X2 X1 X0 R/W 0 0 0 0 0 0 0 0 LOCALPX LOCALX register for program 0880H Set BANK number for LOCAL-X (“0” is disabled because of ov erlapped with Common-area.
TMP92CZ26A 92CZ26A-713 (10) MMU (2/8) Symbol Name Address 7 6 5 4 3 2 1 0 X7 X6 X5 X4 X3 X2 X1 X0 R/W 0 0 0 0 0 0 0 0 LOCALLX LOCALX register for LCD 0888H Set BANK number for LOCAL-X (“0” is dis abled because of overlapped with Common-area.
TMP92CZ26A 92CZ26A-714 (10) MMU (3/8) Symbol Name Address 7 6 5 4 3 2 1 0 X7 X6 X5 X4 X3 X2 X1 X0 R/W 0 0 0 0 0 0 0 0 LOCALRX LOCALX register for read 0890H Set BANK number for LOCAL-X (“0” is dis abled because of overlapped with Common-area.
TMP92CZ26A 92CZ26A-715 (10) MMU (4/8) Symbol Name Address 7 6 5 4 3 2 1 0 X7 X6 X5 X4 X3 X2 X1 X0 R/W 0 0 0 0 0 0 0 0 LOCALWX LOCALX register for write 0898H Set BANK number for LOCAL-X (“0” is dis abled because of overlapped with Common-area.
TMP92CZ26A 92CZ26A-716 (10) MMU (5/8) Symbol Name Address 7 6 5 4 3 2 1 0 X7 X6 X5 X4 X3 X2 X1 X0 R/W 0 0 0 0 0 0 0 0 LOCALESX LOCALX register for DMA source 08A0H Set BANK number for LOCAL-X (“0” is dis abled because of overlapped with Common-area.
TMP92CZ26A 92CZ26A-717 (10) MMU (6/8) Symbol Name Address 7 6 5 4 3 2 1 0 X7 X6 X5 X4 X3 X2 X1 X0 R/W 0 0 0 0 0 0 0 0 LOCALEDX LOCALX register for DMA destination 08A8H Set BANK number for LOCAL-X (“0” is dis abled because of overlapped with Common-area.
TMP92CZ26A 92CZ26A-718 (10) MMU (7/8) Symbol Name Address 7 6 5 4 3 2 1 0 X7 X6 X5 X4 X3 X2 X1 X0 R/W 0 0 0 0 0 0 0 0 LOCALOSX LOCALX register for DMA source 08B0H Set BANK number for LOCAL-X (“0” is dis abled because of overlapped with Common-area.
TMP92CZ26A 92CZ26A-719 (10) MMU (8/8) Symbol Name Address 7 6 5 4 3 2 1 0 X7 X6 X5 X4 X3 X2 X1 X0 R/W 0 0 0 0 0 0 0 0 LOCALODX LOCALX register for DMA destination 08B8H Set BANK number for LOCAL-X (“0” is dis abled because of overlapped with Common-area.
TMP92CZ26A 92CZ26A-720 (1 1) NAND-Flash controller (1/4 ) Symbol Name Address 7 6 5 4 3 2 1 0 WE ALE CLE CE0 CE1 ECCE BUSY ECCRST R/W 0 0 0 0 0 0 0 0 08C0H (Prohibit RMW) WE enable 0: Disable 1: Enabl.
TMP92CZ26A 92CZ26A-721 (1 1) NAND-Flash controller (2/4 ) Symbol Name Address 7 6 5 4 3 2 1 0 ECCD7 ECCD6 ECCD5 ECCD4 ECCD3 ECCD2 ECCD1 ECCD0 R 0 0 0 0 0 0 0 0 08C8H NAND Flash ECC Register (7-0) ECCD.
TMP92CZ26A 92CZ26A-722 (1 1) NAND-Flash controller (3/4 ) Symbol Name Address 7 6 5 4 3 2 1 0 RS0A7 RS0A6 RS0A5 RS0A4 RS0A3 RS0A2 RS0A1 RS0A0 R 0 0 0 0 0 0 0 0 08D0H NAND Flash Reed-Solomon Calculatio.
TMP92CZ26A 92CZ26A-723 (1 1) NAND-Flash controller (4/4 ) Symbol Name Address 7 6 5 4 3 2 1 0 RS3A7 RS3A6 RS3A5 RS3A4 RS3A3 RS3A2 RS3A1 RS3A0 R 0 0 0 0 0 0 0 0 08DCH NAND Flash Reed-Solomon Calculatio.
TMP92CZ26A 92CZ26A-724 (12) DMAC (1/7) Symbol Name Address 7 6 5 4 3 2 1 0 D0SA7 D0SA6 D0SA5 D0SA4 D0SA3 D0SA2 D0SA1 D0SA0 R/W 0 0 0 0 0 0 0 0 0900H Source address for DMA0 (7:0) D0SA15 D0SA14 D0SA13 .
TMP92CZ26A 92CZ26A-725 (12) DMAC (2/7) Symbol Name Address 7 6 5 4 3 2 1 0 D1SA7 D1SA6 D1SA5 D1SA4 D1SA3 D1SA2 D1SA1 D1SA0 R/W 0 0 0 0 0 0 0 0 0910H Set source address for DMA1 (7:0) D1SA15 D1SA14 D1S.
TMP92CZ26A 92CZ26A-726 (12) DMAC (3/7) Symbol Name Address 7 6 5 4 3 2 1 0 D2SA7 D2SA6 D2SA5 D2SA4 D2SA3 D2SA2 D2SA1 D2SA0 R/W 0 0 0 0 0 0 0 0 0920H Source address for DMA2 (7:0) D2SA15 D2SA14 D2SA13 .
TMP92CZ26A 92CZ26A-727 (12) DMAC (4/7) Symbol Name Address 7 6 5 4 3 2 1 0 D3SA7 D3SA6 D3SA5 D3SA4 D3SA3 D3SA2 D3SA1 D3SA0 R/W 0 0 0 0 0 0 0 0 0930H Set source address for DMA3 (7:0) D3SA15 D3SA14 D3S.
TMP92CZ26A 92CZ26A-728 (12) DMAC (5/7) Symbol Name Address 7 6 5 4 3 2 1 0 D4SA7 D4SA6 D4SA5 D4SA4 D4SA3 D4SA2 D4SA1 D4SA0 R/W 0 0 0 0 0 0 0 0 0940H Source address for DMA4 (7:0) D4SA15 D4SA14 D4SA13 .
TMP92CZ26A 92CZ26A-729 (12) DMAC (6/7) Symbol Name Address 7 6 5 4 3 2 1 0 D5SA7 D5SA6 D5SA5 D5SA4 D5SA3 D5SA2 D5SA1 D5SA0 R/W 0 0 0 0 0 0 0 0 0950H Source address for DMA5 (7:0) D5SA15 D5SA14 D5SA13 .
TMP92CZ26A 92CZ26A-730 (12) DMAC (7/7) Symbol Name Address 7 6 5 4 3 2 1 0 DMAE5 DMAE4 DMAE3 DMAE2 DMAE1 DMAE0 R/W 0 0 0 0 0 0 HDMAE DMA enable Register 097EH DMA channel op eration 0: Disable 1: Enab.
TMP92CZ26A 92CZ26A-731 (13) Clock gear , PLL Symbol Name Address 7 6 5 4 3 2 1 0 XTEN USBCLK1 USBCLK0 WUEF PRCK R/W R/W R/W 1 0 0 0 0 SYSCR0 Syst em clock control register0 10E0H Low -frequency oscill.
TMP92CZ26A 92CZ26A-732 (14) 8-bit timer (1/2) Symbol Name Address 7 6 5 4 3 2 1 0 TA0RDE I2TA01 TA01PRUN TA1RUN TA0RUN R/W R/W 0 0 0 0 0 TMRA01 prescaler Up counter (UC1) Up counter (UC0) TA01RUN TMRA.
TMP92CZ26A 92CZ26A-733 (14) 8-bit timer (1/2) Symbol Name Address 7 6 5 4 3 2 1 0 TA4RDE I2TA45 TA45PRUN TA5RUN TA4RUN R/W R/W 0 0 0 0 0 TMRA45 prescaler Up counter (UC5) Up counter (UC4) TA45RUN TMRA.
TMP92CZ26A 92CZ26A-734 (15) 16-bit timer (1/2) Symbol Name Address 7 6 5 4 3 2 1 0 TB0RDE − I2TB0 TB0PRUN TB0RUN R/W R/W R/W R/W R/W 0 0 0 0 0 TMRB0 prescaler Up counter (UC10) TB0RUN TMRB0 RUN register 1180H Double buffer 0: disable 1: enable Always write “0”.
TMP92CZ26A 92CZ26A-735 (15) 16-bit timer (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 TB1RDE − I2TB1 TB1PRUN TB1RUN R/W R/W R/W R/W R/W 0 0 0 0 0 TMRB0 prescaler Up counter (UC12) TB1RUN TMRB1 RUN register 1190H Double buffer 0: disable 1: enable Always write “0”.
TMP92CZ26A 92CZ26A-736 (16) UART/Serial channel s Symbol Name Address 7 6 5 4 3 2 1 0 RB7 TB7 RB6 TB6 RB5 TB5 RB4 TB4 RB3 TB3 RB2 TB2 RB1 TB1 RB0 TB0 R (Receive) /W (Transmission) SC0BUF Serial channe.
TMP92CZ26A 92CZ26A-737 (17) SBI Symbol Name Address 7 6 5 4 3 2 1 0 BC2 BC1 BC0 ACK − SCK2 SCK1 SCK0 /SWRMON R/W R/W R R/W R/W 0 0 0 0 1 0 0 0/1 SBICR1 Serial bus interface control register 1 1240H .
TMP92CZ26A 92CZ26A-738 (18) AD converter (1/3) Symbol Name Address 7 6 5 4 3 2 1 0 ADR01 ADR00 OVR0 ADR0RF R R R 0 0 0 0 ADREG0L AD conversion result register 0 low 12A0H Store Lower 2 bits of AN0 AD .
TMP92CZ26A 92CZ26A-739 (18) AD converter (2/3) Symbol Name Address 7 6 5 4 3 2 1 0 ADRSP1 ADRSP0 OVSRP ADRSPRF R R R 0 0 0 0 ADREGSPL High priority Conversion Register SP low 12B0H Store Lower 2 bits .
TMP92CZ26A 92CZ26A-740 (18) AD converter (3/3) Symbol Name Address 7 6 5 4 3 2 1 0 EOS BUSY I2AD ADS HTRGE TSEL1 TSEL0 R R/W 0 0 0 0 0 0 0 ADMOD0 AD mode control register 0 12B8H Normal AD conversion .
TMP92CZ26A 92CZ26A-741 (19) W atchdog timer Symbol Name Address 7 6 5 4 3 2 1 0 WDTE WDTP1 WDTP0 I2WDT RESCR − R/W R/W 1 0 0 0 0 0 WDMOD WDT mode register 1300H WDT control 1: Enable Select detectin.
TMP92CZ26A 92CZ26A-742 (20) RTC (Re al-T ime Clock) Symbol Name Address 7 6 5 4 3 2 1 0 SE6 SE5 SE4 SE3 SE2 SE1 SE0 R/W Undefined SECR Second register 1320H “0” is read 40 sec. 20 sec. 10 sec. 8 sec. 4 sec. 2 sec. 1 sec. MI6 MI5 MI4 MI3 MI2 MI1 MI0 R/W Undefined MINR Minute register 1321H “0” is read 40 min.
TMP92CZ26A 92CZ26A-743 (21) Melody/alarm generato r Symbol Name Address 7 6 5 4 3 2 1 0 AL8 AL7 AL6 AL5 AL4 AL3 AL2 AL1 R/W 0 0 0 0 0 0 0 0 ALM Alarm- pattern register 1330H Alarm pattern setting FC1 .
TMP92CZ26A 92CZ26A-744 (22) I 2 S (1/2) Symbol Name Address 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 B015 B014 B013 B012 B011 B010 B009 B008 B007 B006 B005 B004 B003 B002 B001 B000 W Undefined Transmiss.
TMP92CZ26A 92CZ26A-745 (22) I 2 S (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 TXE0 *CNTE0 DIR0 BIT0 DTFM T01 DTFM T00 S YSCKE0 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 1808H Transmit 0: Stop 1: Start C.
TMP92CZ26A 92CZ26A-746 (23) MAC (1/ 2 ) Symbol Name Address 7 6 5 4 3 2 1 0 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 R/W Undefined MACMA_LL Data register Multiplier A-LL 1BE0H Multiplier A data register [7:0] .
TMP92CZ26A 92CZ26A-747 (23) MAC (2/ 2 ) Symbol Name Address 7 6 5 4 3 2 1 0 OR39 OR38 OR37 OR36 OR35 OR34 OR33 OR32 R/W Undefined MACOR_HLL Data register Multiply and Accumulate -HLL 1BECH Multiply an.
TMP92CZ26A 92CZ26A-748 6. Package P-FBGA228-1515-0.80A5 TOP VIEW BOTTOM VIEW.
デバイスToshiba TLCS-900の購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
Toshiba TLCS-900をまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはToshiba TLCS-900の技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Toshiba TLCS-900の取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Toshiba TLCS-900で得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Toshiba TLCS-900を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はToshiba TLCS-900の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Toshiba TLCS-900に関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちToshiba TLCS-900デバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
