XilinxメーカーLogiCore LogiCore PCI v3.0の使用説明書/サービス説明書
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R LogiCORE™ PCI v3.0 Getting Star ted Guide UG157 A ugust 31, 2005 v3.0.151.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com UG157 August 31, 2005 Xilinx is disclosing this Specification to you solely f or use in the dev elopment of designs to oper ate on Xilinx FPGAs.
w ww .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 06/24/02 3.0 Initial Xilinx release of corpora te-wide common template set, used for U ser Guides, T utorials, Release Notes, Manuals, a nd ot her lengthy , multiple-chapter documents created by both CMP and ITP .
PCI v3.0.151 Ge tting Started Guide www .xilinx.com UG157 August 31, 2005.
w ww .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Resources . .
PCI v3.0.151 Ge tting Started Guide UG157 August 31, 2005 www .xilinx.com Chapter 5: Synthesizing a Design Synplicity Synplify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Verilog . . . . . .
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 7 UG157 August 31, 2005 R Pr eface About This Guide The PCI Gettin g Started Guide pr ovides information about the LogiCORE™ Peripher al Component Inter connect (PCI) interface, whic h provides a fully verified, pr e-implemented PCI bus interface available in bo th 32-bit and 64-bit versions.
8 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Preface: About This Guide R Additional Resour ces For additional information, go to ht tp://support.xilinx.com . The following table lists some of the resour ces you can access from this website.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 9 UG157 August 31, 2005 Con ventions R Online Document The following conventions ar e used in this document: Italic font V ariables in a syntax stat.
10 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Preface: About This Guide R.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 11 UG157 August 31, 2005 R Chapter 1 Getting Started The PCI interface provides a fully verified, pr e-implemented PCI bus interf ace available in both 32-bit and 64-bit versions with support for operation at 33 MHz and 66 MHz.
12 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 1: Getting Star ted R T echnical Support For technical support, visit www .xilinx.com/support . Questions ar e routed to a team of engineers with expertise using the PCI interface.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 13 UG157 August 31, 2005 R Chapter 2 Installing and Licensing the Cor e This chapter provides instructions for installing and obtaining a license for the PCI interface cor e, which you must do befor e using it in your designs .
14 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 2: Installing and Licens ing the Core R CORE Generator IP Updates Installer 1. From the CORE Generator main GUI, choos e T ools > Updates Installer to start the Updates Installer .
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 15 UG157 August 31, 2005 Installing the Core R the location of the Xilinx installati on. Note that you may need system administrator privileges to install the update.
16 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 2: Installing and Licens ing the Core R Licensing Options Ev aluation The method for obtaining an evaluation license is dete rmined by the version of the PCI core you choose.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 17 UG157 August 31, 2005 Installing Y our Li cense File R Installing Y our License File After selecting a license option, an email will be sent to you that includes instructions for installing your license file.
18 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 2: Installing and Licens ing the Core R.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 19 UG157 August 31, 2005 R Chapter 3 Family Specific Considerations This chapter provides important design inform ation specific to the PCI interface targeting V irtex and Spartan devices. Design Suppor t Ta b l e 3 - 1 provides a list of supported device and int erface combinations.
20 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 3: Fa mily Speci fic Considerations R 2S200-FG456-6C 33 MHz 3.3V 64-bit pcim_lc_33_3_s 2s200fg456_64_33.ucf no guide file 2S200-FG456-6C 66 MHz 3.3V 64-bit pcim_lc_66_3_d 2s200fg456_64_66.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 21 UG157 August 31, 2005 Design Support R V300E-BG432-6C 66 MHz 3.3V 64-bit pcim_lc_66_3_d v300ebg432_64_66.ucf v300ebg432_64_66.ncd V300E-BG432-6C 33 MHz 3.3V 64-bit pcim_lc_33_3_s v300ebg432_64_33.
22 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 3: Fa mily Speci fic Considerations R 2VP20-FF1 152-6C/I 66 MHz 3.3V 64-bit pcim_lc_66_3_s 2vp20ff1152_64_66.ucf 2vp20ff1152_64_66.ncd 2VP20-FF1 152-5C/I 33 MHz 3.3V 64-bit pcim_lc_33_3_s 2vp20ff1152_64_33.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 23 UG157 August 31, 2005 Design Support R 4VSX35-FF668-10C/I global clock 33 MHz 3.3V 64-bit pcim_lc_33_3_g 4vsx35ff668_64_33g.ucf no guide file 4VFX20-FF672-10C/I global clock 33 MHz 3.3V 64-bit pcim_lc_33_3_g 4vfx20ff672_64_33g.
24 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 3: Fa mily Speci fic Considerations R 2S50-PQ208-5C 33 MHz 3.3V 32-bit pcim_lc_33_3_s 2s050pq208_32_33.ucf no guide file 2S100-PQ208-5C 33 MHz 5.0V 32-bit pcim_lc_33_5_s 2s100pq208_32_33.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 25 UG157 August 31, 2005 Design Support R 2S300E-PQ208-6C 33 MHz 3.3V 32-bit pcim_lc_33_3_s 2s300epq208_32_33.ucf no guide file V100E-BG352-6C 33 MHz 3.3V 32-bit pcim_lc_33_3_s v100ebg352_32_33.ucf no guide file V300-BG432-5C 33 MHz 5.
26 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 3: Fa mily Speci fic Considerations R 3S1200E-FG400-4C/I 33 MHz 3.3V 32-bit pcim_lc_33_3_s 3s1200efg400_32_33.ucf no guide file V200-FG256-6C 66 MHz 3.3V 32-bit pcim_lc_66_3_d v200fg256_32_66.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 27 UG157 August 31, 2005 Design Support R See the product r elease notes in cluded with the core for a complete directory structur e and file list. 4VSX35-FF668-1 1C/I regional clock 66 MHz 3.3V 32-bit pcim_lc_66_3r 4vsx35ff668_32_33r.
28 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 3: Fa mily Speci fic Considerations R Wrapper Files W rapper files contain an instance of the PCI interface and the instances of all I/O elements used by the PCI interface.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 29 UG157 August 31, 2005 Device Initialization R De vice Initialization Immediately after FPGA configuration, both the PCI inter face and the user application are initialized by the startup mechanism present in all V irtex and Spartan devices.
30 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 3: Fa mily Speci fic Considerations R Although this technique is not technically co mpliant with the PCI specification due to the extra loading on REQ64# and RST# , the us e of a large series r esistor helps minimize this effe ct.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 31 UG157 August 31, 2005 Input Delay Buffer s R IOBs of the FPGA device. The us e of these delay buf fers is selected through the implementation specific constraints file Some implementations use alternate delay buf fers, selected via the CFG[248:245] bits in the HDL configuration file.
32 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 3: Fa mily Speci fic Considerations R 1. The jitter of the source clock, to determine if it is appropriate for use as an input to a DCM. 2. The DCM configuration, to generate a 200 MHz clock on any appropriate DCM output (CLK FX, CLKDV , and so fort h).
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 33 UG157 August 31, 2005 Regional Clock Usage R For designs using regional clocking, the PCI interface and those portions of the user application clocked from the PCI bus clock must completely fit inside the three clock region s accessible to the r egional clock signal.
34 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 3: Fa mily Speci fic Considerations R Bus Cloc k Usage The bus clock output provided by the in terface is derived fr om the bus clock input, and is distributed using a global clock buffer .
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 35 UG157 August 31, 2005 Electrical Compliance R maximum allowed fre quency , and the fr equenc y may change on a cycle-by-cycle basis. Under certain condition s, the PCI core may also apply phase shifts to this clo ck.
36 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 3: Fa mily Speci fic Considerations R Figur e 3-3 shows the small range of supply voltage values wher e V IL or V IH are technically non-compliant.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 37 UG157 August 31, 2005 Generating Bi tstreams R Figur e 3-4 shows one possible low-cos t solution to generate the r equired 3. 0 volt output driver supply . Xilinx recommends the use of the circuit shown in Figure 3-4 , although other approaches using othe r regulators are possible.
38 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 3: Fa mily Speci fic Considerations R This option is used to intr oduc e additional delay on a global clock net. It is important to note that this additional delay is observable on the CLK output of the PCI interface, which is supplied to the user applica tion.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 39 UG157 August 31, 2005 R Chapter 4 Functional Simulation This chapter describes how to simulate the ping64 example design with global clocks using the supported functional si mulati on tools. For the PCI 32 i nterface, substitute ping32 for ping64 .
40 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 4: Functional Sim u latio n R Most of the files listed ar e related to the example design and its testbench. For oth er testbenches, the foll owing subset must be used for proper simulation of the PCI interface: .
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 41 UG157 August 31, 2005 Model T echnolog y ModelSim R 3. Modify the library search path by changing <Xilinx Install Path> to match the Xilinx installation di rectory and then save the f ile. Most of the files listed ar e related to the example design and its testbench.
42 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 4: Functional Sim u latio n R <Install Path>/vhdl/example/ func_sim 4.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 43 UG157 August 31, 2005 R Chapter 5 Synthesizing a Design This chapter describes how to synthesize the ping64 example design with global clocks using the supported synthesis tools. For the PCI 32 interface, substi tute ping32 for ping64 .
44 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 5: Synthesizing a Design R 4. T o add source files to the new project, click Add. The first file (used by any desig n that instantiates Xili nx primitives) is located in: <Synplicity Install Path>/lib/xilinx 5.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 45 UG157 August 31, 2005 Synplicity Synplify R The next files ar e located in: <Install Path>/verilog/src/x pci 6. Navigate to the xpci directory , select the simulation model and the wrapper files (pci_lc_i.
46 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 5: Synthesizing a Design R 8. After adding the three final file s (for a total of six sou r ce file s), click OK to r eturn to the main project window .
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 47 UG157 August 31, 2005 Synplicity Synplify R 13. On the Device t ab, set the T echnology , Part , Speed, and Package options to r eflect the targeted device (a V300BG432- 6 in this example). Be sure that Disable I/O Insertion is deselected.
48 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 5: Synthesizing a Design R VHDL 1. Start Synplify and choose File > New , or us e the new file icon on the toolbar .
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 49 UG157 August 31, 2005 Synplicity Synplify R 5. Select the virtex.vhd file; then click Add to mo ve this source file into the Files T o Add list. The next files ar e located in: <Install Path>/vhdl/src/xpci 6.
50 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 5: Synthesizing a Design R The final set of design files (the user app lication) is located in: <Install Path>/vhdl/example/ source 7. Navigate to the source directory , select the cfg_ping.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 51 UG157 August 31, 2005 Exemplar Leonar doSpectrum R 12. From the main project window , click Change T arget to display the Options for Implementation dialog box, as shown in Figure 5-17 .
52 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 5: Synthesizing a Design R The end r esult of the synthesis step is an EDIF fi le that is fed into th e Xilinx implementation tools during the implementation step. In practice, the pr ovided script file must be modified to accommodate other des igns.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 53 UG157 August 31, 2005 R Chapter 6 Implementing a Design This chapter describes how to implement the ping64 example design with global clocks using the supporte d FPGA implementation tools (included with the ISE Foundation v7.
54 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 6: Implementing a De sign R •T h e par command, as pr ovided in the script, uses a g uide file in exact guide mode. Note that some designs do not require the use of guide files.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 55 UG157 August 31, 2005 R Chapter 7 T iming Simulation This chapter describes how to perform timing simulation using the ping64 example design with global cl ocks using the supported timing simulation tool s.
56 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 7: Timing Simulation R NC-V erilog processes the simulation files and exits. The testbench prints status messages to the console. After the simulation completes, view the ncverilog.
PCI v3.0.151 Ge tting Started Guide www .xilinx.com 57 UG157 August 31, 2005 Model T echnolog y ModelSim R cp ../xilinx/pcim_top_routed .sdf . 2. V iew the ping.files file. This file lists the individual sou r ce files required, and is shown below: ./pcim_top_routed.
58 www .xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Chapter 7: Timing Simulation R.
デバイスXilinx LogiCore LogiCore PCI v3.0の購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
Xilinx LogiCore LogiCore PCI v3.0をまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはXilinx LogiCore LogiCore PCI v3.0の技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Xilinx LogiCore LogiCore PCI v3.0の取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Xilinx LogiCore LogiCore PCI v3.0で得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Xilinx LogiCore LogiCore PCI v3.0を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はXilinx LogiCore LogiCore PCI v3.0の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Xilinx LogiCore LogiCore PCI v3.0に関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちXilinx LogiCore LogiCore PCI v3.0デバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
