XilinxメーカーUG518の使用説明書/サービス説明書
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[Guide Subtitle] [optional] UG518 (v1.1) A ugust 19, 2009 [ optional] SP601 Har d ware User Guide UG518 (v1.1) A ugust 19, 2009.
SP601 Hard ware Us er Guide www .xilin x.com UG518 (v1.1) A ug ust 19, 2009 Xilinx is disclosing this user gui de, manual, release note , and/or specification (the "Documentation") to y ou solely for use in the de velop ment of designs to operate with Xilinx hardw are devices .
UG518 (v1.1) August 19, 2009 www .xilin x.com SP601 Hardware User Guide Revision History The following table shows the revision history for this document. Date V ersion Revision 07/15/2009 1.0 Initial Xilinx release. 08/19/2009 1.1 • Added Appendix C, “VIT A 57.
SP601 Hard ware Us er Guide www .xilin x.com UG518 (v1.1) A ug ust 19, 2009.
SP601 Hard ware Us er Guide www .xilin x.com 5 UG518 (v1.1) August 19, 2009 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Resources .
6 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Appendix A: References Appendix B: Default Jump er and Switch Settings Appendix C: VITA 57.
SP601 Hard ware Us er Guide www .xilin x.com 7 UG518 (v1.1) August 19, 2009 Pr eface About This Guide This manual accompan ies the Spartan®-6 FP GA SP601 Evaluation Boar d and cont ains information about the SP601 hardwar e and software tools.
8 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Pref ace: About This Guide Online Document The following conventions ar e used in this document: Italic font V ariables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the User Guide for more information.
SP601 Hard ware Us er Guide www .xilin x.com 9 UG518 (v1.1) August 19, 2009 Chapter 1 SP601 Evaluation Board Overview The SP601 board enables har dware and software developers to cr eate or evaluate designs targeting the Spartan®-6 XC6SLX16-2 CSG324 FPGA.
10 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board F eatures The SP601 board pr ovides the following features: • 1. Spartan-6 XC6SLX16-2CS G324 FPGA • 2. 128 MB DDR2 Component Memory • 3.
SP601 Hard ware Us er Guide www .xilin x.com 11 UG518 (v1.1) August 19, 2009 Related Xili nx Documents Bloc k Diagram Figur e 1- 1 shows a high-level block diagram of the SP601 and its peripherals. Related Xilinx Documents Prior to using the SP601 Evaluation Board, user s sh ou ld be f am il iar wi th X il in x res ourc es.
12 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board Detailed Description Figur e 1-2 shows a board photo with number ed features corresponding to Ta b l e 1 -1 and the section headings in this document.
SP601 Hard ware Us er Guide www .xilin x.com 13 UG518 (v1.1) August 19, 2009 Detailed Des cription 1. Spar tan-6 XC6SLX16-2CSG 3 24 FPGA A Xilinx Spartan-6 XC6SLX16-2CSG324 FPGA is install ed on the Embedded Development Board.
14 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board Ref erences See the Xilinx Spartan-6 FPGA docu mentation for mor e information at http://www .xilinx.com/support/documentation/spartan-6.htm .
SP601 Hard ware Us er Guide www .xilin x.com 15 UG518 (v1.1) August 19, 2009 Detailed Des cription Ta b l e 1 - 5 shows the connections and pin numbers for the DDR2 Component Memory .
16 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board Figur e 1-3 provides the user constraints file (UCF) for the DDR2 SDRAM address pins, including the I/O pin assignment and the I/O standar d used.
SP601 Hard ware Us er Guide www .xilin x.com 17 UG518 (v1.1) August 19, 2009 Detailed Des cription Figur e 1-4 provides the UCF constraints for the DDR2 SDRAM d ata pins, including the I/O pin assignment and I/O standard used.
18 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board 3 . SPI x4 Flash The Xilinx Spartan-6 FPGA hosts a SPI interfa ce which is visible to the Xili nx iMP ACT configuration tool. The SPI memory device oper ates at 3.
SP601 Hard ware Us er Guide www .xilin x.com 19 UG518 (v1.1) August 19, 2009 Detailed Des cription X-Ref Target - Figure 1-7 Figure 1- 7: SPI Flash Interface T opology T able 1- 6: SPI x4 Memory Conne.
20 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board Figur e 1-8 provides the UCF constraint s for the SPI serial flash PR OM. Ref erences See the W inbond Serial Flash specifications for more information at http://www .
SP601 Hard ware Us er Guide www .xilin x.com 21 UG518 (v1.1) August 19, 2009 Detailed Des cription H16 FLASH_A6 23 A6 H15 FLASH_A7 22 A7 H14 FLASH_A8 20 A8 H13 FLASH_A9 19 A9 F18 FLASH_A10 18 A10 F17 .
22 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board Note: Memor y U10 pin 56 address A24 is not connected on the 16 MB device . It is made av ailable f or larg er density de vices. Ref erences See the Numonyx Flash Memory specifications for more information at http://www .
SP601 Hard ware Us er Guide www .xilin x.com 23 UG518 (v1.1) August 19, 2009 Detailed Des cription 5. 10/100/1000 T ri-Speed Ether net PHY The SP601 uses the onboar d Marvell Alaska P H Y d e v i c e ( 8 8 E 11 11 ) f o r E t h e r n e t communications at 10, 100, or 1000 Mb/s.
24 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board P18 PHY_RXD7 120 A9 PHY_TXC_GTXCLK 14 B9 PHY_TXCLK 10 A8 PHY_TXER 13 B8 PHY_TXCTL_TXEN 16.
SP601 Hard ware Us er Guide www .xilin x.com 25 UG518 (v1.1) August 19, 2009 Detailed Des cription Ref erences See the Marvell Alaska Gigabit Ethernet T ransc eiver product page for mor e information at http://www .marvell.com/products/tr ansceivers/alaska_gigabit/index.
26 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board Ref erences T echnical information on the Silicon Labs CP2103GM and the VCP drivers can be found on their website at https://www .silabs.com/Pages/default.
SP601 Hard ware Us er Guide www .xilin x.com 27 UG518 (v1.1) August 19, 2009 Detailed Des cription 8-Kb NV Memor y The SP601 hosts a 8-Kb ST Microelectroni cs M24C08-WDW6TP IIC parameter storage memory device (U7) . The IIC address of U7 is 0b1010100, and U7 is not write protected (WP pin 7 is tied to GND).
28 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board Oscillator Sock et (Single-Ended, 2.5V or 3 . 3 V) One populated single-ended clock socket (X2) is provided for user applications. The option of 3.
SP601 Hard ware Us er Guide www .xilin x.com 29 UG518 (v1.1) August 19, 2009 Detailed Des cription T able 1-13: LPC Pinout KJ H G FE D C B A 1 NC NC VREF_A_M2C GND NC NC PG_C2M GND NC NC 2 NC NC PRSNT.
30 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board 34 NC NC LA30_P LA31_N NC NC TRST_L GA0 NC NC 35 NC NC LA30_N GND NC NC GA1 12P0V NC NC 3.
SP601 Hard ware Us er Guide www .xilin x.com 31 UG518 (v1.1) August 19, 2009 Detailed Des cription X-Ref T arget - Figure 1-18 NET "FMC_CLK0_M2C_N" LOC = "A10"; NET "FMC_CLK0_.
32 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board 10. Status LEDs Ta b l e 1 - 1 4 defines the status LEDs. T able 1- 14: Status LEDs Reference Designator Signal Name Color Label Description DS1 FMC_PWR_GOOD_ FLASH_RST_B Green PWR GOOD Indicates power available for VIT A 57.
SP601 Hard ware Us er Guide www .xilin x.com 33 UG518 (v1.1) August 19, 2009 Detailed Des cription 11. FPGA A wak e LED and Suspend Jumper The suspend mode jumper perm its the FP GA to enter an inactive, "su spend" mode. The FPGA A w ake LED DS 8 will go o ut when th e FPGA ent ers this m ode.
34 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board 12. FPGA INIT and DONE LEDs The typical Xilinx FPGA power up and conf iguration status LEDs are pres ent on the SP601. The INIT LED DS10 comes on after the FPGA powers up and completes its internal power-on pr ocess.
SP601 Hard ware Us er Guide www .xilin x.com 35 UG518 (v1.1) August 19, 2009 Detailed Des cription 1 3 . User I/O The SP601 provides the following user and general purpose I/O capabilities: • User L.
36 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board User DIP s witch The SP601 includes an active high four pole DIP switch, as described in Figur e 1-24 and Ta b l e 1 - 1 8 .
SP601 Hard ware Us er Guide www .xilin x.com 37 UG518 (v1.1) August 19, 2009 Detailed Des cription User Pushb utton Switches The SP601 provides five active high pushbu tton switches: SW6, SW4, SW5, SW7 and SW 9. The five pushbuttons all have the same topology as the sample shown in Fi gure 1-25 .
38 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board GPIO Male Pin Header The SP601 provides a 2X6 GPIO male pin he ader supporting 3.3V power , GND and eight I/Os. Figure 1-26 and Ta b l e 1 - 2 0 describe the J13 GPIO Male Pin Header .
SP601 Hard ware Us er Guide www .xilin x.com 39 UG518 (v1.1) August 19, 2009 Detailed Des cription X-Ref Target - Figure 1-27 NET "GPIO_LED_0" LOC = "E13"; NET "GPIO_LED_1&quo.
40 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board 14. FPGA_PR OG_B Pushbutton Switch The SP601 provides one dedicated, active low FPGA_PROG_B pushbutton switch, as shown in Figure 1- 28 .
SP601 Hard ware Us er Guide www .xilin x.com 41 UG518 (v1.1) August 19, 2009 P ower Management The SP601 uses power solutions fr om L TC. An estimate of the current draw on the var ious power supply rails is shown in Ta b l e 1 - 2 2 . X-Ref Target - Figure 1- 3 0 Figure 1-30 : Po wer Suppl y 5V PWR J a ck D ua l S witcher L TM4616 3.
42 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board Configuration Options The FPGA on the SP601 Evaluation Boar d can be configured by the following methods: • “3. SPI x4 Flash,” page 18 • “4.
SP601 Hard ware Us er Guide www .xilin x.com 43 UG518 (v1.1) August 19, 2009 Configuration Options Th e J T A G c h a i n c a n be u s e d t o p ro g r a m t h e F P G A an d ac c e s s t h e F P G A fo r h a rd w a re a n d software debug.
44 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board.
SP601 Hard ware Us er Guide www .xilin x.com 45 UG518 (v1.1) August 19, 2009 Appendix A Refer ences This section pr ovides refer ences to docume ntation supporting Spartan-6 FPGAs, tools, and IP . For additional informati on, see www .xilinx.com/support/documentation/index.
46 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Appendix A: Ref erences.
SP601 Hard ware Us er Guide www .xilin x.com 47 UG518 (v1.1) August 19, 2009 Appendix B Default Jumper and Switch Settings Ta b l e B - 1 shows the default jumper and switch settings f or the SP601.
48 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Appendix B: Default Jumper and Switch Settings.
SP601 Hard ware Us er Guide www .xilin x.com 49 UG518 (v1.1) August 19, 2009 Appendix C VIT A 57.1 FMC Connections Ta b l e C - 1 shows the VIT A 57.1 FMC LPC connections.
50 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Appendix C: VIT A 57.1 FMC Connections G13 FMC_LA08_N E1 1 H13 FMC_LA07_P E7 G15 FMC_LA12_P D6 H14 FMC_LA07_N E8 G16 FMC_LA.
SP601 Hard ware Us er Guide www .xilin x.com 51 UG518 (v1.1) August 19, 2009 Appendix D SP601 Master UCF The UCF template is pr ovided for designs that target the SP601. Net names pr ovided in the constraints below corr elate with net names on the SP601 r ev .
52 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Appendix D: SP601 Mast er UCF NET "DDR2_LDQS_P" LOC = "L4"; NET "DDR2_ODT" LOC = "K6&quo.
SP601 Hard ware Us er Guide www .xilin x.com 53 UG518 (v1.1) August 19, 2009 NET "FMC_LA07_P" LOC = "E7"; NET "FMC_LA08_N" LOC = "E11"; NET "FMC_LA08_P&quo.
54 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Appendix D: SP601 Mast er UCF NET "FPGA_CMP_MOSI" LOC = "V16"; NET "FPGA_D0_DIN_MISO_MISO1" L.
SP601 Hard ware Us er Guide www .xilin x.com 55 UG518 (v1.1) August 19, 2009 NET "PHY_TXCTL_TXEN" LOC = "B8"; NET "PHY_TXC_GTXCLK" LOC = "A9"; NET "PHY_TXD.
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