CypressメーカーCYV15G0104TRBの使用説明書/サービス説明書
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Independent Clock HOTLink II™ Serializer and Reclocking Deserialize r CYV15G0104TRB Cypress Semiconductor Corpora tion • 3901 North First S treet • San Jose , CA 95134 • 408-943-2600 Document #: 38-02100 Rev .
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 2 of 27 The CYV15G0104TRB is ideal for SMPTE applications where different data rates and serial interface standards are necessary for each channel. Some appli cations include multi- format routers, switchers, fo rmat converters, SDI m onitors, cameras, and camera control uni ts.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 3 of 27 INA1+ INA1– INA2+ INA2– INSELA Clock & Data Recovery PLL Shifter LFIA 10 RXDA[9:0] Receive Signal Monitor Output Register RXCLKA+ RXCLK.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 4 of 27 Pin Configuration (T op View) [1 ] Note: 1. NC = Do not conne ct. 123456789 10 11 12 13 14 15 16 17 18 19 20 A NC NC NC NC V CC NC TOUT B1– G.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 5 of 27 Pin Configuration (Bottom V iew) [1] 20 19 18 17 16 15 14 13 12 11 10 987654321 A NC V CC NC V CC V CC ROUT A2– IN A2– GND ROUT A1– IN A1.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 6 of 27 Pin Definitions CYV15G0104TRB HOTLink II Serializer and Reclocking De serializer Name I/O Chara cteristics Signal De scription T ransmit Path Data and St atus Signals TXDB[9:0] L VTTL Input, synchronous, sampled by TXCLKB ↑ or REFCLKB ↑ [2] Tra n s m i t D a ta I n p u ts .
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 7 of 27 BISTST A L VTTL Output, synchronous to th e RXCLKA ± output BIST St atus Output. When RXBIST A[1:0] = 10, BI STST A (along with RXDA[1:0]) displays the status of th e BIST reception. Se e T able 6 fo r the BIST stat us reported for each combination of BISTST A and RXDA[1 :0 ].
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 8 of 27 SPDSELA SPDSELB 3-Level Select [4] static control input Serial Rate Select . The SPDSELA and SPDSELB inputs specify the operating signalin g- rate range of the receive and transmit PLL, respectively .
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 9 of 27 CYV15G0104TRB HOTLink II Operation The CYV15G0104TRB is a highly configur able, independent clocking device designed to support reliable transfer of large quantities of digital video data, using high-speed serial links from multiple sources to multiple destinations.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 10 of 27 Phase-Align Buffer Data from the Input Register is passed to the Phase-Align Buffer , when the TXDB[9:0] in put register is clocked using TXCLKBA (TXCKSELB = 0) or when REFCLKB is a half-rate clock (TXCKSELB = 1 and TXRA TEB = 1).
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 1 1 of 27 INSELA input. The Serial L ine Receiver inputs are differential, and can accommodate wire interconnect and filterin g losses or transmission line attenuatio n greater than 16 dB.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 12 of 27 performed by an integrated PLL that tracks the frequency of the transitions in the incomin g bit stream and alig ns the phase of the internal bit-rate clock to the transitions in the selected serial data stream.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 13 of 27 the device configuration interf ace. When RXPL LPDA = 0, the receive PLL and analog circuitry of th e channel is disabled. The transmit channel is controlled by the TOE1B and the TOE2B latches via the device co nfiguration interface.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 14 of 27 RXPLLPDA Receive Channel Enable . The initializa tio n value of the RXPLLPDA latch = 0. RXPLLPDA selects if the receive channel is enab led or powered-down. When RXPLLPDA = 0, the receive PLL and anal og circuitry are powered-down.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 15 of 27 Device Configuration Strategy The following is a series of ordered even ts needed to load the configuration latches on a per channel basis: 1. Pulse RESET Low after device power-up. This operation resets both channels.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 16 of 27 Receive BIST Detected LOW Monitor Data Received {BISTST A, RXDA[0], No RX PLL Out of Lock Y es, {BISTST A, RXDA[0], RXDA[1]} = BIST_DA T A_COM.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 17 of 27 Maximum Ratings (Above which the useful life may be impaired. User guideline s only , not tested.) S torage T emp erature .............. .............. ...... –65°C to +150°C Ambient T emperature with Power Applied .
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 18 of 27 V OLC Output LOW V oltage (V CC Referenced) 100 Ω differential load V CC – 1.4 V CC – 0.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 19 of 27 t TXCLKR [1 6 , 17, 18, 19] TXCLKB Rise T ime 0.2 1.7 ns t TXCLKF [1 6 , 17, 18, 19] TXCLKB Fall T ime 0.2 1.7 ns t TXDS T ran smit Data Set-up T ime to TXCLKB ↑ (TXCKSELB = 0) 2.2 ns t TXDH T r an smit Data Hold T ime from TXCLKB ↑ (TXCKSELB = 0) 1.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 20 of 27 t TRGH TRGCLKA HIGH T i me (TRGRA TEA = 1)(Half Rate) 5.9 ns TRGCLKA HIGH T ime (TRGRA TEA = 0)(Full Rate) 2.9 [ 16] ns t TRGL TRGCLKA LOW Time (TRGRA TEA = 1)(Half Rate) 5.9 ns TRGCLKA LOW Time (TRGRA TEA = 0)(Full Rate) 2.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 21 of 27 CYV15G0104TRB Receive PLL Characteristics Over the Operating Range t RXLOCK Receive PLL lock to input data stream (cold st art) 376k UI Receive PLL lock to input data stream 376k UI t RXUNLOCK Receive PLL Unlock Rate 46 UI Cap acit ance [16] Parameter D escription T est Cond itions Max.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 22 of 27 CYV15G0104TRB HOTLink II T ransmitter Switching W aveforms (continued) TXCLKOB t TXCLKO Transmit Interfac e TXCLKOB Timing TXRATE = 1 (interna.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 23 of 27 Switching W aveforms for the CYV15G0104TRB HOTLink II Receiver RXCLKA+ RXDA[9:0] t RXDV+ t RXDV – t RXCLKP Receive Interface Read Timing RXC.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 24 of 27 T able 7. Package Co ord inate Signal Allocation Ball ID Signal Name Signal T ype Ball ID Signal Name Signal T y pe Ball ID Signal Name Signal.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 25 of 27 C04 VCC POWER F02 NC NO CONNECT L20 GND GROUND C05 VCC POWER F03 VCC POWER M01 N C NO C ONNECT C06 NC NO CONNECT F04 NC NO CONNECT M02 NC NO C.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 26 of 27 HOTLink is a registered trademark and HO TLink II is a trademark of Cypress Se miconductor. All product and company names mentioned in this document may be the trademarks of th eir respective holders.
CYV15G0104TRB Document #: 38-02100 Rev . *B Page 27 of 27 Document History Page Document Title: CYV15G0104TRB Ind ependent Clock HO TLink II™ Serializer a nd Reclocking Deserializer Document Number: 38 -02100 REV .
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Cypress CYV15G0104TRBを既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はCypress CYV15G0104TRBの不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
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