Freescale SemiconductorメーカーMC9S12XDP512の使用説明書/サービス説明書
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HCS12X Micr ocontr ollers freescale.com MC9S12XDP512 Data Sheet MC9S12XDP512 Rev. 2.11 5/2005.
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MC9S12XDP512 Data Sheet covers MC9S12XDT384 & MC9S12XA512 MC9S12XDP512V2 Rev. 2.11 7/2005.
MC9S12XDP512 Data Sheet, Rev . 2.11 4 F reescale Semiconductor To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 5 Contents Section Number Title Page Chapter 1 Device Overview (MC9S12XDP512V2) . . . . . . . . . . . . . . . . . . . 23 Chapter 2 512 Kbyte Flash Module (S12XFTX512K4V2). . . . . . . . . . .
MC9S12XDP512 Data Sheet, Rev . 2.11 6 F reescale Semiconductor Section Number Title Page Chapter 23 Memory Mapping Control (S12XMMCV2) . . . . . . . . . . . . . . . . 881 Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . .
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 7 Contents Section Number Title Page Chapter 1 Device Overview (MC9S12XDP512V2) 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC9S12XDP512 Data Sheet, Rev . 2.11 8 F reescale Semiconductor Section Number Title Page 2.3.2 Re gister Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 2.4 Functional Description .
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 9 Section Number Title Page 3.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 3.8.1 Description of EEPR OM Interrupt Operation .
MC9S12XDP512 Data Sheet, Rev . 2.11 10 F reescale Semiconductor Section Number Title Page 5.5.4 Po wer On Reset, Lo w V oltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 5.6 Interrupts . . . . . . . . . . .
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 11 Section Number Title Page 7.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 7.6 Interrupts .
MC9S12XDP512 Data Sheet, Rev . 2.11 12 F reescale Semiconductor Section Number Title Page 9.6 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 9.6.1 Deb ug Features .
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 13 Section Number Title Page 11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 11.3.1 Module Memory Map .
MC9S12XDP512 Data Sheet, Rev . 2.11 14 F reescale Semiconductor Section Number Title Page 13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 13.3.2 Register Descriptions . .
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 15 Section Number Title Page Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC9S12XDP512 Data Sheet, Rev . 2.11 16 F reescale Semiconductor Section Number Title Page 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 16.4.1 Master Mode .
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 17 Section Number Title Page 18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 18.3 Memory Map and Register Definition .
MC9S12XDP512 Data Sheet, Rev . 2.11 18 F reescale Semiconductor Section Number Title Page 20.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 20.1.4 Block Diagram . . . .
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 19 Section Number Title Page 22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 22.3 Memory Map and Register Definition .
MC9S12XDP512 Data Sheet, Rev . 2.11 20 F reescale Semiconductor Section Number Title Page A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920 A.1.5 Absolute Maximum Ratings .
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 21 Section Number Title Page Appendix C Recommended PCB Layout Appendix D Derivative Differences D.1 Memory Sizes and Package Options S12XD - Family . . . . . . . . . . . . . . . . . . . . .
MC9S12XDP512 Data Sheet, Rev . 2.11 22 F reescale Semiconductor Section Number Title Page.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 23 Chapter 1 De vice Overview (MC9S12XDP512V2) 1.1 Intr oduction The MC9S12XD family will retain the lo w cost, po wer consumption, EMC and code-size ef ficienc y adv antages currently enjoyed by users of Freescale's e xisting 16-Bit MC9S12 MCU Family.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 24 F reescale Semiconductor 1.1.1 Features • HCS12X Core — 16-bit HCS12X CPU – Upward compatible with MC9S12 instru.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 25 • Fi ve 1 M bit per second, CAN 2.0 A, B softw are compatible modules — Fiv e recei ve an.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 26 F reescale Semiconductor • De velopment support — Single-wire background debug™ mode (BDM) — Four on-chip hardware breakpoints 1.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 27 Figure 1-1. MC9S12XD-Famil y Block Dia gram 512/384/256/128/64-Kbyte Flash 32/20/16/14/10/8/4.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 28 F reescale Semiconductor 1.1.4 Device Memory Map T able 1-1 sho ws the device re gister memory map of the MC9S12XDP512.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 29 NO TE Reserved re gister space sho wn in T able 1-1 is not allocated to any module. This register space is reserv ed for future use. Writing to these locations ha ve no ef fect.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 30 F reescale Semiconductor 1.1.5 Address Mapping 1.1.5.1 Local-to-Global Address Mapping Figure 1-2.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 31 Figure 1-3. Local-to-Global Address Mapping XGA TE $7F_FFFF $00_0000 $10_0000 $FFFF $0000 2K .
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 32 F reescale Semiconductor 1.1.5.2 Logical Address Map Figure 1-4. Memory Map $0000 $FFFF $C000 $8000 $4000 $0800 $1000 .
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 33 1.1.6 Detailed Register Map The follo wing tables sho w the detailed register map of the MC9S12XDP512.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 34 F reescale Semiconductor 0x0010–0x0017 Module Mapping Control (S12XMMC) Map 2 of 4 Address Name Bit 7 Bit 6 Bit 5 Bi.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 35 0x0020–0x0027 Debug Module (S12XDBG) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 36 F reescale Semiconductor 0x0030–0x0031 Module Mapping Control (S12XMMC) Map 3 of 4 Address Name Bit 7 Bit 6 Bit 5 Bi.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 37 0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 1 of 3) Address Nam.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 38 F reescale Semiconductor 0x0056 TC3 (hi) R Bit 15 14 13 12 11 10 9 Bit 8 W 0x0057 TC3 (lo) R Bit 7 654321 Bit 0 W 0x00.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 39 0x006D TIMTST R 00000000 W Reser ved F or F actor y T est 0x006E PTPSR R PTPS7 PTPS6 PTPS5 PT.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 40 F reescale Semiconductor 0x0080–0x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD1) Map (Sheet 1 of 3) Addr.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 41 0x0096 A TD1DR3H R Bit15 14 13 12 11 10 9 Bit8 W 0x0097 A TD1DR3L R Bit7 Bit6 000000 W 0x0098.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 42 F reescale Semiconductor 0x00A C A TD1DR14H R Bit15 14 13 12 11 10 9 Bit8 W 0x00AD A TD1DR14L R Bit7 Bit6 000000 W 0x0.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 43 0x00BB SCI2CR2 R TIE TCIE RIE ILIE TE RE RWU SBK W 0x00BC SCI2SR1 R TDRE TC RDRF IDLE OR NF F.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 44 F reescale Semiconductor 0x00C8–0x00CF Asynchronous Serial Interface (SCI0) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 45 0x00D5 SCI1SR2 R AMAP 00 TXPOL RXPOL BRK13 TXDIR RAF W 0x00D6 SCI1DRH RR 8 T8 000000 W 0x00D7.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 46 F reescale Semiconductor 0x00E5 Reser ved R 0 0 0 0 0 0 0 0 W 0x00E6 Reser ved R 00000000 W 0x00E7 Reser ved R 0000000.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 47 0x00F8–0x00FF Serial Peripheral Interface (SPI2) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 B.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 48 F reescale Semiconductor 0x010C Reserved R 00000000 W 0x010D Reserved R 00000000 W 0x010E Reser ved R 00000000 W 0x010.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 49 0x011C–0x011F Memory Map Control (S12XMMC) Map 4 of 4 Address Name Bit 7 Bit 6 Bit 5 Bit 4 .
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 50 F reescale Semiconductor 0x00130–0x0137 Asynchronous Serial Interface (SCI4) Map Address Name Bit 7 Bit 6 Bit 5 Bit .
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 51 0x013D SCI5SR2 R AMAP 00 TXPOL RXPOL BRK13 TXDIR RAF W 0x013E SCI5DRH RR 8 T8 000000 W 0x013F.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 52 F reescale Semiconductor 0x0150– 0x0153 CAN0ID AR0– CAN0ID AR3 R AC 7 AC 6 AC 5 AC4 AC 3 AC 2 AC 1 AC 0 W 0x0154.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 53 0xXX0x XX10 Extended ID R ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15 CANxTIDR1 W Standard ID R.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 54 F reescale Semiconductor 0x0189 CAN1T AAK R 00000 A B T A K 2 A B T A K 1 A B T A K 0 W 0x018A CAN1TBSEL R 00000 TX2 T.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 55 0x019F CAN1IDMR7 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x01A0– 0x01AF CAN1RXFG R FOREGROUND R.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 56 F reescale Semiconductor 0x01D1 CAN2ID AR1 R AC7 AC 6 AC 5 AC 4 AC 3 AC 2 AC 1 AC 0 W 0x01D2 CAN2ID AR2 R AC7 AC 6 AC .
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 57 0x0200–0x023F Freescale Scalable CAN — MSCAN (CAN3) Address Name Bit 7 Bit 6 Bit 5 Bit 4 .
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 58 F reescale Semiconductor 0x0216 CAN3IDMR2 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x0217 CAN3IDMR3 R AM7 AM6 AM5 AM4 AM3 A.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 59 0x0248 PTS R PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 W 0x0249 PTIS R PTIS7 PTIS6 PTIS5 PTIS4 .
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 60 F reescale Semiconductor 0x0260 PTH R PTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0 W 0x0261 PTIH R PTIH7 PTIH6 PTIH5 PTIH4 .
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 61 0x0278 PT0AD1 R PT0AD1 23 PT0AD1 22 PT0AD1 21 PT0AD1 20 PT0AD1 19 PT0AD1 18 PT0AD1 17 PT0AD1 .
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 62 F reescale Semiconductor 0x028D CAN4MISC R 0000000 BOHOLD W 0x028E CAN4RXERR R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXER.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 63 0x02C0–0x02DF Analog-to-Digital Converter 10-Bit 8-Channel (ATD0) Map Address Name Bit 7 Bi.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 64 F reescale Semiconductor 0x02D6 A TD0DR3H R Bit15 14 13 12 11 10 9 Bit8 W 0x02D7 A TD0DR3L R Bit7 Bit6 000000 W 0x02D8.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 65 0x02F8–0x02FF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x02F8.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 66 F reescale Semiconductor 0x0314 PWMPER0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0315 PWMPER1 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0316 .
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 67 0x0328–0x033F Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0328.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 68 F reescale Semiconductor 0x0354 PITLD3 (hi) R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 W 0x0355 PITLD3 (lo) R PLD.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 69 0x038D XGIF R XGIF_57 XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50 W 0x038E XGIF R.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 70 F reescale Semiconductor 0x03A4 XGR2 (hi) R XGR2[15:8] W 0x03A5 XGR2 (lo) R XGR2[7:0] W 0x03A6 XGR3 (hi) R XGR3[15:8] .
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 71 1.1.7 P ar t ID Assignments The part ID is located in two 8-bit re gisters P AR TIDH and P AR TIDL (addresses 0x001A and 0x001B). The read-only v alue is a unique part ID for each re vision of the chip.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 72 F reescale Semiconductor Figure 1-5. MC9S12XD-Famil y Pin Assignment 144-Pin LQFP P acka ge SS1/PWM3/KWP3/PP3 SCK1/PWM.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 73 Figure 1-6. MC9S12XD-Famil y Pin Assignments 112-Pin LQFP P acka ge V RH V DDA P AD15/AN15 P .
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 74 F reescale Semiconductor Figure 1-7. MC9S12XD-Famil y Pin Assignments 80-Pin QFP P acka ge 1 2 3 4 5 6 7 8 9 10 11 12 .
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 75 1.2.2 Signal Pr oper ties Summary T able 1-3 summarizes the pin functionality.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 76 F reescale Semiconductor PH7 KWH7 SS2 TXD5 — V DDR PERH/PPSH Disabled P or t H I/O, interrupt, SS of SPI2, TXD of SC.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 77 PK0 ADDR16 IQST A T0 — — V DDX PUCR Up Extended address, PIPE status PM7 TXCAN3 TXD3 TXCA.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 78 F reescale Semiconductor NO TE For de vices assembled in 80-pin and 112-pin packages all non-bonded out pins should be configured as outputs after reset in order to a void current drawn from floating inputs.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 79 1.2.3.5 XFC — PLL Loop Filter Pin Please ask your Freescale representati ve for the interacti ve application note to compute PLL loop filter elements.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 80 F reescale Semiconductor 1.2.3.11 PB0 / ADDR0 / UDS / IVD[0] — P or t B I/O Pin 0 PB0 is a general-purpose input or output pin. In MCU expanded modes of operation, this pin is used for the external address b us ADDR0 or as upper data strobe signal.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 81 Figure 1-9. Loop Controlled Pier ce Oscillator Connections (PE7 = 1) Figure 1-10. Full Swing Pierce Oscillator Connections (PE7 = 0) Figure 1-11.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 82 F reescale Semiconductor 1.2.3.16 PE5 / MOD A / T A GLO / RE — P or t E I/O Pin 5 PE5 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 83 1.2.3.23 PH6 / KWH6 / SCK2 / RXD5 — P or t H I/O Pin 6 PH6 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or w ait mode.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 84 F reescale Semiconductor 1.2.3.30 PJ7 / KWJ7 / TXCAN4 / SCL0 / TXCAN0— PORT J I/O Pin 7 PJ7 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or w ait mode.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 85 maintains the external b us access until the external de vice is ready to capture data (write) or provide data (read). The input voltage threshold for PK7 can be configured to reduced le vels, to allo w data from an external 3.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 86 F reescale Semiconductor 1.2.3.44 PM3 / TXCAN1 / TXCAN0 / SS0 — P or t M I/O Pin 3 PM3 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN of the scalable controller area network controllers 1 or 0 (CAN1 or CAN0).
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 87 be configured as master input (during master mode) or slav e output (during slave mode) pin MISO of the serial peripheral interface 2 (SPI2). 1.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 88 F reescale Semiconductor 1.2.3.59 PS4 / MISO0 — P or t S I/O Pin 4 PS4 is a general-purpose input or output pin. It can be configured as master input (during master mode) or slav e output pin (during slav e mode) MOSI of the serial peripheral interface 0 (SPI0).
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 89 1.2.4.2 V DDR1 , V DDR2 , V SSR1 , V SSR2 — P ower and Gr ound Pins for I/O Driver s and f or Internal V oltage Regulator External po wer and ground for I/O dri vers and input to the internal v oltage regulator.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 90 F reescale Semiconductor T able 1-4. MC9S12XDP512 P ower and Ground Connection Summary Mnemonic Pin Number Nominal V oltage Description 144-Pin LQFP 112-Pin LQFP 80-Pin QFP V DD1, 2 15, 87 13, 65 9, 49 2.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 91 1.3 System Clock Description The clock and reset generator module (CRG) provides the internal clock signals for the core and all peripheral modules.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 92 F reescale Semiconductor The program Flash memory and the EEPR OM are supplied by the bus clock and the oscillator clock.The oscillator clock is used as a time base to deri ve the program and erase times for the NVM’ s.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 93 The configuration of the oscillator can be selected using the XCLKS signal (see T able 1-6 ). For a detailed description please refer to the CRG Block Guide.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 94 F reescale Semiconductor 1.5 Modes of Operation 1.5.1 User Modes 1.5.1.1 Normal Expanded Mode Ports K, A, and B are configured as a 23-bit address bus, ports C and D are configured as a 16-bit data b us, and port E provides b us control and status signals.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 95 1.5.2.1 System Stop Modes The system stop modes are entered if the CPU ex ecutes the STOP instruction and the XGA TE doesn’t ex ecute a thread and the XGF A CT bit in the XGMCTL register is cleared.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 96 F reescale Semiconductor T able 1-8. Interrupt V ector Locations (Sheet 1 of 3) V ector Address 1 XGA TE Channel ID 2 .
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 97 V ector base + $BC $5E SPI2 I bit SPI2CR1 (SPIE, SPTIE) V ector base + $BA $5D EEPROM I bit E.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 98 F reescale Semiconductor 1.6.2 Effects of Reset When a reset occurs, MCU registers and control bits are changed to kno wn start-up states. Refer to the respecti ve module Block Guides for re gister reset states.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 99 1.7 COP Configuration The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge of RESET from the Flash control register FCTL ($0107) located in the Flash EEPR OM block.
Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 100 F reescale Semiconductor Consult the A TD_10B8C Block Guide for information about the analog-to-digital con verter module. When the A TD_10B8C Block Guide refers to freeze mode this is equiv alent to activ e BDM mode.
BookTitle, Rev . 2.4 F reescale Semiconductor 101 Chapter 2 512 Kb yte Flash Module (S12XFTX512K4V2) 2.1 Intr oduction This document describes the FTX512K4 module that includes a 512K Kbyte Flash (non volatile) memory. The Flash memory may be read as either bytes, aligned words or misaligned w ords.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 102 F reescale Semiconductor • Security feature to pre vent unauthorized access to the Flash memory • Code integrity check using b uilt-in data compression 2.1.3 Modes of Operation Program, erase, erase verify , and data compress operations (please refer to Section 2.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 103 Figure 2-1. FTX512K4 Block Dia gram 2.2 External Signal Description The Flash module contains no signals that connect of f-chip.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 104 F reescale Semiconductor 2.3 Memor y Map and Register Definition This section describes the memory map and registers for the Flash module. 2.3.1 Module Memory Map The Flash memory map is sho wn in Figure 2-2 .
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 105 Figure 2-2. Flash Memory Map Flash Registers Flash Configuration Field 0x7F_C000 Flash Protected/Unprotected .
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 106 F reescale Semiconductor The Flash module also contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is gi ven in T able 2-2 while their accessibility is detailed in Section 2.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 107 2.3.2 Register Descriptions Register Name Bit 7 654321 Bit 0 0x0000 FCLKDIV R FDIVLD PRDIV8 FDIV5 FDIV4 FDIV3 .
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 108 F reescale Semiconductor 2.3.2.1 Flash Cloc k Divider Register (FCLKDIV) The FCLKDIV register is used to control timed e vents in program and erase algorithms. All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 109 2.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. All bits in the FSEC register are readable b ut are not writable.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 110 F reescale Semiconductor 2.3.2.3 Flash T est Mode Register (FTSTMOD) The FTSTMOD register is used to control Flash test features. MRDS bits are readable and writable while all remaining bits read 0 and are not writable in normal mode.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 111 2.3.2.4 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash interrupts and g ates the security backdoor writes. CBEIE, CCIE and KEY A CC bits are readable and writable while all remaining bits read 0 and are not writable in normal mode.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 112 F reescale Semiconductor 2.3.2.5 Flash Pr otection Register (FPRO T) The FPROT register defines which Flash sectors are protected against program or erase operations. All bits in the FPR O T register are readable and writable with restrictions (see Section 2.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 113 5 FPHDIS Flash Protection Higher Ad dress Range Disable — The FPHDIS bit deter mines whether there is a protected/unprotected area in a specific region of the Flash memor y ending with global address 0x7F_FFFF.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 114 F reescale Semiconductor All possible Flash protection scenarios are sho wn in Figure 2-11 . Although the protection scheme is loaded from the Flash array at global address 0x7F_FF0D during the reset sequence, it can be changed by the user.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 115 Figure 2-11. Flash Protection Scenarios 7654 3210 FPHDIS=1 FPLDIS=1 FPHDIS=1 FPLDIS=0 FPHDIS=0 FPLDIS=1 FPHDIS.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 116 F reescale Semiconductor 2.3.2.5.1 Flash Protection Restrictions The general guideline is that Flash protection can only be added and not remov ed. T able 2-15 specifies all v alid transitions between Flash protection scenarios.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 117 CBEIF , PVIOL, and A CCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read 0 and are not writable in normal mode. F AIL is readable and writable in special mode.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 118 F reescale Semiconductor 2.3.2.7 Flash Command Register (FCMD) The FCMD register is the Flash command register. All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 119 All bits in the FCTL register are readable b ut are not writable. The FCTL register is loaded from the Flash Configuration Field byte at global address 0x7F_FF0E during the reset sequence, indicated by F in Figure 2-15 .
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 120 F reescale Semiconductor All FD A T AHI and FD A T ALO bits are readable b ut are not writable. At the completion of a data compress operation, the resulting 16-bit signature is stored in the FD A T A registers.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 121 All bits read 0 and are not writable. 2.3.2.13 RESER VED3 This register is reserv ed for factory testing and is not accessible. All bits read 0 and are not writable.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 122 F reescale Semiconductor 2.4 Functional Description 2.4.1 Flash Command Operations Write operations are used to ex ecute program, erase, erase verify , erase abort, and data compress algorithms described in this section.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 123 182kHz. In this case, the Flash program and erase algorithm timings are increased ov er the optimum target by: CA UTION Program and erase command ex ecution time will increase proportionally with the period of FCLK.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 124 F reescale Semiconductor Figure 2-24. Determination Procedure f or PRDIV8 and FDIV Bits PRDIV8=1 yes no PRDIV8=0 (reset) 12.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 125 2.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to ex ecute program, erase, erase verify , erase abort, and data compress algorithms.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 126 F reescale Semiconductor CA UTION A Flash word must be in the erased state before being programmed. Cumulati ve programming of bits within a Flash w ord is not allo wed. 0x06 Data Compress Compress data from a selected por tion of the Flash bloc k.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 127 2.4.2.1 Erase V erify Command The erase verify operation will v erify that a Flash block is erased. An example flo w to execute the erase v erify operation is shown in Figure 2-25 .
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 128 F reescale Semiconductor Figure 2-25. Example Erase V erify Command Flow Write: Flash Block Address Write: FCMD register Erase V erify Command 0x05 Write: FST A T register Clear CBEIF 0x80 1.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 129 2.4.2.2 Data Compress Command The data compress operation will check Flash code integrity by compressing data from a selected portion of the Flash memory into a signature analyzer.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 130 F reescale Semiconductor Figure 2-26. Example Data Compress Command Flow Write: Flash Address to star t Write: FCMD register Data Compress Command 0x06 Write: FST A T register Clear CBEIF 0x80 1.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 131 2.4.2.2.1 Data Compress Operation The Flash module contains a 16-bit multiple-input signature register (MISR) for each Flash block to generate a 16-bit signature based on selected Flash array data.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 132 F reescale Semiconductor 2.4.2.3 Pr ogram Command The program operation will program a pre viously erased word in the Flash memory using an embedded algorithm. An example flo w to execute the program operation is sho wn in Figure 2-28 .
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 133 Figure 2-28. Example Program Command Flo w Write: Flash Address Write: FCMD register Program Command 0x20 Write: FST A T register Clear CBEIF 0x80 1.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 134 F reescale Semiconductor 2.4.2.4 Sector Erase Command The sector erase operation will erase all addresses in a 1 Kbyte sector of Flash memory using an embedded algorithm. An example flo w to ex ecute the sector erase operation is shown in Figure 2-29 .
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 135 Figure 2-29. Example Sector Erase Command Flow Write: Flash Sector Address Write: FCMD register Sector Erase Command 0x40 Write: FST A T register Clear CBEIF 0x80 1.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 136 F reescale Semiconductor 2.4.2.5 Mass Erase Command The mass erase operation will erase all addresses in a Flash block using an embedded algorithm. An example flo w to ex ecute the mass erase operation is shown in Figure 2-30 .
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 137 Figure 2-30. Example Mass Erase Command Flow Write: Flash Block Address Write: FCMD register Mass Erase Command 0x41 Write: FST A T register Clear CBEIF 0x80 1. 2.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 138 F reescale Semiconductor 2.4.2.6 Sector Erase Abor t Command The sector erase abort operation will terminate the acti ve sector erase o.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 139 Figure 2-31. Example Sector Erase Abort Command Flow Write: Dummy Flash Address Write: FCMD register Sector Erase Abor t Cmd 0x47 Write: FST A T register Clear CBEIF 0x80 1.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 140 F reescale Semiconductor 2.4.3 Illegal Flash Operations The A CCERR flag will be set during the command write sequence if any of the follo wing illegal steps are performed, causing the command write sequence to immediately abort: 1.
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 141 If the PVIOL flag is set in the FST A T register , the user must clear the PVIOL flag before starting another command write sequence (see Section 2.3.2.6, “Flash Status Register (FST A T)” ).
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 142 F reescale Semiconductor 2.6.1 Unsecuring the MCU using Bac kdoor Ke y Access The MCU may be unsecured by using the backdoor ke y access feature which requires kno wledge of the contents of the backdoor ke ys (four 16-bit words programmed at addresses 0x7F_FF00–0x7F_FF07).
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 143 unaf fected by the backdoor ke y access sequence. After the next reset of the MCU, the security state of the Flash module is determined by the Flash security byte (0x7F_FF0F).
512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 144 F reescale Semiconductor NO TE V ector addresses and their relativ e interrupt priority are determined at the MCU le vel. 2.8.1 Description of Flash Interrupt Operation The logic used for generating interrupts is sho wn in Figure 2-32 .
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 145 Chapter 3 4 Kb yte EEPROM Module (S12XEETX4KV2) 3.1 Intr oduction This document describes the module which includes a Kbyte EEPR OM (non volatile) memory. The EEPR OM memory may be read as either bytes, aligned words, or misaligned words.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 146 F reescale Semiconductor 3.1.4 Bloc k Diagram A block diagram of the EEPR OM module is shown in . 3.2 External Signal Description The EEPR OM module contains no signals that connect off-chip.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 147 The EEPR OM module also contains a set of 12 control and status registers located between EEPR OM module base + 0x0000 and 0x000B.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 148 F reescale Semiconductor 3.3.2 Register Descriptions 3.3.2.1 EEPR OM Clock Divider Register (ECLKDIV) The ECLKDIV register is used to control timed e vents in program and erase algorithms.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 149 All bits in the ECLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable. 3.3.2.2 RESER VED1 This register is reserv ed for factory testing and is not accessible.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 150 F reescale Semiconductor All bits read 0 and are not writable. 3.3.2.4 EEPR OM Configuration Register (ECNFG) The ECNFG register enables the EEPR OM interrupts. CBEIE and CCIE bits are readable and writable while all remaining bits read 0 and are not writable.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 151 3.3.2.5 EEPR OM Protection Register (EPR O T) The EPR O T register defines which EEPR OM sectors are protected against program or erase operations.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 152 F reescale Semiconductor 3.3.2.6 EEPR OM Status Register (EST A T) The EST A T register defines the operational status of the module.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 153 T able 3-7. EST A T Field Descriptions Field Description 7 CBEIF Command Buffer Empty I.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 154 F reescale Semiconductor 3.3.2.7 EEPR OM Command Register (ECMD) The ECMD register is the EEPR OM command register. All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 155 All bits read 0 and are not writable. EEPROM Address Registers (EADDR) The EADDRHI and EADDRLO registers are the EEPR OM address registers.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 156 F reescale Semiconductor 3.4 Functional Description 3.4.1 EEPR OM Command Operations Write operations are used to ex ecute program, erase, erase verify , sector erase abort, and sector modify algorithms described in this section.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 157 CA UTION Program and erase command ex ecution time will increase proportionally with the period of EECLK.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 158 F reescale Semiconductor Figure 3-14. Determination Procedure f or PRDIV8 and EDIV Bits PRDIV8 = 1 yes no PRDIV8 = 0 (reset) >12.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 159 3.4.1.2 Command Write Sequence The EEPR OM command controller is used to supervise the command write sequence to execute program, erase, erase verify , sector erase abort, and sector modify algorithms.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 160 F reescale Semiconductor CA UTION An EEPR OM word (2 bytes) must be in the erased state before being programmed. Cumulati ve programming of bits within a w ord is not allowed.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 161 3.4.2.1 Erase V erify Command The erase verify operation will v erify that the EEPR OM memory is erased. An example flo w to execute the erase v erify operation is shown in Figure 3-15 .
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 162 F reescale Semiconductor Figure 3-15. Example Erase V erify Command Flow Write: EEPROM Address Write: ECMD register Erase V erify Command 0x05 Write: EST A T register Clear CBEIF 0x80 1.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 163 3.4.2.2 Pr ogram Command The program operation will program a pre viously erased word in the EEPR OM memory using an embedded algorithm. An example flo w to execute the program operation is sho wn in Figure 3-16 .
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 164 F reescale Semiconductor Figure 3-16. Example Program Command Flo w Write: EEPROM Address Write: ECMD register Program Command 0x20 Write: EST A T register Clear CBEIF 0x80 1.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 165 3.4.2.3 Sector Erase Command The sector erase operation will erase both words in a sector of EEPR OM memory using an embedded algorithm. An example flo w to ex ecute the sector erase operation is shown in Figure 3-17 .
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 166 F reescale Semiconductor Figure 3-17. Example Sector Erase Command Flow Write: EEPROM Sector Address Write: ECMD register Sector Erase Command 0x40 Write: EST A T register Clear CBEIF 0x80 1.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 167 3.4.2.4 Mass Erase Command The mass erase operation will erase all addresses in an EEPR OM block using an embedded algorithm. An example flo w to ex ecute the mass erase operation is shown in Figure 3-18 .
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 168 F reescale Semiconductor Figure 3-18. Example Mass Erase Command Flow Write: EEPROM Address Write: ECMD register Mass Erase Command 0x41 Write: EST A T register Clear CBEIF 0x80 1.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 169 3.4.2.5 Sector Erase Abor t Command The sector erase abort operation will terminate the.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 170 F reescale Semiconductor Figure 3-19. Example Sector Erase Abort Command Flow Write: Dummy EEPROM Address Write: ECMD register Sector Erase Abort Cmd 0x47 Write: EST A T register Clear CBEIF 0x80 1.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 171 3.4.2.6 Sector Modify Command The sector modify operation will erase both words in a sector of EEPR OM memory followed by a reprogram of the addressed word using an embedded algorithm.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 172 F reescale Semiconductor Figure 3-20. Example Sector Modify Command Flow Write: EEPROM W ord Address Write: ECMD register Sector Modify Command 0x60 Write: EST A T register Clear CBEIF 0x80 1.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 173 3.4.3 Illegal EEPR OM Operations The A CCERR flag will be set during the command write sequence if any of the follo wing illegal steps are performed, causing the command write sequence to immediately abort: 1.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 174 F reescale Semiconductor 3.5 Operating Modes 3.5.1 W ait Mode If a command is acti ve (CCIF = 0) when the MCU enters the w ait mode, the acti ve command and an y buf fered command will be completed.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 175 3.6.1 Unsecuring the MCU in Special Single Chip Mode using BDM Before the MCU can be un.
Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 176 F reescale Semiconductor 3.8.1 Description of EEPR OM Interrupt Operation The logic used for generating interrupts is sho wn in Figure 3-21 .
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 177 Chapter 4 P or t Integration Module (S12XDP512PIMV2) 4.1 Intr oduction The S12XD family port inte gration module (belo w referred to as.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 178 F reescale Semiconductor 4.1.1 Features A full-featured PIM module includes these distinctive registers: •.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 179 Figure 4-1. MC9S12XDP512 Block Dia gram Po r t T PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 EC.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 180 F reescale Semiconductor 4.2 External Signal Description This section lists and describes the signals that do connect off-chip. 4.2.1 Signal Pr oper ties Table 4-1 shows all the pins and their functions that are controlled by the MC9S12XDP512.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 181 E PE[7] XCLKS 1 I Exter nal clock selection input during RESET Mode dependent 3 ECL.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 182 F reescale Semiconductor K PK[7] ROMCTL 1 I ROMON bit control input during RESET Mode dependent 3 EW AIT I E.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 183 M PM7 TXCAN3 O MSCAN3 transmit pin GPIO TXCAN4 O MSCAN4 transmit pin TXD3 O Ser ial.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 184 F reescale Semiconductor P PP7 PWM7 I/O Pulse Width Modulator input/output channel 7 GPIO SCK2 I/O Serial Pe.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 185 H PH7 SS2 I/O Serial Peripheral Interf ace 2 slav e select output in master mode, i.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 186 F reescale Semiconductor J PJ7 TXCAN4 O MSCAN4 transmit pin GPIO SCL0 O Inter Integ rated Circuit 0 serial c.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 187 4.3 Memor y Map and Register Definition This section provides a detailed description of all MC9S12XDP512 registers. 4.3.1 Module Memory Map Table 4-2 shows the register map of the port integration module.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 188 F reescale Semiconductor 0x0241 P or t T Input Register (PTIT) Read 0x0242 P or t T Data Direction Register .
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 189 0x0264 P or t H Pull Device Enab le Register (PERH) Read / Write 0x0265 P or t H P .
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 190 F reescale Semiconductor 4.3.2 Register Descriptions Table 4-3 summarizes the effect on the various configuration bits, data direction (DDR), output level (IO), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the ports.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 191 Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 POR T A R P A7 P A6 P A5 P A4 P A3 P A.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 192 F reescale Semiconductor 0x000E– 0x001B Non-PIM Address Range R Non-PIM Address Range W 0x001C ECLKCTL R N.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 193 0x0244 PER T R PER T7 PERT6 PER T5 PERT4 PER T3 PERT2 PER T1 PERT0 W 0x0245 PPST R .
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 194 F reescale Semiconductor 0x0253 RDRM R RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0 W 0x0254 PERM R PERM7.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 195 0x0262 DDRH R DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 W 0x0263 RDRH R RDRH7.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 196 F reescale Semiconductor 0x0271 PT1AD0 R PT1AD07 PT1AD06 PT1AD05 PT1AD04 PT1AD03 PT1AD02 PT1AD01 PT1AD00 W 0.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 197 4.3.2.1 P or t A Data Register (PORT A) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 198 F reescale Semiconductor Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 199 4.3.2.3 P or t A Data Direction Register (DDRA) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 200 F reescale Semiconductor T able 4-7. DDRB Field Descriptions Field Description 7–0 DDRB[7:0] Data Direction P or t B — This register controls the data direction for por t B.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 201 4.3.2.5 P or t C Data Register (PORTC) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 202 F reescale Semiconductor 4.3.2.7 P or t C Data Direction Register (DDRC) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 203 T able 4-11. DDRD Field Descriptions Field Description 7–0 DDRD[7:0] Data Direction P or t D — This register controls the data direction for por t D.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 204 F reescale Semiconductor 4.3.2.9 P or t E Data Register (PORTE) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 205 4.3.2.10 P or t E Data Direction Register (DDRE) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 206 F reescale Semiconductor 4.3.2.11 S12X_EBI P or ts, BKGD, VREGEN Pin Pull-up Contr ol Register (PUCR) Read: Anytime in single-chip modes. Write: Anytime, except BKPUE which is writable in special test mode only.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 207 4.3.2.12 S12X_EBI P or ts Reduced Drive Register (RDRIV) Read: Anytime. In emulation modes, read operations will return the data from the e xternal bus, in all other modes the data are read from this register.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 208 F reescale Semiconductor 4.3.2.13 ECLK Control Register (ECLKCTL) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 209 4.3.2.14 IRQ Control Register (IRQCR) Read: See individual bit descriptions below. Write: See individual bit descriptions below. 6 NCLKX2 No ECLKX2 — This bit controls the av ailability of a free-r unning clock on the ECLKX2 pin.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 210 F reescale Semiconductor T able 4-18. IRQCR Field Descriptions Field Description 7 IRQE IRQ Select Edge Sensitive Only Special modes: Read or write anytime. Normal and emulation modes: Read anytime, write once.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 211 4.3.2.15 P or t K Data Register (PORTK) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 212 F reescale Semiconductor T able 4-20. DDRK Field Descriptions Field Description 7–0 DDRK[7:0] Data Direction P or t K 0 Associated pin is configured as input.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 213 4.3.2.17 P or t T Data Register (PTT) Read: Anytime. Write: Anytime. 4.3.2.18 P or t T Input Register (PTIT) Read: Anytime. Write: Never, writes to this register have no effect.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 214 F reescale Semiconductor 4.3.2.19 P or t T Data Direction Register (DDRT) Read: Anytime. Write: Anytime. This register configures each port T pin as either input or output.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 215 4.3.2.20 P or t T Reduced Drive Register (RDRT) Read: Anytime. Write: Anytime. This register configures the drive strength of each port T output pin as either full or reduced.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 216 F reescale Semiconductor 4.3.2.22 P or t T P olarity Select Register (PPST) Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 217 If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 218 F reescale Semiconductor 4.3.2.24 P or t S Input Register (PTIS) Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 219 4.3.2.25 P or t S Data Direction Register (DDRS) Read: Anytime. Write: Anytime. This register configures each port S pin as either input or output.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 220 F reescale Semiconductor 4.3.2.26 P or t S Reduced Drive Register (RDRS) Read: Anytime. Write: Anytime. This register configures the drive strength of each port S output pin as either full or reduced.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 221 4.3.2.28 P or t S P olarity Select Register (PPSS) Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 222 F reescale Semiconductor 4.3.2.30 P or t M Data Register (PTM) Read: Anytime. Write: Anytime. Port M pins 75–0 are associated with the CAN0, CAN1, CAN2, CAN3, SCI3, as well as the routed CAN0, CAN4, and SPI0 modules.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 223 3–2 PTM[3:2] The CAN1 function (TXCAN1 and RXCAN1) takes precedence o ver the routed CAN0, the routed SPI0 and the general purpose I/O function if the CAN1 module is enabled.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 224 F reescale Semiconductor 4.3.2.31 P or t M Input Register (PTIM) Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 225 4.3.2.32 P or t M Data Direction Register (DDRM) Read: Anytime. Write: Anytime. This register configures each port M pin as either input or output.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 226 F reescale Semiconductor 4.3.2.33 P or t M Reduced Drive Register (RDRM) Read: Anytime. Write: Anytime. This register configures the drive strength of each Port M output pin as either full or reduced.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 227 4.3.2.35 P or t M P olarity Select Register (PPSM) Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 228 F reescale Semiconductor T able 4-37. W OMM Field Descriptions Field Description 7–0 WOMM[7:0] Wired-OR Mode P or t M 0 Output buffers oper ate as push-pull outputs.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 229 4.3.2.37 Module Routing Register (MODRR) Read: Anytime. Write: Anytime. This register configures the re-routing of CAN0, CAN4, SPI0, SPI1, and SPI2 on alternative ports.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 230 F reescale Semiconductor 4.3.2.38 P or t P Data Register (PTP) Read: Anytime. Write: Anytime. Port P pins 7, and 5–0 are associated with the PWM as well as the SPI1 and SPI2 modules.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 231 4.3.2.39 P or t P Input Register (PTIP) Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 232 F reescale Semiconductor 4.3.2.40 P or t P Data Direction Register (DDRP) Read: Anytime. Write: Anytime. This register configures each port P pin as either input or output.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 233 4.3.2.41 P or t P Reduced Drive Register (RDRP) Read: Anytime. Write: Anytime. This register configures the drive strength of each port P output pin as either full or reduced.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 234 F reescale Semiconductor 4.3.2.43 P or t P P olarity Select Register (PPSP) Read: Anytime.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 235 T able 4-43. PIEP Field Descriptions Field Description 7–0 PIEP[7:0] Interrupt Enable P or t P 0 Interr upt is disabled (interrupt flag masked).
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 236 F reescale Semiconductor 4.3.2.45 P or t P Interrupt Flag Register (PIFP) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 237 4.3.2.46 P or t H Data Register (PTH) Read: Anytime. Write: Anytime. Port H pins 7–0 are associated with the SCI4 and SCI5 as well as the routed SPI1 and SPI2 modules.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 238 F reescale Semiconductor 4.3.2.47 P or t H Input Register (PTIH) Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 239 4.3.2.48 P or t H Data Direction Register (DDRH) Read: Anytime. Write: Anytime. This register configures each port H pin as either input or output.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 240 F reescale Semiconductor 4.3.2.49 P or t H Reduced Drive Register (RDRH) Read: Anytime. Write: Anytime. This register configures the drive strength of each Port H output pin as either full or reduced.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 241 4.3.2.51 P or t H P olarity Select Register (PPSH) Read: Anytime.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 242 F reescale Semiconductor T able 4-49. PIEH Field Descriptions Field Description 7–0 PIEH[7:0] Interrupt Enable P or t H 0 Interr upt is disabled (interrupt flag masked).
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 243 4.3.2.53 P or t H Interrupt Flag Register (PIFH) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 244 F reescale Semiconductor 4.3.2.54 P or t J Data Register (PTJ) Read: Anytime. Write: Anytime. Port J pins 7–4 and 2–0 are associated with the CAN4, SCI2, IIC0 and IIC1, the routed CAN0 modules and chip select signals ( CS0, CS1, CS2, CS3).
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 245 1 PJ1 The SCI2 function takes precedence o ver the gener al pur pose I/O function if the SCI2 module is enabled. Ref er to SCI section f or details.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 246 F reescale Semiconductor 4.3.2.55 P or t J Input Register (PTIJ) Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 247 4.3.2.56 P or t J Data Direction Register (DDRJ) Read: Anytime. Write: Anytime. This register configures each port J pin as either input or output.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 248 F reescale Semiconductor 4.3.2.57 P or t J Reduced Drive Register (RDRJ) Read: Anytime. Write: Anytime. This register configures the drive strength of each port J output pin as either full or reduced.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 249 T able 4-54. PERJ Field Descriptions Field Description 7–0 PERJ[7:4] PERJ[2:0] Pull Device Enable P ort J 0 Pull-up or pull-down device is disab led.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 250 F reescale Semiconductor 4.3.2.59 P or t J P olarity Select Register (PPSJ) Read: Anytime.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 251 T able 4-56. PIEJ Field Descriptions Field Description 7–0 PIEJ[7:4] PIEJ[2:0] Interrupt Enable P or t J 0 Interr upt is disabled (interrupt flag masked).
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 252 F reescale Semiconductor 4.3.2.61 P or t J Interrupt Flag Register (PIFJ) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 253 4.3.2.63 P or t AD0 Data Direction Register 1 (DDR1AD0) Read: Anytime. Write: Anytime. This register configures pins PAD[07:00] as either input or output.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 254 F reescale Semiconductor 4.3.2.64 P or t AD0 Reduced Drive Register 1 (RDR1AD0) Read: Anytime. Write: Anytime. This register configures the drive strength of each output pin PAD[07:00] as either full or reduced.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 255 4.3.2.66 P or t AD1 Data Register 0 (PT0AD1) Read: Anytime. Write: Anytime. This register is associated with AD1 pins PAD[23:16]. These pins can also be used as general purpose I/O.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 256 F reescale Semiconductor 4.3.2.68 P or t AD1 Data Direction Register 0 (DDR0AD1) Read: Anytime. Write: Anytime. This register configures pin PAD[23:16] as either input or output.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 257 4.3.2.69 P or t AD1 Data Direction Register 1 (DDR1AD1) Read: Anytime. Write: Anytime. This register configures pins PAD[15:08] as either input or output.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 258 F reescale Semiconductor 4.3.2.70 P or t AD1 Reduced Drive Register 0 (RDR0AD1) Read: Anytime. Write: Anytime. This register configures the drive strength of each PAD[23:16] output pin as either full or reduced.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 259 4.3.2.72 P or t AD1 Pull Up Enable Register 0 (PER0AD1) Read: Anytime. Write: Anytime. This register activates a pull-up device on the respective PAD[23:16] pin if the port is used as input.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 260 F reescale Semiconductor 4.4 Functional Description Each pin except PE0, PE1, and BKGD can act as general purpose I/O.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 261 4.4.1.2 Input Register This is a read-only register and always returns the buffered state of the pin ( Figure 4-76 ). 4.4.1.3 Data Direction Register This register defines whether the pin is used as an input or an output.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 262 F reescale Semiconductor 4.4.1.8 Interrupt Enable Register If the pin is used as an interrupt input this register serves as a mask to the interrupt flag to enable/disable the interrupt.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 263 4.4.2.3 P or t C and D Port C pins PC[7:0] and port D pins PD[7:0] can be used for either general-purpose I/O, or, in 144-pin packages, also with the external bus interface.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 264 F reescale Semiconductor 4.4.2.6 P or t T This port is associated with the ECT module. Port T pins PT[7:0] can be used for either general-purpose I/O, or with the channels of the enhanced capture timer.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 265 4.4.2.10 P or t H This port is associated with the SPI1, SPI2, SCI4, and SCI5. Port H pins PH[7:0] can be used for either general purpose I/O, or with the SPI and SCI subsystems.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 266 F reescale Semiconductor 4.4.3 Pin Interrupts Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on per-pin basis.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 267 A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level directly or indirectly.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 268 F reescale Semiconductor 4.4.5 Low-P ower Options 4.4.5.1 Run Mode No low-power options exist for this module in run mode. 4.4.5.2 W ait Mode No low-power options exist for this module in wait mode.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 269 • Po wer consumption will increase the more the voltages on general purpose input pins de viate from the supply voltages to wards mid-range because the digital input b uf fers operate in the linear region.
Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 270 F reescale Semiconductor.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 271 Chapter 5 Cloc ks and Reset Generator (S12CRGV6) 5.1 Intr oduction This specification describes the function of the clocks and reset generator (MC9S12XDP512).
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 272 F reescale Semiconductor 5.1.2 Modes of Operation This subsection lists and briefly describes all operating modes supported by the CRG. • Run mode All functional parts of the CRG are running during normal run mode.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 273 5.1.3 Bloc k Diagram Figure 5-1 sho ws a block diagram of the MC9S12XDP512.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 274 F reescale Semiconductor 5.2 External Signal Description This section lists and describes the signals that connect of f chip.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 275 5.3.1 Module Memory Map T able 5-1 gi ves an ov erview on all MC9S12XDP512 re gisters.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 276 F reescale Semiconductor 5.3.2 Register Descriptions This section describes in address order all the MC9S12XDP512 registers and their indi vidual bits.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 277 5.3.2.1 CRG Synthesizer Register (SYNR) The SYNR register controls the multiplication f actor of the PLL.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 278 F reescale Semiconductor NO TE Write to this register initializes the lock detector bit and the track detector bit. 5.3.2.3 Reserved Register (CTFLG) This register is reserv ed for factory testing of the MC9S12XDP512 module and is not av ailable in normal modes.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 279 T able 5-2. CRGFLG Field Descriptions Field Description 7 R TIF Real Time Interrupt Flag — R TIF is set to 1 at the end of the R TI period.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 280 F reescale Semiconductor 5.3.2.5 CRG Interrupt Enable Register (CRGINT) This register enables CRG interrupt requests. Read: Anytime Write: Anytime Module Base +0x_04 76543210 R R TIE ILAF 0 LOCKIE 00 SCMIE 0 W Reset 0 1 000000 1.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 281 5.3.2.6 CRG Cloc k Select Register (CLKSEL) This register controls CRG clock selection. Refer to Figure 5-17 for more details on the ef fect of each bit.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 282 F reescale Semiconductor 5.3.2.7 CRG PLL Contr ol Register (PLLCTL) This register controls the PLL functionality.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 283 5.3.2.8 CRG R TI Control Register (R TICTL) This register selects the timeout period for the real time interrupt. Read: Anytime Write: Anytime NO TE A write to this register initializes the R TI counter.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 284 F reescale Semiconductor T able 5-7. R TI Frequency Divide Rates for R TDEC = 0 RTR[3:0] RTR[6:4] = 000 (OFF) 00.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 285 T able 5-8. R TI Frequency Divide Rates for R TDEC = 1 RTR[3:0] RTR[6:4] = 000 (1x10 3 .
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 286 F reescale Semiconductor 5.3.2.9 CRG COP Contr ol Register (COPCTL) This register controls the COP (computer operating properly) w atchdog. Read: Anytime Write: 1.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 287 5 WR TMASK Write Mask for WCOP and CR[2:0] Bit — This write-only bit ser ves as a mask f or the WCOP and CR[2:0] bits while writing the COPCTL register.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 288 F reescale Semiconductor 5.3.2.10 Reser ved Register (FORBYP) NO TE This reserved re gister is designed for factory test purposes only , and is not intended for general user access.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 289 5.3.2.12 CRG COP Timer Arm/Reset Register (ARMCOP) This register is used to restart the COP time-out period. Read: Always reads 0x_00 Write: Anytime When the COP is disabled (CR[2:0] = “000”) writing to this register has no ef fect.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 290 F reescale Semiconductor 5.4 Functional Description 5.4.1 Functional Bloc ks 5.4.1.1 Phase Loc ked Loop (PLL) The PLL is used to run the MCU from a dif ferent time base than the incoming OSCCLK.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 291 5.4.1.1.1 PLL Operation The oscillator output clock signal (OSCCLK) is fed through the reference programmable di vider and is di vided in a range of 1 to 64 (REFD V + 1) to output the REFERENCE clock.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 292 F reescale Semiconductor The follo wing conditions apply when the PLL is in automatic bandwidth control mode (A UTO = 1): • The TRA CK bit is a read-only indicator of the mode of the filter.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 293 The clock generator creates the clocks used in the MCU (see Figure 5-17 ).
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 294 F reescale Semiconductor A number greater equal than 4096 rising OSCCLK edges within a chec k window is called osc ok . Note that osc ok immediately terminates the current check window .
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 295 NO TE Remember that in parallel to additional actions caused by self clock mode or clock monitor reset 1 handling the clock quality checker continues to check the OSCCLK signal.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 296 F reescale Semiconductor 5.4.2.2 Self Cloc k Mode The VCO has a minimum operating frequency , f SCM .
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 297 Figure 5-21. W ait Mode Entr y/Exit Sequence Enter Wait Mode PLL W AI=1 ? Exit Wait w. CMRESET Exit Wait w. ext.RESET Exit Wait Mode Enter SCM Exit Wait Mode CPU Req’ s W ait Mode.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 298 F reescale Semiconductor There are four dif ferent scenarios for the CRG to restart the MCU from wait mode: • .
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 299 T able 5-12. Outcome of Clock Loss in W ait Mode CME SCME SCMIE CRG Actions 0X X Clock f ailure --> No action, clock loss not detected.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 300 F reescale Semiconductor Figure 5-22. Stop Mode Entry/Exit Sequence Exit Stop w. CMRESET Exit Stop Mode Enter SCM Exit Stop Mode Core req’s Stop Mode. Clear PLLSEL, Disable PLL CME=1 ? INT ? CM fail ? SCME=1 ? SCMIE=1 ? Continue w.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 301 5.4.3.3.1 Wake-up fr om Pseudo Stop Mode (PSTP=1) W ake-up from pseudo stop mode is the same as w ake-up from wait mode.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 302 F reescale Semiconductor T able 5-13. Outcome of Clock Loss in Pseudo Stop Mode CME SCME SCMIE CRG Actions 0X X Clock f ailure --> No action, clock loss not detected.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 303 5.4.3.3.2 Wake-up fr om Full Stop (PSTP = 0) The MCU requires an external interrupt or an e xternal reset in order to wake-up from stop-mode.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 304 F reescale Semiconductor Figure 5-23. Fast W ake-up from Full Stop Mode: Example 1 .
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 305 5.5 Resets This section describes ho w to reset the MC9S12XDP512, and how the MC9S12XDP512 itself controls the reset of the MCU. It explains all special reset requirements.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 306 F reescale Semiconductor NO TE External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a v alid logic 1 within 64 SYSCLK cycles after the lo w driv e is released.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 307 5.5.2 Cloc k Monitor Reset The MC9S12XDP512 generates a clock monitor reset in case all.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 308 F reescale Semiconductor Figure 5-26. RESET Pin Tied to V DD (by a pull-up resistor) Figure 5-27. RESET Pin Held Low Externall y 5.6 Interrupts The interrupts/reset vectors requested by the CRG are listed in T able 5-16 .
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 309 5.6.2 PLL Loc k Interrupt The MC9S12XDP512 generates a PLL Lock interrupt when the LOCK condition of the PLL has changed, either from a locked state to an unlock ed state or vice versa.
Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 310 F reescale Semiconductor.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 311 Chapter 6 Pier ce Oscillator (S12XOSCLCPV1) 6.1 Intr oduction The Pierce oscillator (XOSC) module provides a rob ust, low-noise and lo w-power clock source. The module will be operated from the V DDPLL supply rail (2.
Chapter 6 Pierce Oscillator (S12XOSCLCPV1) MC9S12XDP512 Data Sheet, Rev . 2.11 312 F reescale Semiconductor 6.1.3 Bloc k Diagram Figure 6-1 sho ws a block diagram of the XOSC. Figure 6-1. XOSC Block Dia gram 6.2 External Signal Description This section lists and describes the signals that connect of f chip 6.
Chapter 6 Pierce Oscillator (S12XOSCLCPV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 313 EXT AL input frequency. In full stop mode (PSTP = 0), the EXT AL pin is pulled down by an internal resistor of typical 200 k Ω .
Chapter 6 Pierce Oscillator (S12XOSCLCPV1) MC9S12XDP512 Data Sheet, Rev . 2.11 314 F reescale Semiconductor 6.2.3 XCLKS — Input Signal The XCLKS is an input signal which controls whether a crystal i.
Chapter 6 Pierce Oscillator (S12XOSCLCPV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 315 6.4.3 W ait Mode Operation During wait mode, XOSC is not impacted. 6.4.4 Stop Mode Operation XOSC is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled.
Chapter 6 Pierce Oscillator (S12XOSCLCPV1) MC9S12XDP512 Data Sheet, Rev . 2.11 316 F reescale Semiconductor.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 317 Chapter 7 Analog-to-Digital Con ver ter (A TD10B16CV4) 7.1 Intr oduction The A TD10B16C is a 16-channel, 10-bit, multiplexed input successi ve approximation analog-to-digital con verter .
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 318 F reescale Semiconductor Figure 7-1. A TD10B16C Block Dia gram V SSA AN8 A TD10B16C Analog MUX Mode and Su.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 319 7.2 External Signal Description This section lists all inputs to the A TD10B16C block.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 320 F reescale Semiconductor . NO TE Register Address = Base Address + Address Of fset, where the Base Address is defined at the MCU le vel and the Address Of fset is defined at the module le vel.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 321 7.3.2 Register Descriptions This section describes in address order all the A TD10B16C registers and their indi vidual bits.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 322 F reescale Semiconductor 7.3.2.1 A TD Control Register 0 (A TDCTL0) Writes to this register will abort current con version sequence b ut will not start a new sequence.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 323 7.3.2.2 A TD Control Register 1 (A TDCTL1) Writes to this register will abort current con version sequence b ut will not start a new sequence.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 324 F reescale Semiconductor 7.3.2.3 A TD Control Register 2 (A TDCTL2) This register controls po wer down, interrupt and e xternal trigger. Writes to this register will abort current con version sequence b ut will not start a ne w sequence.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 325 Read: Anytime Write: Anytime Module Base + 0x0002 76543210 R ADPU AFFC A W AI ETRIGLE ETRIGP ETRIGE ASCIE ASCIF W Reset 00000000 = Unimplemented or Reser ved Figure 7-5.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 326 F reescale Semiconductor 1 ASCIE A TD Sequence Complete Interrupt Enable 0 A TD Sequence Complete interrupt requests are disabled. 1 A TD Interrupt will be requested whenev er ASCIF = 1 is set.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 327 7.3.2.4 A TD Control Register 3 (A TDCTL3) This register controls the con version sequence length, FIFO for results registers and beha vior in Freeze Mode.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 328 F reescale Semiconductor T able 7-9. Con version Sequence Length Coding S8C S4C S2C S1C Number of Con vers.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 329 7.3.2.5 A TD Control Register 4 (A TDCTL4) This register selects the con version clock frequency , the length of the second phase of the sample time and the resolution of the A/D con version (i.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 330 F reescale Semiconductor T able 7-13. Cloc k Prescaler V alues Prescale V alue T otal Divisor V alue Max. Bus Clock 1 1 Maximum A TD conv ersion clock frequency is 2 MHz.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 331 7.3.2.6 A TD Control Register 5 (A TDCTL5) This register selects the type of con version sequence and the analog input channels sampled.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 332 F reescale Semiconductor 3:0 C[D:A} Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are sampled and conv er ted to digital codes.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 333 T able 7-17. Analog Input Channel Select Coding CD CC CB CA Analog Input Channel .
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 334 F reescale Semiconductor 7.3.2.7 A TD Status Register 0 (A TDST A T0) This read-only register contains the Sequence Complete Flag, o verrun flags for external trigger and FIFO mode, and the con version counter.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 335 7.3.2.8 Reserved Register 0 (A TDTEST0) Read: Anytime, returns unpredictable v alues Write: Anytime in special modes, unimplemented in normal modes NO TE Writing to this register when in special modes can alter functionality .
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 336 F reescale Semiconductor 7.3.2.10 A TD Status Register 2 (A TDST A T2) This read-only register contains the Con version Complete Flags CCF15 to CCF8. Read: Anytime Write: Anytime, no ef fect T able 7-20.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 337 7.3.2.11 A TD Status Register 1 (A TDST A T1) This read-only register contains th.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 338 F reescale Semiconductor 7.3.2.12 A TD Input Enable Register 0 (A TDDIEN0) Read: Anytime Write: anytime 7.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 339 7.3.2.14 P or t Data Register 0 (PORT AD0) The data port associated with the A TD is input-only. The port pins are shared with the analog A/D inputs AN[15:8].
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 340 F reescale Semiconductor 7.3.2.15 P or t Data Register 1 (PORT AD1) The data port associated with the A TD is input-only. The port pins are shared with the analog A/D inputs AN7-0.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 341 7.3.2.16 A TD Con version Result Register s (A TDDRx) The A/D con version results are stored in 16 read-only result re gisters. The result data is formatted in the result registers bases on tw o criteria.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 342 F reescale Semiconductor 7.3.2.16.2 Right J ustified Result Data 7.4 Functional Description The A TD10B16C is structured in an analog and a digital sub-block.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 343 When not sampling, the sample and hold machine disables its o wn clocks. The analog electronics continue drawing their quiescent current.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 344 F reescale Semiconductor During a con version, if additional acti ve edges are detected the ov errun error flag ETORF is set. In either le vel or edge triggered modes, the first con version begins when the trigger is recei ved.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 345 Entering wait mode, the A TD con version either continues or halts for lo w power depending on the logical v alue of the A W AIT bit.
Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 346 F reescale Semiconductor.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 347 Chapter 8 Analog-to-Digital Con ver ter (A TD10B8CV3) 8.1 Intr oduction The A TD10B8C is an 8-channel, 10-bit, multiplexed input successi ve approximation analog-to-digital con verter . Refer to device electrical specifications for A TD accuracy.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 348 F reescale Semiconductor 8.1.2.2 MCU Operating Modes • Stop mode Entering stop mode causes all clocks to halt and thus the system is placed in a minimum po wer standby mode.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 349 Figure 8-1. A TD Bloc k Diagram V SSA A TD10B8C Analog MUX Mode and Successive App.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 350 F reescale Semiconductor 8.3 Memor y Map and Register Definition This section provides a detailed description of all re gisters accessible in the A TD. 8.3.1 Module Memory Map Figure 8-2 gi ves an o vervie w of all A TD registers.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 351 0x000A Unimplemente d R W 0x000B A TDST A T1 R CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 .
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 352 F reescale Semiconductor 0x0016 A TDDR3H 10-BIT BIT 9 MSB BIT 7 MSB BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 353 0x0011 A TDDR0L 10-BIT BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 B.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 354 F reescale Semiconductor 8.3.2.1 A TD Control Register 0 (A TDCTL0) Writes to this register will abort current con version sequence b ut will not start a new sequence.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 355 1 1 0 AN6 1 1 1 AN7 T able 8-2. Multi-Channel Wrap Around Coding WRAP2 WRAP1 WRAP0.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 356 F reescale Semiconductor 8.3.2.2 A TD Control Register 1 (A TDCTL1) Writes to this register will abort current con version sequence b ut will not start a new sequence.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 357 8.3.2.3 A TD Control Register 2 (A TDCTL2) This register controls po wer down, interrupt and e xternal trigger. Writes to this register will abort current con version sequence b ut will not start a ne w sequence.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 358 F reescale Semiconductor 8.3.2.4 A TD Control Register 3 (A TDCTL3) This register controls the conversion sequence length, FIFO for results registers and behavior in freeze mode.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 359 2 FIFO Result Register FIFO Mode — If this bit is zero (non-FIFO mode), the A/D .
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 360 F reescale Semiconductor 8.3.2.5 A TD Control Register 4 (A TDCTL4) This register selects the con version clock frequency , the length of the second phase of the sample time and the resolution of the A/D con version (i.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 361 T able 8-12. Cloc k Prescaler V alues Prescale V alue T otal Divisor V alue Max. Bus Clock 1 1 Maximum A TD conv ersion clock frequency is 2 MHz.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 362 F reescale Semiconductor 8.3.2.6 A TD Control Register 5 (A TDCTL5) This register selects the type of con version sequence and the analog input channels sampled.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 363 T able 8-14. A vailable Result Data Formats SRES8 DJM DSGN Result Data Formats Des.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 364 F reescale Semiconductor 8.3.2.7 A TD Status Register 0 (A TDST A T0) This read-only register contains the sequence complete flag, o verrun flags for external trigger and FIFO mode, and the con version counter .
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 365 8.3.2.8 Reserved Register (A TDTEST0) Read: Anytime, returns unpredictable v alues Write: Anytime in special modes, unimplemented in normal modes NO TE Writing to this register when in special modes can alter functionality .
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 366 F reescale Semiconductor 8.3.2.10 A TD Status Register 1 (A TDST A T1) This read-only register contains the con version complete flags. Read: Anytime Write: Anytime, no ef fect T able 8-19.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 367 8.3.2.11 A TD Input Enable Register (A TDDIEN) Read: Anytime Write: Anytime 8.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 368 F reescale Semiconductor 8.3.2.13 A TD Con version Result Register s (A TDDRx) The A/D con version results are stored in 8 read-only result re gisters. The result data is formatted in the result registers based on tw o criteria.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 369 8.3.2.13.2 Right J ustified Result Data 8.4 Functional Description The A TD is structured in an analog and a digital sub-block. 8.4.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 370 F reescale Semiconductor 8.4.1.2 Analog Input Multiplex er The analog input multiplex er connects one of the 8 external analog input channels to the sample and hold machine.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 371 During a con version, if additional acti ve edges are detected the ov errun error flag ETORF is set. In either le vel or edge triggered modes, the first con version begins when the trigger is recei ved.
Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 372 F reescale Semiconductor 8.4.2.3 Low P ower Modes The A TD can be configured for lower MCU po wer consumption in 3 different ways: 1. Stop mode: This halts A/D con version.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 373 Chapter 9 XGA TE (S12XGA TEV2) 9.1 Intr oduction The XGA TE module is a peripheral co-processor that allows autonomous data transfers between the MCU’ s peripherals and the internal memories.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 374 F reescale Semiconductor 9.1.2 Modes of Operation There are four run modes on S12X de vices. • Run mode, wait mode, stop mode The XGA TE is able to operate in all of these three system modes.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 375 9.3 Memor y Map and Register Definition This section provides a detailed description of address space and re gisters used by the XGA TE module. The memory map for the XGA TE module is giv en belo w in T able 9-1 .
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 376 F reescale Semiconductor 9.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard re gister diagram with an associated figure number.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 377 Register Name 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 0x0010 XGIF R XGIF_3F XGIF_3E XGIF_3D XGIF.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 378 F reescale Semiconductor Register Name 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 0x0026 XGR3 R XGR3 W 0x0028 XGR4 R XGR4 W 0x002A XGR5 R XGR5 W 0x002C XGR6 R XGR6 W 0x002E XGR7 R XGR7 W = Unimplemented or Reser ved Figure 9-2.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 379 9.3.2.1 XGA TE Control Register (XGMCTL) All module level switches and flags are located in the module control register Figure 9-3 .
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 380 F reescale Semiconductor 11 XGF ACTM XGF ACT Mask — This bit controls the write access to the XGF ACT bit. The XGF A CT bit can only be set or cleared if a "1" is written to the XGF A CTM bit in the same register access.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 381 4 XGSS XGA TE Single Step — This bit forces the e xecution of a single instruction if the XGA TE is in DEBUG Mode and no software error has occurred (XGSWEIF cleared).
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 382 F reescale Semiconductor 9.3.2.2 XGA TE Channel ID Register (XGCHID) The XGA TE channel ID register ( Figure 9-4 ) sho ws the identifier of the XGA TE channel that is currently acti ve.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 383 9.3.2.4 XGA TE Channel Interrupt Flag V ector (XGIF) The interrupt flag vector ( Figure 9-6 ) pro vides access to the interrupt flags bits of each channel.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 384 F reescale Semiconductor Write: Anytime NO TE Suggested Mnemonics for accessing the interrupt flag vector on a w ord basis are: .
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 385 9.3.2.5 XGA TE Software T rig ger Register (XGSWT) The eight software triggers of the XGA TE module can be set and cleared through the XGA TE software trigger register ( Figure 9-7 ).
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 386 F reescale Semiconductor 9.3.2.6 XGA TE Semaphore Register (XGSEM) The XGA TE provides a set of eight hardware semaphores that can be shared between the S12X_CPU and the XGA TE RISC core.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 387 9.3.2.7 XGA TE Condition Code Register (XGCCR) The XGCCR register ( Figure 9-9 ) pro vides access to the RISC core’ s condition code register.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 388 F reescale Semiconductor 9.3.2.8 XGA TE Program Counter Register (XGPC) The XGPC register ( Figure 9-10 ) pro vides access to the RISC core’ s program counter. Read: In debug mode if unsecured Write: In debug mode if unsecured 9.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 389 9.3.2.10 XGA TE Register 2 (XGR2) The XGR2 register ( Figure 9-13 ) pro vides access to the RISC core’ s register 2. Read: In debug mode if unsecured Write: In debug mode if unsecured 9.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 390 F reescale Semiconductor 9.3.2.12 XGA TE Register 4 (XGR4) The XGR4 register ( Figure 9-15 ) pro vides access to the RISC core’ s register 4. Read: In debug mode if unsecured Write: In debug mode if unsecured 9.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 391 9.3.2.14 XGA TE Register 6 (XGR6) The XGR6 register ( Figure 9-17 ) pro vides access to the RISC core’ s register 6. Read: In debug mode if unsecured Write: In debug mode if unsecured 9.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 392 F reescale Semiconductor 9.4 Functional Description The core of the XGA TE module is a RISC processor which is able to access the MCU’ s internal memories and peripherals (see Figure 9-1 ).
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 393 9.4.2 Pr ogrammer’ s Model Figure 9-19. Programmer’ s Model The programmer’ s model of the XGA TE RISC core is shown in Figure 9-19 .
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 394 F reescale Semiconductor Figure 9-20. XGA TE V ector Block 9.4.4 Semaphores The XGA TE module offers a set of eight hardware semaphores.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 395 Figure 9-21. Semaphore State T ransitions UNLOCKED LOCKED BY S12X_CPU LOCKED BY XGATE CSEM Instruction %.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 396 F reescale Semiconductor Figure 9-22 gi ves an e xample of the typical usage of the XGA TE hardware semaphores. T wo concurrent threads are running on the system. One is running on the S12X_CPU and the other is running on the RISC core.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 397 9.5 Interrupts 9.5.1 Incoming Interrupt Requests XGA TE threads are triggered by interrupt requests which are routed to the XGA TE module (see S12X_INT Section).
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 398 F reescale Semiconductor • Single Stepping Writing a "1" to the XGSS bit will call the RISC core to execute a single instruction. All RISC core registers will be updated accordingly.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 399 3. T agged Breakpoints The S12X_DBG module is able to place tags on fetched opcodes. The XGATE is able to enter debug mode right before a tagged opcode is executed (see section 4.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 400 F reescale Semiconductor 9.8.1.1 Naming Con ventions RD Destination register , allowed range is R0–R7 RD.L Lo w byte of the destination register , bits [7:0] RD.H High byte of the destination register , bits [15:8] RS, RS1, RS2 Source register , allowed range is R0–R7 RS.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 401 9.8.1.4 Immediate 4-Bit Wide (IMM4) The 4-bit wide immediate addressing mode is supported by all shift instructions.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 402 F reescale Semiconductor 9.8.1.8 Dy adic Addressing (D Y A) In this mode the result of an operation between two re gisters is stored in one of the registers used as operands.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 403 9.8.1.13 Index Register plus Register Offset (IDR) For load and store instructions (RS, RI) pro vides a variable of fset in a register. Examples: LDB R4,(R1,R2) ; loads a byte from R1+R2 into R4 STW R4,(R1,R2) ; stores R4 as a word to R1+R2 9.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 404 F reescale Semiconductor 9.8.2.2 Logic and Arithmetic Instructions All logic and arithmetic instructions support the 8-bit immediate addressing mode (IMM8: RD = RD ∗ #IMM8) and the triadic addressing mode (TRI: RD = RS1 ∗ RS2).
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 405 9.8.2.5 Bit Field Operations This addressing mode is used to identify the position and size of a bit field for insertion or extraction. The width and of fset are coded in the lo wer byte of the source register 2, RS2.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 406 F reescale Semiconductor 9.8.3 Cyc le Notation T able 9-17 show the XGA TE access detail notation. Each code letter equals one XGA TE cycle. Each letter implies additional wait c ycles if memories or peripherals are not accessible.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 407 Operation RS1 + RS2 + C ⇒ RD Adds the content of register RS1, the content of re gister RS2 and the value of the Carry bit using binary addition and stores the result in the destination register RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 408 F reescale Semiconductor Operation RS1 + RS2 ⇒ RDRD + IMM16 ⇒ RD (translates to ADDL RD, #IMM16[7:0]; ADDH RD, #[15:8]) Performs a 16-bit addition and stores the result in the destination register RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 409 Operation RD + IMM8:$00 ⇒ RD Adds the content of high byte of register RD and a signed immediate 8-Bit constant using binary addition and stores the result in the high byte of the destination register RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 410 F reescale Semiconductor Operation RD + $00:IMM8 ⇒ RD Adds the content of register RD and an unsigned immediate 8-Bit constant using binary addition and stores the result in the destination register RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 411 Operation RS1 & RS2 ⇒ RDRD & IMM16 ⇒ RD (translates to ANDL RD, #IMM[7:0]; ANDH RD, #IMM16[15:8]) Performs a bit wise logical AND of two 16-bit v alues and stores the result in the destination register RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 412 F reescale Semiconductor Operation RD.H & IMM8 ⇒ RD.H Performs a bit wise logical AND between the high byte of register RD and an immediate 8-Bit constant and stores the result in the destination register RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 413 Operation RD.L & IMM8 ⇒ RD.L Performs a bit wise logical AND between the lo w byte of register RD and an immediate 8-Bit constant and stores the result in the destination register RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 414 F reescale Semiconductor Operation n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with the sign bit (RD[15]).
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 415 Operation If C = 0, then PC + $0002 + (REL9 << 1) ⇒ PC T ests the Carry flag and branches if C = 0. CCR Effects Code and CPU Cycles BCC Branch if Carry Cleared (Same as BHS) BCC NZ V C ———— N: Not affected.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 416 F reescale Semiconductor Operation If C = 1, then PC + $0002 + (REL9 << 1) ⇒ PC T ests the Carry flag and branches if C = 1. CCR Effects Code and CPU Cycles BCS Branch if Carry Set (Same as BLO) BCS NZ V C ———— N: Not affected.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 417 Operation If Z = 1, then PC + $0002 + (REL9 << 1) ⇒ PC T ests the Zero flag and branches if Z = 1. CCR Effects Code and CPU Cycles BEQ Branch if Equal BEQ NZ V C ———— N: Not affected.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 418 F reescale Semiconductor Operation RS1[( o + w ): o ] ⇒ RD[ w :0]; 0 ⇒ RD[15:( w +1)] w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position o and writes them right aligned into re gister RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 419 Operation FirstOne (RS) ⇒ RD; Searches the first “1” beginning from the MSB=15 do wn to LSB=0 in register RS and places the result into the destination register RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 420 F reescale Semiconductor Operation RS1[ w : 0 ] ⇒ RD[( w+o ):o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0 and writes them into re gister RD at position o .
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 421 Operation !RS1[ w : 0 ] ⇒ RD[ w +o:o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0, in verts them and writes into register RD at position o .
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 422 F reescale Semiconductor Operation !(RS1[ w : 0 ] ^ RD[w+o:o]) ⇒ RD[ w +o:o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0, performs an XNOR with RD[w+o:o] and writes the bits back.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 423 Operation If N ^ V = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 424 F reescale Semiconductor Operation If Z | (N ^ V) = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 425 Operation If C | Z = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 426 F reescale Semiconductor Operation If C = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 427 Operation RD.H & IMM8 ⇒ NONE Performs a bit wise logical AND between the high byte of register RD and an immediate 8-Bit constant.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 428 F reescale Semiconductor Operation RD.L & IMM8 ⇒ NONE Performs a bit wise logical AND between the lo w byte of register RD and an immediate 8-Bit constant. Only the condition code flags get updated, b ut no result is written back .
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 429 Operation If Z | (N ^ V) = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 430 F reescale Semiconductor Operation If C = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 431 Operation If C | Z = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 432 F reescale Semiconductor Operation If N ^ V = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 433 Operation If N = 1, then PC + $0002 + (REL9 << 1) ⇒ PC T ests the Sign flag and branches if N = 1. CCR Effects Code and CPU Cycles BMI Branch if Minus BMI NZ V C ———— N: Not affected.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 434 F reescale Semiconductor Operation If Z = 0, then PC + $0002 + (REL9 << 1) ⇒ PC T ests the Zero flag and branches if Z = 0. CCR Effects Code and CPU Cycles BNE Branch if Not Equal BNE NZ V C ———— N: Not affected.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 435 Operation If N = 0, then PC + $0002 + (REL9 << 1) ⇒ PC T ests the Sign flag and branches if N = 0. CCR Effects Code and CPU Cycles BPL Branch if Plus BPL NZ V C ———— N: Not affected.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 436 F reescale Semiconductor Operation PC + $0002 + (REL10 << 1) ⇒ PC Branches always CCR Effects Code and CPU Cycles BRA Branch Always BRA NZ V C ———— N: Not affected.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 437 Operation Put XGA TE into Debug Mode (see Section 9.6.2, “Entering Debug Mode” )and signals a Softw are breakpoint to the S12X_DBG module (see section 4.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 438 F reescale Semiconductor Operation If V = 0, then PC + $0002 + (REL9 << 1) ⇒ PC T ests the Overflo w flag and branches if V = 0. CCR Effects Code and CPU Cycles BVC Branch if Overflow Cleared BVC NZ V C ———— N: Not affected.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 439 Operation If V = 1, then PC + $0002 + (REL9 << 1) ⇒ PC T ests the Overflo w flag and branches if V = 1. CCR Effects Code and CPU Cycles BVS Branch if Overflow Set BVS NZ V C ———— N: Not affected.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 440 F reescale Semiconductor Operation RS2 – RS1 ⇒ NONE (translates to SUB R0, RS1, RS2) RD – IMM16 ⇒ NONE (translates to CMPL RD, #IMM16[7:0]; CPCH RD, #IMM16[15:8]) Subtracts two 16-bit v alues and discards the result.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 441 Operation RS.L – IMM8 ⇒ NONE, only condition code flags get updated Subtracts the 8-Bit constant IMM8 contained in the instruction code from the lo w byte of the source register RS.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 442 F reescale Semiconductor Operation ~RS ⇒ RD (translates to XNOR RD, R0, RS) ~RD ⇒ RD (translates to XNOR RD, R0, RD) Performs a one’ s complement on a general purpose register.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 443 Operation RS2 – RS1 − Χ ⇒ NONE (translates to SBC R0, RS1, RS2) Subtracts the carry bit and the content of register RS2 from the content of re gister RS1 using binary subtraction and discards the result.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 444 F reescale Semiconductor Operation RS.H - IMM8 - C ⇒ NONE, only condition code flags get updated Subtracts the carry bit and t.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 445 Operation Unlocks a semaphore that was lock ed by the RISC core. In monadic address mode, bits RS[2:0] select the semaphore to be cleared. CCR Effects Code and CPU Cycles CSEM Clear Semaphore CSEM NZ V C ———— N: Not affected.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 446 F reescale Semiconductor Operation n = RS or IMM4 Shifts the bits in register RD n positions to the left. The lo wer n bits of the register RD become filled with the carry flag. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 447 Operation n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with the carry flag.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 448 F reescale Semiconductor Operation PC + $0002 ⇒ RD; RD ⇒ PC Jumps to the address stored in RD and sa ves the return address in RD. CCR Effects Code and CPU Cycles JA L Jump and Link JAL NZ V C ———— N: Not affected.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 449 Operation M[RB, #OFFS5 ] ⇒ RD.L; $00 ⇒ RD.H M[RB, RI ] ⇒ RD.L; $00 ⇒ RD.H M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H; RI+1 ⇒ RI; 1 RI-1 ⇒ RI; M[RS, RI] ⇒ RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 450 F reescale Semiconductor Operation IMM8 ⇒ RD.H; Loads an eight bit immediate constant into the high byte of register RD. The lo w byte is not affected. CCR Effects Code and CPU Cycles LDH Load Immediate 8-Bit Constant (High Byte) LDH NZ V C ———— N: Not affected.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 451 Operation IMM8 ⇒ RD.L; $00 ⇒ RD.H Loads an eight bit immediate constant into the lo w byte of register RD. The high byte is cleared. CCR Effects Code and CPU Cycles LDL Load Immediate 8-Bit Constant (Low Byte) LDL NZ V C ———— N: Not affected.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 452 F reescale Semiconductor Operation M[RB, #OFFS5 ] ⇒ RD M[RB, RI ] ⇒ RD M[RB, RI] ⇒ RD; RI+2 ⇒ RI 1 RI-2 ⇒ RI; M[RS, RI] ⇒ RD IMM16 ⇒ RD (translates to LDL RD, #IMM16[7:0]; LDH RD, #IMM16[15:8]) Loads a 16-bit v alue into the register RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 453 Operation n = RS or IMM4 Shifts the bits in register RD n positions to the left. The lo wer n bits of the register RD become filled with zeros. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 454 F reescale Semiconductor Operation n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with zeros. The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 455 Operation RS ⇒ RD (translates to OR RD, R0, RS) Copies the content of RS to RD. CCR Effects Code and CPU Cycles MO V Move Register Content MOV NZ V C ∆∆ 0— N: Set if bit 15 of the result is set; cleared otherwise.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 456 F reescale Semiconductor Operation –RS ⇒ RD (translates to SUB RD, R0, RS) –RD ⇒ RD (translates to SUB RD, R0, RD) Performs a two’ s complement on a general purpose register.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 457 Operation No Operation for one cycle. CCR Effects Code and CPU Cycles NOP No Operation NOP NZ V C ———— N: Not affected. Z: Not aff ected. V: Not aff ected.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 458 F reescale Semiconductor Operation RS1 | RS2 ⇒ RDRD | IMM16 ⇒ RD (translates to ORL RD, #IMM16[7:0]; ORH RD, #IMM16[15:8] Performs a bit wise logical OR between two 16-bit v alues and stores the result in the destination register RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 459 Operation RD.H | IMM8 ⇒ RD.H Performs a bit wise logical OR between the high byte of register RD and an immediate 8-Bit constant and stores the result in the destination register RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 460 F reescale Semiconductor Operation RD.L | IMM8 ⇒ RD.L Performs a bit wise logical OR between the lo w byte of register RD and an immediate 8-Bit constant and stores the result in the destination register RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 461 Operation Calculates the number of ones in the register RD. The Carry flag will be set if the number is odd, otherwise it will be cleared. CCR Effects Code and CPU Cycles PA R Calculate Parity PAR NZ V C 0 ∆ 0 ∆ N: 0; cleared.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 462 F reescale Semiconductor Operation n = RS or IMM4 Rotates the bits in register RD n positions to the left. The lo wer n bits of the register RD are filled with the upper n bits. T wo source forms are a vailable.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 463 Operation n = RS or IMM4 Rotates the bits in register RD n positions to the right. The upper n bits of the register RD are filled with the lo wer n bits. T wo source forms are a v ailable.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 464 F reescale Semiconductor Operation T erminates the current thread of program ex ecution and remains idle until a new thread is started by the hardware scheduler. CCR Effects Code and CPU Cycles RT S Return to Scheduler RTS NZ V C ———— N: Not affected.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 465 Operation RS1 - RS2 - C ⇒ RD Subtracts the content of register RS2 and the v alue of the Carry bit from the content of register RS1 using binary subtraction and stores the result in the destination re gister RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 466 F reescale Semiconductor Operation Attempts to set a semaphore. The state of the semaphore will be stored in the Carry-Flag: 1 = Semaphore is locked by the RISC core 0 = Semaphore is locked by the S12X_CPU In monadic address mode, bits RS[2:0] select the semaphore to be set.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 467 Operation The result in RD is the 16-bit sign extended representation of the original tw o’ s complement number in the lo w byte of RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 468 F reescale Semiconductor Operation Sets the Interrupt Flag of an XGA TE Channel. This instruction supports two source forms. If inherent address mode is used, then the interrupt flag of the current channel (XGCHID) will be set.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 469 Operation RS.L ⇒ M[RB, #OFFS5 ] RS.L ⇒ M[RB, RI ] RS.L ⇒ M[RB, RI]; RI+1 ⇒ RI; RI–1 ⇒ RI; RS.L ⇒ M[RB, RI] 1 Stores the lo w byte of register RD to memory.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 470 F reescale Semiconductor Operation RS ⇒ M[RB, #OFFS5 ] RS ⇒ M[RB, RI ] RS ⇒ M[RB, RI]; RI+2 ⇒ RI; RI–2 ⇒ RI; RS ⇒ M[RB, RI] 1 Stores the content of register RS to memory.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 471 Operation RS1 – RS2 ⇒ RDRD − IMM16 ⇒ RD (translates to SUBL RD, #IMM16[7:0]; SUBH RD, #IMM[15:8]) Subtracts two 16-bit v alues and stores the result in the destination register RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 472 F reescale Semiconductor Operation RD – IMM8:$00 ⇒ RD Subtracts a signed immediate 8-Bit constant from the content of high byte of register RD and using binary subtraction and stores the result in the high byte of destination register RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 473 Operation RD – $00:IMM8 ⇒ RD Subtracts an immediate 8 Bit constant from the content of register RD using binary subtraction and stores the result in the destination register RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 474 F reescale Semiconductor Operation TFR RD,CCR: CCR ⇒ RD[3:0], 0 ⇒ RD[15:4] TFR CCR,RD: RD[3:0] ⇒ CCR TFR RD,PC: PC+4 ⇒ RD T ransfers the content of one RISC core register to another.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 475 Operation RS – 0 ⇒ NONE (translates to SUB R0, RS, R0) Subtracts zero from the content of register RS using binary subtraction and discards the result.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 476 F reescale Semiconductor Operation ~(RS1 ^ RS2) ⇒ RD~(RD ^ IMM16) ⇒ RD (translates to XNOR RD, #IMM[15:8]; XNOR RD, #IMM16[7:0]) Performs a bit wise logical exclusi ve NOR between two 16-bit v alues and stores the result in the destination register RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 477 Operation ~(RD.H ^ IMM8) ⇒ RD.H Performs a bit wise logical exclusi ve NOR between the high byte of re gister RD and an immediate 8-Bit constant and stores the result in the destination register RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 478 F reescale Semiconductor Operation ~(RD.L ^ IMM8) ⇒ RD.L Performs a bit wise logical exclusi ve NOR between the lo w byte of register RD and an immediate 8-Bit constant and stores the result in the destination register RD.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 479 9.8.6 Instruction Coding T able 9-18 summarizes all XGA TE instructions in the order of their machine coding.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 480 F reescale Semiconductor Logical T riadic AND RD , RS1, RS2 00010 R D R S 1 R S 2 00 OR RD , RS1, RS2 00010 R D R S 1 R S 2 10 XN.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 481 ANDH RD , #IMM8 1 0 0 0 1 RD IMM8 BITL RD , #IMM8 1 0 0 1 0 RD IMM8 BITH RD , #IMM8 1 0 0 1 1 RD IMM8 OR.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 482 F reescale Semiconductor 9.9 Initialization and Application Information 9.9.1 Initialization The recommended initialization of the XGA TE is as follows: 1. Clear the XGE bit to suppress any incoming service requests.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 483 XGCHID EQU XGATE_REGS+$02 ;XGATE Channel ID Register XGVBR EQU XGATE_REGS+$06 ;XGATE Vector Base Registe.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 484 F reescale Semiconductor STD 2,X+ STD 2,X+ MOVW #$FF00, XGSWT ;clear all software triggers ;#####################################.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 485 STB R4,(R2,#(SCIDRL-SCI_REGS)) ;initiate SCI transmit CMPL R4,#$0D BEQ XGATE_CODE_DONE RTS XGATE_CODE_DO.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 486 F reescale Semiconductor.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 487.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 488 F reescale Semiconductor.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 489.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 490 F reescale Semiconductor.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 491.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 492 F reescale Semiconductor.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 493.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 494 F reescale Semiconductor.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 495.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 496 F reescale Semiconductor.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 497.
Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 498 F reescale Semiconductor.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 499 Chapter 10 Security (S12X9SECV2) 10.1 Intr oduction This specification describes the function of the security mechanism in the S12X chip family (MC9S12XDP512). 10.1.1 Features The user must be reminded that part of the security must lie with the application code.
Chapter 10 Security (S12X9SECV2) MC9S12XDP512 Data Sheet, Rev . 2.11 500 F reescale Semiconductor 10.1.2 Modes of Operation 10.1.3 Securing the Micr ocontr oller Once the user has programmed the Flash and EEPR OM, the chip can be secured by programming the security bits located in the options/security byte in the Flash memory array.
Chapter 10 Security (S12X9SECV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 501 The meaning of the bits KEYEN[1:0] is sho wn in T able 10-2 . Please refer to Section 10.1.5.1, “Unsecuring the MCU Using the Backdoor K ey Access” for more information.
Chapter 10 Security (S12X9SECV2) MC9S12XDP512 Data Sheet, Rev . 2.11 502 F reescale Semiconductor 10.1.4.1 Normal Single Chip Mode (NS) • Background debug module (BDM) operation is completely disabled. • Execution of Flash and EEPR OM commands is restricted.
Chapter 10 Security (S12X9SECV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 503 10.1.5 Unsecuring the Micr ocontr oller Unsecuring the microcontroller can be done by three dif ferent methods: 1. Backdoor ke y access 2. Reprogramming the security bits 3.
Chapter 10 Security (S12X9SECV2) MC9S12XDP512 Data Sheet, Rev . 2.11 504 F reescale Semiconductor If all four 16-bit words match the Flash contents at 0xFF00–0xFF07 (0x7F_FF00–0x7F_FF07), the microcontroller will be unsecured and the security bits SEC[1:0] in the Flash Security register FSEC will be forced to the unsecured state (‘10’).
Chapter 10 Security (S12X9SECV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 505 Special single chip erase and unsecure sequence: 1. Reset into special single chip mode. 2. Write an appropriate v alue to the ECLKDIV register for correct timing.
Chapter 10 Security (S12X9SECV2) MC9S12XDP512 Data Sheet, Rev . 2.11 506 F reescale Semiconductor.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 507 Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.1 Intr oduction The HCS12 enhanced capture timer module has the features .
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 508 F reescale Semiconductor 11.1.3 Bloc k Diagram Figure 11-1.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 509 11.2 External Signal Description The ECT module has a total of eight external pins. 11.2.1 IOC7 — Input Capture and Output Compare Channel 7 This pin serves as input capture or output compare for channel 7.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 510 F reescale Semiconductor 11.3 Memory Map and Register Definition This section provides a detailed description of all memory and re gisters. 11.3.1 Module Memory Map The memory map for the ECT module is gi ven belo w in T able 11-1 .
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 511 0x001E Timer Input Capture/Output Compare Register 7 High (TC7) R/W 3 0x001F.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 512 F reescale Semiconductor 11.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard re gister diagram with an associated figure number.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 513 0x000D TSCR2 R TO I 000 TCRE PR2 PR1 PR0 W 0x000E TFLG1 R C7F C6F C5F C4F C3.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 514 F reescale Semiconductor 0x001C TC6 (High) R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W .
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 515 0x002B ICSYS R SH37 SH26 SH15 SH04 TFMOD P ACMX BUFEN LA TQ W 0x002C Reser v.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 516 F reescale Semiconductor 11.3.2.1 Timer Input Capture/Output Compare Select Register (TIOS) Read or write: Anytime All bits reset to zero.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 517 11.3.2.2 Timer Compare Force Register (CFORC) Read or write: Anytime b ut reads will always return 0x0000 (1 state is transient).
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 518 F reescale Semiconductor 11.3.2.4 Output Compare 7 Data Register (OC7D) Read or write: Anytime All bits reset to zero. Module Base + 0x0003 76543210 R OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 W Reset 00000000 Figure 11-6.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 519 11.3.2.5 Timer Count Register (TCNT) Read: Anytime Write: Has no meaning or ef fect All bits reset to zero.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 520 F reescale Semiconductor 11.3.2.6 Timer System Control Register 1 (TSCR1) Read or write: Anytime e xcept PRNT bit is write once All bits reset to zero.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 521 11.3.2.7 Timer T oggle On Overflo w Register 1 (TT O V) Read or write: Anytime All bits reset to zero. Module Base + 0x0007 76543210 R T OV7 T O V6 TO V5 TO V4 TO V3 T OV2 T O V1 TO V0 W Reset 00000000 Figure 11-10.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 522 F reescale Semiconductor 11.3.2.8 Timer Control Register 1/Timer Contr ol Register 2 (TCTL1/TCTL2) Read or write: Anytime All bits reset to zero.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 523 11.3.2.9 Timer Control Register 3/Timer Contr ol Register 4 (TCTL3/TCTL4) Read or write: Anytime All bits reset to zero.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 524 F reescale Semiconductor 11.3.2.10 Timer Interrupt Enable Register (TIE) Read or write: Anytime All bits reset to zero. The bits C7I–C0I correspond bit-for -bit with the flags in the TFLG1 status register.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 525 11.3.2.11 Timer System Control Register 2 (TSCR2) Read or write: Anytime All bits reset to zero. Module Base + 0x000D 76543210 R TO I 000 TCRE PR2 PR1 PR0 W Reset 00000000 = Unimplemented or Reser ved Figure 11-16.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 526 F reescale Semiconductor 11.3.2.12 Main Timer Interrupt Flag 1 (TFLG1) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 527 11.3.2.13 Main Timer Interrupt Flag 2 (TFLG2) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 528 F reescale Semiconductor 11.3.2.14 Timer Input Capture/Output Compare Registers 0–7 Module Base + 0x0010 15 14 13 12 11 10 9 8 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 00000000 Figure 11-19.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 529 Module Base + 0x0016 15 14 13 12 11 10 9 8 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 00000000 Figure 11-25.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 530 F reescale Semiconductor Read: Anytime Write anytime for output compare function. Writes to these re gisters have no meaning or ef fect during input capture.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 531 11.3.2.15 16-Bit Pulse Accumulator A Contr ol Register (P A CTL) Read: Anytime Write: Anytime All bits reset to zero.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 532 F reescale Semiconductor . 11.3.2.16 Pulse Accumulator A Flag Register (P AFLG) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 533 P AFLG indicates when interrupt conditions hav e occurred.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 534 F reescale Semiconductor When clocking pulse and write to the registers occurs simultaneously , write takes priority and the re gister is not incremented.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 535 11.3.2.19 16-Bit Modulus Down-Counter Contr ol Register (MCCTL) Read: Anytime Write: Anytime All bits reset to zero.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 536 F reescale Semiconductor 11.3.2.20 16-Bit Modulus Down-Counter FLA G Register (MCFLG) Read: Anytime Write only used in the flag clearing mechanism for bit 7.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 537 11.3.2.21 ICP AR — Input Control Pulse Accum ulators Register (ICP AR) Read: Anytime Write: Anytime. All bits reset to zero. The 8-bit pulse accumulators P A C3 and P A C2 can be enabled only if P AEN in P A CTL is cleared.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 538 F reescale Semiconductor 11.3.2.22 Delay Counter Contr ol Register (DL YCT) Read: Anytime Write: Anytime All bits reset to zero. Module Base + 0x0029 76543210 R DL Y7 DL Y6 DL Y5 DL Y4 DL Y3 DL Y2 DL Y1 DL Y0 W Reset 00000000 Figure 11-44.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 539 11.3.2.23 Input Control Overwrite Register (ICO VW) Read: Anytime Write: Anytime All bits reset to zero.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 540 F reescale Semiconductor 11.3.2.24 Input Control System Contr ol Register (ICSYS) Read: Anytime Write: Once in normal modes All bits reset to zero.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 541 11.3.2.25 Precision Timer Prescaler Select Register (PTPSR) Read: Anytime Write: Anytime All bits reset to zero.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 542 F reescale Semiconductor 11.3.2.26 Precision Timer Modulus Counter Prescaler Select Register (PTMCPSR) Read: Anytime Write: Anytime All bits reset to zero.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 543 11.3.2.27 16-Bit Pulse Accumulator B Contr ol Register (PBCTL) Read: Anytime Write: Anytime All bits reset to zero.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 544 F reescale Semiconductor 11.3.2.28 Pulse Accumulator B Flag Register (PBFLG) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 545 11.3.2.29 8-Bit Pulse Accumulator s Holding Registers (P A3H–P A0H) Read: Anytime. Write: Has no ef fect. All bits reset to zero.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 546 F reescale Semiconductor 11.3.2.30 Modulus Down-Counter Count Register (MCCNT) Read: Anytime Write: Anytime. All bits reset to one. A full access for the counter register will tak e place in one clock cycle.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 547 11.3.2.31 Timer Input Capture Holding Registers 0–3 (TCxH) Module Base + 0x0038 15 14 13 12 11 10 9 8 R TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 W Reset 00000000 = Unimplemented or Reser ved Figure 11-57.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 548 F reescale Semiconductor Read: Anytime Write: Has no ef fect. All bits reset to zero. These registers are used to latch the v alue of the input capture registers TC0–TC3.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 549 Figure 11-65. Detailed Timer Block Dia gram in Latch Mode when PRNT = 0 16 BIT MAIN TIMER P1 Comparator TC0H Hold Reg.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 550 F reescale Semiconductor Figure 11-66. Detailed Timer Block Dia gram in Latch Mode when PRNT = 1 16 BIT MAIN TIMER P1 Comparator TC0H Hold Reg.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 551 Figure 11-67. Detailed Timer Block Dia gram in Queue Mode when PRNT = 0 16 BIT MAIN TIMER P1 TC0H Hold Reg.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 552 F reescale Semiconductor Figure 11-68. Detailed Timer Block Dia gram in Queue Mode when PRNT = 1 16 BIT MAIN TIMER P1 TC0H Hold Reg.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 553 Figure 11-69. 8-Bit Pulse Accumulator s Block Dia gram P0 Load Holding Regis.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 554 F reescale Semiconductor Figure 11-70. 16-Bit Pulse Accumulator s Block Dia gram Figure 11-71.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 555 11.4.1 Enhanced Capture Timer Modes of Operation The enhanced capture timer has 8 input capture, output compare (IC/OC) channels, same as on the HC12 standard timer (timer channels TC0 to TC7).
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 556 F reescale Semiconductor If the corresponding NO VWx bit of the ICO VW register is set, the capture register or its holding register cannot be written by an e vent unless the y are empty (see Section 11.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 557 11.4.1.2 OC Channel Initialization Internal register whose output dri ves OCx when TIOS is set, can be force loaded with a desired data by writing to CFORC register before OCx is configured for output compare action.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 558 F reescale Semiconductor 11.4.1.6 Flag Clearing Mechanisms The flags in the ECT can be cleared one of two w ays: 1. Normal flag clearing mechanism (TFFCA = 0) Any of the ECT flags can be cleared by writing a one to the flag.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 559 11.4.3 Interrupts This section describes interrupts originated by the ECT block. The MCU must service the interrupt requests. T able 11-37 lists the interrupts generated by the ECT to communicate with the MCU.
Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 560 F reescale Semiconductor.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 561 Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) 12.1 Intr oduction The PWM definition is based on the HC12 PWM definitions.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 562 F reescale Semiconductor 12.1.3 Bloc k Diagram Figure 12-1 sho ws the block diagram for the 8-bit 8-channel PWM block. Figure 12-1. PWM Block Dia gram 12.2 External Signal Description The PWM module has a total of 8 external pins.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 563 12.2.3 PWM5 — PWM Channel 5 This pin serves as w av eform output of PWM channel 5. 12.2.4 PWM4 — PWM Channel 4 This pin serves as w av eform output of PWM channel 4.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 564 F reescale Semiconductor NO TE Register Address = Base Address + Address Of fset, where the Base Address is defined at the MCU le vel and the Address Of fset is defined at the module le vel.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 565 0x000B PWMSCNTB 1 R 00 0 00000 W 0x000C PWMCNT0 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 .
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 566 F reescale Semiconductor 12.3.2.1 PWM Enable Register (PWME) Each PWM channel has an enable bit (PWMEx) to start its wa veform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output is enabled immediately.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 567 An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the lo w order PWMEx bit.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 568 F reescale Semiconductor 12.3.2.2 PWM P olarity Register (PWMPOL) The starting polarity of each PWM channel wa veform is determined by the associated PPOLx bit in the PWMPOL register.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 569 Read: Anytime Write: Anytime NO TE Register bits PCLK0 to PCLK7 can be written an ytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 570 F reescale Semiconductor Read: Anytime Write: Anytime NO TE PCKB2–0 and PCKA2–0 register bits can be written an ytime. If the clock pre-scale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 571 12.3.2.5 PWM Center Align Enable Register (PWMCAE) The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned outputs for each PWM channel.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 572 F reescale Semiconductor 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 573 12.3.2.7 Reser ved Register (PWMTST) This register is reserv ed for factory testing of the PWM module and is not av ailable in normal modes.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 574 F reescale Semiconductor NO TE When PWMSCLA = $00, PWMSCLA v alue is considered a full scale value of 256. Clock A is thus di vided by 512. Any v alue written to this register will cause the scale counter to load the ne w scale value (PWMSCLA).
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 575 Read: Always read $00 in normal modes Write: Unimplemented in normal modes NO TE Writing to these registers when in special modes can alter the PWM functionality .
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 576 F reescale Semiconductor Write: Anytime (an y value written causes PWM counter to be reset to $00). 12.3.2.13 PWM Channel Period Register s (PWMPERx) There is a dedicated period register for each channel.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 577 12.3.2.14 PWM Channel Duty Registers (PWMDTYx) There is a dedicated duty register for each channel. The v alue in this register determines the duty of the associated PWM channel.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 578 F reescale Semiconductor Write: Anytime 12.3.2.15 PWM Shutdown Register (PWMSDN) The PWMSDN register pro vides for the shutdown functionality of the PWM module in the emer gency cases.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 579 12.4 Functional Description 12.4.1 PWM Cloc k Select There are four a vailable clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B).
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 580 F reescale Semiconductor Figure 12-18. PWM Clock Select Bloc k Diagram 128 2 4 8 16 32 64 PCKB2 PCKB1 PCKB0 M U X Clock A Clock B Clock SA Clock A/2, A/4, A/6,....
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 581 Clock A is used as an input to an 8-bit do wn counter. This do wn counter loads a user programmable scale v alue from the scale register (PWMSCLA).
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 582 F reescale Semiconductor 12.4.2 PWM Channel Timer s The main part of the PWM module are the actual timers. Each of the timer channels has a counter , a period register and a duty re gister (each are 8-bit).
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 583 On the front end of the PWM timer , the clock is enabled to the PWM circuit by the PWMEx bit being high. There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 584 F reescale Semiconductor Each channel counter can be read at anytime without af fecting the count or the operation of the PWM channel.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 585 NO TE Changing the PWM output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irre gularities in the PWM output.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 586 F reescale Semiconductor Figure 12-21. PWM Left Aligned Output Example W aveform 12.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 587 T o calculate the output frequenc y in center aligned output mode for a particular chan.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 588 F reescale Semiconductor As an example of a center aligned output, consider the follo wing case: Clock Source = E, where E = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10 MHz/8 = 1.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 589 Figure 12-24. PWM 16-Bit Mode Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the lo w order PWMEx bit.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 590 F reescale Semiconductor Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the lo w order CAEx bit. The high order CAEx bit has no ef fect.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 591 12.6 Interrupts The PWM module has only one interrupt which is generated at the time of emergenc y shutdown, if the corresponding enable bit (PWMIE) is set.
Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 592 F reescale Semiconductor.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 593 Chapter 13 Inter -Integrated Circuit (MC9S12XDP512) Bloc k Description 13.1 Intr oduction The inter-IC b us (IIC) is a two-wire, bidirectional serial bus that pro vides a simple, efficient method of data exchange between de vices.
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 594 F reescale Semiconductor 13.1.2 Modes of Operation The IIC functions the same in normal, special, and emulation modes. It has two lo w power modes: w ait and stop modes.
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 595 13.2 External Signal Description The MC9S12XDP512 module has two e xternal pins.
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 596 F reescale Semiconductor 13.3.2 Register Descriptions This section consists of register descriptions in address order . Each description includes a standard register diagram with an associated figure number .
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 597 13.3.2.2 IIC Frequency Divider Register (IBFD) Read and write anytime T able 13-2.
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 598 F reescale Semiconductor The number of clocks from the falling edge of SCL to the first t.
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 599 Figure 13-5. SCL Divider and SD A Hold The equation used to gener.
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 600 F reescale Semiconductor 11 56 9 22 29 12 64 13 26 33 13 72 13 30 37 14 80 17 34 41 15 88 .
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 601 3E 3072 513 1534 1537 3F 3840 513 1918 1921 MUL=2 40 40 14 12 22 .
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 602 F reescale Semiconductor 6A 896 130 444 450 6B 1024 130 508 514 6C 1152 194 572 578 6D 128.
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 603 96 416 84 184 212 97 512 84 232 260 98 320 36 152 164 99 384 36 1.
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 604 F reescale Semiconductor 13.3.2.3 IIC Control Register (IBCR) Read and write anytime Offset Module Base + 0x0002 76543210 R IBEN IBIE MS/SL Tx/Rx TXAK 00 IBSW AI W RST A Reset 00000000 = Unimplemented or Reser ved Figure 13-6.
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 605 W ait mode is entered via e xecution of a CPU W AI instruction. In the e vent that the IBSW AI bit is set, all clocks internal to the IIC will be stopped and any transmission currently in progress will halt.
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 606 F reescale Semiconductor 6 IAAS Addressed as a Slave Bit — When its own specific address (I-bus address register) is matched with the calling address, this bit is set.
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 607 13.3.2.5 IIC Data I/O Register (IBDR) In master transmit mode, when data is written to the IBDR a data transfer is initiated.
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 608 F reescale Semiconductor Figure 13-9. IIC-Bus T ransmission Signals 13.
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 609 13.4.1.2 Slave Address T ransmission The first byte of data transfer immediately after the ST AR T signal is the slave address transmitted by the master .
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 610 F reescale Semiconductor 13.4.1.5 Repeated ST ART Signal As sho wn in Figure 13-9 , a repeated ST AR T signal is a ST AR T signal generated without first generating a STOP signal to terminate the communication.
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 611 13.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer . Slav e devices may hold the SCL lo w after completion of one byte transfer (9 bits).
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 612 F reescale Semiconductor IIC Interrupt can be generated on 1. Arbitration lost condition (IB AL bit set) 2. Byte transfer condition (TCF bit set) 3.
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 613 13.7.1.3 P ost-T ransfer Software Response T ransmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte communication is finished.
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 614 F reescale Semiconductor 13.7.1.5 Generation of Repeated ST ART At the end of data transfe.
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 615 Figure 13-12. Flow-Chart of T ypical IIC Interrupt Routine Clear .
Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 616 F reescale Semiconductor.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 617 Chapter 14 Freescale’ s Scalable Contr oller Area Network (S12MSCANV3) 14.1 Intr oduction Freescale’ s scalable controller area net.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 618 F reescale Semiconductor 14.1.2 Bloc k Diagram Figure 14-1. MSCAN Block Dia gram 14.1.3 Features The basic features of the MSCAN are as follo ws: • Implementation of the CAN protocol — V ersion 2.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 619 • Three lo w-po wer modes: sleep, po wer do wn, and MSCAN enable • Global initialization of configuration registers 14.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 620 F reescale Semiconductor Figure 14-2. CAN System 14.3 Memory Map and Register Definition This section provides a detailed description of all re gisters accessible in the MSCAN.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 621 T able 14-1. MSCAN Memory Map Offset Address Register Access 0x0000 MSCAN Control Register 0 (CANCTL0) R/W 1 1 Ref er to detailed register description for write access restrictions on per bit basis.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 622 F reescale Semiconductor 14.3.2 Register Descriptions This section describes in detail all the registers and re gister bits in the MSCAN module.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 623 3 TIME Timer Enable — This bit activ ates an inter nal 16-bit wide free running timer which is clocked b y the bit clock r ate.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 624 F reescale Semiconductor 14.3.2.2 MSCAN Control Register 1 (CANCTL1) The CANCTL1 register pro vides various control bits and handshake status information of the MSCAN module as described belo w .
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 625 2 WUPM W ake-Up Mode — If WUPE in CANCTL0 is enabled, this bit defines whether the integrated lo w-pass filter is applied to protect the MSCAN from spurious wake-up (see Section 14.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 626 F reescale Semiconductor 14.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0) The CANBTR0 register configures v arious CAN bus timing parameters of the MSCAN module.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 627 14.3.2.4 MSCAN Bus Timing Register 1 (CANBTR1) The CANBTR1 register configures v arious CAN bus timing parameters of the MSCAN module.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 628 F reescale Semiconductor The bit time is determined by the oscillator frequency , the baud rate prescaler , and the number of time quanta (Tq) clock cycles per bit (as sho wn in T able 14-8 and T able 14-9 ).
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 629 T able 14-10. CANRFLG Register Field Descriptions Field Description 7 WUPIF W ake-Up Interrupt Flag — If the MSCAN detects CAN bus activity while in sleep mode (see Section 14.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 630 F reescale Semiconductor 14.3.2.6 MSCAN Receiver Interrupt Enable Register (CANRIER) This register contains the interrupt enable bits for the interrupt flags described in the CANRFLG re gister.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 631 14.3.2.7 MSCAN T ransmitter Flag Register (CANTFLG) The transmit buf fer empty flags each hav e an associated interrupt enable bit in the CANTIER register.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 632 F reescale Semiconductor 14.3.2.8 MSCAN T ransmitter Interrupt Enable Register (CANTIER) This register contains the interrupt enable bits for the transmit b uffer empty interrupt flags.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 633 14.3.2.9 MSCAN T ransmitter Message Abort Request Register (CANT ARQ) The CANT ARQ register allo ws abort request of queued messages as described below.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 634 F reescale Semiconductor 14.3.2.10 MSCAN T ransmitter Message Abor t Ac knowledge Regis.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 635 14.3.2.11 MSCAN T ransmit Buffer Selection Register (CANTBSEL) The CANTBSEL register allo ws the selection of the actual transmit message buf fer , which then will be accessible in the CANTXFG register space.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 636 F reescale Semiconductor 14.3.2.12 MSCAN Identifier Acceptance Control Register (CANID A C) The CANID A C register is used for identifier acceptance control as described belo w.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 637 The IDHITx indicators are always related to the message in the fore ground buf fer (RxFG). When a message gets shifted into the foreground b uffer of the recei ver FIFO the indicators are updated as well.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 638 F reescale Semiconductor 14.3.2.15 MSCAN Receive Error Counter (CANRXERR) This register reflects the status of the MSCAN recei ve error counter.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 639 14.3.2.16 MSCAN T ransmit Err or Counter (CANTXERR) This register reflects the status of the MSCAN transmit error counter.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 640 F reescale Semiconductor 14.3.2.17 MSCAN Identifier Acceptance Registers (CANID AR0-7) On reception, each message is written into the background recei ve b uffer.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 641 Read: Anytime Write: Anytime in initialization mode (INITRQ = .
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 642 F reescale Semiconductor 14.3.2.18 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 643 Read: Anytime Write: Anytime in initialization mode (INITRQ = .
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 644 F reescale Semiconductor 14.3.3 Pr ogrammer’ s Model of Message Storage The follo wing section details the organization of the recei ve and transmit message b uffers and the associated control registers.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 645 Read: For transmit b uffers, an ytime when TXEx flag is set (see Section 14.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 646 F reescale Semiconductor Write: For transmit b uffers, an ytime when TXEx flag is set (see Section 14.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 647 Module Base + 0x00X1 76543210 R ID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15 W Reset: xxxxxxxx Figure 14-26. Identifier Register 1 (IDR1) — Extended Identifier Mapping T able 14-27.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 648 F reescale Semiconductor 14.3.3.1.2 IDR0–IDR3 f or Standard Identifier Mapping Module Base + 0x00X3 76543210 R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR W Reset: xxxxxxxx Figure 14-28.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 649 Module Base + 0x00X1 76543210 R ID2 ID1 ID0 RTR IDE (=0) W Reset: xxxxxxxx = Unused; alwa ys read ‘x’ Figure 14-30.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 650 F reescale Semiconductor 14.3.3.2 Data Segment Registers (DSR0-7) The eight data segment re gisters, each with bits DB[7:0], contain the data to be transmitted or receiv ed.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 651 14.3.3.3 Data Length Register (DLR) This register k eeps the data length field of the CAN frame.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 652 F reescale Semiconductor In cases of more than one b uf fer having the same lo west priority , the message buf fer with the lower inde x number wins.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 653 Read: Anytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN T ransmitter Flag Register (CANTFLG) ”) and the corresponding transmit buf fer is selected in CANTBSEL (see Section 14.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 654 F reescale Semiconductor 14.4.2 Message Storage Figure 14-38. User Model for Messa ge Buffer Organization MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 655 14.4.2.1 Message T ransmit Bac kground Modern application laye.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 656 F reescale Semiconductor The MSCAN then schedules the message for transmission and signals the successful transmission of the buf fer by setting the associated TXE flag.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 657 field of the CAN frame, is recei ved into the ne xt av ailable RxBG. If the MSCAN recei ves an in valid message in its RxBG (wrong identifier , transmission errors, etc.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 658 F reescale Semiconductor • Four identifier acceptance filters, each to be applied to — a) the 14 most significant bits of the extended identifier plus the SRR and IDE bits of CAN 2.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 659 Figure 14-40.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 660 F reescale Semiconductor Figure 14-41.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 661 14.4.3.1 Protocol Violation Pr otection The MSCAN protects the user from accidentally violating the CAN protocol through programming errors.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 662 F reescale Semiconductor If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the f aster CAN bus rates.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 663 The synchronization jump width (see the Bosch CAN specification for details) can be programmed in a range of 1 to 4 time quanta by setting the SJW parameter.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 664 F reescale Semiconductor 14.4.5 Modes of Operation 14.4.5.1 Normal Modes The MSCAN module beha ves as described within this specification in all normal system operation modes.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 665 14.4.6.1 Operation in Run Mode As sho wn in T able 14-37 , only MSCAN sleep mode is a vailable as lo w power option when the CPU is in run mode.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 666 F reescale Semiconductor • If there are one or more message buf fers scheduled for tr.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 667 The MSCAN is able to lea ve sleep mode (wak e up) only when: .
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 668 F reescale Semiconductor 14.4.6.5 MSCAN Initialization Mode In initialization mode, any on-going transmission or reception is immediately aborted and synchronization to the CAN bus is lost, potentially causing CAN protocol violations.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 669 14.4.6.6 MSCAN P ower Down Mode The MSCAN is in po wer do wn m.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 670 F reescale Semiconductor 14.4.8.1 Description of Interrupt Operation The MSCAN supports four interrupt vectors (see T able 14-38 ), any of which can be indi vidually masked (for details see sections from Section 14.
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 671 Section 14.3.2.5, “MSCAN Receiv er Flag Register (CANRFLG) ” and Section 14.3.2.6, “MSCAN Recei ver Interrupt Enable Re gister (CANRIER) ”).
Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 672 F reescale Semiconductor 14.5.2 Bus-Off Reco very The bus-of f recov ery is user configurable. The b us-off state can either be left automatically or on user request.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 673 Chapter 15 Serial Comm unication Interface (S12MC9S12XDP512V5) 15.1 Intr oduction This block guide provides an o vervie w of the serial communication interface (SCI) module. The SCI allo ws asynchronous serial communications with peripheral de vices and other CPUs.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 674 F reescale Semiconductor • Hardware parity checking • 1/16 bit-time noise detection 15.1.2 Modes of Operation The SCI functions the same in normal, special, and emulation modes.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 675 15.2 External Signal Description The SCI module has a total of two e xternal pins. 15.2.1 TXD — T ransmit Pin The TXD pin transmits SCI (standard or infrared) data.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 676 F reescale Semiconductor 15.3.2 Register Descriptions This section consists of register descriptions in address order . Each description includes a standard register diagram with an associated figure number .
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 677 15.3.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) Read: Anytime, if AMAP = 0. If only SCIBDH is written to, a read will not return the correct data until SCIBDL is written to as well, follo wing a write to SCIBDH.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 678 F reescale Semiconductor 15.3.2.2 SCI Control Register 1 (SCICR1) Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0. NO TE This register is only visible in the memory map if AMAP = 0 (reset condition).
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 679 2 IL T Idle Line T ype Bit — IL T determines when the receiver star ts counting logic 1s as idle character bits. The counting begins either after the star t bit or after the stop bit.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 680 F reescale Semiconductor 15.3.2.3 SCI Alternative Status Register 1 (SCIASR1) Read: Anytime, if AM.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 681 15.3.2.4 SCI Alternative Control Register 1 (SCIA CR1) Read: Anytime, if .
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 682 F reescale Semiconductor 15.3.2.5 SCI Alternative Control Register 2 (SCIA CR2) Read: Anytime, if .
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 683 15.3.2.6 SCI Control Register 2 (SCICR2) Read: Anytime Write: Anytime Module Base + 0x0003 76543210 R TIE TCIE RIE ILIE TE RE RWU SBK W Reset 00000000 Figure 15-9.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 684 F reescale Semiconductor 15.3.2.7 SCI Status Register 1 (SCISR1) The SCISR1 and SCISR2 registers pro vides inputs to the MCU for generation of SCI interrupts.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 685 3 OR Overrun Flag — OR is set when software f ails to read the SCI data register before the receiv e shift register receives the ne xt frame.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 686 F reescale Semiconductor 15.3.2.8 SCI Status Register 2 (SCISR2) Read: Anytime Write: Anytime Module Base + 0x0005 76543210 R AMAP 00 TXPOL RXPOL BRK13 TXDIR RAF W Reset 00000000 = Unimplemented or Reser ved Figure 15-11.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 687 15.3.2.9 SCI Data Registers (SCIDRH, SCIDRL) Read: Anytime; reading acces.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 688 F reescale Semiconductor 15.4 Functional Description This section provides a complete functional description of the SCI block, detailing the operation of the design from the end user perspecti ve in a number of subsections.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 689 15.4.1 Infrared Interface Submodule This module provides the capability of transmitting narro w pulses to an IR LED and receiving narro w pulses and transforming them to serial bits, which are sent to the SCI.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 690 F reescale Semiconductor 15.4.3 Data Format The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data format where zeroes are represented by light pulses and ones remain lo w .
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 691 15.4.4 Baud Rate Generation A 13-bit modulus counter in the baud rate generator deri ves the baud rate for both the recei ver and the transmitter .
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 692 F reescale Semiconductor 15.4.5 T ransmitter Figure 15-16. T ransmitter Block Diagram 15.4.5.1 T ransmitter Character Length The SCI transmitter can accommodate either 8-bit or 9-bit data characters.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 693 The SCI also sets a flag, the transmit data register empty flag (TDRE), e very time it transfers data from the buf fer (SCIDRH/L) to the transmitter shift register .
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 694 F reescale Semiconductor When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 695 Figure 15-17 sho ws two cases of break detect. In trace RXD_1 the break symbol starts with the start bit, while in RXD_2 the break starts in the middle of a transmission.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 696 F reescale Semiconductor 15.4.5.5 LIN T ransmit Collision Detection This module allo ws to check for collisions on the LIN bus.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 697 15.4.6 Receiver Figure 15-20. SCI Receiver Block Dia gram 15.4.6.1 Receiver Character Length The SCI recei ver can accommodate either 8-bit or 9-bit data characters.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 698 F reescale Semiconductor indicating that the recei ved byte can be read. If the recei ve interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 699 T o determine the v alue of a data bit and to detect noise, recovery logic tak es samples at R T8, R T9, and R T10. T able 15-18 summarizes the results of the data bit samples.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 700 F reescale Semiconductor In Figure 15-22 the verification samples R T3 and R T5 determine that the first low detected w as noise and not the beginning of a start bit.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 701 In Figure 15-24 , a large b urst of noise is perceiv ed as the beginning of a start bit, although the test sample at R T5 is high.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 702 F reescale Semiconductor Figure 15-26 shows a b urst of noise near the beginning of the start bit that resets the R T clock. The sample after the reset is lo w but is not preceded by three high samples that w ould qualify as a falling edge.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 703 15.4.6.5 Baud Rate T olerance A transmitting de vice may be operating at a baud rate belo w or abov e the recei ver baud rate.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 704 F reescale Semiconductor 15.4.6.5.2 F ast Data T olerance Figure 15-29 sho ws ho w much a fast recei ved frame can be misaligned. The fast stop bit ends at R T10 instead of R T16 but is still sampled at R T8, R T9, and R T10.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 705 15.4.6.6.1 Idle Input line W akeup (W AKE = 0) In this wakeup method, an idle condition on the RXD pin clears the R WU bit and wakes up the SCI.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 706 F reescale Semiconductor Enable single-wire operation by setting the LOOPS bit and the receiv er source bit, RSRC, in SCI control register 1 (SCICR1).
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 707 15.5.2.2 W ait Mode SCI operation in wait mode depends on the state of the SCISW AI bit in the SCI control register 1 (SCICR1).
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 708 F reescale Semiconductor 15.5.3.1 Description of Interrupt Operation The SCI only originates interrupt requests. The follo wing is a description of ho w the SCI makes a request and ho w the MCU should ackno wledge that request.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 709 15.5.3.1.6 RXEDGIF Description The RXEDGIF interrupt is set when an acti ve edge (f alling if RXPOL = 0, rising if RXPOL = 1) on the RXD pin is detected.
Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 710 F reescale Semiconductor.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 711 Chapter 16 Serial P eripheral Interface (S12SPIV4) 16.1 Intr oduction The SPI module allo ws a duplex, synchronous, serial communication between the MCU and peripheral de vices. Software can poll the SPI status flags or the SPI operation can be interrupt dri ven.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 712 F reescale Semiconductor This is a high le vel description only , detailed descriptions of operating modes are contained in Section 16.4.7, “Low Po wer Mode Options” .
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 713 16.2 External Signal Description This section lists the name and description of all ports including inputs and outputs that do, or may , connect of f chip.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 714 F reescale Semiconductor 16.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard re gister diagram with an associated figure number.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 715 16.3.2.1 SPI Control Register 1 (SPICR1) Read: Anytime Write: Anytime Module Base +0x___0 76543210 R SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE W Reset 00000100 Figure 16-3.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 716 F reescale Semiconductor 16.3.2.2 SPI Control Register 2 (SPICR2) Read: Anytime Write: Anytime; writes to the reserv ed bits have no ef fect T able 16-3.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 717 16.3.2.3 SPI Baud Rate Register (SPIBR) Read: Anytime Write: Anytime; writes to the reserv ed bits have no ef fect The baud rate di visor equation is as follo ws: BaudRateDivisor = (SPPR + 1) • 2 (SPR + 1) Eqn.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 718 F reescale Semiconductor T able 16-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate 0 0 0 0 0 0 2 12.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 719 1 0 0 1 1 1 1280 19.53 kHz 1 0 1 0 0 0 12 2.08333 MHz 1 0 1 0 0 1 24 1.04167 MHz 1 0 1 0 1 0 48 520.83 kHz 1 0 1 0 1 1 96 260.42 kHz 1 0 1 1 0 0 192 130.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 720 F reescale Semiconductor 16.3.2.4 SPI Status Register (SPISR) Read: Anytime Write: Has no ef fect Module Base +0x___3 76543210 R SPIF 0 SPTEF MODF 0000 W Reset 00100000 = Unimplemented or Reser ved Figure 16-6.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 721 16.3.2.5 SPI Data Register (SPIDR) Read: Anytime; normally read only when SPIF is set Write: Anytime The SPI data register is both the input and output re gister for SPI data.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 722 F reescale Semiconductor Figure 16-8. Reception with SPIF Serviced in Time Figure 16-9.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 723 16.4 Functional Description The SPI module allo ws a duplex, synchronous, serial communication between the MCU and peripheral de vices. Software can poll the SPI status flags or SPI operation can be interrupt dri ven.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 724 F reescale Semiconductor 16.4.1 Master Mode The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI data re gister.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 725 16.4.2 Sla ve Mode The SPI operates in slav e mode when the MSTR bit in SPI control register 1 is clear. • SCK clock In slav e mode, SCK is the SPI clock input from the master.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 726 F reescale Semiconductor 16.4.3 T ransmission Formats During an SPI transmission, data is transmitted (shifted out serially) and recei ved (shifted in serially) simultaneously.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 727 Data reception is double buf fered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 728 F reescale Semiconductor In slav e mode, if the SS line is not deasserted between the successiv e transmissions then the content of the SPI data register is not transmitted; instead the last recei ved byte is transmitted.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 729 Figure 16-12. SPI Clock Format 1 (CPHA = 1) The SS line can remain acti ve lo w between successiv e transfers (can be tied low at all times).
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 730 F reescale Semiconductor 16.4.4 SPI Baud Rate Generation Baud rate generation consists of a series of di vider stages.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 731 16.4.5.2 Bidirectional Mode (MOMI or SISO) The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (see T able 16-9 ).
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 732 F reescale Semiconductor 16.4.6 Err or Conditions The SPI has one error condition: • Mode fault error 16.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 733 16.4.7.2 SPI in W ait Mode SPI operation in wait mode depends upon the state of the SPISW AI bit in SPI control register 2.
Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 734 F reescale Semiconductor 16.4.7.4 Reset The reset v alues of registers and signals are described in Section 16.3, “Memory Map and Register Definition” , which details the registers and their bit fields.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 735 Chapter 17 V oltage Regulator (S12VREG3V3V5) 17.1 Intr oduction Module VREG_3V3 is a dual output voltage re gulator that provides two separate 2.5V (typical) supplies dif fering in the amount of current that can be sourced.
Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 736 F reescale Semiconductor 17.1.3 Bloc k Diagram Figure 17-1 shows the function principle of VREG_3V3 by means of a block diagram. The regulator core REG consists of two parallel subblocks, REG1 and REG2, pro viding two independent output v oltages.
Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 737 17.2 External Signal Description Due to the nature of VREG_3V3 being a v oltage regulator pro viding the chip internal po wer supply voltages, most signals are po wer supply signals connected to pads.
Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 738 F reescale Semiconductor 17.2.4 VDDPLL, VSSPLL — Regulator Output2 (PLL) Pins Signals V DDPLL /V SSPLL are the secondary outputs of VREG_3V3 that provide the po wer supply for the PLL and oscillator.
Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 739 17.3.2 Register Descriptions This section describes all the VREG_3V3 registers and their indi vidual bits. 17.3.2.1 HT Control Register (VREGHTCL) The VREGHTCL is reserved for test purposes.
Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 740 F reescale Semiconductor 17.3.2.3 Autonomous P eriodical Interrupt Control Register (VREGAPICL) The VREGAPICL register allo ws the configuration of the VREG_3V3 autonomous periodical interrupt features.
Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 741 17.3.2.4 Autonomous P eriodical Interrupt T rimming Register (VREGAPITR) The VREGAPITR register allo ws to trim the API timeout period.
Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 742 F reescale Semiconductor 17.3.2.5 Autonomous P eriodical Interrupt Rate High and Low Register (VREGAPIRH / VREGAPIRL) The VREGAPIRH and VREGAPIRL register allo ws the configuration of the VREG_3V3 autonomous periodical interrupt rate.
Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 743 Y ou can calculate the selected period depending of APICLK as: Period = 2*(APIR[11:0] + 1) * 0.1 ms or period = 2*(APIR[11:0] + 1) * b us clock period T able 17-8.
Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 744 F reescale Semiconductor 17.3.2.6 Reserved_06 The Reserved_06 is reserv ed for test purposes. 17.3.2.7 Reserved_07 The Reserved_07 is reserv ed for test purposes. 17.
Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 745 17.4.2.2 Reduced P ower Mode In Reduced Po wer Mode, the gate of the output transistor is connected directly to a reference v oltage to reduce po wer consumption.
Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 746 F reescale Semiconductor The API T rimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency is desired. See T able 17-6 for the trimming ef fect of APITR.
Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 747 17.4.10.1 Low-V oltage Interrupt (L VI) In FPM, VREG_3V3 monitors the input v oltage V DD A . Whene ver V DD A drops belo w lev el V L VIA, the status bit L VDS is set to 1.
Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 748 F reescale Semiconductor.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 749 Chapter 18 P eriodic Interrupt Timer (S12PIT24B4CV1) 18.1 Intr oduction The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules or raise periodic interrupts.
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 750 F reescale Semiconductor 18.1.3 Bloc k Diagram Figure 18-1 sho ws a block diagram of the PIT . Figure 18-1. MC9S12XDP512 Block Dia gram 18.2 External Signal Description The PIT module has no external pins.
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 751 18.3 Memory Map and Register Definition This section provides a detailed description of address space and re gisters used by the PIT.
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 752 F reescale Semiconductor 18.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard re gister diagram with an associated figure number.
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 753 0x000D PITLD1 (Low) R PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W 0x000E PITCNT1 (Hig.
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 754 F reescale Semiconductor 18.3.2.1 PIT Control and For ce Load Micro Timer Register (PITCFLMT) Read: Anytime .
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 755 18.3.2.2 PIT Force Load Timer Register (PITFL T) Read: Anytime Write: Anytime; writes to the reserv ed bits have no ef fect 18.
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 756 F reescale Semiconductor 18.3.2.4 PIT Multiplex Register (PITMUX) Read: Anytime Write: Anytime; writes to the reserv ed bits have no ef fect 18.
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 757 18.3.2.6 PIT Time-Out Flag Register (PITTF) Read: Anytime Write: Anytime (write to clear); writes to the reserv ed bits have no ef fect 18.
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 758 F reescale Semiconductor T able 18-8. PITMTLD0–1 Field Descriptions Field Description 7:0 PMTLD[7:0] PIT Micro Timer Load Bits 7:0 — These bits set the 8-bit modulus do wn-counter load value of the micro timers.
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 759 18.3.2.8 PIT Load Register 0 to 3 (PITLD0–3) Read: Anytime Write: Anytime Module .
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 760 F reescale Semiconductor 18.3.2.9 PIT Count Register 0 to 3 (PITCNT0–3) Read: Anytime Write: Has no meanin.
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 761 18.4 Functional Description Figure 18-19 sho ws a detailed block diagram of the PIT module.
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 762 F reescale Semiconductor Whene ver a 16-bit timer counter and the connected 8-bit micro timer counter ha ve .
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 763 is set, an interrupt service is requested whene ver the corresponding time-out flag PTF in the PIT time-out flag (PITTF) register is set.
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 764 F reescale Semiconductor.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 765 Chapter 19 Bac kground Deb ug Module (S12XBDMV2) 19.1 Intr oduction This section describes the functionality of the background deb ug module (BDM) sub-block of the HCS12X core platform.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 766 F reescale Semiconductor • Software control of BDM operation during wait mode • Software selectable clocks • Global page access functionality • Enabled but not acti ve out of reset in emulation modes • CLKSW bit set out of reset in emulation mode.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 767 19.1.2.3 Low-P ower Modes The BDM can be used until all b us masters (e.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 768 F reescale Semiconductor 19.2 External Signal Description A single-wire interface pin called the background deb ug interface (BKGD) pin is used to communicate with the BDM system.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 769 19.3.2 Register Descriptions A summary of the registers associated with the BDM is sho wn in Figure 19-2 . Registers are accessed by host-dri ven communications to the BDM hardw are using READ_BD and WRITE_BD commands.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 770 F reescale Semiconductor 19.3.2.1 BDM Status Register (BDMSTS) Figure 19-3.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 771 6 BDMA CT BDM Active Status — This bit becomes set upon entering BDM. The standard BDM fir mware lookup table is then enabled and put into the memory map.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 772 F reescale Semiconductor 19.3.2.2 BDM CCR LO W Holding Register (BDMCCRL) Figure 19-4.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 773 19.3.2.3 BDM CCR HIGH Holding Register (BDMCCRH) Figure 19-5.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 774 F reescale Semiconductor 19.4 Functional Description The BDM recei ves and e xecutes commands from a host via a single wire serial interface. There are two types of BDM commands: hardware and firmw are commands.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 775 After being enabled, BDM is acti v ated by one of the follo wing 1 : • Hardware B A C.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 776 F reescale Semiconductor 19.4.4 Standar d BDM Firmware Commands Firmware commands are used to access and manipulate CPU resources. The system must be in acti ve BDM to ex ecute standard BDM firmware commands, see Section 19.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 777 T able 19-6. Firmware Commands Command 1 1 If enabled, A CK will occur when data is ready for transmission f or all BDM READ commands and will occur after the wr ite is complete f or all BDM WRITE commands.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 778 F reescale Semiconductor 19.4.5 BDM Command Structure Hardware and firmware BDM commands start with an 8-bit opcode follo wed by a 16-bit address and/or a 16-bit data word depending on the command.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 779 The external host should w ait at least for 76 bus clock c ycles after a TRA CE1 or GO command before starting any ne w serial command.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 780 F reescale Semiconductor 19.4.6 BDM Serial Interface The BDM communicates with external de vices serially via the BKGD pin. During reset, this pin is a mode select input which selects between normal and special modes of operation.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 781 Figure 19-8. BDM Host-to-T arget Serial Bit Timing The recei ve cases are more complicated. Figure 19-9 sho ws the host recei ving a logic 1 from the target system.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 782 F reescale Semiconductor Figure 19-10 sho ws the host recei ving a logic 0 from the target.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 783 compared to the serial communication rate. This protocol allo ws a great flexibility for the POD designers, since it does not rely on any accurate time measurement or short response time to an y ev ent in the serial communication.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 784 F reescale Semiconductor Dif ferently from the normal bit transfer (where the host initiates the transmission), the serial interface A CK handshake pulse is initiated by the tar get MCU by issuing a neg ativ e edge in the BKGD pin.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 785 GO_UNTIL command can not be aborted. Only the corresponding A CK pulse can be aborted by the SYNC command.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 786 F reescale Semiconductor Figure 19-14 sho ws a conflict between the A CK pulse and the SYNC request pulse. This conflict could occur if a POD de vice is connected to the target BKGD pin and the tar get is already in debug acti ve mode.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 787 The A CK_EN ABLE sends an A CK pulse when the command has been completed. This feature could be used by the host to e v aluate if the target supports the hardw are handshake protocol.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 788 F reescale Semiconductor within a fe w percent of the actual target speed and the communication protocol can easily tolerate speed errors of se veral percent.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 789 19.4.11 Serial Communication Time Out The host initiates a host-to-target serial transmission by generating a f alling edge on the BKGD pin.
Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 790 F reescale Semiconductor.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 791 Chapter 20 Deb ug (S12XDBGV2) 20.1 Intr oduction The DBG module provides an on-chip trace buf fer with flexible triggering capability to allo w non-intrusi ve debug of application softw are.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 792 F reescale Semiconductor 20.1.2 Features • Four comparators (A, B, C, and D): — Comparators A and C compare the full address an.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 793 XGA TE activity can still be compared, traced and can be used to generate a breakpoint to the XGA TE module. When the CPU enters acti ve BDM mode through a B ACKGR OUND command, with the DBG module armed, the DBG remains armed.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 794 F reescale Semiconductor . T able 20-2. External System Pins Associated With DBG Pin Name Pin Functions Description T AGHI (See DUG) T AGHI When instruction tagging is on, tags the high half of the instruction word being read into the instruction queue.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 795 20.3 Memory Map and Register Definition A summary of the registers associated with the DBG sub-block is sho wn in Figure 20-2 . Detailed descriptions of the registers and bits are gi ven in the subsections that follo w.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 796 F reescale Semiconductor 20.3.1.1 Debug Contr ol Register 1 (DBGC1) Read: Anytime Write: Bits 7,1,0 anytime, Bit 6 can be written an ytime but alw ays reads back as 0. Bits 5:2 anytime DBG is not armed.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 797 T able 20-3. DBGC1 Field Descriptions Field Description 7 ARM Arm Bit — The ARM bit controls whether the DBG module is armed.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 798 F reescale Semiconductor 20.3.1.2 Debug Status Register (DBGSR) Read: Anytime Write: Ne ver 01 Comparator B DBGSCR2 10 Comparator C.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 799 20.3.1.3 Debug T race Control Register (DBGTCR) Read: Anytime Write: Bits 7:6 only when DBG is neither secure nor armed. Bits 5:0 anytime the module is disarmed.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 800 F reescale Semiconductor 20.3.1.4 Debug Contr ol Register2 (DBGC2) Read: Anytime Write: Anytime the module is disarmed. This register configures the comparators for range matching. 11 T race only in range from comparator C to compar ator D T able 20-11.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 801 20.3.1.5 Debug T race Buffer Register (DBGTBH:DBGTBL) Read: Anytime when unlock ed and not secured and not armed. Write: Aligned word writes when disarmed unlock the trace b uffer for reading b ut do not af fect trace buf fer contents T able 20-14.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 802 F reescale Semiconductor 20.3.1.6 Debug Count Register (DBGCNT) Read: Anytime Write: Ne ver 0x0026 76543210 R 0 CNT W Reset 0 — — ————— P O R 00000000 Unimplemented or Reser ved Figure 20-9.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 803 20.3.1.7 Debug State Contr ol Registers Each of the state sequencer states 1 to 3 features a dedicated con.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 804 F reescale Semiconductor 20.3.1.9 Debug State Contr ol Register 2 (DBGSCR2) Read: Anytime Write: Anytime when DBG not armed. This register is visible at 0x0027 only with COMR V[1:0] = 01.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 805 20.3.1.10 Debug State Contr ol Register 3 (DBGSCR3) Read: Anytime Write: Anytime when DBG not armed. This register is visible at 0x0027 only with COMR V[1]=1.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 806 F reescale Semiconductor (DBGXCTL)” . Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 807 20.3.1.11.1 Debug Comparator Contr ol Register (DBGXCTL) The contents of this register bits 7 and 6 dif fe.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 808 F reescale Semiconductor T able 20-28 shows the ef fect for R WE and R W on the comparison conditions. These bits are not useful for tagged operations since the trigger occurs based on the tagged opcode reaching the ex ecution stage of the instruction queue.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 809 20.3.1.11.2 Debug Comparator Address High Register (DBGXAH) Read: Anytime Write: Anytime when DBG not armed. 20.3.1.11.3 Debug Comparator Address Mid Register (DBGXAM) Read: Anytime Write: Anytime when DBG not armed.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 810 F reescale Semiconductor 20.3.1.11.4 Debug Comparator Address Lo w Register (DBGXAL) Read: Anytime Write: Anytime when DBG not armed. 20.3.1.11.5 Debug Comparator Data High Register (DBGXDH) Read: Anytime Write: Anytime when DBG not armed.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 811 20.3.1.11.6 Debug Comparator Data Lo w Register (DBGXDL) Read: Anytime Write: Anytime when DBG not armed. 20.3.1.11.7 Debug Comparator Data High Mask Register (DBGXDHM) Read: Anytime Write: Anytime when DBG not armed.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 812 F reescale Semiconductor 20.3.1.11.8 Debug Comparator Data Lo w Mask Register (DBGXDLM) Read: Anytime Write: Anytime when DBG not armed. 20.4 Functional Description This section provides a complete functional description of the DBG module.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 813 Figure 20-22. DBG Overview 20.4.2 Comparator Modes The DBG contains 4 comparators, A, B, C, and D. Each comparator can be configured to monitor either CPU or XGA TE busses using the SRC bit in the corresponding comparator control register.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 814 F reescale Semiconductor If the T A G bit is clear (forced type trigger) a comparator match is generated when the selected address appears on the system address b us. If the selected address is an opcode address, the match is generated when the opcode is fetched from the memory .
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 815 20.4.2.2 Exact Address Comparator Match (Comparator s B and D) Comparators B and D feature SZ and SZE control bits. If SZE is clear , then the comparator address match qualification functions the same as for comparators A and C.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 816 F reescale Semiconductor 20.4.2.3.2 Outside Range (Address < CompA C_Addr or Address > CompBD_Ad dr) In the outside range comparator mode, either comparator pair A and B or comparator pair C and D can be configured for range comparisons.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 817 20.4.3.4 T rigger On XGA TE S/W Breakpoint Request The XGA TE S/W breakpoint request issues a forced breakpoint request to the CPU immediately independent of DBG settings.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 818 F reescale Semiconductor 20.4.4 State Sequence Contr ol Figure 20-23. State Sequencer Diagram The state sequence control allo ws a defined sequence of e vents to pro vide a trigger point for tracing of data in the trace buf fer.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 819 20.4.4.1 Final State On entering final state a trigger may be issued to the trace buf fer according to the trace position control as defined by the T ALIGN field (see Section 20.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 820 F reescale Semiconductor is continued for another 32 lines. Upon tracing completion the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary .
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 821 Loop1 mode only inhibits consecuti ve duplicate source address entries that w ould typically be stored in most tight looping constructs.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 822 F reescale Semiconductor information (R/W , S/D etc.). The numerical suffix indicates which tracing step.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 823 20.4.5.3.1 Inf ormation Byte Organization The format of the control information byte for both CPU and XGA TE modules is dependent upon the acti ve trace mode and tracing source as described belo w.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 824 F reescale Semiconductor This describes the format of the information byte used only when tracing from CPU or XGATE in detail mode. When tracing from the CPU in detail mode, information is stored to the trace buffer on all cycles except opcode fetch and free cycles.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 825 20.4.5.3.2 Reading Data fr om T race Buffer The data stored in the trace buf fer can be read using either .
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 826 F reescale Semiconductor 20.4.5.3.3 T race Buffer Reset State The trace buf fer contents are not initialized by a system reset. Thus should a system reset occur , the trace session information from immediately before the reset occurred can be read out.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 827 20.4.6.1 External T ag ging using T A GHI and T A GLO External tagging using the external T A GHI and T AGLO pins can only be used to tag CPU opcodes; tagging of XGA TE code using these pins is not possible.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 828 F reescale Semiconductor 20.4.7.2 Breakpoints From Internal Comparator Channel Final State T riggers Breakpoints can be generated when internal comparator channels trigger the state sequencer to the final state.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 829 20.4.7.5 DBG Breakpoint Priorities XGA TE software breakpoints hav e the highest priority .
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 830 F reescale Semiconductor When program control returns from a tagged breakpoint using an R TI or BDM GO command without program counter modification it will return to the instruction whose tag generated the breakpoint.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 831.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 832 F reescale Semiconductor.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 833.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 834 F reescale Semiconductor.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 835.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 836 F reescale Semiconductor.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 837.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 838 F reescale Semiconductor.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 839.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 840 F reescale Semiconductor.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 841.
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 842 F reescale Semiconductor.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor PRELIMINAR Y 843 NON-DISCLOSURE A GREEMENT REQUIRED Chapter 21 Interrupt (S12MC9S12XDP512V1) 21.1 Intr oduction The XINT module decodes the priority of all system exception requests and pro vides the applicable vector for processing the exception to either the CPU or the XGA TE module.
Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 844 PRELIMINAR Y F reescale Semiconductor NON-DISCLOSURE A GREEMENT REQUIRED 21.
Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor PRELIMINAR Y 845 NON-DISCLOSURE A GREEMENT REQUIRED • W ait mode In wait mode, the XINT module is frozen. It is ho wev er capable of either waking up the CPU if an interrupt occurs or waking up the XGA TE if an XGA TE request occurs.
Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 846 PRELIMINAR Y F reescale Semiconductor NON-DISCLOSURE A GREEMENT REQUIRED 21.
Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor PRELIMINAR Y 847 NON-DISCLOSURE A GREEMENT REQUIRED 21.
Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 848 PRELIMINAR Y F reescale Semiconductor NON-DISCLOSURE A GREEMENT REQUIRED 21.3.1 Register Descriptions This section describes in address order all the XINT registers and their indi vidual bits.
Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor PRELIMINAR Y 849 NON-DISCLOSURE A GREEMENT REQUIRED 21.3.1.1 Interrupt V ector Base Register (IVBR) Read: Anytime Write: Anytime Address: 0x0121 76543210 R IVB_ADDR[7:0] W Reset 11111111 Figure 21-3.
Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 850 PRELIMINAR Y F reescale Semiconductor NON-DISCLOSURE A GREEMENT REQUIRED 21.
Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor PRELIMINAR Y 851 NON-DISCLOSURE A GREEMENT REQUIRED 21.
Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 852 PRELIMINAR Y F reescale Semiconductor NON-DISCLOSURE A GREEMENT REQUIRED 21.
Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor PRELIMINAR Y 853 NON-DISCLOSURE A GREEMENT REQUIRED Read: Anytime Write: Anytime Address: 0x012C 76543210 R RQST 0000 PRIOL VL[2:0] W Reset 0000000 1 1 1 Please refer to the notes following the PRIOLVL[2:0] description below.
Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 854 PRELIMINAR Y F reescale Semiconductor NON-DISCLOSURE A GREEMENT REQUIRED T able 21-6.
Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor PRELIMINAR Y 855 NON-DISCLOSURE A GREEMENT REQUIRED 21.4 Functional Description The XINT module processes all exception requests to be serviced by the CPU module.
Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 856 PRELIMINAR Y F reescale Semiconductor NON-DISCLOSURE A GREEMENT REQUIRED 21.4.2.1 Interrupt Priority Stack The current interrupt processing le vel (IPL) is stored in the condition code re gister (CCR) of the CPU.
Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor PRELIMINAR Y 857 NON-DISCLOSURE A GREEMENT REQUIRED If the interrupt source is unkno wn (for examp.
Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 858 PRELIMINAR Y F reescale Semiconductor NON-DISCLOSURE A GREEMENT REQUIRED 21.
Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor PRELIMINAR Y 859 NON-DISCLOSURE A GREEMENT REQUIRED Figure 21-14.
Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 860 PRELIMINAR Y F reescale Semiconductor NON-DISCLOSURE A GREEMENT REQUIRED.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 861 Chapter 22 External Bus Interface (S12XEBIV2) 22.1 Intr oduction This document describes the functionality of the MC9S12XDP512 block controlling the external b us interface. The MC9S12XDP512 controls the functionality of a non-multiplex ed external b us (a.
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 862 F reescale Semiconductor 22.1.3 Bloc k Diagram Figure 22-1 is a block diagram of the MC9S12XDP512 with all related I/O signals. Figure 22-1. MC9S12XDP512 Block Dia gram 22.
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 863 T able 22-1. External System Signals Associated with MC9S12XDP512 Signal I 1 /O 1 All inp.
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 864 F reescale Semiconductor 22.3 Memory Map and Register Definition This section provides a detailed description of all re gisters accessible in the MC9S12XDP512 . 22.
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 865 22.3.2.1 External Bus Interface Control Register 0 (EBICTL0) Read: Anytime. In emulation modes, read operations will return the data from the e xternal bus, in all other modes, the data are read from this register.
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 866 F reescale Semiconductor T able 22-3. Input Threshold Levels on External Signals ITHRS External Signal NS SS NX ES.
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 867 22.3.2.2 External Bus Interface Control Register 1 (EBICTL1) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register.
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 868 F reescale Semiconductor 22.4 Functional Description This section describes the functions of the external bus interface.
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 869 22.4.2 Internal Visibility Internal visibility allows the observation of the internal MCU address and data bus as well as the determination of the access source and the CPU pipe (queue) status through the external bus interface.
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 870 F reescale Semiconductor The following terminology is used: ‘addr’ — v alue(ADDRx); small letters denote the.
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 871 22.4.2.2.2 Write Access Timing T able 22-12. Write Access (1 Cycle) Access #0 Access #1 Access #2 Bus cycle -> ... 123 ... ECLK phase ...
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 872 F reescale Semiconductor 22.4.2.2.3 Read-Write-Read Access Timing 22.
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 873 Stretched accesses are controlled by: 1. EXSTR[2:0] bits in the EBICTL1 register configuring fix ed amount of stretch cycles 2. Acti v ation of the external w ait feature by EW AITE in EBICTL1 register 3.
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 874 F reescale Semiconductor 22.4.5.2 Emulation Modes and Special T est Mode In emulation modes and special test mode, the external signals LSTRB, R/W , and ADDR0 indicate the access type (read/write), data size and alignment of an external b us access.
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 875 22.4.6 Lo w-P ower Options The MC9S12XDP512 does not support any user-controlled options for reducing power consumption. 22.4.6.1 Run Mode The MC9S12XDP512 does not support any options for reducing power in run mode.
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 876 F reescale Semiconductor 22.5.1 Normal Expanded Mode This mode allows interfacing to external memories or peripherals which are available in the commercial market.
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 877 22.5.2 Em ulation Modes In emulation mode applications, the development systems use a custom PRU device to rebuild the single-chip or expanded bus functions which are lost due to the use of the external bus with an emulator.
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 878 F reescale Semiconductor 22.5.2.1 Example 2a: Emulation Single-Chip Mode This mode is used for emulation systems in which the target application is operating in normal single-chip mode.
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 879 22.5.2.2 Example 2b: Emulation Expanded Mode This mode is used for emulation systems in which the target application is operating in normal expanded mode.
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 880 F reescale Semiconductor.
MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 881 Chapter 23 Memory Mapping Control (S12XMMCV2) 23.1 Intr oduction This section describes the functionality of the module mapping control (MMC) sub-block of the S12X platform. The block diagram of the MMC is sho wn in Figure 1-1 .
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 882 F reescale Semiconductor • W ait mode MMC is functional during wait mode. • Stop mode MMC is inacti ve during stop mode. 23.1.2.2 Functional Modes • Single chip modes In normal and special single chip mode the internal memory is used.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 883 T able 1-2 and T able 1-3 outline the pin names and functions.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 884 F reescale Semiconductor 23.3 Memory Map and Registers 23.3.1 Module Memory Map A summary of the registers associated with the MMC block is sho wn in Figure 1-2 . Detailed descriptions of the registers and bits are gi ven in the subsections that follo w .
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 885 23.3.2 Register Descriptions 23.3.2.1 MMC Control Register (MMCCTL0) Read: Anytime. In emulation modes read operations will return the data from the e xternal bus.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 886 F reescale Semiconductor The MMCCTL0 register is used to control e xternal bus functions, i.e., a v ailability of chip selects. CA UTION XGA TE write access to this register during an CPU access which makes use of this register could lead to une xpected results.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 887 23.3.2.2 Mode Register (MODE) Read: Anytime. In emulation modes read operations will return the data read from the e xternal bus. In all other modes the data are read from this register .
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 888 F reescale Semiconductor Figure 23-5. Mode T ransition Diagram when MCU is Unsecured Normal Single-Chip 100 Normal.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 889 23.3.2.3 Global Pa g e Index Register (GP A GE) Read: Anytime Write: Anytime The global p.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 890 F reescale Semiconductor 23.3.2.4 Direct Pa g e Register (DIRECT) Read: Anytime Write: anytime in special modes, one time only in other modes. This register determines the position of the direct page within the memory map.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 891 23.3.2.5 MMC Control Register (MMCCTL1) Read: Anytime. In emulation modes read operations will return the data from the e xternal bus. In all other modes the data are read from this register .
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 892 F reescale Semiconductor 23.3.2.6 RAM Pa g e Index Register (RP A GE) Read: Anytime Write: Anytime The RAM page in.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 893 Figure 23-12. RP A GE Address Mapping NO TE Because RAM page 0 has the same global address as the register space, it is possible to write to registers through the RAM space when RP AGE = $00.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 894 F reescale Semiconductor 23.3.2.7 EEPROM P age Index Register (EP A GE) Read: Anytime Write: Anytime The EEPR OM p.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 895 23.3.2.8 Program P age Index Register (PP A GE) Read: Anytime Write: Anytime The program .
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 896 F reescale Semiconductor The fixed 16K page from $4000–$7FFF (when R OMHM = 0) is the page number $FD. The reset v alue of $FE ensures that there is linear Flash space av ailable between addresses $4000 and $FFFF out of reset.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 897 23.3.2.10 RAM XGA TE Upper Boundary Register (RAMXGU) Read: Anytime Write: Anytime when R WPE = 0 23.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 898 F reescale Semiconductor 23.3.2.12 RAM Shared Region Upper Boundar y Register (RAMSHU) Read: Anytime Write: Anytime when R WPE = 0 23.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 899 • Normal expanded mode The external b us interface is configured as an up to 23-bit address bus, 8 or 16-bit data b us with dedicated bus control and status signals.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 900 F reescale Semiconductor Figure 23-21. Expansion of the Local Address Map $7F_FFFF $00_0000 $7F_C000 $14_0000 $13_.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 901 23.4.2.1.1 Expansion of the Local Address Map Expansion of the CPU Local Address Map The .
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 902 F reescale Semiconductor Expansion of the BDM Local Address Map PP A GE, RP A GE, and EP A GE registers are also used for the e xpansion of the BDM local address to the global address.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 903 Figure 23-22. BDMGPR Address Mapping 23.4.2.3 Implemented Memor y Map The global memory spaces reserved for the internal resources (RAM, EEPR OM, and FLASH) are not determined by the MMC module.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 904 F reescale Semiconductor When the de vice is operating in expanded modes e xcept emulation single-chip mode, acces.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 905 Figure 23-23. Local to Implemented Global Address Mapping (Without GP A GE) $7F_FFFF $00_.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 906 F reescale Semiconductor 23.4.2.4 XGA TE Memor y Map Scheme 23.4.2.4.1 Expansion of the XGA TE Local Address Map The XGA TE 64 Kbyte memory space allows access to internal resources only (Re gisters, RAM, and FLASH).
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 907 Figure 23-24. Local to Global Address Mapping (XGA TE) $7F_FFFF $00_0000 $0F_FFFF $FFFF $.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 908 F reescale Semiconductor 23.4.3 Chip Access Restrictions 23.4.3.1 Illegal XGA TE Accesses A possible access error .
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 909 The follo wing conditions must be satisfied to ensure correct operation of the RAM protection mechanism: • V alue stored in RAMXGU must be lower than the v alue stored in RAMSHL.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 910 F reescale Semiconductor 23.4.4 Chip Bus Contr ol The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM and XGA TE) with the rest of the system (master buses).
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 911 23.4.4.2 Access Conflicts on T arget Buses The arbitration scheme allo ws only one master to be connected to a target at an y giv en time.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 912 F reescale Semiconductor This sequence is uninterruptable. There is no need to inhibit interrupts during the CALL instruction ex ecution. A CALL instruction can be performed from any address to any other address in the local CPU memory space.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 913 Due to internal visibility of CPU accesses the CPU will be halted during XGA TE or BDM access to any PRR. This rule applies also in normal modes to ensure that operation of the de vice is the same as in emulation modes.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 914 F reescale Semiconductor 23.5.3 On-Chip R OM Contr ol The MCU of fers two modes to support emulation. In the first mode (called generator) the emulator provides the data instead of the internal FLASH and traces the CPU actions.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 915 23.5.3.3 ROM Contr ol in Normal Expanded Mode In normal expanded mode the e xternal b us will be connected to the application. If the R OMON bit is set, the internal FLASH provides the data.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 916 F reescale Semiconductor 23.5.3.4 ROM Contr ol in Emulation Expanded Mode In emulation expanded mode the e xternal bus will be connected to the emulator and to the application.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 917 Figure 23-31. ROMON = 0 in Em ulation Expanded Mode 23.5.3.5 ROM Contr ol in Special T est Mode In special test mode the external b us is connected to the application.
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 918 F reescale Semiconductor.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 919 Appendix A Electrical Characteristics A.1 General NO TE The electrical characteristics gi ven in this section should be used as a guide only . V alues cannot be guaranteed by Freescale and are subject to change without notice.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 920 F reescale Semiconductor V SS1 and V SS2 are internally connected by metal. V DD A , V DDX , V DDR as well as V SSA , V SSX , V SSR are connected by anti-parallel diodes for ESD protection.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 921 the injection current may flo w out of V DD35 and could result in external po wer supply going out of regulation. Ensure e xternal V DD35 load will shunt current greater than maximum injection current.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 922 F reescale Semiconductor A.1.6 ESD Protection and Latch-up Imm unity All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automoti ve grade integrated circuits.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 923 A.1.7 Operating Conditions This section describes the operating conditions of the de vice. Unless otherwise noted those conditions apply to all the follo wing data.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 924 F reescale Semiconductor A.1.8 P ower Dissipation and Thermal Characteristics Po wer dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 925 T able A-5. Thermal P ackage Characteristics 1 1 The values f or ther mal resistance are achiev e.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 926 F reescale Semiconductor A.1.9 I/O Characteristics This section describes the characteristics of all I/O pins except EXT AL, XT AL,XFC,TEST and supply pins. T able A-6. 3.3-V I/O Characteristics Conditions are 3.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 927 T able A-7. 5-V I/O Characteristics Conditions are 4.5 V < V DD35 < 5.5 V temperature from –40 ° C to +140 ° C , unless otherwise noted I/O Characteristics for all I/O pins e xcept EXT AL, XT AL,XFC,TEST and supply pins .
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 928 F reescale Semiconductor A.1.10 Supply Currents This section describes the current consumption characteristics of the de vice as well as the conditions for the measurements.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 929 T able A-9. shows the configuration of the peripherals for run current measurement.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 930 F reescale Semiconductor A.1.10.2 Additional Remarks In expanded modes the currents flo wing in the system are highly dependent on the load at the address, data, and control signals as well as on the duty cycle of those signals.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 931 T able A-11. Pseudo Stop and Full Stop Current Conditions are shown in T able A-4 unless otherwis.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 932 F reescale Semiconductor A.2 A TD Characteristics This section describes the characteristics of the analog-to-digital con verter. A.2.1 A TD Operating Characteristics The T able A-12 and T able A-13 sho w conditions under which the A TD operates.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 933 T able A-13. A TD Operating Characteristics 3.3V A.2.2 Factor s Influencing Accuracy Three factors — source resistance, source capacitance and current injection — ha ve an influence on the accuracy of the A TD.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 934 F reescale Semiconductor A.2.2.3 Current Injection There are two cases to consider .
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 935 A.2.3 A TD Accuracy A.2.3.1 5-V Range T able A-15 specifies the A TD con version performance excluding an y errors due to current injection, input capacitance, and source resistance.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 936 F reescale Semiconductor A.2.3.3 A TD Accuracy Definitions For the follo wing definitions see also Figure A-1 . Dif ferential non-linearity (DNL) is defined as the dif ference between two adjacent switching steps.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 937 Figure A-1. A TD Accuracy Definitions NO TE Figure A-1 sho ws only definitions, for specification v alues refer to T able A-15 .
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 938 F reescale Semiconductor A.3 NVM, Flash, and EEPROM NO TE Unless otherwise noted the abbre viation NVM (non volatile memory) is used for both Flash and EEPR OM. A.3.1 NVM Timing The time base for all NVM program or erase operations is deri ved from the oscillator .
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 939 A.3.1.3 Sector Erase Erasing a 1024-byte Flash sector or a 4-byte EEPR OM sector takes: The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes: The setup time can be ignored for this operation.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 940 F reescale Semiconductor T able A-17. NVM Timing Characteristics Conditions are shown in T able A-4 unless otherwise noted Num C Rating Symbol Min T yp Max Unit 1 D Exter nal oscillator clock f NVMOSC 0.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 941 A.3.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life f ailures.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 942 F reescale Semiconductor Figure A-2. T ypical Endurance vs T emperature T ypical Endurance [10 3 Cycles] Operating T emper.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 943 A.4 V oltage Regulator T able A-19. V oltage Regulator Electrical Characteristics Num C Characteristic Symbol Min T yp Max Unit 1 P Input voltages V VDDR,A 3.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 944 F reescale Semiconductor A.5 Reset, Oscillator , and PLL This section summarizes the electrical characteristics of the v arious startup scenarios for oscillator and phase-locked loop (PLL).
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 945 If the MCU is woken-up by an interrupt and the f ast wake-up feature is enabled (FSTWKP = 1 and SCME = 1), the system will resume operation in self-clock mode after t fws .
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 946 F reescale Semiconductor T able A-21. Oscillator Characteristics Conditions are shown in T able A-4 unless otherwise noted Num C Rating Symbol Min T yp Max Unit 1a C Cr ystal oscillator range (loop controlled Pierce) f OSC 4.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 947 A.5.3 Phase Locked Loop The oscillator provides the reference clock for the PLL. The PLL´s v oltage controlled oscillator (VCO) is also the system clock source in self clock mode.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 948 F reescale Semiconductor And finally the frequency relationship is defined as W ith the abov e values the resistance can be calculated.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 949 The relati ve de viation of t nom is at its maximum for one clock period, and decreases tow ards zero for larger number of clock periods (N).
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 950 F reescale Semiconductor A.6 MSCAN A.7 SPI Timing This section provides electrical parametrics and ratings for the SPI. In T able A-24 the measurement conditions are listed.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 951 A.7.1 Master Mode In Figure A-6 the timing diagram for master mode with transmission format CPHA = 0 is depicted.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 952 F reescale Semiconductor In T able A-25 the timing characteristics for master mode are listed. A.7.2 Slave Mode In Figure A-8 the timing diagram for sla ve mode with transmission format CPHA = 0 is depicted.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 953 In Figure A-9 the timing diagram for sla ve mode with transmission format CPHA = 1 is depicted. Figure A-9. SPI Slave Timing (CPHA = 1) In T able A-26 the timing characteristics for sla ve mode are listed.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 954 F reescale Semiconductor A.8 External Bus Timing The follo wing conditions are assumed for all follo wing external b us timing values: • Crystal input within 45% to 55% duty • Equal loads of pins • Pad full dri ve (reduced dri ve must be of f) A.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 955 T able A-27. Example 1a: Normal Expanded Mode Timing V DD35 = 5.0 V (EW AITE = 0) No. C Characteristic Symbol Min Max Unit — — F requency of inter nal bus f i D .
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 956 F reescale Semiconductor A.8.2 Normal Expanded Mode (External W ait Feature Enabled) Figure A-11.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 957 Figure A-12. Example 1b: Normal Expanded Mode — Stretched Write Access CSx ADDRx RE D A T Ax (W.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 958 F reescale Semiconductor T able A-28. Example 1b: Normal Expanded Mode Timing V DD35 = 5.0 V (EW AITE = 1) No. C Characteristic Symbol 2 Stretch Cycles 3 Stretch Cycles Unit Min Max Min Max — — F requency of internal bus f i D .
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 959 A.8.3 Emulation Single-Chip Mode (Without W ait States) Figure A-13.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 960 F reescale Semiconductor T able A-29. Example 2a: Emulation Single-Chip Mode Timing V DD35 = 5.0 V (EW AITE = 0) No. C Characteristic 1 1 T ypical supply and silicon, room temperature only Symbol Min Max Unit — — Frequency of internal bus f i D .
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 961 A.8.4 Emulation Expanded Mode (With Optional Access Stretching) Figure A-14.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 962 F reescale Semiconductor Figure A-15. Example 2b: Emulation Expanded Mode Ò Write with 1 Stretc h Cycle ECLK R/ W D A T A.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 963 T able A-30. Example 2b: Emulation Expanded Mode Timing V DD35 = 5.
Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 964 F reescale Semiconductor A.8.5 External T ag T rigger Timing Figure A-16.
Appendix B Pac kage Information MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 965 Appendix B P ac kage Inf ormation B.1 General This section provides the ph ysical dimensions of the MC9S12XDP512 packages.
Appendix B Pac kage Information MC9S12XDP512 Data Sheet, Rev . 2.11 966 F reescale Semiconductor B.2 144-Pin LQFP Figure B-1. 144-Pin LQFP Mechanical Dimensions (Case No. 918-03) N 0.20 T L-M 144 GA GE PLANE 73 109 37 SEA TING 108 1 36 72 PLANE 4X 4X 36 TIPS PIN 1 IDENT VIEW Y B B1 V1 A1 S1 V P G A S 0.
Appendix B Pac kage Information MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 967 B.3 112-Pin LQFP P ackage Figure B-2. 112-Pin LQFP Mechanical Dimensions (Case No. 987) DIM A MIN MAX 20.000 BSC MILLIMETERS A1 10.000 BSC B 20.000 BSC B1 10.
Appendix B Pac kage Information MC9S12XDP512 Data Sheet, Rev . 2.11 968 F reescale Semiconductor B.4 80-Pin QFP P ackage Figure B-3. 80-Pin QFP Mechanical Dimensions (Case No. 841B) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER.
Appendix C Recommended PCB Lay out MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 969 Appendix C Recommended PCB La yout The PCB must be carefully laid out to ensure proper operation of the v oltage regulator as well as of the MCU itself.
Appendix C Recommended PCB Lay out MC9S12XDP512 Data Sheet, Rev . 2.11 970 F reescale Semiconductor T able C-1. Recommended Decoupling Capacitor Choice Component Purpose T ype V alue C1 V DD1 filter .
Appendix C Recommended PCB Lay out MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 971 Figure C-1. 144-Pin LQFP Recommended PCB Lay out C5 C4 C10 C9 R1 V DDR 1 V SSR1 V DDPLL V SSPLL C7 C.
Appendix C Recommended PCB Lay out MC9S12XDP512 Data Sheet, Rev . 2.11 972 F reescale Semiconductor Figure C-2. 112-Pin LQFP Recommended PCB Lay out C5 C4 C1 C6 C3 C2 C10 C9 R1 V DDX V SSX V DDR V SSR.
Appendix C Recommended PCB Lay out MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 973 Figure C-3. 80-Pin QFP Recommended PCB Lay out C5 C4 C3 C2 C10 C9 R1 C6 C1 V DD1 V SS1 V SS2 V DD2 V.
Appendix D Derivative Differences MC9S12XDP512 Data Sheet, Rev . 2.11 974 F reescale Semiconductor Appendix D Deriv ative Differences D .1 Memor y Sizes and P ac kage Options S12XD - F amily Device Pa.
Appendix D Derivative Differences MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 975 9S12XD128 1 112 LQFP 128K 8K 2K 80 QFP 9S12XD64 1 80 QFP 64K 4K 1K 1 P ar t includes module versions S12XDBGV3 and S12XMMCV3 which arenot co vered in this data sheet.
Appendix D Derivative Differences MC9S12XDP512 Data Sheet, Rev . 2.11 976 F reescale Semiconductor D .2 Memor y Sizes and P ac kage Options S12XA - F amily Device Package Flash RAM EEPROM 9S12XA512 144 LQFP 512K 32K 4K 112 LQFP 80 QFP 9S12XA256 1 1 P ar t includes module versions S12XDBGV3 and S12XMMCV3 which are not cov ered in this data sheet.
Appendix D Derivative Differences MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 977 D .3 MC9S12XD-Famil y Flash Configuration 12345 1. XGA TE read access to Flash not possible on DG128/D128 and D64 2. Program P ages av ailable on DT384 are $E0 - $E7 and $F0 - $FF 3.
Appendix D Derivative Differences MC9S12XDP512 Data Sheet, Rev . 2.11 978 F reescale Semiconductor D .4 P eripheral Sets S12XD - Famil y Device Package XGATE CAN SCI SPI IIC ECT PIT A/D I/O 9S12XDP512.
Appendix D Derivative Differences MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 979 D .5 P eripheral Sets S12XA - Famil y 2 ATD1 routed to PAD00-15 instead of PAD08-23.
Appendix D Derivative Differences MC9S12XDP512 Data Sheet, Rev . 2.11 980 F reescale Semiconductor D .6 Pinout explanations: • A/D is the number of modules/total number of A/D channels. • I/O is the sum of ports capable to act as digital input or output.
Appendix E Ordering Inf ormation MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 981 Appendix E Or dering Information The follo wing figure provides an ordering number e xample for the MC9S12XD-Family de vices Figure E-1.
Appendix E Ordering Inf ormation MC9S12XDP512 Data Sheet, Rev . 2.11 982 F reescale Semiconductor.
Appendix E Ordering Inf ormation MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 983 T able E-1. MC and SC P ar t Numbers MC P ART NUMBER (MASKSET -INDEPENDENT) FOR OUR RECOMMENDED MASKSE.
Appendix E Ordering Inf ormation MC9S12XDP512 Data Sheet, Rev . 2.11 984 F reescale Semiconductor MC9S12XDT512VFV SC104024VFV 144 MC9S12XDT384CFV SC104025CFV 144 MC9S12XDT384MFV SC104025MFV 144 MC9S12XDT384VFV SC104025VFV 144 MC9S12XD384CFV SC104026CFV 144 MC9S12XD384MFV SC104026MFV 144 MC9S12XD384VFV SC104026VFV 144 T able E-1.
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