Freescale SemiconductorメーカーMPC860Tの使用説明書/サービス説明書
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PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE MPC860T AD/D Re v . 0.8, 09/1999 ª MPC860T (Re v . D) F ast Ethernet Contr oller Supplement to the MPC860 P ow erQUICC™ User’ s Manual Fr eescale S emiconduct or , I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.
© Motorola Inc. 1999. All rights reserved. DigitalDNA and Mfax are trademarks of Motorola, Inc. The PowerPC name, the PowerPC logotype, and PowerPC 603e are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation.
MOTOROLA Contents iii PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE CONTENTS P aragraph Number Title Pag e Number Chapter 1 Overview 1.1 Document Revision History ................................................................................. 1-1 1.
iv MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE CONTENTS P aragraph Number Title Pag e Number Chapter 4 Parallel I/O Ports 4.1 Port D Pin Functions.........................................
MOTOROLA Contents v PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE CONTENTS P aragraph Number Title Pag e Number 6.3.1 Hardware Initialization................................................................................... 6-22 6.3.2 User Initialization (before Setting ECNTRL[ETHER_EN]) .
vi MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE CONTENTS P aragraph Number Title Pag e Number Fr eescale S emiconduct or , I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.
MOTOROLA Illustrations vii PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE ILLUSTRATIONS Figure Number Title Pag e Number 1-1 MPC860T Block Diagram .................................................................................. 1-4 1-2 MPC860T Interrupt Structure .
viii MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE ILLUSTRATIONS Figure Number Title Pag e Number Fr eescale S emiconduct or , I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.
MOTOROLA T ables ix PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE TABLES Ta b l e Number Title Pag e Number 1-1 Document Revision History ................................................................................ 1-1 2-1 FEC Signal Descriptions .
x MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE TABLES Ta b l e Number Title Pag e Number 6-27 Receive Buffer Descriptor (RxBD) Field Description...................................... 6-25 6-29 Transmit Buffer Descriptor (TxBD) Field Descriptions .
MOTOROLA Chapter 1. Overview 1-1 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE Chapter 1 Overview 10 10 This chapter provides an o vervie w of Rev . D of the MPC860T, focussing primarily on the Fast Ethernet controller (FEC). It pro vides a discussion of its basic features and a general look at ho w the MPC860T can be implemented.
1-2 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE The MPC860T integrates three separate processing blocks.
MOTOROLA Chapter 1. Overview 1-3 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE management of transmit and recei ve b uffer memory ¥ 10/100 base-T media access control (MA C) features Ñ Address re.
1-4 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE Figure 1-1. MPC860T Block Diagram The FEC complies with the IEEE 802.3 speciÞcation for 10- and 100-Mbps connecti vity . Full-duplex 100-Mbps operation is supported at system clock rates of 40 MHz and higher .
MOTOROLA Chapter 1. Overview 1-5 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE in memory management of transmit and recei ve data frames. External memory (DRAM) is inexpensi ve, and because BD rings in e xternal memory hav e no inherent size limitations, memory management easily can be optimized to system needs.
1-6 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE Figure 1-3 sho ws the glueless connection of the serial channels to physical layer framers and transcei vers.
MOTOROLA Chapter 2. FEC External Signals 2-1 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE Chapter 2 FEC External Signals 20 20 This chapter contains brief descriptions of the MPC860T FEC input and output signals in their functional groups.
2-2 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE PD[12] L1RSYNCB MII_MDC R16 General-pur pose I/O por t D bit 12ÑThis is bit 12 of the general-purpose I/O por t D . L1RSYNCBÑInput receive data sync signal to the TDM channel B .
MOTOROLA Chapter 2. FEC External Signals 2-3 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE PD[4] REJECT3 MII_TXD[2] U16 General-pur pose I/O por t D bit 4ÑThis is bit 4 of the general-purpose I/O por t D . Reject 3ÑThis input to SCC3 allows a CAM to reject the current Ethernet frame after it determines the frame address did not match.
2-4 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE Fr eescale S emiconduct or , I Freescale Semiconductor, Inc.
MOTOROLA Chapter 3. F ast Ethernet Controller Operation 3-1 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE Chapter 3 F ast Ethernet Contr oller Operation 30 30 This chapter discusses the operation of the FEC.
3-2 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE 3.2 FEC Frame T ransmission FEC transmissions require almost no host intervention.
MOTOROLA Chapter 3. F ast Ethernet Controller Operation 3-3 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE (I_EVENT[B ABT] = 1); ho wev er , the entire frame is sent (no truncation). Whether b uf fer or frame interrupts can be generated is determined by I_MASK settings.
3-4 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE of the frame to the associated data buf fer . R_BUFF_SIZE[R_BUFF_SIZE] determines b uf fer length, which should be at least 128 bytes. R_BUFF_SIZE must be quad-word (16-byte) aligned.
MOTOROLA Chapter 3. F ast Ethernet Controller Operation 3-5 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE broadcast address. If it is, the frame is accepted unconditionally; otherwise (multicast address) a hash table lookup is performed using the 64-entry hash table deÞned in the hash table registers.
3-6 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE of the CRC-encoded result to generate a number between 0 and 63. Bit 31 of the CRC result selects HASH_T ABLE_HIGH (bit 31 = 1) or HASH_T ABLE_LOW (bit 31 = 0).
MOTOROLA Chapter 3. F ast Ethernet Controller Operation 3-7 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE 3.10 Internal and External Loopbac k The FEC supports Both internal and external loopback. In loopback mode, both FIFOs are used and the FEC operates in full-duplex f ashion.
3-8 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE Table 3-4. Reception Errors Error Description Overrun Error The FEC maintains an internal FIFO for receiving data. If a receiv er FIFO overrun occurs, the FEC closes the buff er and sets RxBD[O V].
MOTOROLA Chapter 4. Parallel I/O P orts 4-1 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE Chapter 4 P arallel I/O P or ts 40 40 This chapter sho ws how to use port D pin multiple xing to support Fast Ethernet controller (FEC) operations.
4-2 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE T able 4-1 sho ws the port D pin assignments. 4.1.1 P ort D Registers Port D has three memory-mapped, read/write, 16-bit control registers.
MOTOROLA Chapter 5. SDMA Bus Arbitration and T ransf ers 5-1 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE Chapter 5 SDMA Bus Arbitration and T ransfer s 50 50 This chapter describes SDMA functions speciÞc to the MPC860T, particularly where the functionality dif fers from the MPC860.
5-2 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE 5.2.1 SDMA ConÞguration Register (SDCR) The SDMA conÞguration register (SDCR), sho wn in Figure 5-2, is used to conÞgure all 16 SDMA channels.
MOTOROLA Chapter 6. Pr ogramming Model 6-1 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE Chapter 6 Pr ogramming Model 60 60 This chapter gi ves an ov erview of the MPC860T implementation of the F ast Ethernet controller (FEC) registers, b uf fer descriptors (BDs), and initialization.
6-2 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE 6.2.1 RAM P erfect Match Ad dress Low Register (ADDR_LO W) The ADDR_LO W re gister , shown in Figure 6-1, is written by and must be initialized by the user .
MOTOROLA Chapter 6. Pr ogramming Model 6-3 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE T able 6-2 describes the ADDR_LOW Þelds. 6.2.2 RAM P erfect Match Ad dress High (ADDR_HIGH) The ADDR_HIGH re gister , shown in Figure 6-2, is written by and must be initialized by the user .
6-4 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE T able 6-4 describes HASH_T ABLE_HIGH Þelds.
MOTOROLA Chapter 6. Pr ogramming Model 6-5 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE T able 6-5 describes HASH_T ABLE_LOW Þelds. 6.2.5 Beginning of RxBD Ring (R_DES_ST ART) The R_DES_ST AR T register , shown in Figure 6-5, is like the RB ASE register used by other protocols.
6-6 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE T able 6-7 describes X_DES_ST AR T Þelds. 6.2.7 Receive Buffer Size Register (R_BUFF_SIZE) The R_BUFF_SIZE re gister , shown in Figure 6-7, is like the MRBLR re gister used by other protocols.
MOTOROLA Chapter 6. Pr ogramming Model 6-7 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE T able 6-8 describes R_BUFF_SIZE Þelds. 6.2.8 Ethernet Contr ol Register (ECNTRL) The Ethernet control register (ECNTRL), sho wn in Figure 6-8, is used to enable and disable the FEC.
6-8 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE T able 6-9 describes ECNTRL Þelds.
MOTOROLA Chapter 6. Pr ogramming Model 6-9 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE and RFINT to notify at the end of frame. 6.2.10 Ethernet Interrupt V ector Register (IVEC) The Ethernet inte.
6-10 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE T able 6-11 describes IVEC Þelds.
MOTOROLA Chapter 6. Pr ogramming Model 6-11 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE T able 6-12 describes R_DES_A CTIVE Þelds. 6.2.12 TxBD Active Register (X_DES_A CTIVE) The TxBD acti ve re.
6-12 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE T able 6-13 describes X_DES_A CTIVE Þelds.
MOTOROLA Chapter 6. Pr ogramming Model 6-13 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE T able 6-14 describes MII_D A T A Þelds. T o read or write on the MII management interface, MII_D A T A is written by the user .
6-14 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE completes. At this time the contents of MII_D A T A match the original value written e xcept for the D A T A Þeld, whose contents have been replaced by the v alue read from the PHY register .
MOTOROLA Chapter 6. Pr ogramming Model 6-15 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE be non-zero to source a read or write management frame. After the management frame is complete, MII_SPEED may optionally cleared to turn of f the MDC.
6-16 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE 6.2.16 FIFO Receive Star t Register (R_FST ART) The R_FST AR T register , shown in Figure 6-16, is programmed by the user to indicate the starting address of the recei ve FIFO.
MOTOROLA Chapter 6. Pr ogramming Model 6-17 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE for the system bus. Setting the w atermark to a high value lo wers the risk of a transmit FIFO underrun due to system bus contention. T able 6-19 bit Þeld descriptions for X_WMRK.
6-18 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE T able 6-20 describes X_FST AR T Þelds.
MOTOROLA Chapter 6. Pr ogramming Model 6-19 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE T able 6-21 describes FUN_CODE Þelds. 6.2.20 Receive Contr ol Register (R_CNTRL) The R_CNTRL register, shown in Figure 6-20, is programmed by the user to control the operational mode of the recei ve block.
6-20 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE T able 6-22 describes R_CNTRL Þelds. 6.2.21 Receive Hash Register (R_HASH) With revision D of the MPC860T silicon, R_HASH[MAX_FRAME_LENGTH], shown in Figure 6-21, is programmable.
MOTOROLA Chapter 6. Pr ogramming Model 6-21 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE T able 6-22 describes R_HASH Þelds. 6.2.22 T ransmit Contr ol Register (X_CNTRL) The transmit control register (X_CNTRL), sho wn in Figure 6-22, is written by the user to conÞgure the transmit block.
6-22 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE 6.3 Initialization Sequence This section describes which registers and RAM locations are reset due to hardw are reset, which are reset due to the microcontroller , and what locations the user must initialize before enabling the FEC.
MOTOROLA Chapter 6. Pr ogramming Model 6-23 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE exact v alues depend on the application. The sequence resembles that sho wn in T able 6-27. 6.3.2.1 Descriptor Contr oller Initialization In the FEC, the descriptor control machine initializes a fe w registers whene ver ECNTRL[ETHER_EN] is set.
6-24 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE (though these steps could also be done before setting ETHER_EN). 6.4 Buffer Descriptor s (BDs) Data for Fast Ethernet frames must reside in memory e xternal to the MPC860T device.
MOTOROLA Chapter 6. Pr ogramming Model 6-25 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE The RxBD format is sho wn in T able 6-27. 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 +0 E RO1 W R O 2 L 0 0 M B CM CL GN OS HC R O V T R +2 DA T A LENGTH +4 RX BUFFER POINTER A[0Ð15] +6 RX BUFFER POINTER A[16Ð31] Figure 6-23.
6-26 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE 6.4.2 Ethernet T ransmit Buffer Descriptor (TxBD) Data is presented to the FEC for transmission by arranging it in buf fers referenced by the channelÕ s TxBDs.
MOTOROLA Chapter 6. Pr ogramming Model 6-27 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE On transmit, an underrun occurs if the transmit FIFO empties of data before the end of the frame. In this case, a bad CRC is appended to the partially transmitted data.
6-28 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE Fr eescale S emiconduct or , I Freescale Semiconductor, Inc.
MOTOROLA Chapter 7. Electrical Characteristics 7-1 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE Chapter 7 Electrical Characteristics 70 10 This chapter contains detailed information on DC and A C electrical characteristics and A C timing speciÞcations for the MPC860T MII signals and a MPC860T pinout diagram.
7-2 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE Figure 7-1. MII Receive Signal Timing Diagram The recei ver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement.
MOTOROLA Chapter 7. Electrical Characteristics 7-3 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE Figure 7-2. MII Transmit Signal Timing Diagram 7.3.3 MII Async Inputs Signal Timing (CRS, COL) T able 7-3 provides information on the MII async inputs signal timing, sho wn in Figure 7-3.
7-4 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE 7.3.4 MII Serial Management Channel Timing (MDIO ,MDC) T able 7-4 provides information on the MII serial management channel signal timing, sho wn in Figure 7-4.
MOTOROLA Chapter 7. Electrical Characteristics 7-5 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE 7.4 MPC860T Pin Assignments Figure 7-5 shows the MPC860T pin assignments.
7-6 MPC860T (Rev . D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE Fr eescale S emiconduct or , I Freescale Semiconductor, Inc.
MOTOROLA Chapter 7. Electrical Characteristics 7-7 PRELIMINAR YÑSUBJECT T O CHANGE WITHOUT NO TICE Fr eescale S emiconduct or , I Freescale Semiconductor, Inc.
Fr eescale S emiconduct or , I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc. ...
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