AMDメーカー8151の使用説明書/サービス説明書
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24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unne l Data Shee t 1 Cover page AMD-8151 TM HyperT ransport TM AGP 3.0 Graphics T unnel Data Sheet 1O v e r v i e w The AMD-8151 TM HyperT ransport TM AGP3.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 2 T rad emarks AMD, the AMD Arrow lo go, and combina tions th ereof, and AMD-8151 are tr ademarks of Advanced Micro Devices, Inc. HyperT ransport is a licens ed trademar k of the Hyp erT ransp ort T echnology Cons ortium.
3 24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet T able of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Device Features .
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 4 List of Figur es Figure 1: System blo ck diagram. ................... ........................... .................. ........................... ...... ............ ..... 1 Figure 2: Configurati on space.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 5 List of T ables T able 1: IO signal t ypes. ..................... ........................... .................. ........................... .......... ................. ..... 6 T able 2: T ransla tion from AGP req uests to link request s.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 6 2 Or derin g I nfo rm atio n 3 Sign al D esc ripti on s 3.1 T erminology See sect ion 5.1.2 fo r a des criptio n of the regi ster namin g conven tion used in t his documen t. See the AMD-8151 TM HyperT ransport TM AGP3.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 7 3.2 T unnel Link Signals The foll owing are s ignals as sociate d with the Hy perT ransp ort TM links. [ B, A] in the signal na mes belo w refer to the A a nd B sides o f the tunnel.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 8 3.3 AGP Sig na ls In the table below, “Term” indicates the standard AGP 3.0 termination impedance to ground; “PU” indicates a weak pullup resistor; “PD” indicates a weak pulldown resistor.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 9 The SERR# and PERR# signals a re not sup ported on t he AGP bridge . A_G NT# . AGP master grant signal. Output VDD15 T erm Low PU High A_IRDY#. AGP master ready signal. IO VDD15 T erm T erm PU PU A_MB8XDET#.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 10 3.4 T est and Miscellaneous Signals 3.5 Power and Gr ound VDD12[B, A]. 1.2 v olt power plan e for the HyperT ransport TM technology pins. VDD12A prov ides power to the A sid e of the t unnel.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 11 4 Functional Operation 4.1 Ove rview The IC conne cts to the host through either the s ide A or side B HyperT ransport TM lin k interf ace. The other sid e of the t unnel may or may not b e connected t o another d evice.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 12 In summary , St op Grant br oadcasts with SMAF fiel ds specif ied by DevA:0 xF0[ICGSMAF] enab le the clock gating wi ndow and S TPCLK deassert ion broadc asts dis able the window .
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 13 All AGP tran sac tio ns a re comp lia nt to AG P o rde ring rul es. APG tran sac tio ns a re trans late d i nto lin k t ransa c- tions as fol low s: 4.5.2 V arious Behaviors • The AGP bridg e does not claim lin k special cycles.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 14 The first calibration cycle occurs approximately 4 mill iseconds after the deas sertion of R ESET# (whether AGP 2.0 or 3.0 signal ing is enabled). 5 Regis ters 5.1 Regis ter Over view The IC includes s everal s ets of re gisters accessed through a v ariety o f address spaces.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 15 The foll owing are c onfigu ration space s: The IC does not cl aim confi guration- regist er access es to unimplemente d functio ns within its devic es (they are forwarde d to the other side of the tunnel ).
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 16 AGP Device S tatus And Command Register DevA:0x04 Default: 0 210 0000h Attribu te: See below . AGP Device Revi sion and Class Code Regist er DevA:0x08 Default: 0 600 00??h Attribu te: See below .
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 17 AGP Device Graphic V irtual Memory Aperture Regis ter DevA:0x10 It is e xpected t hat the s tate of thi s regist er is copi ed into t he host by software. This re gister c ontrols no hard- ware in the I C.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 18 AGP Miscella neous Contr ol Regis ter DevA:0x40 Default: 0 000 0000h Attribu te: See below . Bits D es cri ption 31:8 Reserve d. 7 Mu st b e low . This b it is requi red to be low at all tim es; s etti ng it h igh res ults in und efi ned beh av ior .
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 19 AGP PHY Contr ol Regi ster DevA:0x[54, 50] These registers apply to t he compensat ion value s of AGP clock -forwarde d data and strobe si gnals as f ollows: • DevA:0x50: data sign als A_AD[31:0 ], A_CBE_L[3:0], A_DBI[ H, L], and A_SBA[7 :0].
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 20 AGP PHY Skew Contr ol Register DevA:0x58 DSKEW and SSKE W are desi gned su ch that when they are both programmed t o the s ame value, the AGP out - put str obes tran sition near the cent er of the data eye.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 21 AGP Mos t R ec ent Req uest R egi ster DevA :0 x60 As each P IPE mode or SBA mode AGP reques t is transferred into the I C, the fields are placed in to this register . Thus, this regi ster provi des t he fields of the most recen t AGP reque sts.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 22 AGP Command Register DevA:0xA8 Default : 0000 0000h Attribu te: Read-wri te. 4 FWSUP: f ast wri te support flag. 0= Fast writes are not suppor ted. 1 =Fast write s are su pported. The state of this bit is contr olled by De vA:0x40[FWDIS].
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 23 AGP Control Register DevA:0xB0 Default : 0000 0000h Attribu te: Read-wri te. AGP Apertur e Size Re gister DevA:0xB4 Default: 0 001 0F00h Attribu te: See below . 2:0 DRA TE: data transf er mode ra te.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 24 AGP Device GAR T Pointer DevA:0xB8 This register control s no hardwar e in the IC. I t is expec ted that the stat e of this registe r is copied into the h ost by softwa re. Default : 0000 0000 0 000 0000h Attribu te: Read- write.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 25 Link Config uration And Contr ol Registe r DevA:0xC4 and DevA:0xC8 DevA:0x C4 applies side A of t he tunnel and De vA:0xC8 ap plies to side B of the t unnel. The defaul t value for bit[5 ] may vary ( see the de fini tion) .
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 26 18:16 Max link width in. Read only . This spe cifies the width o f the inc oming link to be 16 bits wi de for side A and 8 b its wide for si de B. 15 Reserve d. 14 EXTCTL: extended contr ol time during ini tializati on.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 27 Link Fr equency Capability 0 Register DevA:0xCC Default: 0 035 0022h. Attribu te: See below . Link Fr equency Capability 1 Register DevA:0xD0 Default: 0 035 0002h. Attribu te: See below .
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 28 Link PHY Compensation Contr ol Registers DevA:0x[E8, E4, E0] The lin k PHY ci rcu itry inc lud es au tom ati c co mpen sat ion that is used to adj ust the el ect rica l ch arac ter isti cs f or the link tra nsmitter s and receive rs on both s ides of the t unnel.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 29 Clock Contr ol Register DevA:0xF0 See sect ion 4.3.1 fo r deta ils on clock gating. AMD s ystem reco mmendations f or System Mana gement Acti on Field (SMAF) cod es are: 0=ACPI C2; 1=ACPI C3; 2 =FID/VID change; 3=ACPI S1; 4=ACPI S3; 5=Throt- tling; 6 =ACPI S4/S5.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 30 5.3 AGP Bridge Confi guration Regis ters These regist ers are loca ted in PCI configur ation sp ace, i n the seco nd device (devi ce B), functi on 0. See se ction 5.1.2 for a descr iption of t he register naming conve ntion.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 31 AGP Bridge Bus Number s And Secondary Latency Regis ter DevB:0x18 Default : 0000 0000h Attribu te: Read-wri te.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 32 • Host- initia ted trans actions inside the windows are route d to the AGP bu s.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 33 DevB :0 x24 . Default: 0 000 FFF0h Attribu te: Read- write. DevB :0 x30 . Default: 0 000 FFFFh Attribu te: Read-wri te. AGP Bridge Interrupt and Bridge Contr ol Register DevB:0x3C Default: 0 000 00FFh Attribu te: See below .
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 34 6 Elect rical Data 6.1 Absolute Ra tings The IC is not des igned to opera te beyond t he paramet ers shown in t he following t able.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 35 6.3 DC Characteri stics See the Hyp erT ransport TM T echnology El ectrica l Specifica tion for the DC chara cterist ics of lin k signals . The foll owing tabl e shows curr ent consu mption in amps and power i n watts fo r each power plane.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 36 The fol lowing t able shows DC cha racteri stics for sig nals on the VDD15 power plane whe n AGP 2.0 sign aling is enabl ed. The fol lowing t able shows DC cha racteri stics for sig nals on the VDD15 power plane whe n AGP 3.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 37 6.4 AC Characteri stics See the Hyp erT ransport T echnology El ectrica l Specifi cation f or the AC cha racteri stics of link si gnals. The foll owing tabl e shows AC spec ificati on data f or clocks .
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 38 The foll owing tabl e shows AC spec ificati on data f or clock- forwarded operation of AGP signals. AGP 2X AGP 4X AGP 8X Symbol Parameter Description Min Max M in Max Min Max Units Notes t TSF A_PCLK to transmit str obe f irst strobe edge 2 12 1.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 39 7 Ba ll D es igna tion s To p s i d e v i e w. 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 A L T ACAD _.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 40 Alphabet ical list ing of sig nals and co rrespondi ng BGA designa tors. Signal n ame Ball S ignal nam e Ball Signal name Ball Si.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 41 Signal name Ball Signal nam e Ball Signal nam e Ball Signal name Ball Signal name Ball Signal name Ball Signal name Ball VDD12A 1.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 42 8 Package Specificati on Figur e 4: Package mechanical drawing. AMD Øb PACKAGE D1/E1 D2/E2 SYMBOL D/E D3/E3 aaa bbb ccc 6. "x" in front of package variation denotes non-qualified package c) Die and passive fudicials a) Marking on die, label on package 7.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 43 9T e s t The IC incl ude s the f ollo wi ng t est m odes. 9.1 High Impedance Mode In high- impedance mode , all the signals of the IC are pla ced into t he hig h-impedance state. 9.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 44 NAND tree 1: output si gnal is STRAPL[5] . However , the gate con nected to the last si gnal in t his NAND tree (LDTCOMP[3]) i s an AND gate r ather th an a NAND gat e; so t he expect ed output o f this NAND tr ee is invert ed compared to t he other NAND t rees.
24888 Rev 3.0 3 - July 12 , 2004 AMD-8151 TM AGP T unnel Data Sheet 45 NAND tree 3: output signal is STRAPL[3] . Nand tree 4: output signal is STRAPL[ 2]. Notes: • LDTSTOP#, A_TYPEDET#, TEST , STRAPL[ 0], A_REFCG , A_REFGC, A_CALD, A_CALD#, A_CALS, and A_CALS# are not in th e NAND trees.
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