Intelメーカー440GXの使用説明書/サービス説明書
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Intel ® 440GX A GPset Design Guide March 1999 Order N umber: 29 0651-00 1.
Intel ® 440GX A GPset Design Gui de Information in this doc ument is provided in co nnection with Inte l products. No license, express or imp lied, by estopp el or ot he rwise, to any intellectual proper ty r ights is granted by this docume nt.
Intel ® 440GX AGPset Design Guide iii Contents 1 Introducti on ................... ............. .................... ............. ............ .................... ............. .. 1- 1 1.1 About Thi s Design Gu ide .................. .............
iv Intel ® 440GX A G Pset De sign Guide 2.6 Val idation ................... ............. ................... ............. ................... ............. .... 2- 15 2.6.1 Flight Time M easurement .................... ............ ................
Intel ® 440GX AGPset Design Guide v 3.7 82371EB (PIIX4E) ......... .................... ............. ............ .................... ............. 3-16 3.7.1 PIIX4E Conn ection s ............. ...... ....... ...... ...... ....... ...... ....... ..
vi Intel ® 440GX A G Pset De sign Guide 4.3 Debug Feat ures .. .................... ............. ............. ................... ............. ............ 4-2 4.3.1 I ntel ® Penti um ® II Pr ocessor LAI Issue ........... .................... ..
Intel ® 440GX AGPset Design Guide vii Figures 1-1 Intel ® Pe ntium ® II P rocessor / Intel ® 44 0GX AG Pset System Bl ock Dia gram.. .................... ............. ............ .................... ............. .. 1-4 2-1 Major Sig nal Sectio ns (8244 3GX Top View ).
viii Intel ® 440GX A G Pset De sign Guide Tables 2-1 Reco mmende d Trace Leng ths for S ingle Pr ocessor Design ..... ............. ...... 2- 7 2-2 Reco mmende d Trace Leng ths for Du al Proc essor Designs2 .... ................... 2-8 2-3 SET Trace Len gth Requ ireme nts .
Intel ® 440GX AGPset Design Guide ix Revision History Date Revision Description 3/99 -001 Initial Release ..
x Intel ® 440GX A G Pset De sign Guide.
1 Intr oduction.
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Intel ® 440GX AGPset Design Guide 1-1 Introducti on Intr oduction 1 This documen t provides d esign guideli nes for de velopi ng Int el ® Pentium ® II processor / Intel ® 440GX A GPset based systems. Motherboard and memory sub system design guidelines are cov ered.
Intel ® 440GX AGPset Design Guide 1-2 Introducti on 1.2 References • Intel ® P entium ® II Pr ocessor Datas heet • Intel ® 440GX A GPset Datasheet ( WWW ; order numb er 2906 38) • Intel 8237.
Intel ® 440GX AGPset Design Guide 1-3 Introducti on 1.3 Intel ® P e ntium ® II Pr ocessor / Intel ® 440GX A GPset Overview The follo wing is a list of featur es that a Intel ® Pentium ® II proce.
Intel ® 440GX AGPset Design Guide 1-4 Introducti on Intel introduced the In tel ® Pen tiu m ® II p rocesso r as 350/ 100 an d 400/10 0 speeds wi th 512 KB L2 cache versions. 1. 3.2 In tel ® 440GX A GPset • The Intel ® 440GX A GP set is the four th gen eration chips et bas ed on the Intel ® Pentium ® Pro processor architecture.
Intel ® 440GX AGPset Design Guide 1-5 Introducti on Figure 1-1 sh ows a blo ck diagram o f a typical platform b ased on the In tel ® 440GX A GPset. The 82443GX system b us interface suppor ts up to two I ntel ® Pentium ® II processors at the max imum bus frequen cy of 100 MHz.
Intel ® 440GX AGPset Design Guide 1-6 Introducti on 1.3.2. 4 PCI Inte rf ac e The 82443GX PCI interface is 3 3 MHz Re vis ion 2.1 co mpliant and supports up to f i v e exter nal PCI bus masters in additio n to the I/O bridge (PIIX4E).
Intel ® 440GX AGPset Design Guide 1-7 Introducti on Manageability features in each of these four technolog y areas combine to form the W ired for Management Baseline Specif ication. A cop y of the W ired for Management Baseline Specif ication can be obt ained from: ftp://download.
Intel ® 440GX AGPset Design Guide 1-8 Introducti on 1.3.3. 3 Remote W ake -U p If a PC supp orts a r educed po wer state, it mus t be pos sible to bri ng the sys tem to a fully po wered state in which all management interf aces are a v ailable. T ypically , the LAN adapter recog nizes a special packet as a signal to w ake up the system.
Intel ® 440GX AGPset Design Guide 1-9 Introducti on 1.4.2 General Design Recommendations 1. Intel recommends using an industry standard p rogrammabl e V oltage Re gulator Module (VRM) in stall ed in a VRM header o r an onb oard p rogrammab le v olt age re gulator d esign ed for Intel ® Pentium ® II processors.
Introductio n 1-10 Intel ® 440GX A G Pset De sign Guide.
2 Motherboard Design.
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Intel ® 440GX AGPset Design Guide 2-1 Mother board Layout and Routin g Guidel ines Motherboar d La y out and Routing Guidelines 2 This chapter des cribes layout and rou tin g recommendati ons to in sure a rob us t design. Foll o w these guidelines as clos ely as possibl e.
Motherboa rd Lay out and Ro uting Gui delines 2-2 Intel ® 440GX A G Pset De sign Guide Figu re 2-2 and Figu re 2-3 sho w the proposed com ponent placement fo r a sin gle processor f or both A TX and NLX form factor designs. A TX Fo r m Fa ct o r : 1.
Intel ® 440GX AGPset Design Guide 2-3 Mother board Layout and Routin g Guidel ines NLX F orm Fact or: 1. The NLX placement a nd layout belo w is recommended for a single ( UP) Intel ® Pentiu m ® II processo r / Intel ® 44 0GX A GPset system design .
Motherboa rd Lay out and Ro uting Gui delines 2-4 Intel ® 440GX A G Pset De sign Guide Note: The top an d bott om rout ing la yers specify 1/2 oz. cu.
Intel ® 440GX AGPset Design Guide 2-5 Mother board Layout and Routin g Guidel ines Additional guidelines on board b uildup, placement and layout include: • For a 4-laye r single p rocessor de sign, doub le ended terminati on is recom m ended for GTL+ signals.
Motherboa rd Lay out and Ro uting Gui delines 2-6 Intel ® 440GX A G Pset De sign Guide 2.3.1 GTL+ Description GTL+ is the electrical bus techn ology used for the I ntel ® Pen tium ® Pro processor and Inte l ® Pen tiu m ® II p rocessor s ystem b us.
Intel ® 440GX AGPset Design Guide 2-7 Mother board Layout and Routin g Guidel ines 2.3.3.2 Single Pr ocessor Recommended T race Lengths Single processor trace length recommendation s are summarize d in Ta b l e 2 - 1 . The recommended lengths are deri ved from the parametric sweeps and Monte Carlo analysis described in the follo wing s ection.
Motherboa rd Lay out and Ro uting Gui delines 2-8 Intel ® 440GX A G Pset De sign Guide 2.3.4 Dual Pr o cessor Systems 2.3.4.1 Dual Pr ocessor Netw ork T opology and Conditions 2.3.4.2 Dual Pr ocessor Recomm ended T race Lengths The recommended trace lengths for dual processor d esigns are summari zed in Ta b l e 2 - 2 .
Intel ® 440GX AGPset Design Guide 2-9 Mother board Layout and Routin g Guidel ines In the SET topology , the only termination is on the Intel ® Pent ium ® II pr ocessor substrate.
Motherboa rd Lay out and Ro uting Gui delines 2-10 Intel ® 440GX A G Pset De sign Guide 2.3.6 A dditiona l Gu ide l ine s 2.3.6.1 Minimizing Cr osstalk The follo wing general rules will minimize the impact of crosstalk in the high speed GTL+ b us design: • Maximize the space between traces.
Intel ® 440GX AGPset Design Guide 2-11 Mother board Layout and Routin g Guidel ines 2.3.7 Design Methodology Intel r ecommends us ing t he follo wing desig n methodo log y when desi gning s ystems based on on e or two Intel ® Pen tiu m ® II p rocessors and one Intel ® 440 GX A GPset.
Motherboa rd Lay out and Ro uting Gui delines 2-12 Intel ® 440GX A G Pset De sign Guide 2.3.8 P erf ormance Requirements Prior to perform ing interconne ct sim ul ations, establ ish the minim um and max imum flight time requirement s. Set up and h old requ irements determ ine the f light t ime boun ds for the host b us.
Intel ® 440GX AGPset Design Guide 2-13 Mother board Layout and Routin g Guidel ines Section 2.7, “T iming Analysis” on page 2-17 describes the timing analysis for the 10 0 MHz host bus in more detail . Ta b l e 2 - 4 pro vides recommende d fligh t time sp ecifications for si ngle and dual Intel ® Pentium ® II processor systems.
Motherboa rd Lay out and Ro uting Gui delines 2-14 Intel ® 440GX A G Pset De sign Guide The methodology th at Intel recommends is kno wn as “Sensiti vity Analysis”. In sensiti vity analysis, intercon nect paramet ers are v aried to underst and ho w they af fect system timing a nd sign al integrity .
Intel ® 440GX AGPset Design Guide 2-15 Mother board Layout and Routin g Guidel ines 2.5.1 Cr osstalk and the Multi-Bit Adjustment F actor Coupled lines s hould be in cluded in the post -layout simul ations. The fligh t times listed in Ta b l e 2 - 4 apply to single bit sim ulations only .
Motherboa rd Lay out and Ro uting Gui delines 2-16 Intel ® 440GX A G Pset De sign Guide 2.6.2 Signal Quality Measurement Signal integrity is specif ied at the pro cessor core, which is not accessible. Intel has found that there can be substantial miscorrelation between r ingback at the edge f inger versus the core.
Intel ® 440GX AGPset Design Guide 2-17 Mother board Layout and Routin g Guidel ines 2.7 Timing Analysis T o determine the av ailable flight time win do w perform an initial ti ming analysis. An alysis of s etup and hold co nditions w ill determine the m inimum and ma ximum flight time bounds fo r the host bus.
Motherboa rd Lay out and Ro uting Gui delines 2-18 Intel ® 440GX A G Pset De sign Guide Notice that the timing eq uations include an extra te rm to account for th e delay du e to routing of the BCLK trace on the processor sub strate from the pr ocessor edge f ingers and the processor core.
Intel ® 440GX AGPset Design Guide 2-19 Mother board Layout and Routin g Guidel ines 2.8 A GP Lay out an d Routing Guidelin es For the def inition of A GP Interface functionality (protocols, rules and signalin g mechanisms, as well as the platform lev el aspects of AGP functionality), refer to the latest AGP Interface Specifi cation r e v 1.
Motherboa rd Lay out and Ro uting Gui delines 2-20 Intel ® 440GX A G Pset De sign Guide It is always best to reduce the line length mismatch wherev er possible to insure added mar gin. It is also best to separate the traces by as much as possible to red uce the amount of trace to trace coupling.
Intel ® 440GX AGPset Design Guide 2-21 Mother board Layout and Routin g Guidel ines For trace leng ths that are b etween 1.0 inch and 4.5 inches, a 1: 1 trace spacing is recommend ed for data lines. The strobe requ ires a 1:2 trace spacing. This is for designs that req uire less than 4.
Motherboa rd Lay out and Ro uting Gui delines 2-22 Intel ® 440GX A G Pset De sign Guide Some of t he control sign als requi re pull -up resi stors to be in stalle d on th e motherbo ard. A GP signals m ust be p ulled up to VCC 3.3 usi ng 8.2 K to 10 K ohm pu ll- up resi stors (refer to Section 3.
Intel ® 440GX AGPset Design Guide 2-23 Mother board Layout and Routin g Guidel ines There are also “popu lation” rules which need to b e observ ed. T o properly adjust memory timings for 100 MHz o peration, it is asked of the OEM and end user to populate the motherboar d starting with the DIMM located the furthest from the 82443GX.
Motherboa rd Lay out and Ro uting Gui delines 2-24 Intel ® 440GX A G Pset De sign Guide 2.9.1.3 T race Width vs. T race Spacing T o minimize the crosstalk, a 1:2 trace width vs. trace spacing routing (e.g ., 6 mils on 9 mils o r 5 mils on 10 mils) should be used fo r all memory interf ace signals.
Intel ® 440GX AGPset Design Guide 2-25 Mother board Layout and Routin g Guidel ines . T able 2-18. FET Switch DQ Route E xample Figure 2-20. Mot herboard Model—Data (MDxx), 4 D IMMs v004 0.6” 82443GX 1.1” - 2.0” 0.7” - 2.4 ” 0.3” - 1.0” 0.
Motherboa rd Lay out and Ro uting Gui delines 2-26 Intel ® 440GX A G Pset De sign Guide Figure 2-21. Motherboard Model—DQMA[0,2 :4,6:7], 4 DIMMs Figure 2-22. Motherboard Model—DQM_A [1,5], 4 DIMM s 82443G X 1.0” - 3.25” 0.4” - 0.6” DIMM Modul e 1 DIMM Modul e 2 0.
Intel ® 440GX AGPset Design Guide 2-27 Mother board Layout and Routin g Guidel ines Figure 2-24. Mot herboard Model—DQM_B[1,5], 4 DIM Ms 82443G X 1.0” - 3.25” 0.4” - 0.6” DIMM Mod ule 3 DIMM Mod ule 4 Figure 2-25. Mot herboard Model—CS_A#/CS_B#, 4 DIMMs Figure 2-26.
Motherboa rd Lay out and Ro uting Gui delines 2-28 Intel ® 440GX A G Pset De sign Guide T able 2-19 . Motherboard Model: SR AS_B#, 4 DIMM s T able 2-20 . Motherboard Model: SC AS_A#, 4 DIMM s T able 2-21 . Motherboard Model: SC AS_B#, 4 DIMM s 82443GX 1.
Intel ® 440GX AGPset Design Guide 2-29 Mother board Layout and Routin g Guidel ines T able 2-22. Motherboard Model: WE_A#, 4 DIMMs T able 2-23. Motherboard Model: WE_B#, 4 DIMMs T able 2-24. Motherboard Model: MA_A[14:0], 4 D IMMs 82443G X 1.0” - 3.
Motherboa rd Lay out and Ro uting Gui delines 2-30 Intel ® 440GX A G Pset De sign Guide 2.9.3 4 DIMM Routing Guideli nes [NO FET] 2.9.4 PCI Bus Routing Guidelines The 82443GX pro vides a PCI Bus interface that is compliant with the PCI Local Bus S pecif ication.
Intel ® 440GX AGPset Design Guide 2-31 Mother board Layout and Routin g Guidel ines Because of the specif ics of an A TX layout, it is recommended that the PIIX4E compo nent is at the “END” of the PCI b us, as show n in F igure 2-2 8 . This insures proper “t ermination” of the PCI Bus signals.
Motherboa rd Lay out and Ro uting Gui delines 2-32 Intel ® 440GX A G Pset De sign Guide 2.9.6 Intel ® 440GX A G Pset Cloc k La yout Recommendations 2.
Intel ® 440GX AGPset Design Guide 2-33 Mother board Layout and Routin g Guidel ines 2.9.6.3 P CI Cloc k La yout PCI cloc k net s should be routed a point- to-po int conne ctions w ith a 22 O hm ser ies resis tor that is to be placed as close to the ou tput pins on th e clock dri ver as possible (<0.
Motherboa rd Lay out and Ro uting Gui delines 2-34 Intel ® 440GX A G Pset De sign Guide 2.9. 6.5 A GP C loc k Lay out Series T ermination: 22 Ohm series termination should be used for the A GP clocks. Layout guidelines: T he feedback clock tr ace length equals the standard clock motherboard trace length plus the car d trace length.
3 Design Checklist.
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Intel ® 440GX AGPset Design Guide 3-1 Design Ch ecklist Design Chec klist 3 3.1 Overview The following checklist is intended to be used for schematic revie ws of Intel ® 440GX A G Ps et desktop d esigns.
Intel ® 440GX AGPset Design Guide 3-2 Design Ch ecklist 3.3 Intel ® P e ntium ® II Pr ocessor Checklist 3. 3.1 In tel ® Pe n t i u m ® II Proce ssor Figure 3-1. Pull-up Resistor Example T able 3-1. Slot Connectivity (Shee t 1 of 3) Processor Pin Pin Connection 100/66# UP: Connected to CK100.
Intel ® 440GX AGPset Design Guide 3-3 Design Ch ecklist DBSY# UP : Connect to 82443GX; DP : Conn ect CPUs and 82443GX . DEFER# UP: Connect to 82443GX; DP : Connect CPU s and 82443GX. DEP[7:0] No connect. DRD Y# UP: Connect to 82443GX; DP : Connect CPUs an d 82443GX.
Intel ® 440GX AGPset Design Guide 3-4 Design Ch ecklist TDO UP : Connected to ITP . 150 ohm pull-up t o 2.5V . DP : Connected to jumpers betw een ITP and CPU signals. See DP schematics f or details. TDI UP : Connected to ITP . 150 ohm - 330 ohm pull-up to 2.
Intel ® 440GX AGPset Design Guide 3-5 Design Ch ecklist 3. 3.2 In tel ® Pe n t i u m ® II Proce ssor Cloc ks • Include a circuit fo r the system b us clock to core f r equency ratio to the pr ocessor . The ratio should be conf igurable as opposed to hard wi red.
Intel ® 440GX AGPset Design Guide 3-6 Design Ch ecklist used b y other logic req uiring CMOS/TTL logic le vels. The VID lines on the Slot 1 connector are 5V tolerant. • Vcc (±5%) s hould be pro vided to t he Slot 1 sign al Vcc p in B 109. T his po wer connection is not used by the Intel ® Pentium ® II processor .
Intel ® 440GX AGPset Design Guide 3-7 Design Ch ecklist 3.3.4 Uni-Pr ocessor (UP) Slot 1 Chec klist • A UP system must connect BREQ0# of the Sl ot 1 co nnector t o the 824 43GX’ s BREQ0# signal. This will assign an agent ID of 0 to the processo r .
Intel ® 440GX AGPset Design Guide 3-8 Design Ch ecklist 3.4 Intel ® 440GX A GPset Clocks 3.4.1 CK100 - 100 MHz Clock Synthesizer • The system clock which pro vides 100 MHz to the processor and th e Intel ® 440 GX A GPset, and the clocks for the APIC must be +2 .
Intel ® 440GX AGPset Design Guide 3-9 Design Ch ecklist 3.4.2 CKBF - SDRAM 1 to 18 Clock Buffer • A 4.7K ohm pu ll-up to VCC 3. 3 on the OE pin is needed to enab le the bu f fer . • Note that DCLKRD pi n has been chang e d to a no connect (NC). The DC LK RD fun ctionality has been combined with DCLKWR.
Intel ® 440GX AGPset Design Guide 3-10 Design Ch ecklist 3.5 82443GX Host B ridge 3.5.1 82443GX Inte rfa ce T able 3-4. 82443GX Connectivity (S heet 1 of 3) SIGNAL CONNECTION AD#[31:0] Connected to PCI b us. ADS# Connected to CPUs. AGPREF Connected to be 0.
Intel ® 440GX AGPset Design Guide 3-11 Design Ch ecklist GADSTBA, GADSTBB, GDEVSE L# , GFRAME#, GGNT#, GIRD Y#, GREQ#, GST OP#, GTRD Y# , 8.2K ohm pull-ups to 3.3V . Connected to A G P connector. GP AR 100K ohm pull-down required. C onnect to AG P connector .
Intel ® 440GX AGPset Design Guide 3-12 Design Ch ecklist • GTLREFx pins are dri ven from indepe ndent v oltage di viders which set th e GTLREFx pins to VTT*2/3 usi ng a 75 ohm and 15 0 ohm re sisto r ratio . • The 82443GX GTL_ REF[B: A] pins shou ld be adeq uately dec oupled .
Intel ® 440GX AGPset Design Guide 3-13 Design Ch ecklist — TMS (connecto r pin A3) and TDI (connect or pin A4) should be independentl y bussed and pulled up with 5K o h m (approximate) resistors . — TRST# (connect or pin A1) and TC K (connector pin B2) should be indepen dently b ussed and pull ed do wn with 5K ohm (app roxim ate) res istor s.
Intel ® 440GX AGPset Design Guide 3-14 Design Ch ecklist 3.6 Intel ® 440GX A GPset Memory Interface 3.6.1 SDRAM Con nections NO TES: 1. So me of the pin ranges abov e are dependent on which DIMM is being re viewed. “x” and “y” indicate signal copies.
Intel ® 440GX AGPset Design Guide 3-15 Design Ch ecklist 3.6.2 DIMM Solution Wit h FET Switc hes • W ith ex isti ng 64Mb it technol ogy , 512 MB, 1 GB and 2 GB support for ser ver s and work stations must h av e 4 double si ded DIMMs. • 500 ohm - 1K ohm pull-do wn resistors on each of the secon d inputs (1A2, 2A2, etc.
Intel ® 440GX AGPset Design Guide 3-16 Design Ch ecklist 3.7 82371EB (PIIX4E) 3.7.1 PIIX4E Connections T able 3-7. PIIX4E Connectivity (Sheet 1 of 4) Signal Names Connection 48MHz Connect to CK100 through a 22 ohm series resistor . A20GA TE Connected to SIO .
Intel ® 440GX AGPset Design Guide 3-17 Design Ch ecklist IOCHCK# Connected to ISA slots. 4.7K ohm pull-up to VCC. IOCHRD Y Connected to ISA slots and Ult ra I/O . 1K ohm pull-up to VCC. IOCS16# Connec ted to ISA slots. 1K ohm pull-up t o VCC . IOR# Connected to ISA slots, Ultra I/O , LM79.
Intel ® 440GX AGPset Design Guide 3-18 Design Ch ecklist PHLD# Connected to 82443GX. 8.2K ohm pull-up t o VCC3. PHLD A# Connected to 82443GX. 8.2K ohm pull-up t o VCC3. PIORD Y Connec ted to IDE through 47 ohm series resistor . 1K ohm pull-up to VCC on the PIIX4E side of the ser ies resistor .
Intel ® 440GX AGPset Design Guide 3-19 Design Ch ecklist SMBCLK , SMBD A T A Connect to all de vices on SMBus. 2.7K ohm pull-up to VCC3. Thi s value m ay need to be adjusted based on b us loading. SMEMR#, SMEMW# Connected to ISA slots . 1K ohm pull-up to VCC .
Intel ® 440GX AGPset Design Guide 3-20 Design Ch ecklist 3.7. 2 IDE Rou ti ng Gu ideline s This section contains guidelines for connecting and routing the PIIX4E IDE interf ace.
Intel ® 440GX AGPset Design Guide 3-21 Design Ch ecklist One resis tor per IDE connector is recommend ed for all s ignals. F or signals labeled as 22-47 Ω , the correct v alue should be determined for each unique moth erboard de sign, based on signal quality .
Intel ® 440GX AGPset Design Guide 3-22 Design Ch ecklist 3.7.3 PIIX4E P o wer And Ground Pins • Vcc, Vcc(R TC), Vcc(SUS), and Vcc(USB) must be tied t o 3.3V . • V REF mus t be tied to 5V in a 5V to lerant system. This si gnal must be p ower u p before or simulta neous to Vcc, and i t must be po wer do wn after or s imultaneo us to Vcc.
Intel ® 440GX AGPset Design Guide 3-23 Design Ch ecklist Third, if the design currently uses an in -line acti ve g ate/buf fer on PCIRST# to dri ve the PCI bus, consider removal of this gate/buf fer entirely . The PIIX4/PIIX4E is des igned to drive the entire PCI bus .
Intel ® 440GX AGPset Design Guide 3-24 Design Ch ecklist 3.11 USB In terface • Contact your local Intel Field Sales representativ e for the following Application Note: 82371AB PI IX4 Appli cation No te #1: USB Design Guide And Chec klist Rev 1.
Intel ® 440GX AGPset Design Guide 3-25 Design Ch ecklist 3.13 Fl ash Design 3.13.1 Dual-Footprint Flash Design New featur es are coming to the PC continue to increase the size o f BIOS code, pushing the limits of the 1 Mbit bo undary . OEMs have already con ver ted man y PC designs to 2 Mbit BIOS and higher, and more will follow .
Intel ® 440GX AGPset Design Guide 3-26 Design Ch ecklist Following are general layout guidelin es for us ing the Intel’ s boot blo c k flash memories (28F001 GX/28F002 BC) in t he syst em: • If adding a switch on VPP for wr ite protection, switch to GND instead of VCC.
Intel ® 440GX AGPset Design Guide 3-27 Design Ch ecklist (WP# pin not a vailable on 8-Mbit 4 4-lead PSOP . In this package, treat as if the WP# p in is internally tied low , effectiv ely eliminating th e last ro w of the table below .
Intel ® 440GX AGPset Design Guide 3-28 Design Ch ecklist 3.14 Syste m and T est Sig nals • 8.2K ohm pu ll-up resistor i s recommen ded on the TES T# pin of the PIIX4E. 3.15 P ower Management Sig nals • A power b utton is required by the A CP I speci fication.
Intel ® 440GX AGPset Design Guide 3-29 Design Ch ecklist standb y v olt age is not prov ided b y the po wer s uppl y , the n tie PWR OK signal on the PIIX4E to the RSMRST# s ignal.
Intel ® 440GX AGPset Design Guide 3-30 Design Ch ecklist • The system reset button has typically b een connected indirectly to th e PWR OK input of the PIIX4/PIIX4E. This techniqu e will not reset the susp end well logic, which includ es the SMBus Host and Slav e controllers.
Intel ® 440GX AGPset Design Guide 3-31 Design Ch ecklist • Poll the p o wer b utton status bit durin g POS T while SMIs are not l oaded and go directl y to so ft- of f if it gets set. • Always install an SMI handler for the power b utton that ope rates un til A C PI is enabled.
Intel ® 440GX AGPset Design Guide 3-32 Design Ch ecklist be stubbed of f the trace r un and must be as close as po ssible to the PIIX4/PIIX4E . The capacitor must be no further than 0.5 inch from the PIIX4/PIIX4 E. If a stub is requ ired, it should be k ept to a fe w mm maximu m leng th.
Intel ® 440GX AGPset Design Guide 3-33 Design Ch ecklist PIIX4E. F or A CPI compliance, this signal must be conn ected to the IO APIC. There are two different routing options: — INTIN9: IRQ9OUT# can be con nected to INTIN9 on the IO APIC. The A CPI BIOS will report to the OS that the S CI uses IRQ9 for bo th PIC and APIC enabled platforms .
Intel ® 440GX AGPset Design Guide 3-34 Design Ch ecklist • Analog inpu ts feed i n vertin g op-amp stages, useful f or moni toring p ower suppl y re gulat ion. • The LM79 is a 5 V part, ho wev er SMBus requires a 3.3V interface. Level translation circuitry is required.
Intel ® 440GX AGPset Design Guide 3-35 Design Ch ecklist 3.18.4 W ake On LAN (W OL) Header • A 3-pin W O L header i nterconnects the NIC an d motherbo ard, and requires a 5VSB to pi n1. • The WOL supports the MP_W akeup pulse, allo wing it to turn on the system via a signal pulse.
Intel ® 440GX AGPset Design Guide 3-36 Design Ch ecklist 3.19.2 Design Considera t ions • For UP systems to suppo r t both the curren t Intel ® Pentium ® II processor and future processors, it is h ighly recomm ended that storage space fo r two (o r more) BIOS Updates be provided.
Intel ® 440GX AGPset Design Guide 3-37 Design Ch ecklist 3.21.1 Design Considera t ions • The Intel ® Pentium ® II processor retention mech anism, retention mechanism attach mo unt and heat sink suppo rt is an optional sup port stru cture for retaining th e Slot 1 processor in the system du ring shock and vi bration situatio ns.
Intel ® 440GX AGPset Design Guide 3-38 Design Ch ecklist 3.23 Lay out Ch ec klist 3.23.1 Routing and Board F ab ricatio n • VRM 8.2 Su pport: Is the Vcc CORE trace/power plane suf ficient to ensur e Vcc CO RE mee ts specification. See the Intel ® P entium ® II Dat asheet for trace/po wer plane resistance and length requirements.
4 Deb ug Recommendations.
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Intel ® 440GX AGPset Design Guide 4-1 Debug Recomme ndatio ns Deb ug Recommendations 4 This chapter provides tool informatio n, logic suggestion s, technical support options and a summary of the p roblems wh ich ha ve been fou nd to be ass ociated with s ystem d eb ug.
Intel ® 440GX AGPset Design Guide 4-2 Debug Recomme ndatio ns Contact your local Intel Field Sales representati v e to complete the prop er software license agreement and n on-disclosure agr eement required to rec eive the ITP .
Intel ® 440GX AGPset Design Guide 4-3 Debug Recomme ndatio ns The extra loading of the LAI562 requires stronger pull-u p v alues on the target system. Ho wev er , due to the current limitations o f some signal drivers, this stronger v alue may not be feasible.
Intel ® 440GX AGPset Design Guide 4-4 Debug Recomme ndatio ns Inputs t o the Sl ot 1 co nnector , from system l ogic (as suming a 14 mA driv er): • PWRGOOD 150 - 330 ohm • INIT# 150 - 330 ohm •.
Intel ® 440GX AGPset Design Guide 4-5 Debug Recomme ndatio ns 4.3.2.1 Debug C onsiderations • As tec hno lo g y dr ives bet t er lo w po wer mo des, the Vcc CORE current demand could appr oach 0 Amps. This may cause a regulator to go out of re gulation.
Intel ® 440GX AGPset Design Guide 4-6 Debug Recomme ndatio ns • The Global Descriptor T able (GDT) must be align ed. The GDT mu st be located on a D W ord boundary , or else setting the PE bit and branching will cause a SHUTDOWN transaction. • The ITP “pins” command may be u sed to check reset con figuratio n pin states.
5 Third P arty V endors.
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Intel ® 440GX AGPset Design Guide 5-1 Third-Party V endor Inf or mation Thir d-P ar ty V endor Inf ormation 5 This desi gn gu id e has bee n compiled to gi ve an o vervie w of important d esi gn con si d erati ons whi le prov iding sources for additio nal information.
Intel ® 440GX AGPset Design Guide 5-2 Third-Party V endor Inf or mation 5.1.1 V oltage Regulator Modules The follo wing v endors are dev eloping DC-DC con verter mod ules for Intel ® Pentiu m ® II processo r volt age and current requ irements per the VR M 8.
Intel ® 440GX AGPset Design Guide 5-3 Third-Party V endor Inf or mation 5.2 Intel ® 440GX A GPset 5.2.1 Cloc k Drivers Intel h as su pplied specif ications to clock dri ver v endors, includi ng the fo llo wing. The specif icatio ns def ine r equirement s for Int el ® Pen tiu m ® II p roces sor -based sy stems wit h Int el ® 440GX A GPset.
Third-P ar ty V end or Informa tion 5-4 Intel ® 440GX A G Pset De sign Guide 5.3 Other Processor Componen ts 5.3.1 Slot 1 Co nnector Public informatio n; see Intel ® Pentium ® II Proces sor Sup port Compon ents W eb page: http://developer .intel.com/ design/P entiumII/components/in dex.
A Refer ence Design Schematics.
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Intel ® 440GX AGPset Design Guide A-1 Intel ® 440GX A GPset Platform R ef erence Design Intel ® 440GX A GPset Platf orm Reference Design A This section describes the DP/Intel ® 440GX A GPset 4-DIMM Reference Design Schematics. The description of each schem atic page is named b y the logic block sho wn on that page.
Intel ® 440GX A GPset Pl atform Reference De sign A-2 Intel ® 440GX A G Pset De sign Guide 82443GX Component (Syst em bus and DRAM Interfaces) 8 This page sho ws the 82443GX component, System b us and DRAM Interfaces.
Intel ® 440GX AGPset Design Guide A-3 Intel ® 440GX A GPset Platform R ef erence Design Ultra I/O Component 20 This page shows the Ultra I/O component. The R TC may optionally be used. An Infra Red Header Port is also optional. A GP Connector 21 This page sho ws the A GP connector .
Intel ® 440GX A GPset Pl atform Reference De sign A-4 Intel ® 440GX A G Pset De sign Guide Power Connectors Front Panel Jumpers 32 This page sho ws the system A TX po wer connector , hardware reset logic, and standard chassis connectors fo r the hard disk, po wer LEDs, and speak er ou tput.
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ですが、ユーザガイドが果たす重要な役割の一つは、Intel 440GXに関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちIntel 440GXデバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
