Intelメーカー820Eの使用説明書/サービス説明書
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Intel ® 820E Chipset Design Guide May 2001 Docum ent Number : 298187-003 R.
Intel ® 820E Chipset R 2 Design Guide Information in this document i s provided in connection with Intel® products. No license, express or impli ed, by estoppel or ot herwise, to any intellectual property rights is granted by this document.
Intel ® 820E Chipset R Design Guide 3 Contents 1. Introduction ................................................................................................................... ............. 13 1.1. About This Des ign Guide ........................
Intel ® 820E Chipset R 4 Design Guide 2.8.3. 2×/4× Tim ing Dom ain Routing Guidelines ................................................... 62 2.8.4. AGP 2.0 Routing Sum mary ......................................................................... 64 2.
Intel ® 820E Chipset R Design Guide 5 2.22. LAN Lay out Guidelines ................................................................................................ 102 2.22.1. ICH2 – LAN Interconnect G uidelines ....................................
Intel ® 820E Chipset R 6 Design Guide 3.2.3. Pre-Lay out Simulation ................................................................................ 145 3.2.3.1. Methodology ............................................................................
Intel ® 820E Chipset R Design Guide 7 4.8. Decoupling Recom m endation for CK133 and DRCG ................................................. 174 4.9. DRCG Frequency Selection and the DRCG+ ............................................................. 175 4.
Intel ® 820E Chipset R 8 Design Guide Figures Figure 1. Intel ® 820E Chipset Platfor m Per form ance Des ktop Block Diagram ........................ 18 Figure 2. Intel ® 820E Chipset Platfor m Perform ance Des ktop Bloc k Diagr am (with ISA Bridge).
Intel ® 820E Chipset R Design Guide 9 Figure 47. Device-Side IDE Cable Detection ........................................................................... 82 Figure 48. Connection Requirem ents f or Prim ary IDE Connector ..........................
Intel ® 820E Chipset R 10 Design Guide Figure 100. 4.5 m il Stack- Up .................................................................................................. 1 81 Figure 101. Intel ® 820E Chipset Power Delivery Example....................
Intel ® 820E Chipset R Design Guide 11 Table 45. USB .................................................................................................................. ...... 134 Table 46. LAN Connect I/F..............................................
Intel ® 820E Chipset R 12 Design Guide Revision History Rev. Descripti on Date -001 • Initi al Release June 2000 -002 • Minor edits f or clarit y July 2000 -003 • Revised ICH2 s ecti ons May 20.
Intel ® 820E Chipset R Design Guide 13 1. Introduction The Intel ® 820E Chi pset De sign Guide provide s design r eco mm endat ions for systems using the Intel ® 820E chipset. This inclu des m otherboard lay out , routin g gu idelin es, sy stem desi gn is sues , sy stem requiremen ts, debug recom men dations, and board schematics.
Intel ® 820E Chipset R 14 Design Guide 1.2. Reference Documents • Intel ® 820 Chi pset Fami ly: 82820 Mem ory Cont roller Hub (M CH) Datasheet (d ocument number : 290630) http://developer.
Intel ® 820E Chipset R Design Guide 15 1.3. Sy stem Ov erv iew The Intel 820E ch ipset is desig ned for In tel ® Pe ntium ® III microprocesso rs and is the first chipset to support the in tegrated LA N capability and expanded USB capability . It supports the 4 × capability of the AGP 2.
Intel ® 820E Chipset R 16 Design Guide 1.3.1. Chipset Components The Intel 820E ch ipset con sist s of th e Intel ® 82820 Memory Controller H ub (MCH) an d the Intel ® 82801BA I/O C o ntroller Hub (IC H2). Additional fun ctionality can be provided thro ugh the use o f a PCI-to-ISA bridge.
Intel ® 820E Chipset R Design Guide 17 FWH Flash BIOS The FWH Flash BIOS co mponent is a k ey element in providing a new security and man ageability infrastru cture for the PC platf o rm. The devi ce operates under the FWH Flash B IOS interface and protocol.
Intel ® 820E Chipset R 18 Design Guide 1.3.3. Sy stem Configuration The follow ing fig ures show typical platf orm confi gurati ons us ing the Int el 820E chipse t: Figure 1.
Intel ® 820E Chipset R Design Guide 19 Figure 3. Intel ® 820E Chipset Platf orm Dual-Processor Perf ormance Desktop Blo ck Diagram I/O Co ntro ll er Hub Intel ® 82801BA (ICH2) Main Memory (Direct R.
Intel ® 820E Chipset R 20 Design Guide 1.4. Platform Initiativ es 1.4.1. Direct Rambus RAM (RDRA M *) The Direct Rambus RA M (RDRAM) initiativ e provides the mem o ry bandw idth necessary to obtain optim al performan ce from the Pentium III processor as w ell as a high-perf orman ce AGP graph ics controller.
Intel ® 820E Chipset R Design Guide 21 1.4.5. Integrated LA N Controller The ICH2 component incorporates an integrated LAN Cont roller. Its bus master capabilities enable the component to process high- level comm ands and perform mu ltiple operations, which low ers pro cessor utilization by off -loading comm unication tasks from th e processor.
Intel ® 820E Chipset R 22 Design Guide Function Disabl e The ICH2 pro vides the ability to disable the f ollowing functions : AC’ 97 Modem, AC’97 Au d io, IDE, USB o r SMB us. Once disab led , these functio ns no longe r de cod e I/O , memory or P CI co nfigurati on space.
Intel ® 820E Chipset R Design Guide 23 1.4.9. A C’97 The Audio Codec ’97 (AC ’97) specifi cation defin es a digital interf ace that can be used to attach an audio codec (AC), a m odem codec (MC), an audio/m odem codec (AMC) or both an A C and an MC.
Intel ® 820E Chipset R 24 Design Guide Figure 4. (A -C) A C’97 Connections 4A. AC' 97 with Audio Codec s (4-Channel Secondary) 4B. AC' 97 with Modem and Audi o Codecs 4C.
Intel ® 820E Chipset R Design Guide 25 1.4.10. Low -Pin-Count (LPC) Interf ace In the In tel 820E chipset plat form , the super I/O com ponent h as m igrated to the L ow -Pin -Cou nt (LPC) interface. Mig ration to the L PC interface enables lower-cost s uper I/O design s.
Intel ® 820E Chipset R 26 Design Guide This page is intentionally left blank..
Intel ® 820E Chipset R Design Guide 27 2. Layout/Routing Guidelines This chapte r docum ents the m otherboard layou t and rou ting guidelines for Inte l 820E chipse t-based sy stem s. T his chapter does n o t discuss the fu nctional aspects of any bus or the lay out gu idelines f or an add-in device.
Intel ® 820E Chipset R 28 Design Guide Figure 5. MCH 324-Ball µBGA * CSP Quadr ant Lay out (Top View) mch_quad A GP 2.0 Hub inter face S y stem bus S y stem bus Direct RDRAM* MCH (324-Ball µ BGA* CSP) Pin 1 Figure 6.
Intel ® 820E Chipset R Design Guide 29 2.3. Intel ® 820E Chipset Component Placement Notes: 1. T he ATX and NL X placemen ts and layouts show n in the follow ing fig ure are recom men d ed for sing le (UP) Intel 820E chips et-bas ed sy stem desi gn.
Intel ® 820E Chipset R 30 Design Guide 2.4. Core Chipset Routing Recommendations The follow ing tw o figures s how MCH core routin g examples: Figure 8.
Intel ® 820E Chipset R Design Guide 31 Figure 9. S e condary -Side M CH Core Routing Exa mple (A TX).
Intel ® 820E Chipset R 32 Design Guide 2.5. Source-Sy nchronous Strobing A techno logy used in AG P 4 × , Direct RDRAM and the h ub interface, source-sy nchronous s trobing allow s very high data trans fer rates. A s buse s becom e faster an d cycle times becom e shorter, the propagation delay becomes a lim iting factor in the bu s speed.
Intel ® 820E Chipset R Design Guide 33 Table 2. AGP 2× Data/Strobe Association Data A ssociated Strobe AD[15:0] and C/BE[ 1:0]# AD_STB0 AD[31:16] and C/BE[ 3:2]# AD_STB1 SBA[7:0] SB_STB In this ex a.
Intel ® 820E Chipset R 34 Design Guide Because of the tolerances of com ponents such as PCBs, connectors, and term ination resistors, there will be some reflected voltage on the interconnect. In this multi-sy mbol interconnect, tim ings are pattern dependent because th e reflections interfere w ith the next transfer.
Intel ® 820E Chipset R Design Guide 35 2.7.2.1. RSL Routing The RSL signals ent er the fi rst RI MM on t he left sid e, p rop agat e thro ugh the RIM M, and exit o n the right. T he signal co ntinues through the rest of the existing RI MMs until it is terminated at V TERM .
Intel ® 820E Chipset R 36 Design Guide The follow ing f igure show s a top view of the trace width/s p acing requ iremen ts for the RSL si gnals. Figure 14.
Intel ® 820E Chipset R Design Guide 37 Figure 16. Secondary-Side RS L Breakout Example.
Intel ® 820E Chipset R 38 Design Guide 2.7.2.2. RSL Termination All RSL sig nals m ust be termin ated to 1.8 V (V TERM ) using 27- Ω 1% or 28 Ω 2% resistors at the end of the chann el opposite the MCH. Resistor pack s are acceptable. V TERM must be deco uple d using high- speed bypas s capacitors—one 0.
Intel ® 820E Chipset R Design Guide 39 Figure 18. Direct RDRA M * Termination Example 2.7.2.3 . Direct RDRA M* Ground Pla ne Reference All RSL sig nals m ust be referenced to GND to provide the optimal current retu rn path. T he Direct RDRA M groun d plane reference m ust be continu o us to th e V TERM capacitors.
Intel ® 820E Chipset R 40 Design Guide Figure 19. Incorrect Direct RDRA M* Ground Plane Referencing 3.3-V P l ane 1.8-V Plane MCH Wrong dir_Ra mbus_gnd_plane _re f_incor rect RIMM2 RIMM1 Figure 20. Direct RDRA M * Ground Plane Reference Extend GND plane reference is land beyond V TERM capacit ors GND Plane 1.
Intel ® 820E Chipset R Design Guide 41 All four lay ers of the motherboard require correct grounding betw een the RSL signals on th e motherboard, as follow s: • Lay er 1 = Ground isol ation • La.
Intel ® 820E Chipset R 42 Design Guide Table 4. Copper Tab A rea Calculation Dielectric Thickness (D) Separation between Signal Trace and Copper Tab Min. Ground Flood Ai r G a p between Signal and GND Flood Compensating Capacitance (pF) Copper Tab (C-TA B) A rea (A ) (sq.
Intel ® 820E Chipset R Design Guide 43 Figure 21. Conn ector Compensatio n Example.
Intel ® 820E Chipset R 44 Design Guide Figure 22. S ection A (S ee Note), Top Laye r Note: R efer to Fi gure 21. F or clarity , the ground f lood was rem oved from the pict ure.
Intel ® 820E Chipset R Design Guide 45 Figure 23. Section A (See Not e), Botto m Layer Note: R efer to Fi gure 21. F or clarity , the ground f lood was rem oved from the pict ure.
Intel ® 820E Chipset R 46 Design Guide Figure 24. S ection B (See Note), Top Layer Note: R efer to Fi gure 21. F or clarity , the ground f lood was rem oved from the pict ure.
Intel ® 820E Chipset R Design Guide 47 Figure 25. Section B (See Note), Bott om Layer Note: R efer to Fi gure 21. F or clarity , the ground f lood was rem oved from the pict ure.
Intel ® 820E Chipset R 48 Design Guide The copper tab area for th e recomm ended stack- up was det ermi ned by means of simulat ion. The am ount of capacitance required is determin ed by the lay er on which th e RSL or clo cking signal is routed.
Intel ® 820E Chipset R Design Guide 49 The CTAB can be implemen ted on the mu ltip le layers to m inimize routing and space constraints. Figure 28 show s the us e of CTABs on th e top and bottom l ay er for bottom -lay er RSL and clock ing sig nals routed betw een RIMMs.
Intel ® 820E Chipset R 50 Design Guide Figure 29. RS L Signal Lay er A lternation MCH Signal on secondary s i de Signal on prim ary si de Sign al A Sign al B Sign al A Signal B rsl_s ig-l ay_alt er. vsd Route on EITHER l ayer. Ground isolation is REQUIRED! Term Table 7.
Intel ® 820E Chipset R Design Guide 51 All RSL sign als mu st satisfy th e followin g equation: Equation 2. RDRA M RSL Signal T race Length Calculation Package dimension + board trace length = Nominal RSL length ± 10 mils Figure 30.
Intel ® 820E Chipset R 52 Design Guide It is necessary to compensate f or the sligh t differen ce in electrical characteristics betw een a dum my via and a real via. R efer to the f o llow ing s ection for m ore information on via compensation . 2.7.
Intel ® 820E Chipset R Design Guide 53 Table 8. Line Matching and Via Compensa tion E xample 1,2,3,4,5,6,7,8,9,10 Signal Ball on MCH Nomin al RSL Length (mils) Package Dimen sion (mil s) Motherboard Trace Length When Routed on Bottom (i.e., Real Vi a) Motherboard Trace Length When Routed on Top (i.
Intel ® 820E Chipset R 54 Design Guide 2.7.3. Direct RDRAM* Reference Volt age The Direc t RDRAM re ferenc e volta ge (RAMRE F) must be gene rate d as sho wn in Figure 32. The RAMREF should be generated from a typical resistor divider using 2%-tolerance resistors.
Intel ® 820E Chipset R Design Guide 55 Figure 33. High- Speed CM OS Termin ation high_spd_cmos_term MCH RIMM _ 0 RIMM _ 1 91 Ω Vterm 39 Ω R1 R2 2.7.4.1. SIO Routing The SIO signal m ust be routed f rom R IMM to RIMM, as sh ow n in Fig ure 34. The SIO sign al requires a 2.
Intel ® 820E Chipset R 56 Design Guide 2.7.4.2. Suspend-to-RA M Shunt Transistor When an In tel 820E chipset sy stem enters or exits Suspend to RA M, pow er w ill be rampin g to the MCH (i.e., it will be pow ering up or po w ering dow n). W hile power is ram ping, the states of the MCH outputs are not guaran teed.
Intel ® 820E Chipset R Design Guide 57 2.7.5. Direct RDRAM* Clock Routi ng Refer to Chapter 4 C locking for the Intel 820E ch ipset platform ’s Direct RDR AM clock routin g guide lines. 2.7.6. Direct RDRAM* Design Checkl i st Use the follow ing checklis t as a fin al check to en sure that th e moth erboard incorporates solid desi gn practices.
Intel ® 820E Chipset R 58 Design Guide If any RSL sig nals are rout ed, even f o r a short dist ance, out of the last R IMM (tow ards termin ation) on the bottom side, ensure th at the ground reference plane (on the th ird layer) is continuous u nder the term ination resistors/cap acitors.
Intel ® 820E Chipset R Design Guide 59 All RSL signals are routed adjacent to a grou nd reference plane. This includes all s ignals f rom the last RIMM to the term ination.
Intel ® 820E Chipset R 60 Design Guide 2.8. A GP 2.0 For detailed AGP interface fun ctionality (e.g ., protocols, rules, signaling m echanisms), ref er to Revision 2.0 of th e latest AGP In terface Specification obtainable from h tt p : / / www.a g p fo r u m.
Intel ® 820E Chipset R Design Guide 61 Signal Gr oups • 1 × timin g domain CLK (3.3 V) RBF# WBF# ST[2:0] PIPE# REQ# GNT# PAR FRAME# IRDY# TRDY# STOP.
Intel ® 820E Chipset R 62 Design Guide Table 10. AGP 2.0 Data/Strobe Associations Data A ssociated S trobe in 1× A ssociated Strobe in 2× A ssociated S trobes in 4× AD[15:0] and C/BE[ 1:0]# Strobes are not used in 1 × m ode. All data is sam pled on rising c lock edges .
Intel ® 820E Chipset R Design Guide 63 5.8 inches long. An other st robe set (e.g ., SB_STB and SB_STB#) could be 4.2 inch es long, and th e data sign als associated w ith those strobe si gnals (e.g ., SB A[7:0]) can be 3.7 in ches to 4.7 inches long .
Intel ® 820E Chipset R 64 Design Guide The strobe sig nals (AD_S TB0, AD_STB0#, AD_S TB1, AD_STB1#, SB_STB, and SB_STB#) act as clocks on th e source-syn chronous AGP interf ace. T herefore, special care m ust be taken w hen routing these sig nals. Because each strobe pair is tru ly a differen tial pair, the pair should be routed tog ether.
Intel ® 820E Chipset R Design Guide 65 2.8.5. A GP Clock Routing The maxi mu m total AGP clock sk ew (betw een the MCH an d the graphics com ponent) is 1 n s for all data transfer m od es. This 1 ns includes skew and jitter that or iginates on th e motherboard, add-in card, and cloc k synthesizer .
Intel ® 820E Chipset R 66 Design Guide Figure 37. Top Signal La yer Ground Reference It is strong ly recomm ended that, at a min im um , the follow ing critical sign als be referenced to ground from .
Intel ® 820E Chipset R Design Guide 67 Note: T he m otherboard provides 3.3 V to th e V CC pins of the AG P connector. If th e graphics controller needs a low er voltage, then the add-in card mu st regulate the 3.3 V V CC voltag e to the controller’s requirem ents.
Intel ® 820E Chipset R 68 Design Guide Figure 38. A GP V DDQ Gener ation Example Circuit SHDN IPOS VIN INEG GND GATE FB COMP C1 1 k Ω 47 µ F 10 pF 7.5 k Ω C2 5 Ω R3 R4 C3 O O O +12V +3.3V VDDQ R1 1 µ F TYPEDET # U1 LT1575 1 2 3 4 5 6 7 8 C5 R5 C4 R2 301 Ω 1.
Intel ® 820E Chipset R Design Guide 69 Durin g a 3.3 V AGP 2.0 operation , V REF mus t be 0.4 V DDQ . How ever, durin g a 1.5 V A GP 2.0 operation, V REF mu st be 0.5 V DDQ . This requires a flexible voltage divider f or V REF . Variou s meth ods of accomplish ing th is exist, su ch as the ex ample in the follow ing figu re.
Intel ® 820E Chipset R 70 Design Guide 2.8.9. Compensation The MCH AGP interf ace supports res istive bu ffer com pensation (RCOMP). Tie the GRCO MP pin to a 40 Ω, 2% (or 39- Ω , 1%) pull- dow n resis tor (to groun d), via a 10 mil- w ide, very short (<0.
Intel ® 820E Chipset R Design Guide 71 2.8.10.1. AGP Signal Voltage Tolerance List The follow ing s ignals on the A GP interface are 3.3 V toleran t during a 1.
Intel ® 820E Chipset R 72 Design Guide 2.8.12. A GP Universal Retention Mechanism (RM ) Environm ental testing and field reports indicate that, w ithout prop er retention, AGP cards and A GP In-L ine Memory Module (AIMM) cards may com e unseated durin g system shipping an d handling.
Intel ® 820E Chipset R Design Guide 73 Figure 41. A GP Left-Handed RM Keep-Out Information Recom men d ed for all AG P cards, the AGP RM is detailed in Eng ineering Change Reques t No. 48 (ECR #48), w hich detai ls approved ch anges to the Acceler ated Graphics Port ( AGP) Interface Specification , Revisio n 2.
Intel ® 820E Chipset R 74 Design Guide 2.9. Hub Interface The MCH and ICH2 ballout assign ments hav e been optim ized to simplify the hub interface routin g betw een these dev ices. It is recom mended that the h ub interface signals be routed directly from the MCH to ICH2, with all sig nals referenced to V SS .
Intel ® 820E Chipset R Design Guide 75 2.9.1. 8-Bit Hub Interface Routing Guidelines This section docum ents the routing guidelin es for the 8- bit hub interface. This hub interf ace connects the ICH2 to the MCH. This in terface supports tw o buffer m odes: normal and en hanced.
Intel ® 820E Chipset R 76 Design Guide Table 16. 8-Bit Hub Interface HUBREF Generation Circuit Specifications Buffer Mo de HUBREF V oltage S p eci ficatio n (V ) Recommended Resi stor Valu es for the.
Intel ® 820E Chipset R Design Guide 77 2.9.1.4. 8-Bit H ub Interface Compensation The hub interf ace uses a com pensation sign al to adjust buf fer characteris tics to the specif ic board characteristic. The hub in terface requires resistive com pensation (RCOMP).
Intel ® 820E Chipset R 78 Design Guide 2.10.1. Sy stem Bus Ground Plane Refer e nce All sy stem bus signals m ust be referenced to GND to provide the optimal current retu rn path. The ground reference m ust be continu ous from the MCH to the Intel PGA370 s o cket.
Intel ® 820E Chipset R Design Guide 79 A ddit i onal Considerati ons • Distribute V TT w ith a w ide trace. A 0.050 inch m inimu m trace is recomm ended to min im ize DC losses. Ro ute the V TT trace to all components on the host bus. Be su re to include decoupling capacitors.
Intel ® 820E Chipset R 80 Design Guide 2.12.1. Cable Detection for Ultra A TA /66 and Ultra A TA / 100 The ICH2 IDE controller su pports PI O, m ultiw ord (8237-style) DMA , and Ultra DMA modes 0 thro ugh 5.
Intel ® 820E Chipset R Design Guide 81 Figure 46. Combin ation Host- Side/Device-Side IDE Cable Detect ion 80-cond uctor IDE cabl e IDE dri ve 5 V ICH2 GPIO GPIO Open IDE d rive 5 V 40-con ductor cable IDE d rive 5 V PDIAG# ICH2 GPIO GPIO IDE d rive 5 V Resistor required for non-5V-tolerant GPI.
Intel ® 820E Chipset R 82 Design Guide 2.12.3. Device-Side Cable Detection For platform s that m ust implem ent device-side detection only (e.g., N LX plat form s), a 0.047 µF capacitor is required on the motherboard, as show n in the followin g figure.
Intel ® 820E Chipset R Design Guide 83 2.12.4. Primary IDE Connector Requirements Figure 48. Conne ction Requirements for Primar y IDE Connector PCIRST# * PDD[15:0] PDA[2:0] PDCS1# PDCS3# PDIOR# PDIOW # PDDREQ PIORDY IRQ1 4 PDDACK# GPIOx ICH2 Prim ary IDE Connector IDE_pri mary_conn_r equi re Reset# PDIAG# / CBLID# N.
Intel ® 820E Chipset R 84 Design Guide 2.12.5. Secondar y IDE Connector Requi rements Figure 49. Conne ction Requirements for Seconda ry IDE Connector PCIRST # * SDD[15:0] SDA[2:0] SDCS1# SDCS3# SDIOR# SDIOW # SDDREQ SIORDY IRQ1 5 SDDACK# GPIOy ICH2 Secondary IDE Connector IDE_ secondar y_conn_r equire Reset# PDIAG# / CBLID# N.
Intel ® 820E Chipset R Design Guide 85 2.13. A C’97 The ICH2 implem ents an A C’97 2.1- complian t digital cont roller. Any codec attached to the ICH2 AC- link also mu st be A C’97 2.1 com pliant. Please contact y our codec IHV for inf ormation on 2.
Intel ® 820E Chipset R 86 Design Guide Clocki ng i s provided f rom the prim ary codec on th e link via BITCL K, and is derived f rom a 24.576 MHz crys tal or oscillator. Ref er to the prim ary codec vendor f or the cry stal or oscillator requirem ents.
Intel ® 820E Chipset R Design Guide 87 Figure 51. CDC_DN_ENA B# Support Circuitry for a S i ngle Codec on Motherboard Codec A RESET# SDATA_IN Co dec C RESET# SDATA_IN AC 97_RESET# Vcc CDC_DN_ENAB# CN.
Intel ® 820E Chipset R 88 Design Guide Figure 52. CDC_DN_ENA B# Support Circuitry for M ulti-Channel A udio Upgrade Primary A udio Codec RESET# SD AT A_I N A udio Codec RESET# ID0# SD AT A_I N A C97_.
Intel ® 820E Chipset R Design Guide 89 Figure 54. CDC_DN_ENA B# Support Circuitry for Tw o-Codecs on Motherboard / T wo-Codecs on CNR Codec A RESET# SD AT A_ IN Codec C RESET# SD AT A_I N A C97_RESET.
Intel ® 820E Chipset R 90 Design Guide Valid Codec Confi gurat ions Table 19. Codec Configura tions Valid Codec Configurations Invalid Codec Configurations AC(Prim ary) MC(Prim ary) + X(any other typ.
Intel ® 820E Chipset R Design Guide 91 2.13.3. A C’97 Routing To ensure the m aximu m perf ormance of th e codec, proper component placem ent and routing techniqu es are required.
Intel ® 820E Chipset R 92 Design Guide 2.13.4. Motherboard Implementation The follow ing des ign con siderations are provided for the im plementation of an IC H2 platform using AC’ 97. T hese design gu id elines have been developed to ensure m aximum flexibility for board designers, w hile reducing the risk of board-related iss ues.
Intel ® 820E Chipset R Design Guide 93 Figure 56. USB Da ta Signals 15k 15k 15 Ω Ω Ω Ω 15 Ω Ω Ω Ω ICH2 P+ P- USB Connector < 1" < 1" 90 Ω 45 Ω 45 Ω Driver Driver.
Intel ® 820E Chipset R 94 Design Guide 2.16. I/O A PIC Design Recommendation UP system s not using th e integrated I/O APIC should co mply with the f ollowing recom mendations: • On the ICH2 Connec t PI CCLK dir ectl y to ground . Connec t PI CD0 and PI CD1 to ground thro ugh a 10 k Ω resistor.
Intel ® 820E Chipset R Design Guide 95 Figure 57. SM BUS/SM Link Int erface 82801B A ICH2 Ho st con troll er slave i nter fac e SMBus SMBC LK SPD da ta Temperature on ther ma l s ensor Networ k inter.
Intel ® 820E Chipset R 96 Design Guide 2.18. PCI The ICH2 provides a PCI Bus in terface that is compliant w ith the PCI Local Bus Specification , Revision 2.2. The implem entation is optimized f or high-perform ance data streamin g w hen the ICH2 acts as eith er the target or the initiator on th e PCI bus.
Intel ® 820E Chipset R Design Guide 97 2.19.1. RTC Cry stal The ICH2 RTC m odule requires an extern al 32.768 kHz oscillatin g source con nected on the RTCX1 and RTCX2 p ins. The follow ing fi gure show s the external circuitry th at co mprises the oscillator of the ICH2 RTC.
Intel ® 820E Chipset R 98 Design Guide 2.19.3. RTC Lay out Considerations • Minim ize the RTC lead lengths. A pproximately 0.25 inch is s uff icient. • Minim ize the capacitance between Xin and Xout in the routin g. • Put a ground plan e under the XTAL components.
Intel ® 820E Chipset R Design Guide 99 A st andby power suppl y shou ld be used i n a desk top sy stem to prov ide continuou s pow er to the RTC wh en available, which w ill significantly increase the RTC b attery lif e and thereby in crease the RTC accuracy .
Intel ® 820E Chipset R 100 Design Guide 2.19.6. RTC Routing Guidelines • All RTC OSC s ignals (RTCX1, RTCX2, VBIAS) sh ould be routed w ith trace length s of less than 1 inch. The shorter, the better. • Minim ize the capacitance between RTCX1 and RTCX2 in th e routing .
Intel ® 820E Chipset R Design Guide 101 logic low. When the jumper is not populated, a low can still be read on the signal line if the effective impedan ce due to the speak er and codec circuit is equal to or less th an that of the integ rated pull-up resistor.
Intel ® 820E Chipset R 102 Design Guide Interr upts B , D, E, and H se rvice d evices i nternal to the ICH 2. Inte rrup ts A, C, F, and G are unuse d and can be used by PCI slots. The follow ing figu re show s an exam ple of IRQ line routing to the PCI slots .
Intel ® 820E Chipset R Design Guide 103 Figure 64. ICH2 / LAN Connect Section ICH2_LAN_connect Dual footpri nt Intel ® 82562EH/825 62ET ICH2 Magnetics module Connec tor A B D C Refer to Intel 82562EH/825 62ET section Table 22.
Intel ® 820E Chipset R 104 Design Guide 2.22.1.1. Bus Topologies The LAN C onnect Interf ace can be configured in s everal topologies, as follow s: • Direct point-t o-point con nection betw een the ICH2 and th e LAN compon ent • Dual f ootprint (see Section 2.
Intel ® 820E Chipset R Design Guide 105 Figure 66. LOM/CNR Interconnect IO_subsys_LOM-CNR_inte rcomm ICH2 Res. pack CNR PLC card B A PLC C D Table 23. Length Require ments for Figure 66 Config uration A B C D Intel ® 82562EH 0.5” to 6” 4” t o (10” – A) Intel ® 82562ET 0.
Intel ® 820E Chipset R 106 Design Guide Figure 67. LA N_CLK Routing Example LA N_ RXD0 LA N_CLK 2.22.1.5. Crosstalk Consideration Crosstalk -induced n o ise m ust be caref ully minim ized. Crosstalk is the prin cipal cause of tim ing skew s and is the largest part of the t RM ATCH sk ew parameter.
Intel ® 820E Chipset R Design Guide 107 2.22.2. Gener al LAN Routing Guidelines and Considerati ons 2.22.2.1. General Trace Routing Considerations Trace routing cons iderations are im portant to min im ize the eff ects of crosstalk an d propagation delay s on board sections w here high -speed s ignals exist.
Intel ® 820E Chipset R 108 Design Guide 2.22.2.1. 1. Trace Geometry and Length The key f actors in controlling trace EMI radiation are the trace leng th and th e ratio of trace w idth to trace heigh t above the g round plane.
Intel ® 820E Chipset R Design Guide 109 Figure 69. Ground Plane Separ ation Separate Ch assis Ground Plane Good groun d ing requires t he m inimizat ion of i nductan ce levels in th e interconnecti ons.
Intel ® 820E Chipset R 110 Design Guide 2.22.2.3. 4-Layer Board D esign Top-Lay er Rout i ng Sensitive an alog signals are routed com p letely on th e top layer w ithout the use of vias. This allow s tight control of signal integ rity and rem oves any im p edance inconsistencies due to lay er changes.
Intel ® 820E Chipset R Design Guide 111 should be k ept at least 0.3 inch from the nearest receive trace. Possible exception s are only where the traces enter or ex it the magnetics , the RJ-45/11, an d the PLC. 6. Use of an inferior m agnetics m odule .
Intel ® 820E Chipset R 112 Design Guide 2.22.3. Intel ® 82562EH Home/PNA * Guidelines Table 24. Relat ed Documents Title Doc # Intel ® 82562EH Hom ePNA 1-Mbit/ s Physi cal Layer Int erface P roduct.
Intel ® 820E Chipset R Design Guide 113 For noise-f r ee and stable operation , place the cry stal and associated discretes as clos e as possible to th e Intel 82562EH com ponent, keepi ng th e length as short as possible. Do not rout e any noisy s ign als in this area.
Intel ® 820E Chipset R 114 Design Guide 2.22.3.5. Critical Dimensions As s how n in the follow ing figu r e, there are three dim ensions to cons ider during layou t: Distance B, from the line RJ11 co.
Intel ® 820E Chipset R Design Guide 115 2.22.3.5. 3. Dist ance f r om LPF t o Phone RJ11 Distance ‘ C’ sh ould be less than 1 inch . Regarding trace sy mmetry , route differen tial pairs w ith consistent separation and w ith exactly th e same len gths an d physical dim ensions.
Intel ® 820E Chipset R 116 Design Guide 2.22.4.2. Crystals and Oscillators To minim ize the effects of EMI, clock sources sh ould not be placed n ear I/O ports or board edges. Radiation from thes e devices may be coupled onto th e I/O ports or out of t he sy stem ch assis.
Intel ® 820E Chipset R Design Guide 117 Figure 73. Critical Dimensions for Component Placement Intel® 82562ET / 82562EM B A ICH2 EEPROM Magnetics Mod u l e Line RJ45 crit _dim_comp_plac Distance Prio rity Gui deline A 1 <1 inch B 2 <1 inch 2.22.
Intel ® 820E Chipset R 118 Design Guide 2.22.4.4. 2. Distance fr om t he Intel ® 82562ET Component to t he Magnetics Module Distance ‘ B’ in Figu re 73 also should be design ed to be less than 1 inch between devices.
Intel ® 820E Chipset R Design Guide 119 Figure 74. T ermination Plan e N/C RJ-45 Magnetics Module RDP RDN TDP TDN Termination Plane Additional capacitance that may need to be added for EFT testing term_plane 2.
Intel ® 820E Chipset R 120 Design Guide There are four pin s whic h are us ed to put th e Intel 82562ET/EM controller in diff erent operati ng s tates: Test_En, Isol _Tck, Isol_Ti, and Isol _Tex. The table below describes the operati onal/dis able features f or this design.
Intel ® 820E Chipset R Design Guide 121 Figure 77. Dua l-Footprint Ana log Interfac e IO_subsys_dual_footpr i nt_analog_ IF Magnetics module TDP RJ45 Intel ® 82562EH/8 2562ET TDN RDP RDN RJ11 TXP TXN Tip Ring Intel 82562EH config. Intel 82562ET config.
Intel ® 820E Chipset R 122 Design Guide • Traces from m agnetics to con nector m ust be shared and n o t stubbed. A n RJ-11 connector th at fits into the RJ-45 slot is available. Any amount of stubbing will destroy b oth HomePNA* and Ethernet perform ance.
Intel ® 820E Chipset R Design Guide 123 Figure 78. De coupling Capacitor Layout 3.3 V Core 1.8 V Core 1.8 V Standby 3.3 V Standby 3.3 V Core 1.8 V Standby 5 V Ref ICH2_de coupling_cap The previous f igure show s the layou t of th e ICH2 decoupling capacitors for various pow er planes around the ICH2.
Intel ® 820E Chipset R 124 Design Guide 2.23. FWH Flash BIOS Guidelines The general com p atibility g uidelines and the desi gn recom mendations f o r supportin g the FWH Flash BIOS device are discussed next. Most changes w ill be incorpo rated into the BIOS.
Intel ® 820E Chipset R Design Guide 125 2.24. ICH2 Design Checklist Thi s checkl ist highlight s desi gn consid era tions t hat shoul d be revie wed befo re manufac turing a n Intel 820E chipset- based motherboard t hat im plement s an IC H2.
Intel ® 820E Chipset R 126 Design Guide Table 27. Hu b Interface Checklist Item s Recommendations Reason/Effect HL[11] No pull-up resis tor is requi red. Use a no-st uff or a tes t point t o put the ICH2 into NA ND chain m ode test ing. HL_COMP Tie the COMP pin to a 40 Ω , 1% or 2% (or 39 Ω , 1%) pul l-up resis tor (to 1.
Intel ® 820E Chipset R Design Guide 127 Table 31. In terrupt In terface Checklist Item s Recom m endations Reason/Effect PIRQ#[D: A] These si gnals require a pull -up resist or. A 2.7 k Ω pull-up resi stor to V CC 5 V or an 8.2 k Ω pull-up resisto r to V CC 3.
Intel ® 820E Chipset R 128 Design Guide Table 32. G PIO Checklist Item s Recommendations Reason/Effect GPIO pins GPIO[0:7]: • These pi ns are in the m ain power well. Pull-ups m ust use the 3.3 V plane. • Unused core well inputs m ust eit her be pulled up to VCC3.
Intel ® 820E Chipset R Design Guide 129 Table 34. Power Management Checklist Item s Recommendations Reason/Effect THRM# Connect t o temperat ure sensor. Pull-up if not used. Input to I CH2 cannot f loat. THRM# polarity bit defaults THRM# to acti ve low, so p ull-up .
Intel ® 820E Chipset R 130 Design Guide Table 36. System M anagement Checklist Item s Recommendations Reason/Effect SMBDATA SMBCL K Requires external pull-up res istors to 3.3 V or 3.3 V st andby. Value of pull -up resist ors is det ermined by the line load.
Intel ® 820E Chipset R Design Guide 131 Table 39. Miscellaneous Signals Checklist Item s Recommendations Reason/Effect SPKR No extra pull-up resistors Effec tive im pedance due to s peaker and codec c ircuit ry must be greater than 50 k Ω , or a m eans to is olate the res istive load from the signal while PW ROK is low mus t be found.
Intel ® 820E Chipset R 132 Design Guide Figure 73. 5V REF Circuitry Vcc s upply (3.3 V) 5 V supply To sy stem To sy stem Vref sys_des_5Vref_circ 1 µ F 1 k Ω Table 41. IDE Ch ecklist Checklist Item s Recommendati ons Reason/Effect PDD[15:0] , SDD[ 15:0] No extra series term ination res istors or other pull-ups /pull-downs are required.
Intel ® 820E Chipset R Design Guide 133 Checklist Items Recommendations Reason/Effect Cable Detect * • Host S ide/Devic e Side Detec tion: Connec t the IDE pin PDIA G/CBLID to an ICH2 GPI O pin. Connect a 10 k Ω resis tor to GND on t he signal line.
Intel ® 820E Chipset R 134 Design Guide 2.25. ICH2 Lay out Checklist Table 43. 8- Bit Hub Int erface # Lay out Recommendations Yes No Comments 1 Board im pedance m ust be 60 Ω ± 10% .
Intel ® 820E Chipset R Design Guide 135 Table 46. L A N Con nect I/F # Lay out Recommendations Yes No Comments 1 Stack -up: 5 m ils wide, 10 m il spac ing 2 Z 0 = 60 Ω ± 15% Signal integrit y requirement 3 LAN m ax. trace length, ICH2 to CNR : L = 3 inches t o 9 inches (0.
Intel ® 820E Chipset R 136 Design Guide # Lay out Recommendations Yes No Comments 20 Isolat e I/O s ignals from high-speed s ignals. To mi nimize c rosst alk 21 Place t he 82562ET/EM part m ore than 1.5 i nches from any board edge. This minim izes the potential of EMI radiation problem s.
Intel ® 820E Chipset R Design Guide 137 Table 49. CK- SKS Clocking # Lay out Recommendations Yes No Comments 1 CLK_33 goes to I CH2, FW H FLAS H BIOS, and SIO. Clock c hip to seri es resis tor = 0.5 inc h, and from series res istor t o receiver = 15 inc hes max.
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Intel ® 820E Chipset R Design Guide 139 3. Advanced System Bus Design Section 2.10 des cribes the recom men dations for desi gnin g Intel 820E chi pset-bas ed platforms . This section di scus ses in m o re detail th e methodolog y used to dev elop the advanced s ys tem bus guideli nes.
Intel ® 820E Chipset R 140 Design Guide Term De finition Flight tim e Flight tim e is a timing equation term that includes the signal propagation delay, any effects of the sy stem on the T CO of the driv er, plus an y adjus tmen ts to the signal at the receiver n eeded to guaran tee the setup tim e of the receiver.
Intel ® 820E Chipset R Design Guide 141 Term De finition Simultan eous switching output (SSO) effects Difference in electrical timing parameters an d degradation in signal quality caused by m ultiple signal outputs simultaneously switching voltage levels (e.
Intel ® 820E Chipset R 142 Design Guide 3.2.1. In itial Timing A naly sis Perform an initial tim ing analy sis of the sy stem using th e follo w ing tw o equations, which are th e b asis for timin g analy sis.
Intel ® 820E Chipset R Design Guide 143 A designer u sing com p onents other than those listed previously m ust evaluate additional combinations of driver and receiv er.
Intel ® 820E Chipset R 144 Design Guide The following tw o tables were derived assum ing the followin g: • CLK SKE W = 0.2 ns Note: This assumes that clock driver pin-to-pin skew is red uced to 50 ps by tying tw o host clock outp uts toge ther ( “ganging”) at the c loc k drive r out put p ins, and the P CB cl ock r outing ske w is 150 ps.
Intel ® 820E Chipset R Design Guide 145 Table 53. Examp le T FLT_MIN Calculations 1 (Frequenc y Indepe ndent) Driver Receiver THOLD ClkS KEW T CO_MIN Recommended TFLT_MIN Process or 2 Proces sor 2 0.8 0.2 -0.1 1.2 Process or 2 Intel ® 82820 M CH 0.28 0.
Intel ® 820E Chipset R 146 Design Guide 3.2.3.3. Monte Carlo A naly sis Perform a Monte Carlo A nalysis to ref ine the passing solution s pace region. A Monte Carlo Analy sis involves ran domly varying param eters independently of one an other, over their tolerance ran ges.
Intel ® 820E Chipset R Design Guide 147 The transm ission line packag e models mu st be inserted betw een the ou tput of th e buffer and the n et it is driving . Likew ise, the packag e model m ust also be placed betw een a net and the inpu t of a receiver model .
Intel ® 820E Chipset R 148 Design Guide AGTL+. Intragrou p AGTL+ crosstalk involv es interference betw een AGTL+ signals w ithin the sam e group. (S ee Section 3.
Intel ® 820E Chipset R Design Guide 149 Figure 74. PICD[1,0] Uniprocessor Topology ICH2 Intel ® PGA37 0 Z 0 = 60 Ω ± 15% 1.5 150 Ω picd_uniprocessor_topo Figure 75. PICD[1,0] Dual-Processor Topology ICH2 Intel® PG A370 Z 0 = 60 Ω ± 15 % 1.5 V 300–330 Ω Intel PG A370 1.
Intel ® 820E Chipset R 150 Design Guide 3.2.5.2. Crosstalk A naly sis AGTL+ cross talk si mu lations can consider as n o n-cou p led the process or core package, the In tel 82820 MCH package, an d the Intel PGA370 socket. Sim ulate the traces as loss less f or wors t-case cross talk and lossy where m ore accuracy is n eeded.
Intel ® 820E Chipset R Design Guide 151 Figure 76. T est Load v s. A ct ual System Load V TT Q Q SET CLR D Vcc CLK R TEST Test load Driver pin Driver pad T REF T CO I/O Buffer Q Q SET CLR D Vcc CLK D.
Intel ® 820E Chipset R 152 Design Guide 3.3. Theory 3.3.1. A GTL+ AGTL+ is th e electrical bus techn o logy used for the processor bus . This is an inciden t wave sw itching, open-drain bus w ith external pull- up resistors that provide both the high logic level an d termination at each load.
Intel ® 820E Chipset R Design Guide 153 3.3.3. Crosstalk Theory AGTL+ si gnals swing acro ss a smaller volta ge range and ha ve a co rre spond ingly smaller no ise margin than techn ologies traditionally us ed in personal computer designs , so designers using AGT L+ m ust be more aw are of crosstalk th an they m ay have been in prev ious desig ns.
Intel ® 820E Chipset R 154 Design Guide Additional aggressors are possible in the z-direction, if adjacent sign al layers are not routed in m utually perpendicular direction s.
Intel ® 820E Chipset R Design Guide 155 3.4. More Details and Insight 3.4.1. Textbook Timing Equati ons The “tex tbook” equa tions u sed to calculate th e propagation rate of a PC B are the basi s for spreads heet calculations of tim ing margin b ased on the componen t parameters.
Intel ® 820E Chipset R 156 Design Guide 3.4.2. Effectiv e Impedance and Tolerance/Variation The impedan ce of the PCB m ust be controlled w hen the PCB is fabricated. The best impedan ce control specification m ethod for each situ ation m ust be determined.
Intel ® 820E Chipset R Design Guide 157 3.4.3.2. Reference Planes and PCB St ack-Up It is strongly recom mended that bas eboard stack-up be arrang ed such that A GTL+ sign als are refe renc ed to a gro und ( V SS ) plane, and that the A GTL+ signals do not traverse m ultiple signal layers.
Intel ® 820E Chipset R 158 Design Guide Figure 81. Layer Sw itch w ith M ultiple Ref erence Planes (Same T ype) lay_sw_m ult_refplane Signal Layer A Signal Lay er B Lay er Lay er Ground Plane Ground .
Intel ® 820E Chipset R Design Guide 159 Figure 83. On e Layer with M ult iple Reference Planes 1lay_Mult_refplane Ground Signal Layer A Power 3.4.3.3. High-Frequency Decoupling Thi s secti on co ntains seve ral high-freq uency dec oup ling rec ommendati ons that will improve the re turn path for an A GTL+ signal.
Intel ® 820E Chipset R 160 Design Guide 3.4.4. Clock Routing Analog sim ulations are required to ensure that th e clock net signal quality and skew are acceptable. The sy stem clock skew must be mi nim ized. (The calculations and sim ulations for the ex ample topology in this docum ent have a total clock skew of 200 ps and 150 ps of clock jitter).
Intel ® 820E Chipset R Design Guide 161 3.5.1. V REF Guard Band To account for noise sou rces that m ay affect th e w ay an AGTL+ sig nal becomes valid at a receiv er, V REF is shifted by ∆ V REF for measuri ng the minimum and maximum flight times.
Intel ® 820E Chipset R 162 Design Guide 3.5.4. Flight Time Definition and Measurement Timing meas urem ents consist of m inimu m an d max imum flight times , to take into accou nt the f act that devices can turn on or off an yw here in a V REF guard ba nd re gion.
Intel ® 820E Chipset R Design Guide 163 4. Clocking 4.1. Clock Generation Two clock gen erator com ponents are required in an Int el 820E chips et-base d sy stem . T he Direct RDRA M clock generator (DRCG) g enerates clock f or the Direct RDRAM interf ace, while the C K133 compon ent generates clocks f o r the rest of the system .
Intel ® 820E Chipset R 164 Design Guide The MCH uses th e sam e clock for h ub interface an d AGP. It is im portant that the hub in terface/A GP clocks are rout ed so as to ensu re that the skew requ.
Intel ® 820E Chipset R Design Guide 165 Table 56. In tel ® 820E Chipset Platf orm Clock Skew s Clock Symbols (see Figure 86) Relationship Skew Notes P i n-to-Pin (p s) Board (ps) Total (ps) Min.
Intel ® 820E Chipset R 166 Design Guide The follow ing fig ure show s the In tel 820E chipset clock l engt h routi ng g uidelines. Figure 87. Inte l ® 820E Chipset Clock Rout ing Guidelin es 1,2 Note: 1. Tie 3V66 clock for MCH to 3V 66 clock for AGP connector, to eliminate pin-to-pin skew.
Intel ® 820E Chipset R Design Guide 167 Table 57. In tel ® 820E Chipset Platf orm System Clock Cross-Reference CK133/DRCG Pin Nam e Component Pin Name PCICLK PC I slo t CLK PCI slot CLK PCI slot CLK.
Intel ® 820E Chipset R 168 Design Guide 4.2. Component Placement and Interconnection Lay out Requirements The layout requ iremen ts for each interconnection are explained in detail in the f ollowi ng section s: • Crystal to CK133 • CK133 to D RCG • MCH to DRCG • DRCG to RDRAM channel 4.
Intel ® 820E Chipset R Design Guide 169 4.2.3. MCH to DRCG • Pclk M • Pclk N • VddIPD Figure 89. MCH-to-DRCG Routing Diagram Ground Ground/P owe r Plane 6 mils 4.
Intel ® 820E Chipset R 170 Design Guide 4.2.4. DRCG-to-RDRA M Channel The Direct RDRA M clock sig nals (C TM/CTM# and CFM/CFM#) are h igh- speed, impedance-m atched transm ission lines.
Intel ® 820E Chipset R Design Guide 171 For line section D (DRCG to last RIMM), the CTM/CT M# must be leng th-m atched within ±2 m ils. (Exact m atching is recom mended.) For section C , ±2 mi l trace length match ing is required for th e CFM/CFM# signa ls.
Intel ® 820E Chipset R 172 Design Guide 4.3. DRCG Impedance Matching Circuit The external DRCG im pedance matchin g circuit is show n in the follow ing f igure .
Intel ® 820E Chipset R Design Guide 173 4.3.1. DRCG Lay out Example Figure 95. DRCG Layout Example Rs - 39 Ω (Keep trace from DRCG to Rs VERY sh ort) Rp - 51 Ω (Keep trace from Rs to Rp short) CTM/CT M# route on bottom layer Cmid - 100pF EMI Cap - 4pF Do Not Stuff Decoupling C ap - 0.
Intel ® 820E Chipset R 174 Design Guide 4.7. Unused Outputs All unused c lock o utputs must be tied to gro und thr ough a ser ies re sistor that has a ppr oximatel y the impedance of th e output buffer (sh o w n in the f ollowin g table). These resistors are designed to terminate unused o utputs to eliminate EMI.
Intel ® 820E Chipset R Design Guide 175 4.9. DRCG Frequency Selection and the DRCG+ 4.9.1. DRCG Frequency Selecti on Table and Jitter Speci fi cation To pr ovide additional flexibility in board design, Intel h as enabled a variation of the DRCG, called the DRCG+ .
Intel ® 820E Chipset R 176 Design Guide 4.9.2. DRCG+ Frequency Sel ecti on Schematic The DRCG+ frequ ency can be selected using tw o GPIOs connected to the MUL T [0:1] pins, as sh own in the f ollow ing fig ure. This al low s selection of all frequ encies support ed by t he Int el 820E chips et.
Intel ® 820E Chipset R Design Guide 177 5. System M anufacturing 5.1. Stack-Up Requirement The Intel 820E ch ipset plat form requires a board stack- up with a 4.5 mil prepreg. This chang e in dimen sion (previously , typically 7 mils ) is required becau se of th e sign aling en vironm ent used for th e Direct RDRA M, AGP 2.
Intel ® 820E Chipset R 178 Design Guide 5.1.2. Design Process To meet th e tigh t tolerances required, a good des ign process is as follows: • Specify the material to be used. • Calculate th e board geometries for th e desired impedance or us e the example st ack-u p provided.
Intel ® 820E Chipset R Design Guide 179 5.1.4. Recommended Stack-Up Tho ugh numerous sta ck-up var iati ons ar e po ssible , the fo llowing star ting po int is r ecommended : W = 18 mi ls, H = 4.5 m ils, T = 2.0, 1-ply 2116 prepreg For other possibilities see the following table and the f ollowing figures: Table 61.
Intel ® 820E Chipset R 180 Design Guide Figure 98. M icrostrip (a) and St ripline (b) Cross Section f or 28 Ω Ω Ω Ω Trace G G 4.5 mils 2.1 mils 6 mils 18 mils 10 mils S a) Microstrip cross section for 28- Ω trace b) Stripline cross section for 28- Ω trace G G 5 mils 1.
Intel ® 820E Chipset R Design Guide 181 5.1.7. Testing Board I mpedance The Intel Print ed Cir cuit Boar d (PCB) Test Methodol ogy document ( order# 298179-001) sh ould be used to ensure boards are with in the 28 Ω +/- 10% requirem ent. This docum ent can be found at http://developer.
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Intel ® 820E Chipset R Design Guide 183 6. System Design Considerations 6.1. Pow er Delivery 6.1.1. Terminol ogy and Definitions Term Definition Suspend to RAM (S TR) In the STR state, th e sy stem state is stored in main m emory and all unnecess ary system logic is turned off.
Intel ® 820E Chipset R 184 Design Guide 6.1.2. Pow er Delivery of Intel ® 820E Chipset Customer Reference Board Figu r e 101 show s the pow er delivery architect ure for th e Intel 820E Chipse t Ref erence Board. This pow er delivery architecture su pports the Instan tly Av ailable PC Desig n Gui delines v ia the Suspen d-to- RAM (STR) state.
Intel ® 820E Chipset R Design Guide 185 This desig n guide provi des only exampl es. Many power dis tributi on m ethods achiev e sim ilar results . When devi ating f rom th ese exam ples in any w ay, it is critical to consider the ef fects of the chan ge.
Intel ® 820E Chipset R 186 Design Guide 2.5 VBSY The 2.5 V SBY power plane is u sed to pow er the RDRAM core an d the VCMOS rail on the RDR AMs. The RDRA M core requires an approxim ately 4.5-A maximum averag e DC cu rrent at 2.5 V. In the Intel 820E chipset ref erence board, the 2.
Intel ® 820E Chipset R Design Guide 187 Figure 102. 1.8 V and 2.5 V Power Seq uencing ( Schottky Diode) 1.8 V 2.5 V diod e_1. 8V&2.5V V DDQ The V DDQ plane is used to pow er the MCH A GP interface and th e graphics compon ent AGP interface. Refer to the AGP Interface Specification , Revisi on 2.
Intel ® 820E Chipset R 188 Design Guide 1.8 VSB The 1.8 V SB plane powers the logic to the resu me w ell of the ICH2. This should not be used for VCMOS. The VCMOS des cribed in t he 2.5 V SBY section sh ould be powered dow n in S5. How ever, the 1.8 V SB requires pow er in S5.
Intel ® 820E Chipset R Design Guide 189 Figure 103. Example 1.8V/3.3V Po wer Seq uencing Circui t Q1 PNP Q2 NPN 220 220 470 +3.3V +1.8V When analy zing system s that m ay be “m arginally com pliant.
Intel ® 820E Chipset R 190 Design Guide Figure 104. Example 3.3V/5V REF Sequencing Circuitry VCC Supply (3.3 V) 5 V Supply 1 K 1 µ F To System VREF To Sy stem 6.1.5. Excessive Pow er Consumption by 64/72-Mbit RDRA M Som e 64/72-Mbit RDRA M devices interpret non- broadcast, device-directed com mands as broadcast comm ands.
Intel ® 820E Chipset R Design Guide 191 Figure 105. Use a GPO to Reduce DRCG Frequency DRCG GPO S0 S0 gpo_drcg-freq 6.1.5.2. Option 2: Increase the Cu rrent Capability of the 2.5 V Voltage Regulat or The second implem entation option requires that the 2.
Intel ® 820E Chipset R 192 Design Guide 6.2. ICH2 Pow er Plane Split The following example show s the power plane splits f or the ICH2. Figure 106. Example o f ICH2 Pow er Plane Split.
Intel ® 820E Chipset R Design Guide 193 6.3. Thermal Design Pow er The therm al design pow er is the estim ated maxi mu m possible expected pow er generated in a com ponent by a real istic appl ication. It is based on extrapolations of both hardw are and softw are technology over the life of th e product.
Intel ® 820E Chipset R 194 Design Guide More inform ation regarding this com po nent is available f rom the v endors listed in the follow ing table. Table 64.
Intel ® 820E Chipset R Design Guide 195 Appendix A: Reference Design Schematics (Uniprocessor) This chapter provides the sche matic diag rams for the R eference Board Uniproces sor design .
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5-23-2000_9:18 1 REVISION 0.5 FCPGA 2 RIMM ICH2 REFERENCE SCHEMATICS DRAWN BY: LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630 1900 PRAIRIE CITY ROAD 87 6 54 32 1 A B C D 1 2 3 4 5 6 7 8 D C B A PCG PLATFORM DESIGN REV: 0.
2 5-23-2000_9:18 BLOCK DIAGRAM DRAWN BY: LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630 1900 PRAIRIE CITY ROAD 87 6 54 32 1 A B C D 1 2 3 4 5 6 7 8 D C B A PCG PLATFORM DESIGN REV: 0.
3-20-2000_10:15 3 PROCESSOR CONNECTOR VID0 VID1 VID2 VID3 33 VID[3:0] 0.1UF C80 JP16 1 2 3 RS#0 RS#1 RS#2 6 RS#[2:0] HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 6 HREQ#[4:0] HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 .
3-20-2000_10:15 PROCESSOR CONNECTOR 4 0.1UF C433 0.1UF C432 0.1UF C434 0.1UF C435 0.1UF C431 TDO R511 22 C428 10PF R514 1K R515 47 R516 150 4.7UF C436 2 1 0.
3-20-2000_14:02 CLOCK SYNTHESIZER 5 JP20 10K R230 C364 82PF 4,7 SEL133/100# 4PF C363 CK133_XIN SIO_14MHZ_R IHC_14MHZ_R IHC_48MHZ_R TEST_CLK66_R ICH_CLK66_R MCH_CLK66_R SIO_PCLK7_R FWHPCLK_R PCLK5_R PC.
3-20-2000_14:02 MCH 6 RAMREF 6,11 RAMREF_R 0.1UF C183 0.1UF C158 HD#[63:0] 3,37 HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#2.
3-20-2000_14:02 MCH 7 4.7K R248 PWROK 8,9,34,36 U14 14 7 13 12 HL10 7,8 GAD1 GAD2 GAD3 GAD4 GAD5 GAD6 GAD7 GAD8 GAD9 GAD10 GAD11 GAD12 GAD13 GAD14 GAD15 GAD16 GAD17 GAD18 GAD19 GAD20 GAD21 GAD22 GAD23.
3-20-2000_14:02 8 ICH2 ICH_HLCOMP GPIO18 VDDQ VCC3_3 VCC1_8SBY VCC2_5SBY VCC2_5 4,6,37 CPURST# 9,36 RSMRST# 9,35 SLP_S5# 6,8,10,11,12,24,25,26,27 PCIRST# 4,8,36 PWRGOOD 4,8,36 PWRGOOD GPIO12 GPIO8 12,.
3-20-2000_10:15 9 ICH2 U13 U20 B15 D13 D12 F19 U21 F20 B16 D16 E22 V21 W16 AA13 V19 V20 G21 D17 G19 E21 C15 R20 AB13 W12 AB11 U19 K4 K3 K2 Y20 W19 W13 AB12 Y13 W22 M4 Y11 R21 W15 Y17 C22 D21 D22 E20 D.
3-20-2000_10:15 FWH 10 8.2K R303 FGPI0 FGPI1 R307 10K R304 10K TBLK_LCK 9,12 LFRAME#/FWH4 9,12 LAD3/FWH3 LAD2/FWH2 9,12 LAD1/FWH1 9,12 LAD0/FWH0 9,12 6,8,11,12,24,25,26,27 PCIRST# 5 FWHPCLK WPROT 4,8 HINIT# R299 0K JP21 4.
3-20-2000_10:29 RIMM SOCKETS 11 C61 0.1UF R20 28-1% R26 28-1% 6,11 RAMREF 4,9,11,15,38 SMBDATA_CORE RCMD_A RSCK_A RDQA0_A RDQA1_A RDQA2_A RDQA3_A RDQA4_A RDQA5_A RDQA6_A RDQA7_A RDQA8_A RDQB0_A RDQB1_.
3-20-2000_10:15 12 SUPER I/O R313 4.7K KBCLK 31 9 LPC_PME# U17 27 18 45 44 15 11 10 93 65 53 96 85 14 83 9 67 77 30 95 84 98 87 92 90 16 17 78 75 74 73 72 71 70 69 68 29 3 58 59 26 24 25 23 22 21 20 5.
3-20-2000_10:15 13 AUDIO 13,14 VCC5_AUDIO AC_BITCLK 9,15 0.1UF C358 9,16 AC_SDATAOUT AC_SDATAIN0 16 AC_SYNC 16 R56 0K R106 0K R77 0K RX3D _C U2 3 2 28 27 17 16 10 5 8 33 11 13 12 44 43 40 37 22 21 41 .
3-20-2000_10:15 14 AUDIO LNLVL_L_R 13 LNLVL_OUT_L R2 20K R4 20K U1 8 7 6 5 1 2 3 4 13 MIC_IN 4.7K R30 4.7K R51 4.7K R27 4.7K R52 13 CD_R 13 CD_L 13 CD_REF R18 4.
3-20-2000_14:56 15 COMMUNICATION AND NETWORK RISER (CNR) J2 A10 A19 B9 B27 A18 B23 B16 A26 B2 B1 A2 A1 B17 B13 B10 B7 A17 A14 A9 A6 A3 B19 B15 B18 A16 A15 A13 A22 B21 A21 B22 A25 B25 B12 A11 B11 A8 B8.
16 3-20-2000_10:29 8 LAN_RXD0_ICH2 LAN_TXD2_ICH2 8 RP53 22 5% 1 2 3 45 6 7 8 15 LAN_RXD2_CNR 15 LAN_RXD1_CNR 15 LAN_RXD0_CNR 15 LAN_TXD2_CNR 15 LAN_TXD1_CNR 15 AC_SYNC_CNR 9 AC_SDATAIN0_ICH2 18 LAN_TX.
3-20-2000_10:29 17 LAN (82562EH) 18,19,20 LAN_SPEEDLED R287 10K 18,21 LAN_CLK_X1 18,21 LAN_CLK_X2 1K R286 R341 1K 1K R364 R365 10K 10K R346 5% R367 10K 16,18 LAN_RESET 16,18 LAN_TXD0 16,18 LAN_CLK 16,18 LAN_RXD0 18 PHAD_ISOL_PINS 21 GILAD_RDP 21 GILAD_RDM ??? 18,19,20 LAN_LILED 20% C286 0.
18 3-20-2000_10:29 R254 120 1% 19,20,21 LAN_RDM 19,20,21 LAN_RDP 16,17 LAN_RESET 16 LAN_RXD2 16,17 LAN_CLK 16,17 LAN_RXD0 16 LAN_RXD1 19,20 LAN_ACTLED 17,19,20 LAN_LILED 19,20 LAN_TDM 19,20 LAN_TDP 16.
3-20-2000_14:53 19 LAN (RJ11) U28 10 11 16 15 14 7 6 5 1 2 3 9 8 4 13 12 2KV 20% C333 1500PF 5% 10M R375 0K R374 4.7UH L25 18,20 LAN_TDP 18,20 LAN_TDM 18,20,21 LAN_RDP 18,20,21 LAN_RDM R335 330 R372 R.
3-20-2000_16:55 20 LAN (RJ45) CR11 12 U27 10 11 16 15 14 7 6 5 1 2 3 9 8 4 13 12 J16 14 13 12 10 8 6 4 2 11 9 7 5 3 1 15 16 C318 0.1UF 0.1UF C329 R113 330 R334 330 18,19 LAN_ACTLED 17,18,19 LAN_SPEEDL.
3-20-2000_11:31 21 LAN R378 51.1 1% 25MHZ Y5 12 20MHZ Y2 2 1 9,15 EE_DOUT_ICH2 9,15 EE_SHCLK_ICH2 15 EE_CS_ICH2_OB 1% 51.1 R376 10% 0.022UF C365 R377 R380 U22 8 3 4 2 1 5 6 7 17,18 LAN_CLK_X1 17,18 LA.
22 LAN 25V 20% 0.1UF C387 C388 0.1UF 20% 25V 25V 20% 0.1UF C389 C390 0.1UF 20% 25V 25V 20% 0.1UF C384 C385 0.1UF 20% 25V 25V 20% 0.1UF C380 C381 0.1UF 20% 25V 25V 20% 0.1UF C382 C383 0.1UF 20% 25V C378 0.1UF 20% 25V 25V 20% 0.1UF C377 C375 4.7UF 20% 16V 16V 20% 4.
3-20-2000_11:31 SYSTEM 23 2.2K R103 JP1 GPIO23_FPLED U14 14 7 5 6 U14 4 3 7 14 R253 330 IRRX 12 1M R252 SP1 1 2 IDEACTS# 27 27 IDEACTP# R345 10K R344 10K JP24 1 2 3 JP23 3 2 1 R326 4.
3-20-2000_10:15 AGP CONNECTOR 24 24,34 TYPEDET# R208 200-1% 7 GAD[31:0] GAD0 GAD2 GAD4 GAD6 GAD9 GAD11 GAD13 GAD15 GAD16 GAD18 GAD20 GAD22 GAD24 GAD26 GAD28 GAD30 GAD1 GAD3 GAD5 GAD7 GAD8 GAD10 GAD12 .
PCI CONNECTORS 1 AND 2 3-20-2000_10:15 25 25,26 PTCK 8,24,25,26,38 PIRQ#B 8,25,26,38 PIRQ#D 5 PCLK1 8,38 PREQ#0 C_BE#1 C_BE#0 C_BE#2 C_BE#3 C_BE#0 C_BE#3 C_BE#2 C_BE#1 8,26 C_BE#[3:0] 8,25,26,38 IRDY#.
PCI CONNECTORS 3 AND 4 3-20-2000_10:15 26 VAUX_JP R110 R107 SDONEP3 26 SDONEP4 26 SBOP3 26 SBOP4 26 PRSNT#31 26 PRSNT#32 26 PRSNT#41 26 PRSNT#42 26 PU3_ACK64# 26 PU3_REQ64# 26 PU4_ACK64# 26 PU4_REQ64#.
3-20-2000_10:15 IDE CONNECTORS 27 27 PCIRST_BUF# 6,8,10,11,12,24,25,26 PCIRST# 9 SDCS#1 8,38 IRQ15 9 PIORDY 8,38 IRQ14 9 PDCS#1 9 PDIOW# 9 SDIOW# 9 SDIOR# 33 R333 4.
3-20-2000_10:15 USB CONNECTORS 28 R502 0K USBV0 USBG0 USBV1 USBD1N USBD1P USBG1 10K R97 9 OC#0 R83 330K R48 0K R50 0K USBP1N_R USBP1P_R 4.7K R91 24 USBAGP+ R41 0K R42 0K 9 USBP0N 9 USBP0P 9 USBP1P 15 .
3-20-2000_10:15 PARALLEL PORT 29 PDR7_R PDR6_R PDR5_R PDR4_R PDR3_R SLIN#_R PDR2_R PAR_INIT#_R VCC5_DB25_CR SLCT 12 PE 12 BUSY 12 ACK# 12 SLIN# 12 J6 P15 P16 P13 P23 P10 P25 P12 P24 P11 P22 P9 P21 P8 P20 P7 P19 P6 P18 P5 P17 P4 P3 P2 P14 P1 12 STB# 2.
3-20-2000_10:15 SERIAL PORTS 30 CTS1_C DTR1_C DCD1_C RTS0_C DTR0_C RXD0_C DSR0_C TXD1_C RXD1_C RTS1_C U6 19 18 17 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 16 20 TXD1 12 12 DCD#1 12 RTS#1 12 RXD1 12 CTS#1 1.
3-20-2000_10:15 31 KEYBOARD/MOUSE/FLOPPY RDATA# 12 TRK#0 12 DSKCHG# 12 HDSEL# 12 WGATE# 12 WDATA# 12 STEP# 12 DIR# 12 DS#0 12 MTR#0 12 12 INDEX# DRVDEN#1 12 DRVDEN#0 12 L13 12 L14 2 1 L12 2 1 L16 12 1.
GAME PORT 32 4.7K R35 4.7K R39 47 R38 1K R33 1K R32 R36 1K R37 1K 12 MIDI_IN 12 J1BUTTON2 12 J2BUTTON2 5% R24 2.2K 5% 2.2K R23 47 R34 5% 2.2K R22 5% 2.2K R21 12 JOY2Y 12 JOY1Y 12 MIDI_OUT 12 JOY2X 12 JOY1X 12 J1BUTTON1 12 J2BUTTON1 JOY1X_R JOY2X_R MIDI_OUT_R JOY2Y_R JOY1Y_R MIDI_IN_R J5 2 10 3 11 4 12 5 13 6 14 7 15 8 1 9 31 32 0.
3-20-2000_10:15 33 VRM 8.4 IFB_Q Q21 5 6 7 8 3 2 1 4 VID3 VID0 VID2 VID1 VID[3:0] 3 C472 2200UF 1 2 C471 1200UF 1 2 C469 1200UF 1 2 C468 1200UF 1 2 R71 5.1-5% OUTEN VRM_PWRGD 4,8,9,36 2200UF C100 21 C93 2200UF 1 2 2200UF C103 21 1200UF C87 21 C111 1200UF 1 2 1200UF C107 21 R55 8.
3-20-2000_10:15 34 VOLTAGE REGULATORS 100-1% R538 100-1% R539 100-1% R133 100-1% R134 301-1% R311 131-1% R309 5.1-5% R135 R146 1.21K-1% 1% R141 301 7,8,9,36 PWROK R331 1K 8,9,36 SLP_S3# VR8 3 2 1 U18 7 14 6 5 4 VD_G2 VD_G1 VD_G3 VCC2_5_ADJ VDDQ_FB VDDQ_COMP_R 7.
3-20-2000_10:15 35 VOLTAGE REGULATORS Q19 5 6 7 8 3 2 1 4 301-1% R509 CMDSH-3 CR9 C A R295 10K SBY_IT H_R 100UF C314 2 1 C312 0.1UF V_BOOST C306 4.7UF 1 2 C299 1000PF C292 100PF 100PF C293 C307 0.1UF 2 1 330PF C296 VR7 8 7 6 10 11 15 12 14 16 13 5 3 2 1 4 9 CDRH127-6R1 10UH L23 C294 0.
3-20-2000_10:15 POWER CONNECTOR 36 10K R536 VCOREDET U3 14 7 11 12 13 RSTBTN_SW U20 7 14 3 4 7,8,9,34 PWROK 0K R339 4.7K R349 R342 0K 1M R288 R251 22K R347 4.
3-20-2000_10:15 37 3,6 HREQ#0 62 RP29 8 7 6 5 4 3 2 1 62 RP30 8 7 6 5 4 3 2 1 62 RP33 8 7 6 5 4 3 2 1 62 RP34 8 7 6 5 4 3 2 1 62 RP21 8 7 6 5 4 3 2 1 62 RP22 8 7 6 5 4 3 2 1 62 RP23 8 7 6 5 4 3 2 1 62.
3-20-2000_10:15 PCI/AGP PULLUPS/PULLDOWNS 38 ST0 7,24 ST1 7,24 7,24 ST2 R507 8.2K SBSTB# 7,24 7,24 SBSTB 7,24 GGNT# WBF# 7,24 7,24 PIPE# PIRQ#B 8,24,25,26 PIRQ#A 8,24,25,26 8.2K R89 R81 8.2K SMLINK_CLK 9 4.7K R13 R12 4.7K 8,27 IRQ15 8,27 IRQ14 8.2K R323 R338 8.
3-20-2000_10:15 39 RAMBUS TERMINATION 11 TERM_ROW[2:0] TERM_ROW1 TERM_ROW0 TERM_ROW2 11 TERM_DQB[8:0] TERM_DQB0 TERM_DQB2 TERM_DQB3 TERM_DQB4 TERM_DQB5 TERM_DQB6 TERM_DQB7 TERM_DQB8 TERM_DQB1 11 TERM_.
3-20-2000_10:14 DECOUPLING 40 C137 4.7UF 4.7UF C136 C131 4.7UF 4.7UF C139 4.7UF C134 4.7UF C135 C141 4.7UF 4.7UF C132 C138 4.7UF C133 4.7UF C360 0.1UF 0.1UF C359 0.1UF C362 C361 0.1UF U3 10 9 8 7 14 U20 7 14 11 10 U18 7 14 11 13 12 0.1UF C461 0.1UF C460 0.
3-20-2000_10:14 BULK DECOUPLING 41 0.1UF C256 C257 0.1UF 0.1UF C258 C255 0.1UF 100UF C246 C249 100UF 100UF C250 C251 100UF 100UF C243 C237 100UF 100UF C236 C 235 0.1UF 22UF C265 2 1 C264 22UF 12 C233 0.1UF C222 0.1UF 0.1UF C226 C227 0.1UF 0.1UF C228 C184 0.
3-20-2000_10:14 REVISION HISTORY 42 DRAWN BY: LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630 1900 PRAIRIE CITY ROAD 87 6 54 32 1 A B C D 1 2 3 4 5 6 7 8 D C B A PCG PLATFORM DESIGN REV: 0.
43 TEST_CLK66 5 HL7 7,8 HL6 7,8 HL5 7,8 HL4 7,8 HL8 7,8 HL10 7,8 HL_STB# 7,8 HL_STB 7,8 HL9 7,8 HL3 7,8 HL2 7,8 HL1 7,8 HL0 7,8 6,8 HUBREF J26 11 50 48 4 2 18 16 14 12 10 8 6 46 44 42 40 38 36 34 32 3.
デバイスIntel 820Eの購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
Intel 820Eをまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはIntel 820Eの技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Intel 820Eの取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Intel 820Eで得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Intel 820Eを既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はIntel 820Eの不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Intel 820Eに関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちIntel 820Eデバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
