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PCI/PCI-X Family of Gigabit Ethernet Controllers Sof tware Developer ’ s Manual 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx 317453-005 Revision 3.
ii Software De veloper’s Manual Legal Notice INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CO NNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER WISE, TO ANY INTELLECTUAL PROPER TY RIGHTS IS GRANTED BY THIS DOCUMENT .
Software Developer’s Manua l iii Revision History Date V ersion Comme nts June 2008 3.8 Updated EEPROM Word 21h bit descriptions (section 5.6.18). June 2008 3.
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Software Developer’s Manua l v Contents Contents 1 Introduction ............... ................ ............. ................. ............ ................. ................ ........ 1 1.1 Scope ........... ................ ............. ........
vi Software De veloper’s Manual Contents 3.2.5 Receive Descriptor Write-Back ................ ................ ................ .......... 26 3.2.6 Receive Descriptor Queue St ructure..... ................ ................ ............. 26 3.2.7 Receive Interrupts .
Software Developer’s Manua l vii Contents 5.5 EEUPDATE Utility ........ ............. ................ ............. ................ ................ ............. 97 5.5.1 Command Line Parameters ............... ................... ...............
viii Software De veloper’s Manual Contents 6 Power Management ....... ................ ............. ................ ................ ............. .............. 1 29 6.1 Introduction to Power Management ....... ...... ................ ...........
Software Developer’s Manua l ix Contents 10.1.3 Blink Control ............. ................ ............. ................ ............. .............. 180 11 PHY Functionality and Features .............. ............. ................ ............
x Software De veloper’s Manual Contents 12 Dual Port Characteristics ........ ................. ............. ................ ............. ................ . 203 12.1 Introduction ..... ................ ................ ............. .............
Software Developer’s Manua l xi Contents 13.4.25 Receive Descriptor Base Address Low ........... ... ................ ............. . 3 02 13.4.26 Receive Descriptor Base Address High .......... ... ............. ................ . 3 02 13.4.27 Receive Descriptor Length .
xii Software De veloper’s Manual Contents 13.7.10 Collision Count ......... ................ ................ ............. ................ ........... 341 13.7.11 Defer Count . ................ ................ ............. ................ .....
Software Developer’s Manua l xiii Contents 13.8.5 Receive Data FIFO Packet Count ......... ................ ............. .............. 366 13.8.6 Transmit Data FIFO Head Regist er ............. ................. ................ .... 3 66 13.8.7 Transmit Data FIFO Tail Regist er .
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Introduction Software Developer’s Manua l 1 Introduction 1 1.1 Scope This document serves as a soft ware develope r ’ s manual for 82546GB/EB , 82545GM/E M , 82544GC/EI , 82541(PI/GI/EI) , 8254 1ER , 82547GI/EI , and 82540 EP/EM Gigabit Et hernet Controllers.
Introduction 2 Software De veloper’s Manual For the 82544GC/EI , when connecte d to an appropriate SerDes, it can alternatively provide an Ethernet interface for 1000 Base-SX or LX applicati ons (IEEE 802.3z). Note: The 82546EB/82545EM is SerDes PICMG 2.
Introduction Software Developer’s Manua l 3 • IEEE 802.3x compliant flow control support — Enables control of the transmission of Pa use packets through software or hardware triggering — Provi.
Introduction 4 Software De veloper’s Manual 1.3.5 Additional Performance Features • Provides adaptive Inter Frame Spacing (IFS) cap ability , enabling collision reduction in half duplex networks (.
Introduction Software Developer’s Manua l 5 1.3.6 Manageability Features (Not Ap plicable to the 82544GC/EI or 82541ER) • Manageability support fo r ASF 1.0 and AoL 2.0 by way of SMBus 2.0 interface and either: — TCO mode SMBus-based management packet transmit / receive support — Internal ASF- compliant TCO control ler 1.
Introduction 6 Software De veloper’s Manual 1.4 Conventions This document uses notes that cal l attention to important comments: Note: Indicates details about the hardware’ s operations that are not immediat ely obvious.
Software Developer’s Manua l 7 Architectural Ov erview Architectural Overview 2 2.1 Introduction This section provides an overview of th e PCI/PC I-X Family of Gigab it Ethernet Controllers. The following sections give detailed informat ion about the Ethernet controller ’ s functionali ty , regist er description, and initialization seque nce.
8 Software De veloper’s Manual Architectural Overview 2.2 External Architecture Figure 2-1 shows the external interfaces to the 82546GB/EB . Figure 2-1. 82546GB/EB Ex ternal Interface Figure 2-2 shows the external interfaces to the 82545GM/EM , 82544GC/E I , 82540EP/EM , and 82541xx .
Software Developer’s Manua l 9 Architectural Ov erview Figure 2-3 shows the external interfaces to the 82547GI/EI . Figure 2-3. 8254 7GI(EI) External In terface VLA N PCI Core EEPROM FLASH Slave Acc.
10 Software De veloper’s Manual Architectural Overview 2.3 Microarchitecture Compared to its predecessors, the PCI/PCI-X Family of Gigabit Ethernet Controller ’ s MAC adds improved receive-packet filt ering to support SMBus-based manageab ility , as well as the ability to transmit SMBus-based manageab ility packets.
Software Developer’s Manua l 11 Architectural Ov erview When the Ethernet controller serves as a PCI targ et, it follows the PC I co nfiguration specification, which allows all accesses to it to be automati cally mapped into free memory and I/O space at initialization of the PCI system.
12 Software De veloper’s Manual Architectural Overview • Offloading the receiving and transmitting IP and TCP/UDP checksums • Directly retransmitting from the transmit FIFO an y transmissions resulting in errors (collisio n detection, data underrun ), thus eliminating the need to re-access this data from host memory 2.
Software Developer’s Manua l 13 Architectural Ov erview Note: Refer to the Extended Devi ce Control Regist er (bits 23:22) fo r mode selection (see Section 13.
14 Software De veloper’s Manual Architectural Overview 2.3.8 FLASH Memory Interface The Ethernet controller provides an external para llel interface to a FLAS H device. Accesses to the FLASH are controlled by the Ethe rnet controller and a re accessible to software as normal PCI reads or writ es to the FLAS H memory mapping area.
Software Developer’s Manua l 15 Architectural Ov erview 2.5 Ethernet Addressing Several registers store Ethernet addresses in the Ethernet controller . T wo 32-bit registers make up the address: one is called “high”, and the other is called “low”.
16 Software De veloper’s Manual Architectural Overview 2.6 Interrupt s The Ethernet controller provides a complete set of inte rrupts that allow for ef ficient software management.
Software Developer’s Manua l 17 Architectural Ov erview 2.7 Hardware Acceleration Cap ability The Ethernet controller provides the ability to of fload IP , TCP , and UDP checksum for transmit.
18 Software De veloper’s Manual Architectural Overview Descriptors store the following information about th e buffers: • The physical address • The length • Status and command information about the referenced buffer Descriptors contain an end-of-packet field that indicates the last buf f er for a packet.
Software Developer’s Manua l 19 Receive and T ransmit Description Receive and T ransmit Description 3 3.1 Introduction This section describes the packet reception, packet transmission, tran smit descriptor ring structure, TCP segmentation, and transmit checksum offloading for the PC I/PCI-X Family of Gigabit Ethernet Controllers.
Receive and Transmit Descript ion 20 Software De veloper’s Manual If manageability is enabled and if RCMCP is en abled then ARP request packets can be directed over the SMBus or processed intern ally by the ASF controller rather than delivered to host memory (not applicable to the 82544G C/EI or 82541ER .
Receive and T ransmit Description Software De veloper’s Manual 21 layers. The packet checksum is always reported in t he first descriptor (even in the case of multi- descriptor packets).
Receive and Transmit Descript ion 22 Software De veloper’s Manual Note: See T able 3-5 for a description of sup ported packet types for r eceive checksum offloading. Unsupported packet types eit her have the IXSM bit set, or they don’t have the TCPCS bit set.
Receive and T ransmit Description Software De veloper’s Manual 23 T able 3-3. Receive Errors (RDESC.ERRORS) Layout 76 5 4321 0 RXE IPE TCPE RSV CXE a a.
Receive and Transmit Descript ion 24 Software De veloper’s Manual 3.2.3.3 Receive Descriptor S pecial Field Hardware stores additional information in the receive descriptor fo r 802.1q packets. If the packet type is 802.1q, determined when a packet type field m atches the VLAN 1 Ethernet Register (VET) and RCTL.
Receive and T ransmit Description Software De veloper’s Manual 25 3.2.4 Receive Descriptor Fetching The descriptor fetching strategy is designed to support large bursts across the PCI bus. This is made possible by using 64 on-chip receive descriptors and an optimized fe tching algorithm.
Receive and Transmit Descript ion 26 Software De veloper’s Manual 3.2.5 Receive Descriptor Write-Back Processors have cache line sizes that are larger than the receive desc riptor size (16 bytes). Consequently , writin g back descriptor informat ion for each received packet would cause expensive partial cache line updates.
Receive and T ransmit Description Software De veloper’s Manual 27 The receive descriptor head and ta il pointers reference 16-byte bloc ks of memory . Shaded boxes in the figure represent descriptors that have stored incoming packets but have not yet been recognized by software.
Receive and Transmit Descript ion 28 Software De veloper’s Manual • Receive Descriptor T ail register (RDT) This register holds a value that is an of fset fr om the bas e, and identifies the location beyond the last descrip tor hardware c an process.
Receive and T ransmit Description Software De veloper’s Manual 29 Figure 3- 3. Packet D elay Timer Operation (State Diagram) 3.2.7.1.2 Receive Interrupt Absolute Delay T imer (RADV) The Absolute T imer ensures that a receive interrupt is generated at some pr edefined interval after the first packet is received.
Receive and Transmit Descript ion 30 Software De veloper’s Manual The diagrams below show how the Packet T ime r and Absolute Timer can be used together: 3.
Receive and T ransmit Description Software De veloper’s Manual 31 3.2.7.3 Receive Descriptor Minimum Threshold (ICR.RXDMT) The minimum descriptor threshold h elps avoid descript or under-run by generating an interrup t when the number of free descriptors becomes equal to the minim um amount defined in RCTL.
Receive and Transmit Descript ion 32 Software De veloper’s Manual The Packet checksum is the one’ s complement over the receive packet, starting from the byte indicated by RXCSUM.PCSS (0b corresponds to the fi rst byte of the packet ), after stripping.
Receive and T ransmit Description Software De veloper’s Manual 33 T able 3-6. 82544GC/EI Supporte d Receive Checksum Cap abilities T able 3-5 lists the general details about what packets ar e processed. In more detail, the packets are passed through a series of filters ( Section 3.
Receive and Transmit Descript ion 34 Software De veloper’s Manual 3.2.9.2 SNAP/VLAN Filter This filter checks the next headers looking for an IP header . It is capable of decoding Ethernet II, Ethernet SNAP , and IEEE 802.3ac headers. It skip s past any of thes e intermediate headers and looks for the IP header .
Receive and T ransmit Description Software De veloper’s Manual 35 • The protocol stack calculates the number of packets required to transmit this block based on the MTU size of the media and required packet headers. • For each packet of the data block: — Ethernet, IP and TCP/UDP head ers are prepared by the stack.
Receive and Transmit Descript ion 36 Software De veloper’s Manual T able 3-7. T ransmit Descriptor (TDESC) Layout 3.3.3 Legacy T ransmit Descriptor Format T o select legacy mode operatio n, bit 29 (TDESC. D EXT) should be set to 0b. In this case, the descriptor format is defined as sho wn in T abl e 3-8 .
Receive and T ransmit Description Software De veloper’s Manual 37 Notes: 1. Even though CSO and CSS are in units of bytes, th e checksum calculation typically work s on 16-bit words. Hardware does not enforce even byte alignment. 2. Hardware does not add the 802.
Receive and Transmit Descript ion 38 Software De veloper’s Manual 3.3.3.1 T ransmit Descriptor Command Field Format The CMD byte stores the applicable command and has fields shown in T able 3-10 . T able 3-10. T ransmit Command (T DESC.CMD) Layout 7 6 5 4 3 2 1 0 IDE VLE DEXT RSV RPS a a.
Receive and T ransmit Description Software De veloper’s Manual 39 Notes: 1. VLE, IFCS, and IC are qualified by EOP . That is, hardware interprets these b its ONL Y when EOP is set. 2. Hardware only sets the DD bit for descriptors wit h RS set. 3. Descriptors with the null address (0b) or zero le ngth transfer no data.
Receive and Transmit Descript ion 40 Software De veloper’s Manual Note: The DD bit reflects status of all descriptors up to and including the one with the RS bit set (or RPS for the 82544GC/EI ). 3.3.4 T ransmit Descriptor Special Field Format The SPECIAL field is used to provide the 802.
Receive and T ransmit Description Software De veloper’s Manual 41 3.3.5 TCP/IP Context T ransmit Descripto r Format The TCP/IP context transmit desc riptor provides access to the enha nced checksum of fload facility available in the Ethernet controller .
Receive and Transmit Descript ion 42 Software De veloper’s Manual 3.3.6 TCP/IP Context Descriptor Layout The following section describes the layout of th e TCP/IP context transmit descriptor . T o se lec t th is des cr ipt or f or mat , b it 2 9 ( TDE SC.
Receive and T ransmit Description Software De veloper’s Manual 43 T able 3-14. T ransmit Descriptor (TDESC) Layout T ransmit Descriptor Offload Description TUCSE TCP/UDP Checksum Ending Defines the ending byte for the TCP/UDP checksum offload feature.
Receive and Transmit Descript ion 44 Software De veloper’s Manual Notes: 1. A number of the fields are ignored if the TCP Segmentation enable bit (TDESC.TSE) is cleared, denoting that the descriptor does not refer to the TCP segmentati on context. 2.
Receive and T ransmit Description Software De veloper’s Manual 45 T able 3-15. Command Field (TDESC.TUCMD) Layout Note: 1. The IDE, DEXT , and RS b its are valid regardless of the state of TSE.
Receive and Transmit Descript ion 46 Software De veloper’s Manual 3.3.6.2 TCP/UDP Offload T ransmit Descriptor St atus Field Four bits are reserved to provide transmit status , althoug h only one is currently assigned for this specific descriptor type.
Receive and T ransmit Description Software De veloper’s Manual 47 T able 3-17. T ransmit Descriptor (TDESC) Layout – (T ype = 0001b) 0 Address [63:0] 8 Spec ial POP TS RSV S T A DCMD DTYP DT ALEN .
Receive and Transmit Descript ion 48 Software De veloper’s Manual 3.3.7.1 TCP/IP Dat a Descriptor Command Field The Command field provid es options that control check sum offloading and TCP segmentation features along with some of the gene ric descriptor processing features.
Receive and T ransmit Description Software De veloper’s Manual 49 Note: The VLE, IFCS, and VLAN fields ar e only va lid in certain descriptors. If TSE is enabled, the VLE, IFCS, and VLAN fields are only valid i n the first data descriptor of the TCP segmentatio n context.
Receive and Transmit Descript ion 50 Software De veloper’s Manual 3.3.7.3 TCP/IP Dat a Descriptor Option Field The POP TS field provides a num ber of options which control the handling of this packet. This field is ignored except on the first da ta descriptor of a packet.
Receive and T ransmit Description Software De veloper’s Manual 51 When CTRL.VME is set to 1b, all packets transm itted from the Ethernet controller that has VLE set in the DCMD field is sent with an 802.1Q header added to the packet. The conten ts of the header come from the transmit descriptor special field and fr om the VLAN type register .
Receive and Transmit Descript ion 52 Software De veloper’s Manual Figure 3-4. T ransmit Descriptor Ring Structure Shaded boxes in Figure 3 -4 represent descriptors that have b een transmitted but not yet reclaimed by software. Reclaiming involves freeing up buffers associated with the descriptors.
Receive and T ransmit Description Software De veloper’s Manual 53 Once activated, hardware fetches the descriptor indicated by the hardware head register .
Receive and Transmit Descript ion 54 Software De veloper’s Manual Since the benefit of delaying and then bursting transm i t descriptor write-backs is smal l at best, it is likely that the threshold are left at the default va lue (0b) to force immediat e write-back of transmit descriptors and to preserve backward compatibi lity .
Receive and T ransmit Description Software De veloper’s Manual 55 • Link status change (LSC) - Set when the link st atus changes . When using the internal PHY , link status changes are determined and indicat ed by the PHY via a change in its LINK indication.
Receive and Transmit Descript ion 56 Software De veloper’s Manual 3.5.1 Assumptions The following assumption applies to the TCP Segm entation implementation in the Ethernet controller: • The RS bit operation is not changed. Interrupts are set after data in buffers pointed to by individual descriptors is transferred to hardware.
Receive and T ransmit Description Software De veloper’s Manual 57 3.5.2.1 TCP Segment ation Data Fe tch Control T o perform TCP Segment ation in the Ethernet cont roller , the DMA unit must ensure that the entire payload of the segmented packet fits into the available space in the on-c hip Packet Buffer .
Receive and Transmit Descript ion 58 Software De veloper’s Manual • TCP with options • UDP with limitatio ns. UDP (unlike TCP) is not a “reliable protocol”, and fragmentation is not supported at the UDP level. UDP messages that are larger than the MT U size of t he given network medium are normally fragmented at the IP layer .
Receive and T ransmit Description Software De veloper’s Manual 59 • IPv4 Header — Length should be set to zero — Identification Field should be set as appropr iate for first packet of send (if.
Receive and Transmit Descript ion 60 Software De veloper’s Manual Note: It is recommended that the entir e header sectio n, as described by the TCP Context Descriptor HDRLEN field, be coalesced into a single buffer and described using a single data descriptor .
Receive and T ransmit Description Software De veloper’s Manual 61 Figure 3- 9. IPv4 Head er (Little- Endian Or der) Flags Field Definition: The Flags field is defined below .
Receive and Transmit Descript ion 62 Software De veloper’s Manual The TCP header is first shown in the traditiona l (RFC 793) representation. Because byte and bit ordering is confusing in that representation, the TCP header is also shown in little-endi an format.
Receive and T ransmit Description Software De veloper’s Manual 63 TCP Lengt h = Payload + HDRLEN - TUCSS “Payload” is normally MSS except for the last packet where it represents the remainder of the payload. Figure 3-13. TCP Pseudo Header Cont ent (T raditional Represent ation) Figure 3-14.
Receive and Transmit Descript ion 64 Software De veloper’s Manual UDP pseudo header has the same format as the TCP pseudo header . The IPv4 pseudo header conceptually prefixed to the UD P header con.
Receive and T ransmit Description Software De veloper’s Manual 65 Three specific types of checksu m are supported by the hardware in the context of the TCP Segmentation offload feature: • IPv4 che.
Receive and Transmit Descript ion 66 Software De veloper’s Manual Figure 3-19. Overall Dat a Flow I P/ TCP H eader P acket Da ta P acket Da ta P acket Da ta HO S T M emo ry PC I F I F O H eader U pd.
Receive and T ransmit Description Software De veloper’s Manual 67 3.5.9.1 TCP/IP/UDP Header for the First Frame The hardware makes the following changes to the head ers of the first packet that is derived from each TCP segmentation context.
Receive and Transmit Descript ion 68 Software De veloper’s Manual 3.5.9.3 TCP/IP/UDP Header for the Last Frame The controller makes the following changes to the headers for the last frame of a TCP s.
Receive and T ransmit Description Software De veloper’s Manual 69 Three fields in the TCP/IP Cont ext Descriptor set the context of the IP checksum offloading feature: • IPCSS This field specifies the byte of fset form the start of the transferred data to the first byte to be included in the checksum.
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Software Developer’s Manua l 71 PCI Local Bus Interface PCI Local Bus Interface 4 The PCI/PCI-X Family of Gigabit Ethernet Con tro llers are PCI 2.2 or 2.3 compliant devices and implement the PCI-X Addendum to the PCI Local Bus Sp ecification, Revisi on 1.
72 Software De veloper’s Manual PCI Local Bus Interface The following list provides ex planations of the various PCI registers and their bit fields: V endor ID This uniquely iden tifies all Intel PCI products. This field may be auto-loaded from the EEPROM at power on or upon the assertion of PCI_R ST#.
Software Developer’s Manua l 73 PCI Local Bus Interface Cache Line Size 1 Used to store the cache line size. The value is in units of 4 bytes. A system with a cache line size of 64 bytes sets the value of this register to 10h. The only si zes that are supported are 16, 32 , 64, and 128 bytes.
74 Software De veloper’s Manual PCI Local Bus Interface All base address registers have the followin g fields: Field Bit(s ) Read/ Wri te Initial Va l u e Descript ion Mem 0 R 0b for mem 1b for I/O 0b indicates memory space. 1b indicates I/O. T ype 2:1 R 00b for 32- bit 10b for 64- bit Indicates the address space size.
Software Developer’s Manua l 75 PCI Local Bus Interface Expansion ROM Base Address This register is used to define the address and size information for boot- time access to the optional Flash memory .
76 Software De veloper’s Manual PCI Local Bus Interface Subsystem ID This value can be loaded automatically from the EEPROM upon power-up or PCI reset. A value of 1008h is the default for thi s field upon power-up if the EEPROM does not respond or is not programmed.
Software Developer’s Manua l 77 PCI Local Bus Interface Max_Lat/Min_Gnt 1 The Ethernet controller places a very high load on the PCI bus during peak transmit and receive traffic.
78 Software De veloper’s Manual PCI Local Bus Interface T able 4-4. St atus Register Layout 40 b Memory Write and Invalidate Enable (not applicable to the 82547GI/EI ). 5 0b Palette Snoop Enable. 60 b Parity Error Response (not applicable to the 82547GI/EI ).
Software Developer’s Manua l 79 PCI Local Bus Interface 4.1.1 PCI-X Confi guration Registers The Ethernet controller supports addi tional configur ation registers that ar e specific to PCI-X. These registers are visible in conventional PCI an d PCI-X modes, although they only affect the operation of PCI-X mode.
80 Software De veloper’s Manual PCI Local Bus Interface 4.1.1.3 PCI-X Com mand 15 7 6 4 3 2 1 0 Reserved Max. S plit Trans- actions Read Count RO DP Bits Read Wri te Initial Va l ue Description 0R W 0 b Data Parity Error Recovery Enable. If this bit is 1b, the Ethernet controller attempts to recover from Parity errors.
Software Developer’s Manua l 81 PCI Local Bus Interface 4.1.1.4 PCI-X St atus 31 29 28 26 25 23 22 21 20 19 18 17 16 15 8 7 3 2 0 Res. Read Size Max. S plit Rd Byte Cplx USC SCD 133 64b Bus Number Device Number Func. Num. Bits Read/ Writ e Intial Va l u e Descripti on 2:0 R 0b Fu nction Number.
82 Software De veloper’s Manual PCI Local Bus Interface 4.1.2 Reserved and Undefined Addresses Any PCI or PCI-X register addres s space not explicitly declared in this specification should be considered to be reserved, and should not be written .
Software Developer’s Manua l 83 PCI Local Bus Interface 4.1.3 Message Signaled Interrupts 1 Message Signaled Interrupt (MSI) capabil ity is optional for PCI 2 .
84 Software De veloper’s Manual PCI Local Bus Interface 4.1.3.1.3 Message Control 15 8 7 6 4 3 1 0 Reserved 64b Multiple Enable Multiple Capable En Bits Read/ Writ e Initial Va l u e Descript ion 0R 0 b MSI Enable.
Software Developer’s Manua l 85 PCI Local Bus Interface 4.1.3.1.4 Message Address 4.1.3.1.5 Message Upper Address 4.1.3.1.6 Message Dat a 4.2 Commands The Ethernet controller is capable of decoding and encoding com mands for both PCI and PCI-X modes.
86 Software De veloper’s Manual PCI Local Bus Interface As a target, the Ethernet cont roller only accepts transactions that address its BARs or a configuration transaction in which its IDSEL inp ut is asserted. In PCI-X mode, the Ethernet controller also accepts split completion for an outstanding memory re ad command that it has requested.
Software Developer’s Manua l 87 PCI Local Bus Interface Following are a few specific rules: • For descriptor fetches, the burst length is always equal to the multiple of cache line sizes set by the transmit and receive descript or fetch threshold fields.
88 Software De veloper’s Manual PCI Local Bus Interface Figure 4-4. Mast er W rite Command Usage Algorithm 4.3.1.1 MWI Burst s • If there is at least one cache line of data remaining, then the Ethernet controller continues the MWI burst.
Software Developer’s Manua l 89 PCI Local Bus Interface 4.3.1.2 MW Burst s • The Ethernet controller always continues the burst until th e end. If the system is concerned about MWI usage, it disconnects at the cache line boundary . The Ethernet controller then restarts the transaction and re-evaluates command usage.
90 Software De veloper’s Manual PCI Local Bus Interface Outstanding Memory Read When the Ethernet controller masters a memory read and is responded to wi th a split response it waits for the completion of the data as a target. The Ethernet controller allows one outstanding memory read command at any time.
Software Developer’s Manua l 91 PCI Local Bus Interface 4.4.1 T arget T rans action T ermination When the Ethernet controller accepts a transaction as a target it always di sconnects the transaction after a single data phase by following the “Master Completion T ermination” in PCI 2.
92 Software De veloper’s Manual PCI Local Bus Interface 4.7 CardBus Application (82541PI/GI/EI Only) The 82541PI/GI/EI has some features to facilitate its use in a CardBus application , following revision 7 of the PC Card specification. To u s e t h e 82541PI/GI/EI on CardBus, an external flash memo ry is required.
Software Developer’s Manua l 93 EEPROM Interface EEPROM Interface 5 5.1 General Overview The PCI/PCI-X Family of Gigabit Ethernet Controllers uses an EEPROM devi ce for storing product configurat ion informatio n.
94 Software De veloper’s Manual EEPROM Interface 5.2 Component Identification Via Programming Interface Ethernet controller stepping is identified by the following register contents.
Software Developer’s Manua l 95 EEPROM Interface Note: These Ethernet controllers also provide identification data through the T est Access Port (T A P). 5.3 EEPROM Device and Interface The EEPROM access algorithm, progra mmed into the Ethernet controll er , is compatible with most, but not all, commer ically available 3.
96 Software De veloper’s Manual EEPROM Interface The EEPROM interface trace routing is not critical because the interf ace runs at a very slow speed. Note: For the 82544GC/EI , 82540EP/EM , 82541xx , and 82547 GI/EI , the EEPROM access algorithm drives extra pulses on the shift cloc k at the beginnings an d ends of read and write cycles.
Software Developer’s Manua l 97 EEPROM Interface In ASF Mode 1 , the Ethernet controller's ASF function reads the ASF CRC word to determine if the EEPROM is valid. If the CRC is not valid, the AS F Configuration register s retain their default value.
98 Software De veloper’s Manual EEPROM Interface 5.6 EEPROM Address Map 1 T able 5-2 lists the EEPROM address map for the Ethe rnet controllers. E ach word listed is described in the sections that follow . Note: The “LAN A/B” column in T able 5-2 is only applicable to the 82546GB/EB .
Software Developer’s Manua l 99 EEPROM Interface Wor d Used By Bit 15 - 8 Bit 7 - 0 Image Va l u e LAN A/B 0Dh HW Device ID see Ta b l e 5-1 for specific image values LAN A 0Eh HW V endor ID 8086h b.
100 Software Deve loper’s Manual EEPROM Interface Wor d Used By Bit 15 - 8 Bit 7 - 0 Image Va l u e LAN A/B 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh HW IPv6 Address Byte 2 IPv6 Address Byte 4 IPv6 Address By.
Software Developer’s Manua l 101 EEPROM Interface Wor d Used By Bit 15 - 8 Bit 7 - 0 Image Va l u e LAN A/B 25h 26h HW IPv4 Address Byte 2 IPv4 Address Byte 4 IPv4 Address Byte 1 IPv4 Address Byte 3.
102 Software Deve loper’s Manual EEPROM Interface T able 5-3. 82544GC/EI and 82541ER EEPROM Address Map Word Address HW Access Description (Hi Byte) Description (Low Byte) Default Image V alue (hex).
Software Developer’s Manua l 103 EEPROM Interface 5.6.1 Ethernet Address (Words 00h-02h) The Ethernet Individual Address (IA) is a six-byte field that must be unique for each Ethernet port (and unique for each copy of the EEPROM image ) . The first three bytes ar e vendor specific.
104 Software Deve loper’s Manual EEPROM Interface 5.6.3 SerDes Configuration (W ord 04h) If this word has a value of other than FFFFh, software programs its value into the Extended PHY Specific Control Register 2, located at address 26d in the PHY register space (see T able 13-47 ).
Software Developer’s Manua l 105 EEPROM Interface 5.6.7 Initialization Control W ord 1 (W ord 0Ah) The first word read by the Ethernet contro ller contains initiali zation values that: • Sets defa.
106 Software Deve loper’s Manual EEPROM Interface 5.6.8 Subsystem ID (W ord 0Bh) If the signature bits (15:14) and bit 1 (Load Subsys tem IDs) of word 0Ah are valid, this word is read in to initialize the Subsystem ID.
Software Developer’s Manua l 107 EEPROM Interface 5.6.10 Device ID (Word 0Dh, 1 1h 1 ) If the si gnature bits (15:14) and bit 1 ( Load Subsy stem IDs) of word 0Ah are valid, this word i s read in to initialize the Subsystem ID. For the 82546GB , the Device ID must be forced to 10 7Bh for SerDes-SerDes interface operation.
108 Software Deve loper’s Manual EEPROM Interface Bit Name Description 8 MAC Clock S peed 82541PI/GI Only . 0b = MAC runs at full speed. 1b = MAC runs at 1/4 speed on any drop from 1000 Mb/s. Note: Reserved bit for all other Ethernet controllers (set to 0b ).
Software Developer’s Manua l 109 EEPROM Interface 5.6.13 PHY Register Address Dat a (W ords 10h, 1 1h, and 13h - 1Eh) These settings are specific to individu al platform configurations for the 8 2541xx and 82547GI/EI and should not be altered from the reference design unless instructed to do so.
110 Software Deve loper’s Manual EEPROM Interface T able 5-8. Soft ware Defined Pins Control (W ord 10h, 20h) Bit Name D escription 15 SDPDIR[7] SDPDIR[3] for the 82541xx and 82547GI/EI SDP7(3) Pin - I nitial Direction.
Software Developer’s Manua l 111 EEPROM Interface Note: Since the 82546GB/EB is a dual-port device, the SDP con tro l in 10h corresponds to LAN B, and the SDP control in 20h corresponds to LAN A.
112 Software Deve loper’s Manual EEPROM Interface 5.6.19 Circuit Control (Word 21h) This word is loaded into the C ircuit Control Register (CIRC) fo r setting PCI-X driver strength. See T able 5-2 and T ab le 5-3 for suggested values. Note: PCI-X is not applicable to the 82540EP/EM , 82541 xx , and 82547GI/ EI .
Software Developer’s Manua l 113 EEPROM Interface 5.6.24 Management Control (Word 13h 1 , 23h 2 ) The following table lists the initial settings for the Manageme nt Control Register as well as valid bits for the IPv4 Address and the IPv6 Address. 1.
114 Software Deve loper’s Manual EEPROM Interface Note: Since the 82546GB/EB is a dual-port device, the Manage ment Control in 13h corresponds t o LAN B, and the Management Control in 23h corresponds to LA N A. 5.6.25 SMBus Slave Address (Word 14h 1 low byte, 24h low byte) The following table lists the SM Bus slave address for TCO mode.
Software Developer’s Manua l 115 EEPROM Interface 5.6.26 Initialization Control 3 (Word 14h 1 high byte, 24h high byte) This word controls the general initializatio n values. Note: Since the 82546GB/EB is a dual -port device, the Initiali zation Control W o rd 3 bit assignm ents are port specific.
116 Software Deve loper’s Manual EEPROM Interface 5.6.27 IPv4 Address (Words 15h - 16h 1 and 25h - 26h) The following table lists the initi al values for the IPv4 addresses. Note: Since the 82546GB/EB is a dual-port devi ce, the IPv4 Address in 15h-16h correspon ds to LAN B, and the IPv4 Address in 25h-26h corresp onds to LAN A.
Software Developer’s Manua l 117 EEPROM Interface T able 5-15. Boot Agent Main Setup Options Bit Name Description 15 PPB PXE Presence. Setting this bit to 0b Indicates that the image in the FLASH contains a PXE image. Setting this bit to 1b indicates that no PXE image is contained.
118 Software Deve loper’s Manual EEPROM Interface 5.6.31 Boot Agent Configuratio n Customization Options (W ord 31h) W ord 31h co ntains settings th at can be progra mmed by an OEM or network adm inistrator to customize the operation of the software.
Software Developer’s Manua l 119 EEPROM Interface . T able 5-16. Boot Agent Configuration Customizatio n Options (Wor d 31h) Bit Name Description 15:14 SIG Sig nature. These bits must be set to 1b to indicate that this word has been programmed by the agent or other configuration software.
120 Software Deve loper’s Manual EEPROM Interface 5.6.32 Boot Agent Configuratio n Customization Options (W ord 32h) W ord 32h is used to store the version of the boot agent that is stored in the FLASH image. When the Boot Agent loads, it can check this value to det ermine if any first-time configuration needs to be performed.
Software Developer’s Manua l 121 EEPROM Interface 5.6.33 IBA Cap abilities (Word 33h) W ord 33h is used to enumerate the boot technologies that have b een programmed into the FLASH. It is updated by IBA configuration too ls and is not updated or read by IBA.
122 Software Deve loper’s Manual EEPROM Interface 5.6.35 Checksum Word Calculation (W ord 3Fh) The Checksum word (3Fh) should be calculated su ch that after adding all the words (00h-3Fh), including the Ch ecksum word itself, the sum should be BA BAh.
Software Developer’s Manua l 123 EEPROM Interface 5.7 Parallel FLASH Memory All Ethernet controllers except the 82540EP/EM provide an external parallel interface to an optional FLASH or boot EEPROM device.
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Software Developer’s Manua l 125 FLASH Memory Interface FLASH Memory Interface 7 All Ethernet controllers (except the 82540EP/EM ) provide an external parallel interface to a FLASH, or boot ROM, device such as the Atmel A T49L V010 1 .
126 Software Deve loper’s Manual FLASH Memory Interfa ce 7.2.1 Read Accesses Upon reads to the FLASH address space, the Ethernet controller uses the TRDY# signal to insert target wait states until valid data can be read from the FLASH device and presented on the data lines.
Software Developer’s Manua l 127 FLASH Memory Interface Figure 7- 2. FLASH B uffer Write Cycle FRAME# AD CBE# I RDY# TRD Y# DEVSEL# STOP# ADDRESS DATA MEM- W R BE#s CLK 1 2 3 7 8 9 10 11 12 13 14.
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Software Developer’s Manua l 129 Power Management Power Management 6 6.1 Introduction to Power Ma nagement The PCI/PCI-X Family of Gigabit Ethernet Controllers sup port the Advanced Configuration and Power Interface (ACPI) specificat ion as well as Advanced Power Management (APM).
130 Software Deve loper’s Manual Power Management 6.3 D3 cold support If the AUX pin is co nnected to logic 1b, the Ethernet controller advertises D3 cold W akeup sup port.
Software Developer’s Manua l 131 Power Management 6.3.1.1 Dr St ate At initial boot-up, once LAN_PWR_GOOD is a sserted, the Ethernet controller reads the EEPROM. If the APM Mode bit in the EEPROM’ s Initialization Control W o rd 2 is set then APM W akeup is enabled.
132 Software Deve loper’s Manual Power Management 6.3.1.3 D0a (D0 active) Once memory space is enabled, all in ternal clocks are activated, the Ethernet controller enters an active state, and can then transmit and receive packets if properly config ured by the software driver .
Software Developer’s Manua l 133 Power Management 6.3.2.1 Power Up (Off to Dr to D0u to D0a) Figure 6-2. S tartup T iming 3RZHU LAN_POWER_GOOD CLK# RST# DState 3:5B67$7(>@ D0u Reading EE.
134 Software Deve loper’s Manual Power Management 6.3.2.2 T ransition From D0a to D3 and Back Without PCI Reset Figure 6-3. T ransition from D0a to D3 and Back Without PCI Reset ,B3 &,B &/ .
Software Developer’s Manua l 135 Power Management 6.3.2.3 T ransition From D0a to D3 and Back with PCI Reset Figure 6-4. T ransition From D0a to D3 and Back with PCI Reset &/.
136 Software Deve loper’s Manual Power Management 6.3.2.4 PCI Reset W ithout T ransition to D3 Figure 6-5. PCI Reset Sequence CLK# RST# DSta te PW R_STATE[1:0] D0u Reading EEPR OM Read EEPR OM D0a .
Software Developer’s Manua l 137 Power Management 6.3.3 PCI Power Mana gement Registers Power Management registers are p art of the capabil iti es linked list poin ted to by the Capabilities Pointer (Cap_Ptr) in the PCI configuration space. Refer to Section 4.
138 Software Deve loper’s Manual Power Management 6.3.3.3 Power Management Cap abilities - (PMC) 2 Bytes Offset = 2 (RO) Bit s Default R/W Description 15:1 1 See text Read Only PME_Support – This 5-bit field indicates the power states in which the function may assert PME# a .
Software Developer’s Manua l 139 Power Management 6.3.3.4 Power Management Control / St atus Register - (PMCSR) 2 Bytes Offset = 4 (RO) This register is used to control and monitor power manageme nt events in the Ethernet controller .
140 Software Deve loper’s Manual Power Management 6.3.3.5 PMCSR_BSE Bridge Support Extensio ns 1 Byte Off set = 6 (RO ) This register indicates supp ort for PCI bridge spec ific functions. Note th at these functions are not implemented in the Ethernet controller and the values are set to 00h.
Software Developer’s Manua l 141 Power Management If power management is not disabled and when the Data_Select field is programmed to 0 or 4, the Ethernet controller sets the Data Register to the D0 Power value in the EEPROM.
142 Software Deve loper’s Manual Power Management • Maintains the first magic pack et received in the W akeup Packet Memory (WPM) until the driver writes a 0b to the Magic Packet Received MAG bit in the W akeup Status Register (WUS).
Software Developer’s Manua l 143 Power Management After receiving a wakeup packet, the Ethernet controller ignores any subsequent wakeup packets until the driver clears all of th e “Received” bits in the W akeup St atus Register (WUS).
144 Software Deve loper’s Manual Power Management The Ethernet controller generates a wakeup ev ent after receiving any p acket whose destination address matches one of the 16 valid programmed Receive Addresses if the Dir ected Exact W akeup Enable bit is set in the W akeup Filter Control Regist er (WUFC.
Software Developer’s Manua l 145 Power Management A Magic Packet’ s destination address must match th e address filtering enable d in the configuration registers with the exception that broadcast packets are consid ered to match even if the Br oadcast Accept bit of the Receive Control Register (RCTL.
146 Software Deve loper’s Manual Power Management 6.4.3.1.5 ARP/IPv4 Request Packet 1 The Ethernet controller supports r eceiving ARP Request packets for wa keup if the ARP bit is set in the W akeup Filter Control Register (W UFC). Fo ur IPv4 addresses are supported which are programmed in the IPv4 Address T able (IPv4A T) 2 .
Software Developer’s Manua l 147 Power Management 6.4.3.1.6 Directed IPv4 Packet 1 The Ethernet controller suppo rts receiving Directed IPv4 2 packets for wakeup if the IPv4 bit is set in the W akeUp Filter Control Register (WU FC) . Four IPv4 addresses are supported which are programmed in the IPv4 Address T able (IPv4A T).
148 Software Deve loper’s Manual Power Management 6.4.3.2 Directed IPv6 Packet 1 The Ethernet controller suppor ts receiving Directed IPv6 packets for wakeup if the IP v6 bit is set in the W akeup Fi lter Control Register (WUFC). One IP v6 address is supported and it is programmed in the IPv6 Ad dress T able (IPv6A T).
Software Developer’s Manua l 149 Power Management 6.4.3.3 Flexible Filter The Ethernet controller supports a total of four fl ex ible filters. Each filter i s configured to recognize any arbitrary pattern with in the first 128 bytes of the p acket.
150 Software Deve loper’s Manual Power Management 6.4.3.3.2 Directed IPX Packet Example A valid Directed IPX Packet contains the station’ s MAC add ress, a Protocol T ype o f 8137h, and an IPX Node Address that equals to the station’ s MAC address.
Software Developer’s Manua l 151 Power Management 6.4.3.5 W akeup Packet Storage The Ethernet controller saves the fi rst 128 bytes of the wakeup packet in its intern al buffer , which can be read through t he W akeup Packet Memory (WUPM) after system wakeup.
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Software Developer’s Manua l 153 Ethernet Interface Ethernet Interface 8 8.1 Introduction The PCI/PCI-X Family of Gigabit Ethernet Co ntro llers provide a complete CSMA/CD function supporting IEEE 802.3 (10Mb/s) , 802.3u (100Mb/s), 802.3z and 802.3ab (1000Mb/s) implementations.
154 Software Deve loper’s Manual Ethernet Interface 8.2.1 Internal SerDes Interface/TBI Mode– 1Gb/s 1 The 82546GB/EB and 8254 5GM/EM Ethernet controllers contain one or two int ernal SerDes devices (depending whether or not they support one or two ports).
Software Developer’s Manua l 155 Ethernet Interface 8.2.1.3 Code Group s and Ordered Set s Code group and ordered set definitions are defined in clause 36 of the IEEE 802.3z standard. These represent special symbols used in the en capsulation of Gigabit Ethernet packets.
156 Software Deve loper’s Manual Ethernet Interface 8.2.3 MII – 10/100 Mb/s The internal MII implementation fo r the Ethernet controller provides full IEEE 802.3 and IEEE 802.3u compliant operation for 10Mb/s and 100Mb /s operation in conjunction with the onb oard MII compliant PHY .
Software Developer’s Manua l 157 Ethernet Interface Configuration of the duplex operation of the Ethern et controller can be forced or determined via the Auto-Negotiation process. See Section 8.6 for details on link configuration setup and resolution.
158 Software Deve loper’s Manual Ethernet Interface For receives, the Ethernet cont roller supports carrier extended packets and packets generated during packet burstin g operations (see Section 8.4.2.1 and Section 8.4.2. 2 ). The Ethernet controller can be configured to tran smit in packet burst mode via the TCTL.
Software Developer’s Manua l 159 Ethernet Interface The normal ru les for IPG are followed during packet bursting after the first packet has met the minimum slot time requirement s, with the exception that the Inter Frame Content (IFC) is extension symbols rath er than IDLEs.
160 Software Deve loper’s Manual Ethernet Interface The following section describes the link confi gur ation process in the In ternal Serdes for the 82546GB/EB an d 82545GM/EM (TBI mode for the 82544GC/EI ) and internal PHY modes.
Software Developer’s Manua l 161 Ethernet Interface A set of registers is provided to facilitate either hardware or software Aut o-Negotiation. The hardware supports both hardware and software Auto-Negotiation m ethods for determining link configuration as well as allo wing for manual configuration to force the link.
162 Software Deve loper’s Manual Ethernet Interface Figure 8-3. 802.3z Advertised Base Page Ma pping T able 8-2. Bits Content in TXCW .txConfigWord The reserved bits should be writte n as zero. The remote fault bits [1 3 :12] can be set by software to indicate remote fault t ype to the link p artner if desired.
Software Developer’s Manua l 163 Ethernet Interface 8.6.1.5 Forcing Link In cases where the Ethernet controller is conn ected to a non-Au to-Negotiating link partner, the hardware allows for manual configuration of th e link via the Device Cont rol regist er (CTRL).
164 Software Deve loper’s Manual Ethernet Interface Once PHY Auto-Negotiation is complete, the PHY asserts the link indi cation signal. Software MUST set th e “set link up” bit in the Device Control Register (C TRL.SLU) before the Ether net controller recognizes the link.
Software Developer’s Manua l 165 Ethernet Interface ST A TUS.ASDV [9:8], provi des the results of speed status indication for diagn ostics purposes regardless of whether the Auto-Speed Detection feature is enabled. Th is function is in itiated with a write to the CTRL_EXT .
166 Software Deve loper’s Manual Ethernet Interface 8.6.3 Internal SerDes Mode 1 Control Bit Resolution Ta b l e s 8-3 , 8-4 , and 8-5 2 list how on-chip Aut o-Negotiation affects control bits i n the Ethernet controller . Ta b l e 8 - 5 lis ts the case where software Auto-Neg otiation is not performed and link is forced.
Software Developer’s Manua l 167 Ethernet Interface T able 8-5. Internal Serdes Mode 1 – Auto-Negotiation Skipped TXCW .ANE = 0b 8.6.4 Internal PHY Mode Control Bit Resolution Ta b l e s 8-6 , 8-7 , 8-8 , and 8-9 list how Auto-Negotiati on affects control bits in the Ethernet Controller .
168 Software Deve loper’s Manual Ethernet Interface T able 8-7. GMII/MII Mode – Auto-S peed Detection CTRL.FRCSPD = CTRL.FRCDPLX = 0b; CTRL.ASDE = 1b T able 8-8. GMII/MII Mode – Force Speed CTRL.FRCSPD = 1b; CTRL.FRCD PLX = 0b; CTRL.ASDE = X Control Bit Effect on Control Bits CTRL.
Software Developer’s Manua l 169 Ethernet Interface T able 8-9. GMII/MII Mode – Force Link CTRL.FRCSPD = CTRL.FRCD PLX = CTRL.SLU = 1b 8.6.5 Loss of Signal/Link S t atus Indication For the 82546GB/E B and 82545GM/EM , the internal LOS signal allows for indication of physical link status to the Ethernet controller ’ s MAC.
170 Software Deve loper’s Manual Ethernet Interface 8.7 10/100 Mb/s S p ecific Performance Enhancement s 8.7.1 Adaptive IFS 1 The Ethernet controller supports back-to-back transmit Inter -Frame-Spacing (IFS) of 960 ns in 100 Mb/s operatio n and 9.6 µ s in 10 Mb/s operation.
Software Developer’s Manua l 171 Ethernet Interface 8.7.2 Flow Control Flow control as defined in IEEE specificatio n 8 02.3x, as well as the specific operation of asymmetrical flow control defined by 802.
172 Software Deve loper’s Manual Ethernet Interface The final check for a valid P AUS E frame is the MAC Control Opcode. At this time only the P AUSE control frame opcode is defined. It has a value of 0001h. Frame based flow control diff er entiates XOFF from XON based on the value of the P AUSE timer field.
Software Developer’s Manua l 173 Ethernet Interface Flow control capabilit y must be neg otiated between link partners vi a the Auto-Negoti ation process. The Auto-Negotiation process can m odify the value of th ese bits ba sed on the resolved capability between the local devi ce and the link partner .
174 Software Deve loper’s Manual Ethernet Interface The contents of the Flow Control Receive Thres hold High register (FCR TH) determine at what point hardware transmits a P AUSE frame. Hardware monitors the fullness of the receive FIFO and compares it with the contents of FCR TH.
Software Developer’s Manua l 175 802.1q VLAN Support 802.1q VLAN Support 9 The PCI/PCI-X Family of Gigabit Ethernet Con t rollers provide several specific mechanisms to support 802.1q VLANs: • Optional adding (for transmit s) and stripping (for receives) of IEEE 802.
176 Software Deve loper’s Manual 802.1q VLAN Suppor t T able 9-2. 802.1q T agged Frames 9.2 T ransmitting and Receiving 802.1q Packet s Since the 802.
Software Developer’s Manua l 177 802.1q VLAN Support In summary , the 4096 bit vector is composed of 1 28 32-bit registers. Match ing to this bit v ector follows the same algorithm as indicated in Section 13.5.1 for Multicast Address filtering. The VLAN Identifier (VID) field consists of 12 bits.
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Software Developer’s Manua l 179 Configurable LED Outputs Configurable LED Outputs 10 10.1 Configurable LED Output s 1 The PCI/PCI-X Family of Gigabit Ethernet Controller ’ s MAC implem ents four output drivers intended for driving external LED circuits.
180 Software Deve loper’s Manual Configurable LED Outputs LED outputs can be based on the following expressions: • LINK_UP is asserted while lin k of any speed is maintained • LINK_10 indicates .
Software Developer’s Manua l 181 Configurable LED Outputs Note: It is especially important to note with respect to the blink- control circuit that: • the blink circuit, when enabled, exists as the.
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Software Developer’s Manua l 183 PHY Functionality and Feature s PHY Functionality and Features 11 1 1.1 Auto-Negotiation Auto-Negotiation b etween the PCI/PCI-X Family of Gigabit Ethernet Controllers and its l ink partner is performed by the PHY .
184 Software Deve loper’s Manual PHY Functionality and Features 1 1.1.2 Next Page Exchanges If 1000BASE-T mode is advertised, then the Et hernet controller PHY automati cally sends the appropriate next pages to advertis e the capability and negotiate master /slave mode of operation.
Software Developer’s Manua l 185 PHY Functionality and Feature s 1 1.1.4 St atus Once the PHY completes auto-negoti ation, it upda tes the various statuses in the PHY S tatus Register , Link Partner Ability Register (Base Page), Auto-Negotia tion Expansion Register, and 1000BASE-T Status Register .
186 Software Deve loper’s Manual PHY Functionality and Features 1 1.2.1 Polarity Correction (copper only) The Ethernet controller PHY auto matically corrects for polarity er rors on the receive pairs in 1000BASE-T and 10BASE-T modes. In 100BAS E-TX mode, the polarity d oes not matter .
Software Developer’s Manua l 187 PHY Functionality and Feature s 1 1.3 Cable Length Detection (copper only) In 100/1000 Mbps operation, the Et hernet controller PHY attempts to indicat e the approximate length of the CA T 5 cable attached.
188 Software Deve loper’s Manual PHY Functionality and Features 1 1.4.2 D3 St ate, No Link Required (copper only) Each time the MAC transitions to a D3 or D0u power-state with no link requ ired (wakeup disabled and no manageability enabled), the PHY enters its IEEE power -d own mode, consuming the least amount of power possible.
Software Developer’s Manua l 189 PHY Functionality and Feature s 1 1.5 Initialization Note: Section 1 1.5 throu gh Section 1 1.14 apply only to the 82541xx and 82547GI/EI Ethernet controlle rs. At power-up or reset, the PHY core performs the initialization as shown in Figure 1 1-1 .
190 Software Deve loper’s Manual PHY Functionality and Features 1 1.6 Determining Link St ate The PHY and its link partner determine th e type of link established through one of three methods: • Auto-Negotiation • Parallel Detection • Forced Operation Auto-Negotiation is the only method allowed by the 802.
Software Developer’s Manua l 191 PHY Functionality and Feature s 1 1.6.1 False Link When the PHY is first powered on, reset, or encoun ters a link down state, it must determ ine the line speed and operating co nditions to use for the network link.
192 Software Deve loper’s Manual PHY Functionality and Features 1 1.6.3 Auto Negotiation The PHY supports the IEEE 802.3u Auto-Negotiation scheme with next page capability . Next Page exchange uses PHY register 7d to send informat ion and PHY register 8d to receive them.
Software Developer’s Manua l 193 PHY Functionality and Feature s 1 1.7.3 10BASE-T For 10BASE-T links, the PHY and its link partner begin exchangi ng Normal Link Pulses (NLPs). The PHY transmits an NLP every 16 ms, and expects to receive one every 10 to 20 ms.
194 Software Deve loper’s Manual PHY Functionality and Features T able 10-2 lists the intended operation fo r the various settings of ASM_DIR and Pause. This information is provided fo r reference only; it is the responsibility of the MAC to impl ement the correct function.
Software Developer’s Manua l 195 PHY Functionality and Feature s 1 1.10.1 Powerdown via the PHY Register The PHY can be powered down using the control bit found in PHY register 0d, bit 1 1. This bit powers down a significant portion of th e port but cloc ks to th e register section remain act ive.
196 Software Deve loper’s Manual PHY Functionality and Features Figure 1 1-3. 1000 Base- T PHY Functions Overview Side-stre am Scrambler / Descrambler Trellis Viterbi Encoder/ Decoder 8 8 4 4 MAC In.
Software Developer’s Manua l 197 PHY Functionality and Feature s 1 1.1 1.2 T ransmit Functions This section describes functions used when th e Media Access Controller (MAC) transmits data through the PHY and out onto the twisted-pair connection . 1 1.
198 Software Deve loper’s Manual PHY Functionality and Features 1 1.1 1.3.4 Spectral Shaper This function causes the 4DP AM5 waveform to have a spectral signature that is very close to that of the ML T3 waveform used by 100BASE-TX. Th is enables 1000BASE-T to take advantage of infrastructure (cables, magnetics) designed for 100BASE-TX .
Software Developer’s Manua l 199 PHY Functionality and Feature s Figure 1 1-5. 1000BASE-T Receiv e Flow 1 1.1 1.4 Receive Functions This section describes function blocks that are used when th e PHY receives data from the twisted pair interface and passes it back to the MAC.
200 Software Deve loper’s Manual PHY Functionality and Features • Far-end crosstalk (FEXT) • Propagation delay variation s between channels of up to 120 ns. • Extraneous tones that have been coupled into the receive path. The adaptive filter coef ficients are initially set during the training phase.
Software Developer’s Manua l 201 PHY Functionality and Feature s 1 1.13.1 Link T est In 10 Mbps mode, the PHY always transmits link pulses. If the Link T est Functi on is enabled, it monitors the connection for link pulses.
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Software Developer’s Manua l 203 Dual Port Characteristics Dual Port Characteristics 12 12.1 Introduction 1 The 82546GB/EB architecture includes two instances of both the MAC and PHY (see Figure 2-1 ).
204 Software Deve loper’s Manual Dual Port Characteristics Many of the fields of the PCI h eader space contain hardware default values that are either fixed or can be overridden using EEPROM, but cannot be independently specified for each logical LAN device.
Software Developer’s Manua l 205 Dual Port Characteristics The following fields are implemented unique to each LAN device: 12.2.2 MAC Configuration Register Sp ace All device control/status registers detailed in Section 13.4 , Main Register Descriptions, are implemented per-LAN device.
206 Software Deve loper’s Manual Dual Port Characteristics 12.3 Shared EEPROM The Ethernet controller uses a single EEPROM device to configure hardware default parameters for both LAN devices, including Ethernet Individual Addresses (IA), LED behaviors, receive packet-filters for manageability and wakeup capability , etc.
Software Developer’s Manua l 207 Dual Port Characteristics The result of mul tiple LAN devices’ reading EEPROM is that power-on and reset-initiated EEPROM read sequences might appear slightly di fferently from the sequen ces illustrated during the discussion of powe r-state transitions ( Section 6.
208 Software Deve loper’s Manual Dual Port Characteristics Note: Access contention to FLASH by both LAN devices is more than likely to result in indeterminate data results (during read transactions), corrup ted FLA SH (during write tr ansactions), or other unpredictable behavior .
Software Developer’s Manua l 209 Dual Port Characteristics 12.5.3 Multi-Function Advertisement If one of the LAN devices is disabled, the Ethernet controller no longer is a multi-function device. It normally reports a 01h in the PCI Configuration Header fiel d Header T ype , indicating multi- function capability .
210 Software Deve loper’s Manual Dual Port Characteristics 12.5.6 Summary The following t able lists the various LAN enabled/disabled confi gurations possible: CVDR values sampled-on- reset LAN devi.
Software Developer’s Manua l 211 Register Descriptions Register Descriptions 13 13.1 Introduction This section details the state inside the PCI/PCI-X Famil y of Gigabit Ether n et Controllers that are visible to the programmer . In some cases, it descri bes hardware structures invisible to software in order to clarify a concept.
212 Software Deve loper’s Manual Register Desc riptions • Reserved and/or undefined addresses. Any register not explic itly declared in this specification should be considered to b e reserved and should n ot be written. Writing to reserved or undefined register addresses can cause indeterminate behavior .
Software Developer’s Manua l 213 Register Descriptions 13.2.2 I/O-Mapped Internal Regis ter , Internal Memory , and Flash 1 T o suppo rt pre-boot operation (prio r to the allo cation of physical memory base addresses), all internal registers, memories, and Flash can be accessed using I/O operations.
214 Software Deve loper’s Manual Register Desc riptions The IODA T A register can be written as a byte, word, or Dword access when the IOADDR register contains a value for the Flash (80000h - FFFFFh). In this case, the value in IOADDR must be properly aligned to the data value.
Software Developer’s Manua l 215 Register Descriptions T able 13 -2. Etherne t Controller Regi ster Summary Category Offset Abbreviation Name R/W Page General 00000h CTRL Device Control R/W 220 Gene.
216 Software Deve loper’s Manual Register Desc riptions Categor y Offset Abbrevi ation Name R/W Page TX DMA 03000h TXDMAC TX DMA Control (applicable to the 82544GC/ EI only) R/W 315 TX DMA 03828h TX.
Software Developer’s Manua l 217 Register Descriptions Category Offset Abbreviation Name R/W Page S tatistics 04054h X OFFTXC XOFF Transmitted Count R 345 S tatistics 04058h FCRUC FC Received Unsupp.
218 Software Deve loper’s Manual Register Desc riptions Note: The PHY registers are accesse d indirectly thro ugh the MDI/O interface described in Sectio n 8.
Software Developer’s Manua l 219 Register Descriptions 13.3 PCI-X Register Access Split 1 The PCI-X specification states that accesses to internal device memory spaces must complete within a specific tar get initial latency , or else the device should signal that it completes the transaction later using a split-co mpletion operation.
220 Software Deve loper’s Manual Register Desc riptions The EEPROM configuration bit “Force CSR Read Sp lit” (Initialization Cont rol W ord 2, word 0Fh) provides the ability to configure the de vice to split all internal re gister accesses, rather than providing non-split behavior for the registers listed.
Software Developer’s Manua l 221 Register Descriptions T able 13-3. CTRL Regi ster Bit Description 31 0 Device Control Bits Field Bit(s) Initial Va l u e Descripti on FD 0 1b 0b 1 Full-Duplex Enables software to override the hardware Auto-Negotiation function.
222 Software Deve loper’s Manual Register Desc riptions SLU 6 0b Set Link Up In TBI mode/internal SerDes, provides man ual link configuration. When set, the Link Up signal is forced high once receiver synchronization is achi eved (LOS not asse rted) using CTRL.
Software Developer’s Manua l 223 Register Descriptions FRCDPLX 12 0b Force Duplex When set, software can override t he duplex indication from the PHY which is in internal PHY mode. When set the CTRL .FD bit sets duplex. When cleared, the CTRL.FD is ignored.
224 Software Deve loper’s Manual Register Desc riptions RST 26 0 b Device Res et 0b = normal; 1b = reset. Self clearing. When set, it globally resets the entire Ethernet controller with the exception of the PCI configur ation registers. All registers (receive, transmit, interrupt, statis tics, etc.
Software Developer’s Manua l 225 Register Descriptions The ADVD3WUC bit (Advertise D3Cold W akeup Capability En able control) allows the AUX_PWR pin to determine whether D3C old support is advertised.
226 Software Deve loper’s Manual Register Desc riptions T able 13-5. St atus Register Bit Description 31 13 12 0 Reserved S tatus Field Bit(s) Initial Va l u e Descriptio n FD 0 X Link Full Duplex c onfiguration Indication When cleared, the Ethernet controller operates in half-duplex; when set, the Ethernet controller operates in Full duplex.
Software Developer’s Manua l 227 Register Descriptions SPEED 7:6 X Link speed setting Indicates the configured speed of the link. These bits are either forced by software when forcing the link speed through the CTRL.
228 Software Deve loper’s Manual Register Desc riptions 13.4.3 EEPROM/Flash Control & Dat a Register EECD (00010h; R/W) This register provides a simp lified interface for software acces ses to the EEPROM. Software controls the EEPROM by successive writes to this register .
Software Developer’s Manua l 229 Register Descriptions This register provides software direct access to the EEPROM. Software can control the EEPROM by successive writes to this register . Data & ad dress information is cloc ked into the EEPROM by software toggling the EESK bi t (2) of this register with EECS set to 1b.
230 Software Deve loper’s Manual Register Desc riptions 13.4.4 EEPROM Read Register 1 EERD (00014h; R W) T able 13-7. EEPROM Read Register Bit Description 1.
Software Developer’s Manua l 231 Register Descriptions T able 13-8. EEPROM Read Register Bit Description (82541xx and 82547GI/EI) This register is used by s oftware to cause the Et hernet controller to read individual words in the EEPROM.
232 Software Deve loper’s Manual Register Desc riptions 13.4.5 Flash Access 1 FLA (0001Ch; R/W) This register provides software direct access to the Flash me mory .
Software Developer’s Manua l 233 Register Descriptions 13.4.6 Extended Device Control Register CTRL_EXT (00018h, R/W) This register and the Device Control register (CTRL) control s the major operational modes for the Ethernet controller .
234 Software Deve loper’s Manual Register Desc riptions SDP6_IODIR SDP2_IODIR ( 82541xx and 82547GI/EI ) 10 0b 1 SDP6[2] Pin Directionality . Controls whether software-controllable pin SDP6[2] is configured as an input or output (0b = input, 1b = output).
Software Developer’s Manua l 235 Register Descriptions The Ethernet controller allows for up to two ex t ernally controlled interrupts. The upper two software-definable pins, SDP[7: 6] (SDP[3:2] for the 82541xx and 82547GI/EI ), can be mapped for use as GPI interrupt bits.
236 Software Deve loper’s Manual Register Desc riptions T able 13-12. 82544GC/EI CTRL_EXT Register Bit Description 31 16 15 0 Reserved Extended Device Control Bits Field B it(s) Initial Va l u e Des.
Software Developer’s Manua l 237 Register Descriptions T able 13-13. 82544GC/EI GPI to SDP Bit Mapping SPD_BY PS 15 0 S peed Select Bypass When set to 1b, all speed detection mecha nisms are bypassed, and the Ethernet controller is immedia tely set to the speed indicated by CTRL.
238 Software Deve loper’s Manual Register Desc riptions 13.4.7 MDI Control Register MDIC (00020h; R/W) Software uses this register to read or write Management Data Interface (MDI) registers in the internal PHY .
Software Developer’s Manua l 239 Register Descriptions T able 13-14. MDI Control Register Bit Descript ion 31 30 29 28 27 26 25 21 20 16 15 0 RSV E I R OP PHY REG DA T A Field Bit(s) Initial Va l u e Description DA T A 15:0 X Data In a Write command, software places the dat a bits and the Ethernet controller shifts them out to the PHY .
240 Software Deve loper’s Manual Register Desc riptions 13.4.7.1 PHY Registers This document uses a special nomenclature to define the read/write mode of individual bits in each register . See Ta b l e 1 3 - 1 5 . For all binary equations appearing i n the register map, the symbol “| ” is equivalent to a binary OR operation.
Software Developer’s Manua l 241 Register Descriptions 13.4.7.1. 1 PHY Control Register PCTRL (00d; R/W) T able 13-16. PHY Control Register Bit Description Field Bit(s) Description Mo de HW Rst SW Rst Reserved 5:0 These bits are reserved and should be set to 000000b.
242 Software Deve loper’s Manual Register Desc riptions Power Down 11 1b = Power down. 0b = Normal operation. Power down shuts down the Ethernet controller except for the MAC interface if the MAC interface power down bit is set to 1b. If it equals 0b, then the MAC interface also shuts down.
Software Developer’s Manua l 243 Register Descriptions Auto-Negotiation Enable 12 1b = Enable Auto-Negotiation Process. 0b = Disable Auto-Negotiation Process. A write to this bit does not take effect until a software reset is asserted, Restart Auto-Negotiation is asserted, or Power Down transitions from power down to normal operation.
244 Software Deve loper’s Manual Register Desc riptions 13.4.7.1.2 PHY St atus Register PST A TUS (01d; R) T able 13-17. PHY St atus Register Bit Description Field Bit(s) Description Mode HW Rst S W Rst Extended Capability 0 1b = Extended register capabilities.
Software Developer’s Manua l 245 Register Descriptions 10 Mb/s Full Duplex 12 1b = PHY able to perform full duplex 10BASE-T . 0b = PHY not able to perform full duplex 10BASE-T . 82544GC/EI only: Bit 14 = Bit 13 = Bit 12 = Bit 1 1 = (MODE[3:0] is not any of xx01b, 1x00b, 001xb, 01 1 1b).
246 Software Deve loper’s Manual Register Desc riptions 13.4.7.1.3 PHY Identifi er Regis ter (LSB) PID (02d; R) 13.4.7.1.4 Extended PHY Identifier Regist er (MSB) EPID (03d; R) T able 13-18. PHY Identifier Bit Description Field Bit(s) Description Mode HW Rst S W Rst Organizationally Unique Identifier Bit 18:3 1 1.
Software Developer’s Manua l 247 Register Descriptions 13.4.7.1.5 Auto-Negotiation Advertisement Register ANA (04d; R/W) T able 13-20. Auto-Negotiation Advert isement Register Bit Desc ription Field Bit(s) Description Mod e HW Rst SW Rst Selector Field 4:0 00001b = 802.
248 Software Deve loper’s Manual Register Desc riptions 100BASE-TX Half Duplex 100Base-TX ( 82541xx and 82547GI/EI ) 7 1b = Advertise. 0b = Not advertised. V alues programmed in the Auto- Negotiation advertisement register have no effect unless Auto- Negotiation is restarted (PHY Control Register) or link goes down.
Software Developer’s Manua l 249 Register Descriptions Asymmetric Pause ASM_DIR for the ( 82541xx and 82547GI/EI ) 11 1b = Asymmetric Pause. 0b = No asymmetric Pause. V alues programmed in the Auto- Negotiation advertisement register have no effect unless Auto- Negotiation is restarted (PHY Control Register) or link goes down.
250 Software Deve loper’s Manual Register Desc riptions 82544GC/EI Only: T able 13-21. Auto-Negotiatio n Advertisement Register Bit Description (MODE[3:0] is one of 001xb , 01 1 1b) Field Bit(s) Des.
Software Developer’s Manua l 251 Register Descriptions 13.4.7.1.6 Link Partner Ab ility Register (Base Page) LP A (05d; R) Next Page 15 0b = Not advertised V alues programmed in this register have no effect unless Auto-Negotiation is restarted (PHY Control Register) or th e link goes down.
252 Software Deve loper’s Manual Register Desc riptions 82544GC/EI Only: T able 13-23. Link Partner Abilit y Register (Base Page) Bit Description 1 1. (MODE[3:0] is one of 001 xb, 0111b). Field Bit(s) Description Mode HW Rst S W Rst Reserved 4:0 Reserved.
Software Developer’s Manua l 253 Register Descriptions 82541xx and 82547GI/EI Only: T able 13-24. PHY Link Page Ability Bit Description 1 1. PHY register 8d st ores the Auto-Negot iation Link Partner Rece ive d Next Pages. PHY re gister 5d is not used to store Next Pages.
254 Software Deve loper’s Manual Register Desc riptions 13.4.7.1.7 Auto-Negotia tion Exp ansion Register ANE (06d; R) NOTE: The ANE Register is not valid until the Auto-Negot iation complete bit in the PHY S tatus Register indicates completion of the Auto-Negotiation process.
Software Developer’s Manua l 255 Register Descriptions 13.4.7.1 .8 Next Page T ransmit Register NPT (07d; R/W) T able 13-26. Next Page T ransmit Register Bit Description Field Bit(s) Description Mod e HW Rst SW Rst Message/ Unformatted Field 10:0 T ransmit Code Word Bit 10:0.
256 Software Deve loper’s Manual Register Desc riptions 13.4.7.1.9 Link Partne r Next Page Register LPN (08d; R) T able 13-27. Link Partner Next Page Register Bit Description Bit(s) Field Description Mode HW Rst SW Rst 10:0 Message/ Unformatted Field Received Code Word Bit 10:0.
Software Developer’s Manua l 257 Register Descriptions 13.4.7.1.10 1000BASE-T Control Register GCON (09d; R/W) T able 13-28. 1000BASE-T Contro l Register Bi t Description Bit(s) Field Des cription Mode HW Rst SW Rst 7:0 Reserved Reserved. Should be set to 00000000b.
258 Software Deve loper’s Manual Register Desc riptions NOTES: 1. V alues programmed in bits 12:8 of the 1000BASE-T Co ntrol Register have no effect unless Auto-Negotiation is restarted (PHY Control Register , bit 9) or the link goes down. These bits can also be overridden by the PHY Contro l Regis ter .
Software Developer’s Manua l 259 Register Descriptions 13.4.7.1.12 Extended PHY S tatus Register EPST A TUS (15d; R) NOTES: 1. 1000BASE-X Half Duplex only applicable to the 8 2544GC/EI . 2. Bit 12 = bit 13 = 1b if MODE[3:0] does not = 001xb or 01 1 1b.
260 Software Deve loper’s Manual Register Desc riptions 13.4.7.1.13 PHY Specif ic Control Register PSCON (16d; R/W) T able 13-31. PHY Specif ic Control Register Bit Description Field Bit(s) Description Mode HW Rst SW Rst 1000BASE-T 10/100BASE-T Disable Jabber 0 1b = Disable jabber function.
Software Developer’s Manua l 261 Register Descriptions PHY Port Configuration Register (82541xx an d 82547GI/EI Only) PPCONF (16d; R/W) Energy Detect 9:8 Energy Detect. 0xb = Off. 10b = Sense only on receive. 1 1b = Sense and periodically transmit NLP .
262 Software Deve loper’s Manual Register Desc riptions Auto MDIX Parallel Detect Bypass 4 Auto_MDIX Parallel Detect Bypass. Bypasses the fix to IEEE auto-MDIX algorithm for the case where the PHY is in forced-speed mode and the link partner is auto-negotiating.
Software Developer’s Manua l 263 Register Descriptions 13.4.7.1.14 PHY S pecific St atus Register PSST A T (17d; R) T able 13-33. PHY Specific St atus Reg ister Bit Descripti on Field Bit(s) Description Mod e HW Rst SW Rst Jabber (real time) 0 1b = Jabber .
264 Software Deve loper’s Manual Register Desc riptions S peed and Duplex Resolved 11 1b = Resolved. 0b = Not resolved. S peed, Duplex, MDI Crossover Status, T r ansmit Pause Enable, and Receive Pause Enable bits are valid only after the S peed and Duplex Reso lved bit (1 1) is set.
Software Developer’s Manua l 265 Register Descriptions PHY Port St atus 1 Regi ster (82541xx and 82547GI/EI Only) PPST A T (17d; R) T able 13-34. PHY St atus 1 Register Bit Description Field Bit(s) Description Mod e HW Rst SW Rst LFIT Indicator 0 S tatus bit indicating the Auto- Negotiation Link Fail Inhibit Timer has expired.
266 Software Deve loper’s Manual Register Desc riptions 13.4.7.1.15 PHY Interr upt Enable Register PINTE (18d; R/W) T r ansmit S tatus 13 1b = PHY currently transmitting a packet. 0b = PHY transmitter is IDLE. When in loopback, this bit reads as 0b.
Software Developer’s Manua l 267 Register Descriptions PHY Port Control Register (82541x x and 82547GI/EI Only) PPCONT (18d; R/W) Page Received Interrupt Enable 12 1b = In terrupt enable. 0b = Interrupt disable. R/W 0b Retain Duplex Changed Interrupt Enable 13 1b = In terrupt enable.
268 Software Deve loper’s Manual Register Desc riptions 13.4.7.1.16 PHY Interr upt Status Register PINTS (19d; R) MDI-X Mode 13 Force MDI-X mode. V alid only when operating in manual mode. (PHY register 18, bit 12 = 0b. 1b = MDI-X (cross over). 0b = MDI (no cross over).
Software Developer’s Manua l 269 Register Descriptions PHY Link Health Register (82541xx and 82 547GI/EI Only) PLINK (19d; R) FIFO Over/Underflow 7 1b = Over/Underflow Error . 0b = No FIFO Error . RO, LH 0b 0b False Carr ier 8 1b = False carrier . 0b = No false carrier .
270 Software Deve loper’s Manual Register Desc riptions Auto-Negotiation Fault 6 Auto-Negotiate Fault: This is the logical OR of PHY register 1, bit 4, PHY register 6, bit 4, and PHY register 10, bit 15. RO 0b 0b Reserved 7 Always read as 0b. RO 0b 0b Data Err[0] 8 Mode: 10: 10 Mbps polarity error .
Software Developer’s Manua l 271 Register Descriptions 13.4.7.1.17 Extended PHY S pecific Control Register 1 1 EPSCON1 (20d; R/W) 1. Extended PHY Specific Control Register - EPSCON for the 82544GC/EI only .
272 Software Deve loper’s Manual Register Desc riptions GMII FIFO Register (82541x x and 82547GI/EI Only) PFIFO (20d; R/W) NOTES: 1. The default is determined by EEPROM bit SPD_EN.
Software Developer’s Manua l 273 Register Descriptions 13.4.7.1. 18 PHY Receive Error Counter PREC (21d; R) NOTE: The counter stops at FFFFh and does not roll ove r . PHY Channel Quality Register (82541xx and 82547GI/EI Only) PCHAN (21d; R) 13.4.7.1.
274 Software Deve loper’s Manual Register Desc riptions LED S tretch Disab le 5 Disable the SPEED_TEN_LED Extension Logic. 0b = Enable logic. 1b = Disable logic. Note: Only when both the stretch and blink are disabled the input bypasses the blink logic and is muxed out with no sampling (only combinational logic).
Software Developer’s Manua l 275 Register Descriptions 13.4.7.1 .20 PHY Global S tatus (82544GC/ EI Only) PGST A T (23d; R) NOTE: Bits 3:0 remain high until the active correspondin g interrupt bits are cleared on a read of the PHY Interrupt S tatus Register.
276 Software Deve loper’s Manual Register Desc riptions 13.4.7.1.22 PHY LE D Control Register (825 44GC/EI O nly) PLED (24d; R/W) LED S tretch Disab le 11 Disable the SPEED_1000_LED Extension Logic.
Software Developer’s Manua l 277 Register Descriptions 13.4.7.1.23 Extended PHY S pecific Control Register 2 EPSCON2 (26d; R/W) NOTE: Not applicable to the 82540EP/EM , 82544GC/EI , 82541xx , or 82547GI/EI . 13.4.7.1.24 Extended PHY S pecific St atus Register (82544GC/EI Only) EPSST A T (27d; R) 13.
278 Software Deve loper’s Manual Register Desc riptions 13.4.7.1.26 MDI R egister 30 Access Window 1 R30A W (30d; R/W) 13.4.7.1.27 Documented MD I Regi ster 30 Ope rations 1 Unless otherwise specified, no reset operations are re quired in order for the following operati ons to take effect.
Software Developer’s Manua l 279 Register Descriptions 13.4.7.1.28 PHY Page Select Register (82541x x and 82547GI/EI Only) PP AGE (31d; R/W) 13.4.8 Flow Control Address Low FCAL (00028h; R/W) Flow control packets are defined by IEEE 802.3x to be either a unique multicast address or the station address with the EtherT ype field indi cating P AUSE.
280 Software Deve loper’s Manual Register Desc riptions T able 13-54. FCAH Register Bit Description 13.4.10 Flow Control T ype FCT (00030h; R/W) This register contains the type fi eld that hardw are matches to r ecognize a flow control packet and that hardware uses when transmit ting a P AUSE packet to its rem ote node.
Software Developer’s Manua l 281 Register Descriptions T able 13-56. VET R egister Bit Description 13.4.12 Flow Control T ransmit Timer V alue FCTTV (00170h; R/W) Provides the Pause slot time value to be in cluded in the transmitted XOFF Pause packets.
282 Software Deve loper’s Manual Register Desc riptions 13.4.13 T ransmit Configuration W ord Register 1 TXCW (00178h; R/W) This register is applicable to the TBI mode/int ernal SerDes mode of operatio n. For internal PHY operation, program the register to 0000h.
Software Developer’s Manua l 283 Register Descriptions Note: Careful attention to the IEEE 802.3z standard is requir ed in order to meet specified timing requirements for timin g during a software negotiated link.
284 Software Deve loper’s Manual Register Desc riptions T able 13-59. RXCW Register Bit Description Field Bit(s) Initial Va l u e Descript ion RxConfigWord 15:0 X Data received during Auto-Negotiation process. When performing hardware Auto-Negotiation (TXCW .
Software Developer’s Manua l 285 Register Descriptions 13.4.15 LED Control 1 LEDCTL (00E00h; RW) RxConfig 29 0b /C/ order set reception indication 0b = Receive idle/data stream. 1b = Receiving /C/ orde r sets. Provides an indication as to whether the interface is receiving /C/ order set, or n ormal idle/data stream.
286 Software Deve loper’s Manual Register Desc riptions T able 13-60. LED Control Bit Description 1 13.4.15.1 MODE Encodings for LED Output s 1 The T abl e 13-61 lists the MODE encodings used to sel ect the desired LED s ignal source for each LED output.
Software Developer’s Manua l 287 Register Descriptions T able 13-61. Mode Encodings for LED Output s 1 Mode Pneumonic State / Event Indicated 0000b LINK_10/1000 Asserted when eit her 10 or 1000 Mbps link is established and maintained. 0001b LINK_100/1000 Asserted when eit her 100 or 1000 Mbps link is established and maintained.
288 Software Deve loper’s Manual Register Desc riptions 13.4.16 Packet Buffer Allocation PBA (01000H; R/W) This register sets the on-chip receive and transmit storage alloca tion ratio. The receive allocation value is read/write for the lower seven bits.
Software Developer’s Manua l 289 Register Descriptions 13.4.17 Interrupt Ca use Read Register ICR (000C0H; R) This register contains all interrupt conditi ons for the Ethernet controller . Each time an interrupt causing event occurs, the corresponding interru pt bit is set in this register .
290 Software Deve loper’s Manual Register Desc riptions RXT0 7 0b Receiver Timer Interrupt Set when the receiver timer expires. The receiver timer is used for receiver descriptor packing. T imer expiration flushes any accumulate d descriptors and sets an interrupt event when enabled.
Software Developer’s Manua l 291 Register Descriptions Note: The 82547GI/EI signals interrup ts over the CSA port, not a dedicated interrupt pin. 13.4.18 Interrupt Throttling Registe r 1 ITR (000C4h; R/W) Software can use this register to pace (or even out) the delivery of interrupts to the host CPU.
292 Software Deve loper’s Manual Register Desc riptions 13.4.19 Interrupt Cause Set Register ICS (000C8h; W) Software uses this register to s et an interrup t condition. Any bit written with a 1b sets the corresponding interrupt. This resu lts in the corresponding bit b eing set in the Interrup t Cause Read Register (see Sectio n 13.
Software Developer’s Manua l 293 Register Descriptions 13.4.20 Interrupt Mask Set/Read Register IMS (000D0h; R/W) An interrupt is enabled if its correspondin g mask bi t is set to 1b, and d isabled if its correspon ding mask bit is set to 0b.
294 Software Deve loper’s Manual Register Desc riptions 13.4.21 Interrupt Mask Clear Register IMC (000D8h; W) Software uses this register to disable an interr upt. Interrupts are presented to the bus interface only when the mask bit is set to 1b and the cause bit set to 1b.
Software Developer’s Manua l 295 Register Descriptions Software should write a 1b to the reserved bits to ensure future compatibility . Since this register masks interrupts when 1b is written to the.
296 Software Deve loper’s Manual Register Desc riptions 13.4.22 Receive Control Register RCTL (00100h; R/W) This register controls all Ethern et controller receiver functions. T able 13-67. RCTL Register Bit Descr iption TXD_LOW 15 X Clears the mask for Transmit Desc riptor Low Threshold hit (not applicable to the 82544GC/EI ).
Software Developer’s Manua l 297 Register Descriptions MPE 4 0b Multicast Pr omiscuous Ena bled 0b = Disabled. 1b = Enabled. When set, passes without filtering out all rece ived multicast packets. Otherwise, the Ethernet controller accepts or rejects a multicast packet based on its 4096-bit vector multicast filtering table.
298 Software Deve loper’s Manual Register Desc riptions BAM 15 0b Broadcast Accept Mode. 0 = ignore broadcast; 1 = accept broadcast packets. When set, passes and does not filt er out all received broadcast packets. Otherwise, the Ethernet controller accepts, or rejects a broadcast packet only if it matches through perfect or imperfect filters.
Software Developer’s Manua l 299 Register Descriptions PMCF 23 0b Pass MAC Control Frames 0b = Do not (specially) pass MAC control frames. 1b = Pass any MAC control frame (type field value of 8808h) that does not contain the pause opcode of 0001h. PMCF controls the DMA function of MAC control frames ( other than flow control).
300 Software Deve loper’s Manual Register Desc riptions 13.4.23 Flow Control Receive Threshold Low FCRTL (02160h; R/W) This register contains the receive threshold used to determine when to send an XON packet. It counts in units of bytes. Each time the recei ve FIFO crosses the r eceive high threshold FCR TH.
Software Developer’s Manua l 301 Register Descriptions 13.4.24 Flow Control Receive Threshold High FCRTH (02168h; R/W) This register contains the receive threshold used to determine when to send an XOFF packet.
302 Software Deve loper’s Manual Register Desc riptions 13.4.25 Receive Descriptor Base Address Low RDBAL (02800h;R/W) This register contains the lower bits of th e 64-bit descriptor base address. The four low-order register bits are always ignored.
Software Developer’s Manua l 303 Register Descriptions 13.4.27 Receive Descriptor Length RDLEN (02808h; R/W) This register determines the number of bytes allocated to the circular receive descriptor buffer . This value must be 128-byte aligned (t he maximum cache line size).
304 Software Deve loper’s Manual Register Desc riptions 13.4.29 Receive Descriptor T ail RDT (02818h;R/W) This register contains the tail pointers for the recei ve descriptor buffer . The register points to a 16- byte datum. Software writes the ta il register to add receive descriptors to the hardware fre e list for the ring.
Software Developer’s Manua l 305 Register Descriptions This feature operates by initiating a countdown timer upon successfully receiving each packet to system memory . If a subsequent packet is received BEFORE the time r expires, the timer is re- initialized to the programmed value and re-starts its countdow n.
306 Software Deve loper’s Manual Register Desc riptions When this timer is enabled, a separate absolu te countdown timer is initiated upon successfully receiving each packet to system memory . When this absolute timer expires, pending receive descriptor writebacks are flushed and a receive timer interrupt is generated.
Software Developer’s Manua l 307 Register Descriptions T able 13-76. TCTL Register Bit Description 31 26 25 22 21 12 1 1 4 3 0 Reserved CNTL Bits COLD CT CNTL Bits Field Bit(s) Initial Va l u e Description Reserved 0 0b Reserved Write as 0b for future compatibility .
308 Software Deve loper’s Manual Register Desc riptions For the 82541xx and 82547GI/EI , carrier extens ion (through the TCTL COLD field) provides a method to increase the duration of the carrier ev.
Software Developer’s Manua l 309 Register Descriptions T able 13-77. TIPG Register Bit Descr iption 31 30 29 20 19 10 9 0 Reserved IPGR2 IPGR1 IPG T Field Bit(s) Initial Va l ue Descrip tion IPG T 9.
310 Software Deve loper’s Manual Register Desc riptions 13.4.35 Adaptive IFS Throttle - AIT AIFS (00458;R/W) This register throttles back-to-b ack transmissions in the transmit packet buf fer and delays their transfer to the CSMA/CD transmit function.
Software Developer’s Manua l 311 Register Descriptions T able 13-78. AIFS Register Bit Description 13.4.36 T ransmit Descriptor Base Address Low TDBAL (03800h; R/W) This register contains the lower bits of the 64- bit transmit Descriptor base address.
312 Software Deve loper’s Manual Register Desc riptions 13.4.37 T ransmit Descri ptor Base Address High TDBAH (03804h; R/W) This register co ntains the upper 32 bits of the 64-bit transmit Descriptor base address. T able 13-80. TDBAH Regi ster Bit Description 13.
Software Developer’s Manua l 313 Register Descriptions 13.4.39 T ransmit Descriptor Head TDH (03810h; R/W) This register contains the head pointer for the transmit descriptor ring. It holds a value that is an offset from the base, and indicates the in–progr ess descriptor .
314 Software Deve loper’s Manual Register Desc riptions 13.4.40 T ransmit Descriptor T ail TDT (03818h; R/W) This register contains the tail point er for the transmit descriptor ri ng. It holds a value that is an offset from the base, and indicates the location beyond the last descriptor hardware can process.
Software Developer’s Manua l 315 Register Descriptions T able 13-84. TIDV Register Bit Description 13.4.42 TX DMA Contro l (82544GC/EI only) TXDMAC (03000h; R/W) This register controls the transmit DMA pre-fetching and preemption abilities. T able 1 1-85.
316 Software Deve loper’s Manual Register Desc riptions T able 13-86. TXDCTL Register Bit Descrip tion 31 25 24 23 22 21 16 15 14 13 8 7 6 5 0 L WTHRESH RSV 1 1.
Software Developer’s Manua l 317 Register Descriptions Since write back of transmit descriptors is opt ional (under the control of RS bit in the descriptor), not all processed descriptors ar e counted with respect to WTHR ESH. Descriptors start accumu- lating after a descriptor with RS (or RPS for the 82544GC/EI ) is set.
318 Software Deve loper’s Manual Register Desc riptions The transmit interrupt delay timer (TIDV) can be used to coalesce transmit interrupts. However , it might be necessary to ensure that no com pleted transmit remains unnoticed for too long an interval in order ensure timely release of transmit buffers .
Software Developer’s Manua l 319 Register Descriptions When performing TCP segmentation, the packet prot otype header initially transferred by DMA is stored internally and updated as each packet of the TCP segmentation operation is composed.
320 Software Deve loper’s Manual Register Desc riptions 13.4.46 Receive Descriptor Control RXDCTL (02828h; R/W) This register controls the fetching and write-back of receive descriptors. Th e three threshold values are used to determine when descriptors are read from and written to host memory .
Software Developer’s Manua l 321 Register Descriptions 13.4.47 Receive Checksum Control RXCSUM (05000h; R/W) The Receive Checksum Control regi ster controls the receive check sum of floading features of the Ethernet controller .
322 Software Deve loper’s Manual Register Desc riptions Field Bit (s) Initial Va l ue Descript ion PCSS 7:0 0b Packet Checksum S tart Controls the starting byte for the Packet Checksum calculation. The Packet Checksum is the one’s complement over the receive packet, starting from the byte indicated by RXCSUM.
Software Developer’s Manua l 323 Register Descriptions 13.5 Filter Registers This section contains detailed descriptions for those registers asso ciated with the Ethernet controller ’ s address filter capabilities.
324 Software Deve loper’s Manual Register Desc riptions Of the 16 bits, look at bits 1 1:5, starting from zero. These seven bits corresponds to the row within the MT A table (the M T A has 128 rows which require seven bits to define). In the example, bits 1 1:5 are 1011 1 10b .
Software Developer’s Manua l 325 Register Descriptions 13.5.2 Receive Address Low RAL (05400h + 8*n; R/W) 16 registers contain the lower bits of the 48-bit Et he rnet address. All 32 bits are valid. Software can access the High and Low registers as a register pair if it can perform a 64-bit access to the PCI bus.
326 Software Deve loper’s Manual Register Desc riptions T able 13-91. RAH Register Bit Description 13.5.4 VLAN Filter T a ble Array 1 VFT A[127:0] (05600h – 057FCh; R/W) The Ethernet controller provides a 4096-bit vector VLAN Filter table array .
Software Developer’s Manua l 327 Register Descriptions T able 13-92. VFT A[127:0] Bit Descrip tion 13.6 W akeup Registers 13.6.1 W akeup Control Register WUC (05800h; R/W) This register is reset any tim e LAN_PWR_GOOD is set to 0b. When AUX_POWER equals 0b, this register is also reset by de-asserting (rising edge) RST#.
328 Software Deve loper’s Manual Register Desc riptions 13.6.2 W akeup Filter Control Register WUFC (05808h; R/W) This register is used to enable each of the pre- defined and flexible filt ers for wakeup support. A value of 1b means the filter is turned on, and a value of 0b means the filter is turned off.
Software Developer’s Manua l 329 Register Descriptions 13.6.3 W akeup St atus Register WUS (05810h; R) This register is used to record statistics abou t all wakeup packets received. If a packet matches multiple criteria then mul tiple bits could be set.
330 Software Deve loper’s Manual Register Desc riptions 31 20 19 18 17 16 15 8 7 6 5 4 3 2 1 0 Reserved FLX3 FLX2 FLX1 FLX0 Reserved IPv6 1 IP v4 2 ARP BC MC EX MAG LNKC 1. Not applicable to the 82544GC/EI . 2. IP for the 82544GC/EI . Field Bit(s) Init ial V alue Description LNKC 0 0b Link S tatus Change.
Software Developer’s Manua l 331 Register Descriptions 13.6.4 IP Address V alid IP A V (5838h; R/W) The IP Address V alid indicates whether the IP addresses in th e IP Address T able are valid. The valid bits are reset any time LAN_PWR_G OOD is 0b. When A UX_POWER equals 0b, the valid bits are also reset by deasserting (rising edge) RST#.
332 Software Deve loper’s Manual Register Desc riptions 13.6.5 IPv4 Address T a ble 1 IP4A T (05840h - 05858h; R/W) 2 The IPv4 Address T able is used to store the four IP addresses for ARP Request packet and Directed IP packet wakeup for IPv4. Note: This table is not cleared by any reset.
Software Developer’s Manua l 333 Register Descriptions 13.6.6 IPv6 Address T a ble 1 IP6A T (05880h - 0588Ch; R/W) The IPv6 Address T able is used to store the IPv6 addresses for ARP Request packet and Directed IP packet wakeup for IPv6. Note: This table is not cleared by any reset.
334 Software Deve loper’s Manual Register Desc riptions 13.6.7 W akeup Packet Length WUPL (05900h; R/W) This register indicates the length of the first wakeup packet received. It is valid if one of the bits in the W akeup Status Register (WUSR) is set.
Software Developer’s Manua l 335 Register Descriptions Before writing to the Flexible Filter Length T able th e driver must first disable the flexible filters by writing 0b’ s to the Flexible Filter Enable bits of the W a keup Filter Control Register (WUFC.
336 Software Deve loper’s Manual Register Desc riptions 13.6.1 1 Flexible Filter V alue T able FFVT (09800h - 09BF8h; R/W) The Flexible Filter V alue and T able is used to store the one value for each byte location in a packet for each flexible filter .
Software Developer’s Manua l 337 Register Descriptions All Statistics registers reset when read. 64-bit registers reset whenever the upper 32 bits are read. In addition, they stick at FFFFh_FFFFh when the maximum value is reached. The Statistics registers are not hardware initialized.
338 Software Deve loper’s Manual Register Desc riptions T able 13-94. ALGNERRC Register Bit Description 13.7.3 Symbol Error Count SYMERRS (04008h; R) Counts the number of sym bol errors between reads. The count increases for every bad symbol received, whether or not a packet is currently bein g received and whether or not the link is up.
Software Developer’s Manua l 339 Register Descriptions T able 13-96. RXERRC Regi ster Bit Description 13.7.5 Missed Packet s Count MPC (04010h; R) Counts the number of missed packets. Packets are missed when the receive FIFO has insufficient space to store the incoming packet.
340 Software Deve loper’s Manual Register Desc riptions T able 13-98. SCC Regist er Bit Description 13.7.7 Excessive Collisions Count ECOL (04018h; R) When 16 or more collisions have occurred on a p acket, this register increm ents, rega rdless of t he value of collision threshold .
Software Developer’s Manua l 341 Register Descriptions T able 13-100. MCC Register Bit Description 13.7.9 Late Collisions Count LA TECOL (04020h; R) Late collisions are collisions that occur after 6.
342 Software Deve loper’s Manual Register Desc riptions 13.7.1 1 Defer Count DC (04030h; R) This register counts defer events. A defer eve n t occurs when the transm itter cannot immediately send a .
Software Developer’s Manua l 343 Register Descriptions 13.7.13 Sequence Error Count SEC (04038h; R) This register counts sequen ce error events. The p r oper sequence of 8b/10b sy mbols is as follows: idle, start-of-frame (SOF), data, pad (opti onal), en d-of-frame (EOF), fill (opt ional), idle.
344 Software Deve loper’s Manual Register Desc riptions 13.7.15 Receive Length Error Count RLEC (04040h; R) This register counts receive length error events. A length error occurs if an incoming packet passes the filter criteria but is undersized or oversized.
Software Developer’s Manua l 345 Register Descriptions 13.7.17 XON T ransmitted Count XONTXC (0404Ch; R) This register counts the number of XON packets transmitted. These can be either due to a full queue or due to software initiated action (using TC TL.
346 Software Deve loper’s Manual Register Desc riptions T able 13-1 1 1. XOFFTXC Re gister Bit Description 13.7.20 FC Received Unsupported Count FCRUC (04058h; R) This register counts the number of unsuppo rted flow control fram es that are received.
Software Developer’s Manua l 347 Register Descriptions T able 13 -1 13. PRC64 Regist er Bit Description 13.7.22 Packet s Received (65-127 Bytes) Count PRC127 (04060h; R) This register counts the number of good packets received that are 65-127 bytes (from <Destination Address> through <CRC>, inclusively) in length.
348 Software Deve loper’s Manual Register Desc riptions T able 13-1 15. PRC225 Register Bit Descrip tion 13.7.24 Packets Received (256-51 1 Bytes) Count PRC51 1 (04068h; R) This register counts the number of good p ackets received that ar e 256-51 1 bytes (from <Destination Address> thro ugh <CRC>, inclusivel y) in length.
Software Developer’s Manua l 349 Register Descriptions T able 13-1 17. PRC1023 Register Bit Description 13.7.26 Packet s Received (10 24 to Max Bytes) Count PRC1522 (04070h; R) This register counts .
350 Software Deve loper’s Manual Register Desc riptions T able 13-1 19. GPRC Register Bit Description 13.7.28 Broadcast Packets Received Count BPRC (04078h; R) This register counts the number of good (no errors ) broadcast packets received. This register does not count broadcast packets receive d when the broadcast address filt er is disabled.
Software Developer’s Manua l 351 Register Descriptions T able 13 -121. MPRC Regi ster Bit Description 13.7.30 Good Packets T ransmitted Count GPTC (04080h; R) This register counts the n umber of good (no errors) packets transm itted.
352 Software Deve loper’s Manual Register Desc riptions T able 13-123. GORCL and GORCH Register Bit Description 13.7.32 Good Octets T ransmitted Count GOTCL (04090h; R)/ GOTCH (04094; R) These registers make up a 64-bit regist er that counts the number of good (n o errors) octets transmitted.
Software Developer’s Manua l 353 Register Descriptions This register does not increment when flow control packets are received. T able 13-125. RNBC Regi ster Bit Description 13.
354 Software Deve loper’s Manual Register Desc riptions T able 13-127. RFC Register Bit Description 13.7.36 Receive Oversize Count ROC (040ACh; R) This register counts the number of received fr ames with valid CRC field that passed address filtering, and were greater than maximum size.
Software Developer’s Manua l 355 Register Descriptions T able 13-129. RJC Register Bit Descr iption 13.7.38 Management Pack et s Received Count 1 MG TPRC (040B4h; R) This register counts the total n.
356 Software Deve loper’s Manual Register Desc riptions 13.7.39 Managem ent Packet s Dro pped Count 1 MG TPDC (040B8h; R) This register counts the total number of packet s received that pass the man.
Software Developer’s Manua l 357 Register Descriptions All packets received have their octe ts summed into this register , re gardless of their length, whether they are erred, or whether they ar e flow control packets.
358 Software Deve loper’s Manual Register Desc riptions 13.7.43 T ot al Packet s Received TPR (040D0h; R) This register counts the total number of all pack ets received. All packets received are counted in this register , regardless of their length, whether th ey have errors, or whether they are flow control packets.
Software Developer’s Manua l 359 Register Descriptions 13.7.45 Packet s T ransmit ted (64 Bytes) Count PTC64 (040D8h; R) This register counts the number of packets transm itted that are ex actly 64 bytes (from <Destinatio n Address> through <CRC>, inclusively) in length.
360 Software Deve loper’s Manual Register Desc riptions 13.7.47 Packets T ransmi tted (128-255 Bytes) Count PTC255 (040E0h; R) This register counts the number of packets transmitted that ar e 128-255 bytes (from <Destination Address> through <CRC>, inclusiv ely) in length.
Software Developer’s Manua l 361 Register Descriptions 13.7.49 Packet s T ransmitted (512-1023 B ytes) Count PTC1023 (040E8h; R) This register counts the number of packets transm itted that are 512-1023 b ytes (from <Destination Address> through <CRC>, inclusively) in length.
362 Software Deve loper’s Manual Register Desc riptions 13.7.51 Multicast Packet s T ransmitted Count MPTC (040F0h; R) This register counts the number of multicast packets transmitted. This register does not include flow control packets and increments only if transmits are enable d.
Software Developer’s Manua l 363 Register Descriptions 13.7.53 TCP Segmentation Context T ransmitted Count TSCTC (040F8h; R) This register counts the n umber of TCP segmentation offload transmission.
364 Software Deve loper’s Manual Register Desc riptions 13.8 Diagnostics Registers The Ethernet controller contains several diagnostic registers. T hes e registers enable software to directly access the contents of the Ethernet controller ’ s internal P acket Buffer Memory (PBM), also referred to as FIFO space.
Software Developer’s Manua l 365 Register Descriptions T able 13-143. RDFT Register Bit Descrip tion 13.8.3 Receive Dat a FIFO Head Saved Register RDFHS (02420h; R/W) This register stores a copy of the Receive Data FIFO Head register in case the internal register needs to be restored.
366 Software Deve loper’s Manual Register Desc riptions T able 13-145. RDFTS Regi ster Bit Description 13.8.5 Receive Dat a FIFO Packet Count RDFPC (02430h; R/W) This register reflects the number of receive packets that are curr ently in the Receive FIFO.
Software Developer’s Manua l 367 Register Descriptions T able 13-147. TDFH Register Bit Description) 13.8.7 T ransmit Data FIFO T a il Register TDFT (03418h; R/W) This register stores the head of the Ethernet c ontroller ’ s on–chip transmit data FIFO.
368 Software Deve loper’s Manual Register Desc riptions T able 13-149. TDFHS Regi ster Bit Desc ription 13.8.9 T ransmit Data FIFO T ail Saved Register TDFTS (03428h; R/W) This register stores a copy of th e T ransmit Data FIFO T ail regist er in case the internal register needs to be restored.
Software Developer’s Manua l 369 Register Descriptions T able 13-151. TDFPC Register Bit Descr iption 13.8.1 1 Packet Buffer Memory PBM (10000h - 1FFFCh; R/W) All PBM (FIFO) data is available to diagnostic s. Locations can be acce ssed as 32-bit or 64-bit words.
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Software Developer’s Manua l 371 General Initialization and Reset Operati on General Initialization and Reset Operation 14 14.1 Introduction This section list s all necessary in itializations and describes the reset commands for the PCI/PCI-X Family of Gigabit Ethernet Controllers.
372 Software Deve loper’s Manual General Initialization and Reset Operation • PHY Reset (CTRL.PHY_RST) should be set to 0b. Setting this bit to 1b resets the PHY without accessing the PHY registers. This b it is ignored in internal SerDes mode. • CTRL.
Software Developer’s Manua l 373 General Initialization and Reset Operati on Program the Receive Control (RCTL) register w ith appropriate values for desired operation to include the following: • Set the receiver Enable (RCTL.EN) bit to 1b for no rmal operation.
374 Software Deve loper’s Manual General Initialization and Reset Operation • Configure the Collision Threshold (TCTL.CT) to th e desired value. Eth ernet standard is 10h. This setting only has meaning in half duplex mo de. • Configure the Collision Distan ce (TCTL.
Software Developer’s Manua l 375 General Initialization and Reset Operati on Note: IPGR1 and IPGR2 are not needed in full duplex, but are easier to always program to the values shown. T able 14-1. Signal Descriptions Signal Ball Na me and Func tion LOS / LINK A10 Loss of Signal (TBI) / L ink Indication.
376 Software Deve loper’s Manual General Initialization and Reset Operation 14.5.1 Signal Interface The external GMII/MII interface is similar in function to the interface used to communicate between the MAC and internal PHY .
Software Developer’s Manua l 377 General Initialization and Reset Operati on T able 14-2. Signal Functions 14.5.2 GMII/MII Features not Supported T able 14-3 lists the signals and functions not provided by this interface.
378 Software Deve loper’s Manual General Initialization and Reset Operation T able 14-3. Signal Functions Not Supported 14.5.3 A voiding GMII T est Mode(s) Note that the Ethernet co ntroller contains a set of test mode s that use this in terface for component manufacturing and/or diagnostic test.
Software Developer’s Manua l 379 General Initialization and Reset Operati on 14.5.5 Link Setup The following examples are provided as suggesti ons for configuring comm on settings between the MAC and an Ethernet controller attached in the GMII/MII mode.
380 Software Deve loper’s Manual General Initialization and Reset Operation • MAC/PHY duplex and speed settings both forced by software (fully-forced link setup) (CTRL.FRCDPLX = 1b, CTRL.FRCS PD = 1b, CTRL.S LU = 1b) CTRL.FD ............ .......Set by software to desired full/half duplex operation (must match duplex settin g of PHY) CTRL.
Software Developer’s Manua l 381 General Initialization and Reset Operati on Once link is achieved by the PHY , software is notified when a Link Status Change (LSC) int errupt is generated by the Ethernet controller . This onl y occurs if software en abled the LSC bit in the Interrupt Mask Set/Read (MS) Register .
382 Software Deve loper’s Manual General Initialization and Reset Operation RST#: When asserted, all PCI signals are forced to a high impedance stat e. Upon d eassertion, the Ethernet controller ’ s internal registers, excludi ng the following ex ceptions, are reset.
Software Developer’s Manua l 383 General Initialization and Reset Operati on Default values for certain bi ts of the Device Cont rol Register must be read out of the EEPROM and appropriately set by software if an EEPROM is used. Global Reset does NOT aff ect the direction of the software programmable pins.
384 Software Deve loper’s Manual General Initialization and Reset Operation Driver accessible W akeup Status registers are excluded from all resets except for LAN_PWR_GOOD. This includes: • W akeup Status Register . • W akeup Packet Length. • W akeup Packet Memory .
Software Developer’s Man ual 385 Diagnostics and T estability Diagnostics and T estability 15 15.1 Diagnostics This section explains the regi sters provided fo r diagnostic access. These registers enable system level integration and debugging, including the ability to access all internal memories.
386 Software Deve loper’s Manual Diagnostics and T estability 15.1.3.1 Internal Loopback This loopback mode internally l oops back the transmit to receive path in the PHY , exercising the internal GMII/MII bus. Programming both MAC and PH Y is required.
Software Developer’s Man ual 387 Diagnostics and T estability 15.2.1 EXTEST Instruction This instruction allows testing of off-chip circuitry and board level interconnection s.
388 Software Deve loper’s Manual Diagnostics and T estability Note: This page intentionally left blank..
Software Developer’s Man ual 389 Appendix (Changes From 8254 4EI/82544GC) Appendix (Changes From 82544EI/82544GC) A A.1 Introduction This section describes the new feat ures that hav e been added to.
390 Software Deve loper’s Manual Appendix (Changes From 82544EI/82 5 44GC) A.3 Register Changes Ta b l e A - 1 lists the registers that have been adde d or changed in the Ethernet controller .
Software Developer’s Man ual 391 Appendix (82540 EP/EM and 82545GM/EM Dif ferences) Appendix (82540EP/EM and 82545GM/EM Dif f erences) B B.1 Introduction This section describes t h e differences be tween the 82546GB/EB , the 82540EP/EM and the 82545GM/EM .
392 Software Deve loper’s Manual Appendix (82540EP/EM and 82545GM / EM Differe nces) Note: Though the 82540EP/EM supports devices with up to 512 KB of memory , smaller devices may also be used. Accesses to memo ry beyond the FLASH device size results in access wrapping as only the lower address bits are utilized by the FLASH.
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