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V/Ethernet 4221 Cond or User’ s Guide Document No. UG04221-000, REVB Release date: July 1994 Copyri ght 1994 Inte rpha se Corp ora tion All Rights Reserved.
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Copyright Notice Copyright 1993, 1994 b y Interphase Corporation All rights reserved No part of this publication may be stored in a retriev al system, transmitted, or reproduced in any way , including.
F or Assistance T o place an o rder for an I nterphase product, call: Sales S upport: (214) 919 -9000 For ass istance using this, or any other Interphase pro duct, call: Cus tomer Servi ce: (2 14) 91 .
T ABLE OF CONTENTS vi CHAPTER 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Intended Aud ience . . . . . . . . . . . . . . . . . . . .
vii Command Respons e Block (CRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Command Respons e Status Word (CRSW ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii MAC status/contr ol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Intel 82596 Status/C ontrol – Transmit Functions . . . . . . . . . . . . . . . . . . . . . . .
ix Operating Enviro nment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Fuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIST OF FIGURES xii Figure 1-1. 4221 Co ndor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2-1. 10BaseT Cond or Motherboard Layo ut (PB04221- 000) . . . . . . . . . . . . . . .
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LIST OF T ABLES xiv Table 2-1. Condor Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2-2. 4221 Co ndor LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . .
xv Table 3-36. Report Network Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 3-37. Command Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 CHAPTER 1 INTRODUCTION Intended Audience Interphase wrote this manual for its customer s. It is intended for a highly tech nical audience, specifi cally , users who need to write their own so ftware dri ver s.
Chapter 1 - Intr oduction 2 Conventions This section detail s many of the wri ting con ventions used throu ghout the manual. In addition, it giv es many of the technical con ventions. • The V/Ethernet 4221 Condor will be referred to by the nam e Condor or referenced as the controller .
Options 3 Options Interph ase Corpor ation of fers the followi ng Condor o ptions: • Dual Channel Ethernet (AUI) • Dual Channel Ethernet (1 0BaseT) • 3 Channel Ethernet ( AUI or 10BaseT) • Quad Ethernet Channe l (AUI or 10Bas eT) Physical Description The Cond or physically con forms to the 6U VMEbus bo ard standard.
Chapter 1 - Intr oduction 4 Ethernet Front End Channel (FEC) The 82596 CA ® Local Area Networ k (LAN) Co-processor is used as the FEC Ether net controller .
VMEbus Short I/O In terface 5 VMEbus Short I/O Int erface The VMEbu s Short I/O interface allows for VMEb us host and onboard CPU communications. The host issues commands to the C ondor throu gh the Short I/O interface and the CPU issues status back to the host.
Chapter 1 - Intr oduction 6 interrupt hand ler outputs an interrupt v ector number fo r the non-DMA engine interrupt s or requests access to the LB US for a DMA engine I A CK cycles. CPU/LBUS Interface The CPU/LBUS Interface link s the CPU core with the LBUS resources.
7 CHAPTER 2 HARDWARE INSTALLATION Overvi ew Before attemptin g installation, read this chapter thor oughly to insure the safe inst allation of the Condor into your system. If you ha ve any questions re garding installatio n, which are not answered in this chapter , please contact Interph ase Customer Service at (214 ) 919-9111 .
Chapter 2 - Hardware Installatio n 8 The daughter card installation procedure will vary depending on the desired configuration. V ariables include: • Single Channel AUI/10BaseT.
Overview 9 Figure 2-1 . 10BaseT Con dor Mothe rboard Layout (PB04 221-000) LED 1 LED 2 LED 3 LED 4 LED 5 LED 6 LED 7 SPB SPA J14 J15 J16 J1 8 J12 J13 P2 P1 J23 J24 J26 J25 J19 J20 J21 J22 J9 J3 OPTION.
Chapter 2 - Hardware Installatio n 10 Figur e 2-2. Sin gle Channel AUI or 10Ba seT Motherboard Layout (PB0 04221-001) LED 1 LED 2 LED 3 LED 4 LED 5 LED 6 SPB SPA J14 J15 J16 J 1 8 J12 J13 P2 P1 J23 J2.
Overview 11 Figure 2- 3. AUI C ondor Motherb oard Layout (P B04221-000 ) LED 1 LED 2 LED 3 LED 4 LED 5 LED 6 SPB SPA J14 J15 J16 J1 8 J12 J13 P2 P1 J23 J24 J26 J25 J19 J20 J21 J22 J9 J7 OPTIONAL DAUGH.
Chapter 2 - Hardware Installatio n 12 Figure 2-4 . 10BaseT Con dor Mothe rboard Layout (PB04 221-001) LED 1 LED 2 LED 3 LED 4 LED 5 LED 6 LED 7 SPB SPA J 1 0 J 1 4 J16 J 1 8 J12 J 1 5 P2 P1 J23 J24 J2.
Overview 13 Figure 2- 5. AUI C ondor Motherb oard Layout (P B04221-001 ) LED 1 LED 2 LED 3 LED 4 LED 5 LED 6 SPB SPA J 1 0 J 1 4 J16 J 1 8 J12 J 1 5 P2 P1 J23 J24 J26 J25 J19 J20 J21 J22 J9 J7 OPTIONA.
Chapter 2 - Hardware Installatio n 14 4221 Condo r Hardwa re Installatio n Procedures For proper installation of the Condor, it is imperative that you use the follo wing procedures. Step 1. Visual Inspection Before attempting the in stallation of this board, make sure you are wearing an anti-static or ground ing de vice.
4221 C ondor Hardwar e In stallati on Pr ocedur es 15 Board Status LEDs LEDs 1, 2, 3, and 4 are Board Status LE Ds which provide the fo llowing functions: • Power On Self Test (POST) Mode • Monitor Mode • Run Mode POST Mode: This mode provides diagnostic s for the CPU and Buffer .
Chapter 2 - Hardware Installatio n 16 T able 2-4. Run M ode L ED Ma trix Step 3. Set Onboard Motherboard Jumpers Set all onboard jumpers so that the Condor is properly conf igured for operation within your system. The board layout as illustrated in figure 2-1 shows the location of the jumpers.
4221 C ondor Hardwar e In stallati on Pr ocedur es 17 J9 +12 VOLTS Flash Pr ogramming Protect : IN: +12 V olt po wer connected to EPR OM socket. OUT : +12 V olt po wer disconnected from EPR OM socket. J12 VME Bus Grant: Pins 1 - 12 Reserved Pins 13 - 16 VME Bus Grant: T ab le 2-5.
Chapter 2 - Hardware Installatio n 18 (Pins 5- 6) Cons ole Message Disab le IN = Disable OUT = Enable (Pins 7-8) GDB Enable Point IN = GDB Initialized On Exit OUT = GDB Initialized On Reset J14 Firmwa.
4221 C ondor Hardwar e In stallati on Pr ocedur es 19 T able 2-6. Secondary Short I/O * Facto ry Defa ult J16 Primary Short I/O Siz e / Reset Enable : T able 2-7.
Chapter 2 - Hardware Installatio n 20 J18 Prim ary Channel Addre ss Modifiers: IN = Primary Channel Address Modif iers 29 or 2 D OUT = Primary Channel Addr ess Modifier 2D only J18.
4221 C ondor Hardwar e In stallati on Pr ocedur es 21 J19, J20, J21 & J22 Primary Shor t I/O Base Address: Refer to the following tables when setting Prim ary Short I/O Base Address es for the fol.
Chapter 2 - Hardware Installatio n 22 T able 2-8. Primary Base Address For 2K Short I/O NO TE : 0 = IN (Log ical 0), F = OUT (Log ical 1) ADDRESS J19 PIN SETTINGS J20, J21, J22 PIN S ETTINGS 15-16 13-.
4221 C ondor Hardwar e In stallati on Pr ocedur es 23 T able 2-9. Primary Base Address For 1K Short I/O NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS J20, J21, J22 PIN S ETT.
Chapter 2 - Hardware Installatio n 24 T able 2-10. Pr imary Base Address F or 512 By te Short I /O NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS J20, J21, J22 PIN S ETTINGS .
4221 C ondor Hardwar e In stallati on Pr ocedur es 25 T able 2-10. Primar y Base Addres s For 5 12 Byte Sh ort I/O (Con tinued) NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS.
Chapter 2 - Hardware Installatio n 26 T able 2-11. Pr imary Base Address F or 256 By te Short I /O NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS J20, J21, J22 PIN S ETTINGS .
4221 C ondor Hardwar e In stallati on Pr ocedur es 27 T able 2-11. Primar y Base Addres s For 2 56 Byte Sh ort I/O (Con tinued) NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS.
Chapter 2 - Hardware Installatio n 28 T able 2-11. Primar y Base Addres s For 2 56 Byte Sh ort I/O (Con tinued) NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS J20, J21, J22 P.
4221 C ondor Hardwar e In stallati on Pr ocedur es 29 T able 2-11. Primar y Base Addres s For 2 56 Byte Sh ort I/O (Con tinued) NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS.
Chapter 2 - Hardware Installatio n 30 T able 2-11. Primar y Base Addres s For 2 56 Byte Sh ort I/O (Con tinued) NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS J20, J21, J22 P.
4221 C ondor Hardwar e In stallati on Pr ocedur es 31 T able 2-11. Primar y Base Addres s For 2 56 Byte Sh ort I/O (Con tinued) NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS.
Chapter 2 - Hardware Installatio n 32 T able 2-11. Primar y Base Addres s For 2 56 Byte Sh ort I/O (Con tinued) NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J19 PIN SETTINGS J20, J21, J22 P.
4221 C ondor Hardwar e In stallati on Pr ocedur es 33 J23, J24, J25 & J26 Secondary S hort I/O Addres s: Refer to the following tables when setting Secondary S hort I/O Base Addresses for the foll.
Chapter 2 - Hardware Installatio n 34 T able 2-12. Secondary B ase Address For 2K S hort I/O NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J25, J26 PIN S ETTINGS 15-16 .
4221 C ondor Hardwar e In stallati on Pr ocedur es 35 T able 2-13. Secondary B ase Address For 1K S hort I/O NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J25, J26 PIN .
Chapter 2 - Hardware Installatio n 36 T able 2-13. Second ary B ase A ddre ss For 1K Shor t I/O (Cont inu ed) NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J25, J26 PIN.
4221 C ondor Hardwar e In stallati on Pr ocedur es 37 T able 2- 14. Se conda ry Ba se Addr ess For 5 12 Byte Short I /O NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J2.
Chapter 2 - Hardware Installatio n 38 T able 2-14. Second ary Base Addr ess For 512 Byt e Short I/O (Continue d) NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24,J25,J26 PI.
4221 C ondor Hardwar e In stallati on Pr ocedur es 39 T able 2-14. Second ary Base Addr ess For 512 Byt e Short I/O (Continue d) NO TE: 0 = IN (Logical 0) , F= OUT (Logical 1) ADDRESS J23 PIN SETTINGS.
Chapter 2 - Hardware Installatio n 40 T able 2- 14. Sec ondar y Base Addre ss For 512 Byte Sh ort I/O (Con tinued ADDRESS J23 PIN SETTINGS J24, J25, J26 PIN S ETTINGS 15-16 13-14 11-12 9-10 7-8 5-6 3-.
4221 C ondor Hardwar e In stallati on Pr ocedur es 41 T able 2- 15. Se conda ry Ba se Addr ess For 2 56 Byte Short I /O NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J2.
Chapter 2 - Hardware Installatio n 42 T able 2-15. Second ary Base Addr ess For 256 Byt e Short I/O (Continue d) NO TE: 0 = IN (Lo gical 0), F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J25, J26 .
4221 C ondor Hardwar e In stallati on Pr ocedur es 43 T able 2-15. Second ary Base Addr ess For 256 Byt e Short I/O (Continue d) NO TE: 0 = IN (Lo gical 0), F= OUT (Logical 1) ADDRESS J23 PIN SETTINGS.
Chapter 2 - Hardware Installatio n 44 T able 2-15. Second ary Base Addr ess For 256 Byt e Short I/O (Continue d) NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J25, J26 .
4221 C ondor Hardwar e In stallati on Pr ocedur es 45 T able 2-15. Second ary Base Addr ess For 256 Byt e Short I/O (Continue d) NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J23 PIN SETTING.
Chapter 2 - Hardware Installatio n 46 T able 2-15. Second ary Base Addr ess For 256 Byt e Short I/O (Continue d) NO TE: 0 = IN (Logical 0) , F = OUT (Logical 1) ADDRESS J23 PIN SETTINGS J24, J25, J26 .
4221 C ondor Hardwar e In stallati on Pr ocedur es 47 Step 4. Set Daughter Card Jumpers And Termin ations The follo wing daughter card settin gs are discussed: • Ethernet Single Channel AUI/10 BaseT.
Chapter 2 - Hardware Installatio n 48 Ethernet Single Channel AUI/10BaseT Daugh ter Card COMPO NENT SI DE Figure 2-6. Ethernet Single Channel AUI/10BaseT Daughter Ca rd NO TE: LED3 is located on the sold er side of the daughter card and is not shown in this illustration.
4221 C ondor Hardwar e In stallati on Pr ocedur es 49 Dual Channel 10BaseT E thernet Daughter Card COMPO NENT SI DE Figure 2-7. Dual Channel 10BaseT Eth ernet Daughter C ard The Dual Channel 10B aseT Ethernet Daughter Car d provides two RJ45 connectors as s hown in Figure 2-7 abo ve.
Chapter 2 - Hardware Installatio n 50 Ethern et Dual Channel AUI Dau ghter Card COMPO NENT SI DE Figure 2-8. Ethernet Dual Channel AUI Daughter Card NO TE: LED3 is located on the sold er side of the daughter card and is not shown in this illustration.
4221 C ondor Hardwar e In stallati on Pr ocedur es 51 Step 5. Power Of f System Once the board is conf igured, ensure that the ho st system and peripherals are tu rned OFF . Step 6. Cabling Procedure The cabling pr ocedure depends on ho w you wish to co nfigure the system.
Chapter 2 - Hardware Installatio n 52 RS232 Connect ors And Cables There are two 10 pin connector s (2x5 Headers) which are used as the RS232 port cable connectors. Thes e connectors are the s ame type used for the s econd serial port I/O Extension-X.
53 CHAPTER 3 MACSI HOST INTERFACE Introduction This chapter def ines the MA CSI host interf ace for the Interphase V/Ethernet 4221 Condo r . The Condor and its MA CSI host interface are designed to be backwards compatible with the Interphase V/Ethernet 42 07 Eagle MA CSI host interface.
Chapter 3 - MACSI Host Int erface 54 Field Off set The v alue in the far left column specif ies the field of fset. This value measures incr ements of 16 bits from the begi nning of the record, and may.
System Interfac e 55 System Interface This sec tion defines how the host communicates with the controller . The shared memory interface is defi ned, and each major section descr ibed in detail. Full def initi ons for particular comm ands ( what is communicated) can be f ound in a following section.
Chapter 3 - MACSI Host Int erface 56 The Mas ter Command Entry (MC E) and Comm and Q ueue Entri es (CQ E) are used to queue commands from the host to the controller . A Command Queue Entry (in either the CQE or MCE) is a 12-byte block containing all of the information need ed for the 4221 to locate and execute a comman d issued by the ho st.
Master Control St atus Bloc k (MCSB) 57 Master Cont rol Status Block (MCSB) The MCSB consists of a Master Status Register , which is used to report information from the controller to the host, and th e Ma ster Co ntro l Regist er , w hich p rovides infr eque ntly used c ontr ol fun ctio ns to t he ho st.
Chapter 3 - MACSI Host Int erface 58 Master Control Re gister (MCR) The MCR pro vides the host with infrequently used s ervices. These bits are both set and cleared b y the host. The controller clears these bits on po wer up, and does not alter them at any other time.
Onbo ard Command Queue Ent ry 59 Onboa rd C omma nd Que ue Ent ry The host issues a command to the controller through a Command Queue Entry (CQE). T wo types are provided: the Master Command Entry (MCE) , located at offset 0x001 0 is used to issue control commands, such as Initialize Controller , Report Network Statistics, and the like.
Chapter 3 - MACSI Host Int erface 60 Fetch o ffb oard (FOB) Setting this bit makes the Command Queue entry an of fboard entry . Please see the follo wing section for details. Fetch o ffb oard in prog ress (FIP) This bit is used internally by the controller .
Offboard Command Queue Entry 61 DMA Transfer Control Word This field specifies how the controller sho uld DMA transfer the data from host memory . This field is fully def ined in the Common IOPB Stru cture definition, in the follo wing section. Please refer there for full details.
Chapter 3 - MACSI Host Int erface 62 Command Response Block (C RB) The CRB is used by the controller to post completed commands back to the host. It consists of the following fields: T able 3-8.
Comman d Respo nse Bloc k (CRB) 63 Error (ER) This bit is s et with Command Complete w hen a returned IOPB comp leted with an error . Errored commands are ne ver returned via the Multiple Completion mechanism . The nature of the error can be determined b y examining the Return Status fi eld in the returned IOPB.
Chapter 3 - MACSI Host Int erface 64 Multiple Completed Returned IOPB Structure When multip le commands are returned fr om the controller to the ho st with a single interru pt, the following structure.
Configu ratio n Statu s Block ( CSB) 65 Configurat ion Status Block (CSB) The controller u ses the CSB to re port the f irmware and hardware con figur ation upon po wer up. Thes e contents are v alid from the time Board OK is asserted, to the time the controller posts b ack multiple completed returned com mands in this space.
Chapter 3 - MACSI Host Int erface 66 Firmware Revision Level The f irmware revision le vel, represe nted as a 3-dig it ASCII valu e. Firmware Revision Date The re vision date of th e installed f irmware, repres ented as 8 ASCII digits. F or e xample, a release data of J anuary 15, 1994 w ould be repres ented as 0115 1994.
Controller Statistic s Block 67 Controller S tatisti cs Block This space was u sed to report netw ork statistics in the origin al Eagle MA C SI implementation for single port Ethernet support.
Chapter 3 - MACSI Host Int erface 68 Transmi t Command s Submitte d T otal number of attempted frame transmissi ons (successful and un successful). Transmit DMA Com pletions T otal number of DMA transfers completed as the result of a trans mit command.
Controller Statistic s Block 69 Transmit Completions Posted to H ost T otal number of frame completio ns posted to the Comman d Response Block an d Returned IOPB. Receive Commands S ubmitted T otal number of attempted message receptions (successful and u nsuccessful).
Chapter 3 - MACSI Host Int erface 70 IO Parameter Blocks (IOPBs) This section provides a detailed description of each of the comman ds used by the host to communicate with the controller . Each command is listed belo w , along with the code associated with each co mmand.
Common IOPB Stru ctures 71 Command Code This f ield specifies the command to be e xecuted. Particular v alues are noted for each of the indi vidual commands. Command Options This fi eld specifies operational parameters or optio ns to be associated with the execution of the command.
Chapter 3 - MACSI Host Int erface 72 Address modif ier This f ield contains the VMEbus address modif ier used for the transfer . Refer to your system document ation for possible values for this field. Memory type (MT) This 2-bit field specif ies the width of the data trans fers.
Initialize Co ntroller 73 Initi alize C ont roll er This command allo ws the host to specify global configuration parameters, and initializes the controller for use within a particular s ystem.
Chapter 3 - MACSI Host Int erface 74 Contro ller Initiali zati on Blo ck (CI B) The CIB contains the actual v alues to use when initializing the controller . It may be located anywhere in Short I/O, though it mak es sense to place it after the MCE and before the Command Response Block.
Controlle r Initialization Block (CIB) 75 Spec ial Netwo rk Opt ion s Originally , this f ield allo wed the host to set s eve ral network related options, such as disabling receiv es, or disab ling transmit CRC.
Chapter 3 - MACSI Host Int erface 76 A value between 1 and 0x20 (40 decimal) causes the controller, after b eing granted the bu s, to t ransfer data until 1) there is no m ore data, or 2) 16 m icro seconds elapses, or 3) one of the b us request lines on the VMEb us is asserted.
MAC Control/S tatus 77 MAC Control/Status This command pr ovides a host dr iv er with two distinct le vels of service to an Ether net port located on the 4221. First, it prov ides a general mechanism to control the Ethern et port, without the dri ver ha ving to kno w any particulars about the actual Eth ernet interface chip being used.
Chapter 3 - MACSI Host Int erface 78 T able 3-22. MA C Control / Status Command Code This fi eld must contain 0x4 3 to exec ute the MA C Control IOPB. MA C Control/Statu s O f f s t 1 5 1 4 1 3 1 2 1 .
MAC Control/S tatus 79 Command Options T able 3-23. Command Options Interru pt Enable (IE) Def ined in Commo n IOPB Stru ctures. Set MA C options (SM) When this bit is set, the state of the specified MA C is updated as per those bit s ettings specified in the MA C Status/Control word.
Chapter 3 - MACSI Host Int erface 80 Abort Report (A R) Setting this bit cau ses commands abort ed with either the AA or the AN bit to be reported back to the hos t with the appropriate error code set. Setting this bit has no effect on pend ing receive s for particular ports aborted via t he Abor t Pen ding b it in the MAC Status /Con trol field.
MAC Control/S tatus 81 Setting this bit r esets the port: promiscuou s mode is disabled, multicast is disabled, any supplied multiple indi vidual addresses are lost. All of the internal mem ory structures for the port are reinitialized , and the port is reinitialized with power on default v alues.
Chapter 3 - MACSI Host Int erface 82 T a ble 3-25. Intel 82596 T ransmit St atus / Control Backof f method (BM) (p. 4-13 1) This parameter determines when to start th e back-of f timeout. Disabl e backof f (DB) (p. 4-141) Disables the back off algorithm implemented in the 82596.
MAC Control/S tatus 83 T able 3-26. Intel 82596 Recei ve Status / Contro l Sa ve bad frames (SB) (p. 4-1 29) When set bad fr ames (CRC error , Alignment error , etc.) are sent to the host . Broadcast disable (BD) (p. 4-134) Disables reception of frames with a Broadcast destination add ress or Multicast of all 1 ’ s.
Chapter 3 - MACSI Host Int erface 84 T ime domain reflectometry test (TDR) (p. 4-150 ) This operation acti v ates the T ime Domain Reflectometry test. The result is retu rned in the MA C returned information field. Refer to the 82596 documentation for full details of the returned values.
Change Default Node Ad dress 85 Change Default Node Address This command is used to change the 48 bit physical address associated with any of the attached ports. It also can be used to manage b oth the factory and us er addresses stored in NVRAM, either by setting them to new v alues, or b y restorin g preset v alues.
Chapter 3 - MACSI Host Int erface 86 Command Options T able 3-28. Command Options Interru pt enable (IE) As def ined in the Common IOP B Structures. Update user default (UUD) Setting this bit upd ates the NVRAM-stored u ser default physical node address for the specified port with the v alue provided in the Physical Node Address f ield.
Transm it 87 Tran smit The T ransmit command causes the controller to DMA transfer the specif ied frame from host memory , and then transmit it (if possible) through the specified Ethernet port. T able 3-29. T ransmit Command Code This fi eld must contain 0x5 0 to exec ute the T ransmit IOPB.
Chapter 3 - MACSI Host Int erface 88 Command Options T able 3-30. Command Options Interru pt enable (IE) As def ined in Commo n IOPB Structures . In-line gat her (IG) Setting this bit all o ws the host to define the frame location in sys tem memory as a set of address/count pairs.
Transmit -- In-Line Gath ers 89 T able 3-31. T ransmit - In-Line Gathers Number of Elements This fi eld contains the number of gather elements included in the IOPB. The on ly physical limit on this v alue is that the size of the total IOPB to be processed by the controller must fit in the IOPB l ength field in the CQE.
Chapter 3 - MACSI Host Int erface 90 Receive The host provides the con troller with Recei ve co mmands, which specif y the host resources to be used for incoming frames. As frames come in, the controller trans fers them to the specif ied ho st memory locations, u pdates the pro vided Recei ve comman ds, and posts them b ack to the host.
Receive 91 Command Code This f ield must contain 0x6 0 to exec ute the Recei ve IOPB. Command Options T able 3-33. Command Options Interru pt enable As defined in the Common IOPB Structures section. Port selector This field specif ies the port to which the receiv e resources will be allocated.
Chapter 3 - MACSI Host Int erface 92 Sourc e Addres s When so monitoring the net work, the source addres s for the incoming frame will be contained in this field. Neither this field nor the pre vious will be used for normal fr ame reception activity .
Initialize Multiple Comple tions 93 Initia lize M ultiple Co mple tions This command enables the controller to return multip le completed commands to the host with a single completion via the Command Resp onse Block, with a single (op tional) interrupt.
Chapter 3 - MACSI Host Int erface 94 Command Options No special options ar e av ailable for this com mand. Refer to Common IOPB structures for defined options. Retu rn Status There are not p articular errors currently def ined for this IOPB. Control Flags T able 3-35.
Report Netwo rk Statistics 95 Report Net work Statis tics T ab le 3-36. Report Network Statistics The Report Network Statistics Com mand can be used to obtain network statis tics for any Ethernet p ort av ail able on the controller . These statistics are accumulated since the last controller res et.
Chapter 3 - MACSI Host Int erface 96 Command Options T able 3-37. Command Options Interru pt enable (IE) As def ined in Commo n IOPB Structures . Port selector This field specif ies the port for which the stati stics will be reported. V alid ports range from 0 to 3.
Netwo rk Stati stics Block 97 Network Statis tics Block T able 3-38. Networ k Sta tist ics B lock Data Valid Indicator When the data is transf erred to the host, this field will contain a non-zero v alue. By cleari ng this field to zero, the host can av oid inad vertent accesses to d irty data for repeating network statistics co mmands.
Chapter 3 - MACSI Host Int erface 98 Transmi ts Failed This field contains the number of transmit commands fo r the particular port th at could not b e transmitted out over the media, due to excessi ve collisions. Collisions This field c ontains the total number of collisions for the particular interface.
99 APPENDIX A SPECIFICATIONS VMEbus Specif ications DTB Master A16, A24, A32, D08 (EO), D16, D32: B L T , D64: BL T DTB Slav e A16, D08 (EO), D16, D32 Requester An y of R(0-3), S tatic R WD, R OR Interru pter Any o f I(1-7), Dyn amic D08 (O) Power Requirements Dual A UI Ethernet Motherboard 5.
100 Appe ndix A Mechanical (Nominal) Leng th 233 mm Wi d t h 1 6 0 m m Thicknes s 2 0 mm We i g h t . 4 5 K g Operating E nvironment T emperatur e 0-55 deg rees Centigrade Relat ive Humidit y 10% - 90% N oncon dens ing Air Flow 250 CFM Minim um Fuse The A UI ver sion of the Condor h as a 1.
101 APPENDIX B CONNECTOR PINOUTS AND CABLING Overvi ew This chapter contains the connector pinouts and cabling infor mation needed for v arious Condor co nfiguratio ns.
102 Appe ndix B VMEbus Connectors The follo w ing tables sho w the pin numbers and sig nal description for the P1 and P2 VMEbus Connectors. • Table C-39 - P1 Connector Signal Descrip tions (All Versions) • Table C- 40 - P2 C onn ect or For Moth erbo ards Whic h Only Uses P2 R ow B P1 Connector T able C-39.
103 VMEbus Co nnectors P2 Connector R ow B Only Versi on T able C-40. P2 Connector Fo r Motherboards Which Only Uses P2 Ro w B PIN Ro w A Signal Mnemonic Row B Signal Mnemonic Row C Signal Mnemonic 1+.
104 Appe ndix B Ethernet Conne ctors and Pinouts The Condor suppo rts both the A UI and 10BaseT version s of the Ethernet 802.3 specification. The card will ha ve a 15 pin "D" connector us ed for the A UI signals and a RJ45 connector fo r unshielded twisted pair (10BaseT).
105 Ethernet Connecto rs and Pino uts AUI Connector Signals The A UI signals and connecto r pinout for the DB15 connector are sho wn in the follo wing table.
106 Appe ndix B RS232 Connector and Cable T able C -43. Serial Connector Pinou ts (SP A and SPB) NO TE : The same cable for the second Serial P ort for PC compatible systems can be used for the 4221 Condor . This cable can be b uilt or bou ght off-the-sh elf fr om many computer stor es.
107 APPENDIX C ERROR CODES The Return Status word in the command respon se contains information pertaining to the status of the IOPBs returned in the Comman d Response Block. Error codes are rep orted in he xadecimal format. HEX CODE DESCRIPT ION 0x110 VMEbus Error An attempted VME b us transfer generated a system b us error .
108 Appe ndix B.
INDEX 109 Numerics 82596 4, 8 1, 82 A AA 79 Abort ALL (AA) 79 Abort ANY (AN) 79 Abort P ending (AP) 8 1 Abort R eport (AR) 80, 81 Air Flow 100 AN 79 ANY 91 AP 81 AR 80, 81 B bina ry 2 board ok (BOK) 5.
110 EX 63 Exception (EX) 63 F feature list 2 fetch of fboard ent ry (FOB) 60 Fetch o ffboard in pr ogress (F IP) 60 field offset 54 FIP 60 firmware rev ision level 6 6 FOB 60 Front End C hann el (F EC.
111 P PFM 86 PM 75, 81 POST mode 15 power r equirement s 99 Product C ode 65, 68 Program factory MAC address (PFM) 86 Promiscuous mo de (PM) 75, 81 Q QECR 60 QMS 63 Queue Entr y Control Reg ister (QEC.
112.
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