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4538 PMC ® T1/E1/J1 Comm unications Contr oller Har d ware Ref erence Man u al Document No. UG4538 -001 $ Prin t Date : 2FW REHU.
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Cop yri ght Notice © 2001 b y Interphase Co rporation. All rights reserved. Printed in the United States of America, 2001. This manual is license d by Interphase to the user for internal use only and is protected by copy right.
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4538 Hardware Reference Manual i Contents List of Figures .
Contents ii Interphase Corporation PowerSpan I ² O Reg ist ers .
Contents 4538 Hardware Reference Manual iii CPM RCCR Reset .
Contents iv Interphase Corporation In Situ EPLD Programming .
4538 Hardware Reference Manual v List of Figures Figur e 1-1. 4538 St ructure .................... ................. ................. ................. ................. ...................... ................. ..... 2 Figure 1-2. Lo cal Space Mapping .
List of Figures vi Interphase Corporation.
4538 Hardware Reference Manual vii List of T ables Table 1-1. PCI Local Space Mapping ........ ....................... ................. ................. ................ ................. ................. ..... 5 Table 1-2. Local Interrupts .. ....
List of Tables viii Interphase Corporation Table 5-3. J4 TTY Serial Connector ........................ ................. ................. ................. ................. ................. .......... 98 Table 5 -4. PMC Co nnec tor P 1 ............
4538 Hardware Reference Manual ix List of Examples ([DPSOH 3RZH U6SDQ,QWH UUXSW0DS5HJLVW HUV,QLWLDO L]DWLRQ& RGH .
List of Examples x Interphase Corporation.
4538 Hardware Reference Manual xi Using This Guide Purpose This 4538 Har dwar e Refer ence Manual is desig ned for softw are de v elopers in Interpha se customer org anizations who intend t o de velo p embedded soft ware and/ or host dri vers fo r the 4538 T1 /E1/J1 communi cations cont roller .
Byte Ordering and Bit Coding Convention xii Interphase Corporation Byt e Or dering an d Bit Co ding Con vention The PCI b us uses the Li ttle Endian By te orderi ng: b yte 0 in a 32- bit wor d is the Le ast Signif icant Byte (LS B) from an arithmet ic point of vie w and is noted D(7: 0).
4538 Hardware Reference Manual xiii C A UTION The Caution icon brings to your attentio n those items or steps that, if not properly followed, could cause problems in your machine ’ s configuration or operating system.
Checking and Downloading f rom the Interphase W WW/FTP Site xiv Interphase Corporation Chec king and D ow nloadi ng fr om the Interphase WWW/FT P Site The late st produc tion softw are dri vers, f irmw are, and document ation (i n Adobe Acrobat PDF or te xt format) for o ur curren t products are av ailabl e on our WWW / FTP sit e.
4538 Hardware Reference Manual xv operati ng system s ubdirectori es. In the se cases, you must choose t he proper bus and opera ting system by typing cd <dir ectory> for t he appropr iate subdir ectories . 8. To download one or more fil es to your lo cal dire ctory, enter get <f ilename> 9.
Checking and Downloading f rom the Interphase W WW/FTP Site xvi Interphase Corporation.
1 4538 Hardware Reference Manual 1 1 Har dware Description Over view The Inte rphase 45 38 PMC E1/T1/J 1 Communicati ons Controll er is a network i nterf ace PCI Mezzani ne Card (PMC) equipped wit h four soft ware-se lectable T1/ E1/J1 inter faces (two are pro vided on the fro nt panel) .
The PowerQUICC II 2 Interphase Corporation 4538 Har dware Structure Figure 1- 1 sho ws the 45 38 hardwa re struc ture: Figure 1-1. 4538 Structure The P owerQUICC II The local CPU is a Motorola MPC8260 RISC embedde d processor .
Chapter 1: Hardware Description 4538 Hardware Reference Manual 3 • Three Fast Ser ia l Communi cat io ns Controll er s (FCCs ). One is used to cont r ol t he Ethe rnet Me dia-I ndep ende nt Inte rfa ce (MII ).
The PowerQUICC II 4 Interphase Corporation Once all t he resets are de-asser ted, the Po werQUICC II boot s using it s 8-bit FLASH de vice. The MPC8260 can control t he reset of the v arious communication pe ripherals through certa in CP M I/O p orts.
Chapter 1: Hardware Description 4538 Hardware Reference Manual 5 local p rocessor can also be ca chable. The peripherals cannot be cachable. The area of SDRAM memory used for the transfer of data can not be cach able ei ther , because it can be mod ified by elem ents oth er tha n the P owerQUI CC II , suc h as th e PowerS pan D MA.
The PowerQUICC II 6 Interphase Corporation Figure 1-2. Local Space Mapping 0xF002 0000 0x0000 0000 0x8000 0000 0xC000 0000 0xCFFF FFFF 0xF000 0000 0xFFFF FFFF 0x03FF FFFF 0x83FF FFFF 0xF002 FFFF 0xF00.
Chapter 1: Hardware Description 4538 Hardware Reference Manual 7 N OT E Accesses from the CPM and the PowerSpan ca nnot go through the Memory Management Unit (MM U), unlike the core acc esses. Therefore, t he CPM an d PowerSpan must use the phy sical addresse s when accessing the SDRAM s (most significant bit = 0).
The PowerQUICC II 8 Interphase Corporation Comm unication Pr ocessor Module (CPM) I/O P or ts The CPM part o f the Po werQUICC I I provid es se veral communication f unctions. Thes e functi ons use mul ti-mode pins th at are grouped i n four I /O ports: Po rt A, B, C, and D.
Chapter 1: Hardware Description 4538 Hardware Reference Manual 9 7 DEOH CPM Port C Usage &30,23RUW 3LQ&RQILJXUDWLRQ 'LU 8VDJH 3& 2XWS XW 2 8 QXVHG 3& 2XWSXW 2 4XDG) $/&UH VHW DFWLYH 3& 2XWSXW 2 8QX VHG 3& &/.
The PowerQUICC II 10 Interphase Corporation C A UTION The I/O ports described as “ Unused ” in the tables above must be configured as general purpose outputs (the logical level does not matter) in order to avoid their electric al level to float.
Chapter 1: Hardware Description 4538 Hardware Reference Manual 11 The tw o f irst TDM b uss es of eac h serial interf ace are connec ted to th e four TDM b usse s of the QuadF ALC. The two others TDM b usses of each ser ial int erface a re used in “ pa ss through mod e ” .
The PowerQUICC II 12 Interphase Corporation Three Eth ernet LEDs, LED3, LED4, a nd LED5, dri ven respec tiv ely by the LXT971 A LED/CFG(1:3) outputs, are provi ded on the fr ont panel. TTY Console Serial P or t The SMC1 par t of the CPM is us ed as a simple asy nchr ono us serial por t f or c onne ction to a TTY consol e.
Chapter 1: Hardware Description 4538 Hardware Reference Manual 13 Figure 1-3. Boar d CPU_LEDs The PCI Bridg e A dedicate d PCI bridge, t he T undra Po werSpan, cont rols the i nterfac e between the card and the host 32-bit PCI b us. The Powe rSpa n impl emen ts all t he regist ers nee ded by the PCI 2.
The PCI Bridge 14 Interphase Corporation The Po w erSpan intern al re gister set can be split into si x dif ferent f unctional gr oups: • PCI confi guration registers (these regi sters, de fined by .
Chapter 1: Hardware Description 4538 Hardware Reference Manual 15 These re gisters a re in it ialized wit h f ix ed reset v alues or wit h v alues st or ed i n t he I ² C se ri al EEPR OM and then us.
The PCI Bridge 16 Interphase Corporation P ower Span Pr ocessor Bus Registers These re gisters are u sed to def ine the parameters o f the loca l to PCI windo ws.
Chapter 1: Hardware Description 4538 Hardware Reference Manual 17 P owerSpan DMA Register s These re gisters are u sed to cont rol the four bidirec tional DMA eng ines pro vided in t he Po werSpan.
The PCI Bridge 18 Interphase Corporation P ower Span Miscellaneous Register s This grou p of re gisters i ncludes s ev eral conf igurati on regis ters for the interr upt funct ions, as well as v arious runt ime regis ters: mail boxes, doorbells, interrupt control/st atus, and semaphore s.
Chapter 1: Hardware Description 4538 Hardware Reference Manual 19 P owerSpan I ² O Register s The Po w erSpan include s I ² O messagin g queues con trolled b y se veral re gisters.
The PCI Bridge 20 Interphase Corporation Interr upt pins – INT1 t o – INT4 are c onf igured as out put ports and con vention ally asso ciated with doorb ell bits DB3 to DB6 in the Po werSpan. Each do orbell bit, when s et, will acti v ate its cor responding i nterrupt pi n (le vel = 0), and when res et will deac ti v ate it (le vel =1).
Chapter 1: Hardware Description 4538 Hardware Reference Manual 21 Local to PCI Interrupt ( – INT A) The Po w erQ UICC II can gene rate an i nterrupt to ward the P CI Host by s etting a door bell bit.
The PCI Bridge 22 Interphase Corporation N OT E A PowerSpan PCI-to-Local window mus t ha ve been enabled in the I ² C seria l EEPROM , in order to al low the CompactPCI host to detect it a t system powe r-on or after the “ Hot Sw ap insertion ” of the board and to map it in th e PCI space .
Chapter 1: Hardware Description 4538 Hardware Reference Manual 23 Figure 1-4. Local Spac e Access Fr om PCI Memory Space When the pr ocessor i s running, the PCI b us can acce ss all t he elements co nnected to the local b u s, exc ept the FLASH bo ot memory .
The PCI Bridge 24 Interphase Corporation dual por t RAM, the Quad F ALC framers, and the IMA de vi ce. (th e proce ssor mus t ha v e it s chip sel ects pro grammed). The local spac e mapping is the same as when acces sed by the process or (see PCI Loca l Space Mappi ng on p age 5 ).
Chapter 1: Hardware Description 4538 Hardware Reference Manual 25 On the 4538 boar d, the serial EEPR OM content disab les the windo ws. By default , no Local to PCI wind ow i s enabled.
The PCI Bridge 26 Interphase Corporation Figure 1- 5. PCI I/ O or Memory Space Access f rom Local Space In-sit u EPLDs Pr ogr amming Some glue l ogic is imple mented in some EPLDs that can be pr ogrammed in-si tu through the PC I int erfac e.
Chapter 1: Hardware Description 4538 Hardware Reference Manual 27 These de vic es keep t heir pro gramming d uring po wer of f. S o the EPLD shoul d normally b e alread y programmed an d the normal user should n ot be a ware of its pro gramming. The EPLDs are in a daisy-cha in confi guration, whic h enables al l of them to be pr ogrammed at once.
The PCI Bridge 28 Interphase Corporation T able 1-24. Hard ware Configuration Regist er Fiel d Descriptions Field Description MPC_ID Microprocessor identif ier: 0000: MPC8260ZU2 00, 200/133 /66MHz, re v A.1 0001: MPC8260ZU1 33, 133/133 /66MHz, re v A.
Chapter 1: Hardware Description 4538 Hardware Reference Manual 29 Vital Pr o duct Data (VPD) No VPD has been def ined for the 4538. Interphase-Specific Production Data and Boot Monitor P a rameters Ad.
The QuadFALC T1/E1/J1 Framer 30 Interphase Corporation The FLASH de vice is normal ly cont ro lled b y t he Po werQUICC II memory controll er uni t using chi p-select s ignal CS0. The Po werQUICC II can read a nd re-progra m the FLASH using th e AMD algorit hms.
Chapter 1: Hardware Description 4538 Hardware Reference Manual 31 The QuadF ALC includes a fle xibl e clock un it that uses a cl ock suppl ied on it s MCLK pin. The QuadF ALC MCLK input i s connected to a 12.500 MHz +/- 20ppm f ixed fr equenc y (CPM BRG6) used b y the internal DPLL.
The QuadFALC T1/E1/J1 Framer 32 Interphase Corporation F or each line x, the QuadF ALC provide s four trans mit multif unction port s (XP A_x, XPB_x, XPC_x and XPD_x) and four recei ve multifunc tion ports (RP A_x, RPB_x, RPC_x and RPD_x).
Chapter 1: Hardware Description 4538 Hardware Reference Manual 33 Each line of the Qua dF ALC framers ca n be conf igured indepen dently in Line T ermination mode (L T) or in Ne twork T ermination mode (NT). In the L T mode, the QuadF ALC is in sla ve mod e and synchroni zes on the lines.
TDM Bus Configurations 34 Interphase Corporation TDM Bus Conf igurations Gen eral The TDM b us general stru ctures a re descri bed in Fig ure 1-6 fo r the gene ral b us structu re and in Fi gure 1-7 and Fi gure 1-8 for the g ener al cl ock st ruc t u re.
Chapter 1: Hardware Description 4538 Hardware Reference Manual 35 Figure 1-6. TDM Busses General Struct ure 5'2B 5'2B ;', B ;', B 03& 3 (%.
TDM Bus Configurations 36 Interphase Corporation Figure 1-7. General Cloc k Structure (Framer 1 & 2).
Chapter 1: Hardware Description 4538 Hardware Reference Manual 37 Figure 1-8. General Cloc k Structure (Framer 3 & 4).
TDM Bus Configurations 38 Interphase Corporation Mul ti plex Dir ect M o d e In this mode, P A(7) = SWMODE_N = 1 and P A(0) = COMCLK_N = 1. In multipl ex di rect mode, t he four fra mers ha ve th e same rh ythm. The QuadF ALC system inter face is in mul tiplex m ode; the first Q uadF AL C TDM bus is di rectl y tie d to th e CPM TDM bus TDMa1.
Chapter 1: Hardware Description 4538 Hardware Reference Manual 39 N OT E TDMb1, TDMc1, TDMd1, TDMa2, TDMb2, TDMc2 and TDMd2 signals are not used and must be tristate d.
TDM Bus Configurations 40 Interphase Corporation Figu r e 1-1 0 . Clocks in M u lt ip l ex Dire ct Mod e (F r a me r 1 & 2).
Chapter 1: Hardware Description 4538 Hardware Reference Manual 41 Figure 1-11. Cloc ks in Mul tiplex Di rect Mode ( Framer 3 & 4).
TDM Bus Configurations 42 Interphase Corporation Independent D irect Mode In this mode, P A(7) = SWMODE_N = 1 and P A(0) = COMCLK_N = 1. In indep endent direc t mode, ea ch fr amer can ha v e its o wn rh yth m.
Chapter 1: Hardware Description 4538 Hardware Reference Manual 43 6&/.5 4XDG) $/& 7'0EB/5&/. 0+]G H MLWWHUHG5HFHLYH 6V WHP &ORFN &05 , 56& J HQHUDWH GEWKH'&2 5FLUFX LWRXWSX W RQ6&/.
TDM Bus Configurations 44 Interphase Corporation N OT E S ■ RCLK2, RCLK3 and RCLK4 must be configured as inputs (PC5.CRP=0). ■ XPA1, XPA2, XPA3 and XPA4 should be configured as SYPX (They must not be configured as outputs ). ■ TDMc1, TDMd1, TDMc2 and TDMd2 signals are not used and should be tristated.
Chapter 1: Hardware Description 4538 Hardware Reference Manual 45 Figure 1-12. TDM Busses in Independent Dir ect Mode 5'2B 5'2B ;', B ;', B 03& 3 (%.
TDM Bus Configurations 46 Interphase Corporation Figure 1- 13. Cloc ks in Inde pendent Direct Mode (Framer 1 & 2).
Chapter 1: Hardware Description 4538 Hardware Reference Manual 47 Figure 1-14. Cloc ks in Independent Direct Mode (Framer 3 & 4).
TDM Bus Configurations 48 Interphase Corporation Switc hed Mode In thi s mo d e, P A(7 ) = SWMO DE_N = 0 a nd P A (0) = C OM CLK _N = 1 . In sw itche d mod e , the Q uad F A L C mu lt iplexed TD M bus is ti ed t o the first TDM bus o n P4. The seco nd TDM bus on P4 is tie d to the MPC8260 .
Chapter 1: Hardware Description 4538 Hardware Reference Manual 49 N OT E TDMb1, TDMc1, TDMd1, TDMa2, TDMb2, TDMc2 and TDMd2 signals are not used and must be tristate d.
TDM Bus Configurations 50 Interphase Corporation Figure 1-16. Cloc ks in Switched Mode (Framer 1 & 2).
Chapter 1: Hardware Description 4538 Hardware Reference Manual 51 Figure 1-17. Cloc ks in Switched Mode (Framer 3 & 4).
TDM Bus Configurations 52 Interphase Corporation P ass-Through Mode In this mode, P A(7) = SWMODE_N = 1 and P A(0) = COMCLK_N = 0 . P ass through i s possibl e from framer 1 to framer 2 an d vice v ersa and from framer 3 t o framer 4 and vice v ersa. The f our framers h av e the sa me rhythm ( COM CLK_ N = 0 ) .
Chapter 1: Hardware Description 4538 Hardware Reference Manual 53 N OT E Un used TDM sig nals must b e tri s tate d. )6& 4XDG) $/& 53 $;3 $ 53 $;3 $ 53 $.
TDM Bus Configurations 54 Interphase Corporation Figure 1-18. TDM Busses in P ass-Thr ough Mode (1->2 & 3->4 Example) 5'2B 5'2B ;', B ;', B 03& .
Chapter 1: Hardware Description 4538 Hardware Reference Manual 55 Figure 1-19. TDM Busses in P ass-Through Mode (2->1 & 4->3 Example) 5'2B 5'2B ;', B ;', B 03.
TDM Bus Configurations 56 Interphase Corporation Figure 1-20. Cloc ks in P as s-Thro ugh Mode (Framer 1 & 2).
Chapter 1: Hardware Description 4538 Hardware Reference Manual 57 Figure 1-21. Cloc ks in P as s-Thro ugh Mode (Framer 3 & 4).
TDM Bus Configurations 58 Interphase Corporation.
2 4538 Hardware Reference Manual 59 2 4538 P ower -Up Initialization Over view After po wer -up, th e ST AR TUP code is e xecuted. This code is wr it te n e n ti re ly in assembly language and is the entry poin t after a po wer- up or a reset e xception.
PowerSpan Initialization 60 Interphase Corporation • PWRUP_BOOT=0: The Power QUICC II boots l ocally (n ot through PCI) • PWRUP_DEBUG_EN=0: Disable debug mode • PWRUP_BYPASS_EN=0:Disab le PLL by.
Chapter 2: 4538 P ower-Up Initialization 4538 Hardware Reference Manual 61 Othe r P owe rSpan Ini tiali zation s It is necessar y to initia lize the Po werSpan Int errupt Map regi sters in a specifi c way , in order to use t he inter rupt pins as s pecif ied for the 4538.
PowerQUICC II Hardware Configuration Word 62 Interphase Corporation Example 2-1. P owerSpan Interr upt Map Regist ers Initial ization Code P owerQUICC II Har dware Configu ration W ord When t he Power.
Chapter 2: 4538 P ower-Up Initialization 4538 Hardware Reference Manual 63 • MMR =11: Ext ernal bus r equests are ma sked (PQ2 is the boot maste r) • LBPC = 00: Loc al bus enable d • APPC = 10: .
PowerQUICC II Init ializations 64 Interphase Corporation • LETM = 1: Enable Loc al Extended Tr ansfer Mode • NPQM = 111: Non PowerQUICC II master connec ted • EXDD = 0: External Master Del ay not dis abled • ISPS = 0: Intern al Space Por t Size = 64 bi ts The resul ting re gister val ue is BCR=0xA01C0000.
Chapter 2: 4538 P ower-Up Initialization 4538 Hardware Reference Manual 65 • APPC = 00: Addres s Parity pin s used as l ocal bus • CS10PC = 01: – CS10/ – BCTL1 used as – BCTL1 • BCTLC = 01.
PowerQUICC II Init ializations 66 Interphase Corporation • Refresh the SDRAM eight time s (OP=001) • Write the SDRAM Mode re gis ter (OP=011 ). Fo r t he mai n SDRAM p laced on the 60x bus, t he r.
Chapter 2: 4538 P ower-Up Initialization 4538 Hardware Reference Manual 67 The inst ruction and da ta caches are enabled through bi ts ICE and DCE of r egister HID0 respect i vely . The se tting of ICE bit mus t be preced ed by an isync inst ruction .
PowerQUICC II Init ializations 68 Interphase Corporation.
3 4538 Hardware Reference Manual 69 3 Pr ogramming the P eripherals Over view This chap ter p rovide s inf orma tion speci fic to th e 453 8 bo ard for pe riphe ral pro gram ming . Its in itia l pur pose is n ot to deta il how to pro gram the p eri pher als th emse lves, f or which the de vel opers should r efer to the manufact urers data sheets.
PowerQUICC II CPM Initialization 70 Interphase Corporation • RFSDx = 01: Receive fra me sync dela y for TDMa. 01 for 1 clock del ay. • DSCx = 0: Double speed c lock for TDMa. 0 means the c hannel clock rate is equal t o the data clock. • CTRx = 1: Common receive and tra nsmit pin clocks for TDMa.
Chapter 3: Programming the Peripherals 4538 Hardware Reference Manual 71 TDM Busses in P ass-Through Mode Accordin g to the TDM buss es conf igurati on ( VHH 7'0%XV&RQILJXUDWLRQV on .
PowerQUICC II CPM Initialization 72 Interphase Corporation Final Resul t of SIxAMR (line 1 to 2 and line 3 to 4) and SIxBMR (line 2 to 1 and li ne 4 to 3) re gisters i s 0x0169. N OT E When a TDM is not used, it is not necessary to initialize the c orresponding SIxMR regist er .
Chapter 3: Programming the Peripherals 4538 Hardware Reference Manual 73 Cloc ks and Baud-Rate Generators Introduction The CPM contai ns eight independen t, identical , Baud-Rate Generator s (BRGs) that c an be used with the FCCs, SCCs, a nd SMCs.
PowerQUICC II CPM Initialization 74 Interphase Corporation MCCF1 re gister i nitiali zation: • Group 1 = 00 : Group 1 (MCC cha nnels 0-31) i s used by TDMa1 • Group 2 = 00 : Group 2 (MCC cha nnels.
Chapter 3: Programming the Peripherals 4538 Hardware Reference Manual 75 T1/E1/J1 Frame r Initialization Intr oduction This sec tion deta ils the Qu adF ALC regist er initia lizati on, assuming that for non- specif ied reg isters, the initia lizatio n is the def ault v alue (which is general ly 0x00).
T1/E1/J1 Framer Initiali zation 76 Interphase Corporation Multiplex ed Direct Mode In multiple x direct mode, th e four framer s ha ve the same rhythm. SWMODE_N = 1 a nd COMCLK_N = 1. System Inter face QuadF ALC is con nected to the CPM through an 8 MHz stream.
Chapter 3: Programming the Peripherals 4538 Hardware Reference Manual 77 N OT E For T1/J1 applications, the mapping of the receive 24 line time slots over the 32 available on the system interface is configurable with FMR1.CTM bit. In 4538 Boot firmware, the cho ice is to select ‘ Channel translation mode 1 ’ , by setting FRM1.
T1/E1/J1 Framer Initiali zation 78 Interphase Corporation SEC/FSC Configuration The SEC/FSC sign al of the QuadF A LC is connected t o CPM and is used for the TDM frame synchron ization clo ck (8 KHz sync hronization pulse gene rated by one of the four DCO- Rs).
Chapter 3: Programming the Peripherals 4538 Hardware Reference Manual 79 RCLK1 is one of th e four channe ls ’ in ternally-g enerated recei v e route cl ocks (RCLK) of a QuadF ALC: the channel se lection is set with GPC1. R1S1 and GPC1.R1S 0 bits – when using RCLK1 for sy nchroni zing th e TDM SIxRAM, an ac ti v e cha nnel shou ld be selected.
T1/E1/J1 Framer Initiali zation 80 Interphase Corporation RCLK1 Configuration as TDM b us cloc k 8 KHz syn chronizatio n pulse gen erated b y the interna l DCO1-R circuit , synch ronized to th e lines a nd pro vided to P4.
Chapter 3: Programming the Peripherals 4538 Hardware Reference Manual 81 not go to a con tinuou s level , but is the fre e runnin g freque ncy of DCO-R.
T1/E1/J1 Framer Initiali zation 82 Interphase Corporation Framing and Line Coding Initialization Com m on In it ial i zati on T1 Specific Initialization E1/E1-CRC4 Common Initialization T able 3-4.
Chapter 3: Programming the Peripherals 4538 Hardware Reference Manual 83 E1 Non-CRC4 Specific Initial ization E1-CRC4 Specific Initial ization Cloc k Synchroni zation Initialization Slave Mode Master Mode T able 3 -7.
The Ethernet Port Initialization 84 Interphase Corporation T ransmit Pulse Shape F or each type o f Line Buil d-Out (LBO), the shape of the t ransmit puls e must be adj usted through Qua dF ALC regist ers LIM0, LI M2, XP M0, XPM1, and XPM2 in o rde r t o compl y with FCC 68 or ANSI T1.
Chapter 3: Programming the Peripherals 4538 Hardware Reference Manual 85 F or a simple SM C1 controller example i n polling mode: See Boot F irmwar e: app cmontty .
The TTY Fram er Initialization 86 Interphase Corporation.
4 4538 Hardware Reference Manual 87 4 Accessing the 4538 on the PCI Side P owerSpan Conf iguration by the PCI Host Se vera l element s of the Po werSpan are automat ically conf igured at po wer- up by the hardw are, or b y th e Po werQUICC II . Ho wev er , some PCI-spe cif ic sett ings ha ve to be done by the PC I host .
Controlling the PCI-to-Local Interrupt 88 Interphase Corporation F or a normal use , the card should be r eset b y the PCI h ost (if need ed) using only the – SRESET s ignal. The – HRESET signa l is used for spec ial cases , such as FLASH memory re-pro gramming through PCI.
Chapter 4: Accessing t he 4538 on the PC I Side 4538 Hardware Reference Manual 89 Local to PCI Int errupt ( – INT A) The Po w erQ UICC II can gene rate an i nterrupt to ward the P CI Host by s etting a door bell bit.
Access t o the FLASH EEPROM Through PCI 90 Interphase Corporation When the proc essor i s runni ng, the PCI b us ha s acces s to all the ele ment s connec ted to t he local b us, except the FLASH boot me mory: the mai n SDRAM memory (t he processor ’ s SDRAM memory cont roller must be initializ ed), the QuadF ALC framers, etc.
Chapter 4: Accessing t he 4538 on the PC I Side 4538 Hardware Reference Manual 91 Example 4-5. FLASH Read and Writ e Routines (Fr om PCI Side).
Serial EEPROM Connected to the PowerSpan 92 Interphase Corporation FLASH EEPROM Pr ogramm ing Algorithm s The boot memor y is a 4Mx8 AMD 29L V033 FLASH de vice. T o reprogram the AMD FLASH de vice, sp ecial progra mming algorith ms are def ined b y AMD, which combine reads and wr it es wi th special addr ess pat te rns .
Chapter 4: Accessing t he 4538 on the PC I Side 4538 Hardware Reference Manual 93 In Situ EPLD Programming Glue logi c is implement ed in some EPLDs tha t can be progr ammed in the f i eld using the PCI inte rface. The EPLDs are in a daisy-cha in confi guration, whic h enables al l of them to be pr ogrammed at once.
PCI Deadlock Situations 94 Interphase Corporation Example: The PCI host se ts the DMA b uf fer descr iptors into th e local memor y , and then it runs the DMA (a wri te into a PowerS pan regi ster).
5 4538 Hardware Reference Manual 95 5 Connector s and Fr ont P anel Connector Placement Figure 5- 1. Connector s on the Component Side Figure 5-2. Connector s and LEDs on the Solder Side 03 & .
Front Panel 96 Interphase Corporation Fr ont P anel Figure 5-3. Connectors and Leds on fr ont panel LED Descriptions CPU_LED1: Board user-p rogrammable green LED contro lled by PD( 15) CPU_LED2: Board.
Chapter 5: Connectors and Front Panel 4538 Hardware Reference Manual 97 Ethernet 10/100 RJ45 Connector J3 T able 5-1. RJ48 Connector s J1 and J2 Signal , 1 , 1 2 8 7 2 8 7 T able 5-2.
PMC Connecto rs 98 Interphase Corporation TTY Serial P or t J4 A 2.5mm ste reo jack conne ctor pro vides a c onnection to an asynchro nous seri al de vice such as a T TY console . Signals on thi s connect or ha ve EIA-232- D electri cal le vel s (RS232) for dir ect conne ction to a con sole.
Chapter 5: Connectors and Front Panel 4538 Hardware Reference Manual 99 1RW FRQQHF WHG 1RWFRQQHFWHG *1' 6XSSO *URXQG 1RWFRQQHFWHG 3&,B &/ .
PMC Connecto rs 100 Interphase Corporation 1RWFRQQHFWHG 1RWFRQQHFWHG 3 $5 7 ULVW DWHELGLUHF WLRQDO 3&,3DULW * 1' 6XSS O *URXQG .
Chapter 5: Connectors and Front Panel 4538 Hardware Reference Manual 101 3&,7 ', ,QSXW -7 $*7 HVW,QSXW% HFDXVHWKHERDUG GRHVQRW VXSSRUWWKH,(((6WDQGDUG.
PMC Connecto rs 102 Interphase Corporation 3 $' 7 ULVW DWHELGLUHFW LRQDO 3&,$GGUHVV' DWD &%( 7 ULVW DWHELGLUHFW LRQDO 3&,%XV&.
Chapter 5: Connectors and Front Panel 4538 Hardware Reference Manual 103 PMC Connector P4 PMC connector P4 supports t he four E1/T1 l ines and tw o TDM buss es with clock s and synchron ization sig nals. The f ramers 1, 2, 3 and 4 are respec ti vely tied to the lines 0, 1, 2 and 3.
PMC Connecto rs 104 Interphase Corporation 1RWFRQQHFWHG 1RWFRQQHFWHG 1RWFRQQHFWHG 1RWFRQQHFWHG 1RWFRQQHFWHG 1RWFRQQHFWHG .
Chapter 5: Connectors and Front Panel 4538 Hardware Reference Manual 105 Deb ug P or t J5 On the 4538 , a 2x8-pin connector can be implem ented to pro vide acces s to the BDM (Backgro und De b ug Mode) b us : the Po werQ UICC II de b ug b u s. Signa ls on t his co nnector ha ve 3.
ISP Enable Jumper JP1 106 Interphase Corporation W A RNING J5 Debug Connector is not compliant to PMC component heigh t specification . It should be removed to insert the 4538 and its carrier into a CompactPCI chassis. ISP Enable J um per JP1 The 4538 in cludes a l ocation for a jumper at JP1.
Chapter 5: Connectors and Front Panel 4538 Hardware Reference Manual 107 Connector Summar y Carrier Car d Specification CompactP CI Carr ier Car d Interp hase has de fined a combinati on of cards t o allo w 4538 rear access con fi gurations in CompactPCI ch assis.
Carrier Card Specification 108 Interphase Corporation J3 Columns 1 5 to 19 are unus ed. J5 Columns 1 4 to 19 are unus ed. 30&,2 30&,2 30& , 2 30& , 2 .
Chapter 5: Connectors and Front Panel 4538 Hardware Reference Manual 109 Signals printe d in bol d in Table 5- 8 and Table 5-9 sha ll be routed to the corr esponding PMC connecto r (used on 6435 R TM). Signals printed in it alics and under lined in Tabl e 5- 8 and Table 5- 9 shall not be used on t he carrie r card.
6435 Rear Transition Module 110 Interphase Corporation 6435 Rear T ransition Mo dule Figure 5-6. 8-P or t 6435 Rear T ransition Module La yo ut.
Chapter 5: Connectors and Front Panel 4538 Hardware Reference Manual 111 N OT E PMC site 1 (J14) corresponds to lines 5 to 8, PMC site 2 (J24) corresp onds to line 1 to 4 The 6435 R TM is a fully passi ve modul e ha ving the same f eatures as the Front Panel T1/E1/J1 (de scr ibed in Front Panel on page 96 ).
6435 Rear Transition Module 112 Interphase Corporation.
A 4538 Hardware Reference Manual 113 A Mechanical Inf ormation PMC Ca r d Di mensi ons .
Carrier Card Dimension Requirements 114 Interphase Corporation Carrier Card Dimension Requ irements .
4538 Hardware Reference Manual 115 Bibliograph y Industry Stan dar ds EIA-232-D: In terface Between Data T erminal Equipment and Data Circui t-T erminating Equipment Employing Serial Binary Data Inter.
116 Interphase Corporation PICMG 2.0 CompactPCI Specification PICMG 2.5 CompactPCI Computer T elephony Specifi cation PICMG 2.1 CompactPCI Hot Swap Specif i cation 3&, ,QG XVW ULDO&RPSX .
4538 Hardware Reference Manual 117 ANSI T1.107-19 95: Digital Hierarchy - Fo rmats Specifications. ANSI T1.646-199 5: Broadband ISDN - Physical Layer Specif ication for User -Network Interfaces Includ ing DS1/A TM.
118 Interphase Corporation 1 specif ication and test principles. ETSI ETS 300 166 - T ran sm is sion and Multiplexing (TM); Physical and electrical characteristics of hierar- chical digital interfaces for equipment using the 2 048 kbit/s - based plesiochronous or synchronous digital hierarchies.
4538 Hardware Reference Manual 119 Inf ineon PEB22 554 / QuadF ALC T1/E1/J1 framer 4XDG)UDP LQJDQG/ LQH,QWHUIDFH&RPS RQHQ WIRU(7- 4XDG) $/&70.
120 Interphase Corporation.
4538 Hardware Reference Manual 121 Glossary AAL A TM Adaptation Lay er Service-dependent sublay er of the data link layer . The AAL accepts data from dif ferent applications and presents it to the ATM layer in t he form of 48-b yte A TM payload segment s.
Glossa ry 122 Interphase Corporation BRI Basic Rate Interface ISDN interface composed of two B Channel s and one D Cha nnel for circu it- switched commun ication of voice, video, and data.
Glossary 4538 Hardware Reference Manual 123 DSX1 Cross-conn ection point for DS1 signals. DTE Data T ermina l Equipment Dev i ce at the user end of a user -network interf ace that serv es as a data source, destination, o r both.
Glossa ry 124 Interphase Corporation ITU -T International T elecommunication Un ion T elecommun ication Standardiza tion Sector Interna- tional body that d ev elops worldwide standards for telecom munications technologies. The ITU-T carries out the functio ns of the former CCITT .
Glossary 4538 Hardware Reference Manual 125 PDU Protocol Data Unit A mes sage of a given pro tocol com pris ing p aylo ad an d pr oto col-s peci fic con tro l information, typ ically contained in a head er . PLP Pack et Leve l Prot ocol Netwo rk lay er pr otoc ol in the X.
Glossa ry 126 Interphase Corporation STS Synchron ous T ra nspo rt Si gn al STS1 Synchr onous T ransport Si gnal le vel 1 Basic b uilding block si gnal of SONE T , operating at 51.84 Mbps. F aster SONET rates are def ined as STS- n, where n is a multiple of 51.
When using t his index, ke ep in mind that a page number ind icates only whe re referenc ed material be gins. It may ext end to the pa ge or pages following th e page ref erenced. 4538 Hardware Reference Manual 127 Inde x B BIST Built-i n Self Test ..
デバイスInterphase Tech 4538の購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
Interphase Tech 4538をまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはInterphase Tech 4538の技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Interphase Tech 4538の取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Interphase Tech 4538で得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Interphase Tech 4538を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はInterphase Tech 4538の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Interphase Tech 4538に関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちInterphase Tech 4538デバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
