Analog DevicesメーカーADSP-2181の使用説明書/サービス説明書
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FUNCTIONAL BLOCK DIAGRAM a DSP Microcomputers ADSP-2181/ADSP-2183 FEATURES PERFORMANCE 30 ns Instruction Cycle Time @ 5.0 Volts 33 MIPS Sustained Performance 34.
ADSP-2181/ADSP-2183 REV. 0 –2– This takes place while the processor continues to: • receive and transmit data through the two serial ports • receive and/or transmit data through the internal D.
ADSP-2181/ADSP-2183 REV. 0 –3– Program memory can store both instructions and data, permit- ting the ADSP-2181/ADSP-2183 to fetch two operands in a single cyc le, one from program memory and one from data memory. The ADSP-2181/ADSP-2183 can fetch an operand from program memory and the next instruction in the same cycle.
ADSP-2181/ADSP-2183 REV. 0 –4– • SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law and µ -law companding according to CCITT recommendation G.711. • SPORT receive and transmit sections can generate unique in- terrupts on completing a data word transfer.
ADSP-2181/ADSP-2183 REV. 0 –5– Table I. Interrupt Priority & Interrupt Vector Addresses Interrupt Vector Source of Interrupt Address (Hex) Reset (or Power-Up with PUCR = 1) 0000 ( Highest Prio.
ADSP-2181/ADSP-2183 REV. 0 –6– When the IDLE (n) instruction is used, it effectively slows down the processor’s internal clock and thus its response time to in- coming interrupts. The one-cycle response time of the standard idle state is increased by n , the clock divisor.
ADSP-2181/ADSP-2183 REV. 0 –7– Table II. PMOVLAY Memory A13 A12:0 0 Internal Not Applicable Not Applicable 1 External 0 13 LSBs of Ad dress Overlay 1 Between 0x2000 and 0x3FFF 2 External 1 13 LSBs of Address Overlay 2 Between 0x2000 and 0x3FFF This organization provides for two external 8K overlay segments using only the normal 14 address bits.
ADSP-2181/ADSP-2183 REV. 0 –8– The CMS pin functions like the other memory select signals with the same timing and bus request logic. A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal.
ADSP-2181/ADSP-2183 REV. 0 –9– Table VI. Boot Summary Table MMAP BMODE Booting Method 0 0 BDMA feature is used in default mode to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded.
ADSP-2181/ADSP-2183 REV. 0 –10– If the ADSP-2181/ADSP-2183 is performing an external memory access when the external device asserts the BR signal, then it will not three-state the memory interfaces or assert the BG signal until the processor cycle after the access completes.
ADSP-2181/ADSP-2183 REV. 0 –11– These ADSP-2181/ADSP-2183 pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pull-up or pull-down resistors.
ADSP-2181–SPECIFICA TIONS RECOMMENDED OPERA TING CONDITIONS K Grade B Grade Parameter Min Max Min Max Unit V DD Supply Voltage 4.5 5.5 4.5 5.5 V T AMB Ambient Operating Temperature 0 +70 –40 +85 ° C ELECTRICAL CHARACTERISTICS K/B Grades Parameter Test Conditions Min Max Unit V IH Hi-Level Input Voltage 1, 2 @ V DD = max 2.
ADSP-2181/ADSP-2183 REV. 0 –13– ESD SENSITIVITY The ADSP-2181 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur to devices subjected to high energy electrostatic discharges.
ADSP-2181/ADSP-2183 REV. 0 –14– ADSP-2181 ENVIRONMENTAL CONDITIONS Ambient Temperature Rating: T AMB = T CASE – (PD × θ CA ) T CASE = Case Temperature in ° C PD = Power Dissipation in W θ CA.
ADSP-2181/ADSP-2183 REV. 0 –15– t DECAY , is dependent on the capacitive load, C L , and the current load, i L , on the output pin. It can be approximated by the fol- lowing equation: t DECAY = C L •0 . 5 V i L from which t DIS = t MEASURED – t DECAY is calculated.
ADSP-2181/ADSP-2183 REV. 0 –16– ADSP-2183–SPECIFICA TIONS RECOMMENDED OPERA TING CONDITIONS K Grade B Grade Parameter Min Max Min Max Unit V DD Supply Voltage 3.
ADSP-2181/ADSP-2183 REV. 0 –17– MEMORY TIMING SPECIFICATIONS The table below shows common memory device specifications and the corresponding ADSP-2183 timing parameters, for your convenience.
ADSP-2181/ADSP-2183 REV. 0 –18– ( C × V DD 2 × f ) is calculated for each output: # of Pins × C × V DD 2 × f Address, DMS 8 × 10 pF × 3.3 2 V × 33.3 MHz = 29.0 mW Data Output, WR 9 × 10 pF × 3.3 2 V × 16.67 MHz = 16.3 mW RD 1 × 10 pF × 3.
ADSP-2181/ADSP-2183 REV. 0 –19– ADSP-2183 CAPACITIVE LOADING Figures 17 and 18 show the capacitive loading characteristics of the ADSP-2183. C L – pF RISE TIME (0.4V – 2.4V) – ns 30 0 0 200 25 50 75 100 125 150 175 25 20 15 10 5 T = +85 ° C V DD = 3.
ADSP-2181/ADSP-2183 REV. 0 –20– ADSP-2181 Parameter Min Max Unit Clock Signals and Reset Timing Requirements : t CKI CLKIN Period 60 150 ns t CKIL CLKIN Width Low 20 ns t CKIH CLKIN Width High 20 ns Switching Characteristics: t CKL CLKOUT Width Low 0.
ADSP-2181/ADSP-2183 REV. 0 –21– ADSP-2181 Parameter Min Max Unit Interrupts and Flag Timing Requirements : t IFS IRQx , FI, or PFx Setup before CLKOUT Low 1, 2, 3, 4 0.25t CK + 15 ns t IFH IRQx , FI, or PFx Hold after CLKOUT High 1, 2, 3, 4 0.25t CK ns Switching Characteristics : t FOH Flag Output Hold after CLKOUT Low 5 0.
ADSP-2181/ADSP-2183 REV. 0 –22– ADSP-2181/ADSP-2183 Parameter Min Max Unit Bus Request/Grant Timing Requirements : t BH BR Hold after CLKOUT High 1 0.25t CK + 2 ns t BS BR Setup before CLKOUT Low 1 0.25t CK + 17 ns Switching Characteristics : t SD CLKOUT High to xMS , 0.
ADSP-2181/ADSP-2183 REV. 0 –23– ADSP-2181 Parameter Min Max Unit Memory Read Timing Requirements : t RDD RD Low to Data Valid 0.5t CK – 9 + w ns t AA A0-A13, xMS to Data Valid 0.75t CK – 10.5 + w ns t RDH Data Hold from RD High 0 ns Switching Characteristics : t RP RD Pulse Width 0.
ADSP-2181/ADSP-2183 REV. 0 –24– ADSP-2181/ADSP-2183 Parameter Min Max Unit Memory Write Switching Characteristics : t DW Data Setup before WR High 0.5t CK – 7+ w ns t DH Data Hold after WR High 0.25t CK – 2 ns t WP WR Pulse Width 0.5t CK – 5 + w ns t WDE WR Low to Data Enabled 0 ns t ASW A0-A13, xMS Setup before WR Low 0.
ADSP-2181/ADSP-2183 REV. 0 –25– ADSP-2181/ADSP-2183 Parameter Min Max Unit Serial Ports Timing Requirements : t SCK SCLK Period 50 ns t SCS DR/TFS/RFS Setup before SCLK Low 4 ns t SCH DR/TFS/RFS Hold after SCLK Low 7 ns t SCP SCLK IN Width 20 ns Switching Characteristics : t CC CLKOUT High to SCLK OUT 0.
ADSP-2181/ADSP-2183 REV. 0 –26– ADSP-2181/ADSP-2183 Parameter Min Max Unit IDMA Address Latch Timing Requirements : t IALP Duration of Address Latch 1, 3 10 ns t IASU IAD15–0 Address Setup befor.
ADSP-2181/ADSP-2183 REV. 0 –27– ADSP-2181 Parameter Min Max Unit IDMA Write, Short Write Cycle Timing Requirements : t IKW IACK Low before Start of Write 1 0n s t IWP Duration of Write 1, 2 15 ns .
ADSP-2181/ADSP-2183 REV. 0 –28– ADSP-2181 Parameter Min Max Unit IDMA Write, Long Write Cycle Timing Requirements : t IKW IACK Low before Start of Write 1 0n s t IKSU IAD15–0 Data Setup before IACK Low 2, 3 0.5t CK + 10 ns t IKH IAD15–0 Data Hold after IACK Low 2, 3 2n s Switching Characteristics : t IKLW Start of Write to IACK Low 4 1.
ADSP-2181/ADSP-2183 REV. 0 –29– ADSP-2181 Parameter Min Max Unit IDMA Read, Long Read Cycle Timing Requirements : t IKR IACK Low before Start of Read 1 0n s t IRP Duration of Read 15 ns Switching Characteristics : t IKHR IACK High after Start of Read 1 15 ns t IKDS IAD15–0 Data Setup before IACK Low 0.
ADSP-2181/ADSP-2183 REV. 0 –30– ADSP-2181 Parameter Min Max Unit IDMA Read, Short Read Cycle Timing Requirements : t IKR IACK Low before Start of Read 1 0n s t IRP Duration of Read 15 ns Switching.
ADSP-2181/ADSP-2183 REV. 0 –31– 128-Lead TQFP Package Pinout 65 64 102 IRQL1 TFS1/IRQ1 RFS1/IRQ0 103 1 128 39 38 BG EBG BR EBR IS V DD GND D23 IRD IWR GND D22 D21 D20 D18 D19 D17 D16 D15 V DD GND .
ADSP-2181/ADSP-2183 REV. 0 –32– TQFP Pin Configurations TQFP Pin TQFP Pin TQFP Pin TQFP Pin Number Name Number Name Number Name Number Name 1 IAL 33 A12 65 ECLK 97 D19 2 PF3 34 A13 66 ELOUT 98 D20.
ADSP-2181/ADSP-2183 REV. 0 –33– OUTLINE DIMENSIONS 128-Lead Metric Thin Plastic Quad Flatpack (TQFP) 65 64 102 103 1 128 39 38 E 3 E 1 E B e D 3 D 1 D TOP VIEW (PINS DOWN) SEATING PLANE L A D A 1 A 2 MILLIMETERS INCHES SYMBOL MIN TYP MAX MIN TYP MAX A 1.
ADSP-2181/ADSP-2183 REV. 0 –34– 128-Lead PQFP Package Pinout 65 64 96 97 1 33 32 TOP VIEW (PINS DOWN) 128L PQFP (28mm x 28mm) 128 PF1 PF2 PF3 IAL BG EBG BR EBR IS V DD GND D23 IRD IWR GND D22 D21 .
ADSP-2181/ADSP-2183 REV. 0 –35– PQFP Pin Configurations PQFP Pin PQFP Pin PQFP Pin PQFP Pin Number Name Number Name Number Name Number Name 1 PF0 33 PWD 65 EBR 97 D23 2 WR 34 IRQ2 66 BR 98 GND 3 R.
ADSP-2181/ADSP-2183 REV. 0 –36– OUTLINE DIMENSIONS 128-Lead Metric Plastic Quad Flatpack (PQFP) 65 64 96 97 1 128 33 32 E 3 E 1 E B e D 3 D 1 D TOP VIEW (PINS DOWN) SEATING PLANE L A D A 1 A 2 MILLIMETERS INCHES SYMBOL MIN TYP MAX MIN TYP MAX A 4.
ADSP-2181/ADSP-2183 REV. 0 –37– ORDERING GUIDE Ambient Instruction Temperature Rate Package Package Part Number Range (MHz) Description Option* ADSP-2181KST-115 0 ° C to +70 ° C 28.8 128-Lead TQFP ST-128 ADSP-2181BST-115 –40 ° C to +85 ° C 28.
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–40– C2144–16–6/96 PRINTED IN U.S.A..
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Analog Devices ADSP-2181を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はAnalog Devices ADSP-2181の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
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