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DAQP-208/208H/308 Type II PCMCIA Data Acquisition Adapter s Users Manual OMEGA ENGINEERING, INC. Tel: (203) 359-1660 One Omega Drive Fax: (203) 359-7700 P.O. Box 4047 Toll free: 1-800-826-6342 Stamford, CT 06907-4047 E-mail: das@omega.com www.dasieee.
WARRANTY/DISCLAIMER OMEGA ENGINEERING, INC., warrants this unit to be free of defects in materials and workmanship for a period of 13 months from the date of purchase. OMEGA warranty adds an additional one (1) month grace period to the normal one (1) year product warranty to cover shipping and handling time.
http://www.omega.com info@omega.com Servicing North America : USA : One Omega Drive, Box 4047 E-mail: info@omega.com ISO 9001 Certified Stamford, CT 06907-0047 Tel: (203) 359-1660 FAX: (203) 359-7700 Canada : 976 Bergar E-mail: info @omega.
United Kingdom : One Omega Drive, River Bend Technology Drive ISO 9002 Certified Northbank, Irlam, Manchester M44 5EX, England Tel: 44 (161) 777-6611 FAX: 44 (161) 777-6622 Toll Free in England: 0800-488-488 E-mail: info @omega.co .uk It is the policy of OMEGA to comply with all worldwide safety and EMC/EMI regulations that apply.
N otice The information contained in this document cannot be reproduced in any form without the written consent of Omega Engineering Inc. Any software programs accompanying this document can be used only in accordance with any licensing agreement(s) between Omega Engineering Inc.
Table of Contents 35 5.1.2 Card Configuration and Status Register (CCSR) .................... 35 5.1.1 Configuration and Option Register (COR) ......................... 34 5.1 PCMCIA Interface ................................................ 34 5. I/O Registers .
55 6. Specifications ..................................................... 53 5.2.10 Auxiliary Status Register (base + 15) ............................. 53 5.2.9 Auxiliary Control Register (base + 15) ............................ 51 5.2.8 Timer/Counter Port (base + 10, base + 11) .
List of Figures and Tables 54 Table 5-22. Auxiliary Status Register Bit Definition .................................. 53 Table 5-21. Auxiliary Control Register Bit Definition ................................. 51 Table 5-20. Timer/Counter Modes .......
1 . Introduction DAQP series cards are PCMCIA type II data acquisition adapters with 4 differential or 8 single-ended analog input channels. The number of input channels can be expanded to 128 when used with input expansion cards. DAQP series products include the DAQP-208, the DAQP- 208 H and the DAQP- 308.
2 . Hardware Configuration and Initial Setup 2 . 1 Software Installation: W indows 95 /98 /2000 ® An “ INF ” file ( daqpcard .inf ) is included on the root directory o f the DaqSuite CD to allow easy configuration in the Windows environment.
2.1.2 Windows 98 1. Insert the DAQP card into any available PC Card socket. The first time a new PC Card type is installed the “Add New Hardware Wizard ” window will open. Click Next to continue. 2. The Add New Hardware Wizard provides several options to configure the DAQP card.
2.1.4 Viewing Resources with Device Manager Follow the instruct i ons provided here to view resources used by the DAQP card using the “Device Manager” utility in Windows. 1. Double click the My Computer icon located on the Windows desktop and then double click the Control Panel icon.
To remove the DAQP card from your W indows NT 4.0 system, run the associated driver support uninstallation program using the Add/Remove Programs icon located in the Control Panel folder. (This will remove all registry entries applicable to your hardware).
2 . 3 Data Acquisition Software and Drivers D ata acquisition software and driver support installations are available from the DaqSuite CD demo main menu. 1. Quatech’s DaqEZ ? - This software package was specifically designed to support all Quatech’s data acquisition adapter functions and is included free of charge with your hardware.
2 . 4 Software Installation: Windows 3.x and MS-DOS® T wo software configuration programs are provided with the DAQP card: a Client Driver named DAQPA_CL.SYS and a card Enabler named DAQPA_EN.EXE. Either one of these programs may be used to configure the card but only one may be used at a time .
2 . 4 . 1 Client Driver for MS-DOS For systems using MS-DOS and PCMCIA Card and Socket Services software, a Client Driver named “DAQPA_CL.SYS” is provided to configure the DAQP series cards. PCMCIA Card and Socket Services software is not provided with your DAQP card, but is available from your vendor.
2 . 4 . 1 . 1 Client Driver Command Line Options The DAQP series Client Driver accepts up to eight command line arguments from the user to determine the configuration of the DAQP card.
Example 3 DEVICE = C:DAQPA_CL.SYS (s0,b300,i5) Example 3 is also a single command line argument. The client Driver will attempt to configure the DAQP card inserted in socket 0 at base address 300H and IRQ level 5. If either address 300H or IRQ level 5 is unavailable, the card will NOT be configured.
2.4.1.3 Common Problems Generic Client Drivers Many Card and Socket Services packages include a generic client driver (or SuperClient) which configures standard I/O devices. If one of these generic client drivers is installed, it may configure the DAQP card and cause the DAQP series Client Driver to fail installation.
2.4.2 Enabler for MS-DOS For systems that are not operating PCMCIA Card and Socket Services software, the DAQP series card includes an Enabler program to enable and configure the DAQP card. This Enabler, DAQPA_EN.EXE, will operate in any DOS system using an Intel 82365SL or PCIC compatible PCMCIA host adapter.
6. Reboot the system and note the message displayed when the Enabler is loaded. If the Enabler reports the desired card configuration, the installation process is complete.
2 . 4 . 2 . 1 Enabler Command Line Options To configure a DAQP series card, the Enabler requires one command line argument from the user to determine the configuration. This argument must be enclosed in parenthesis. Within the argument, a comma (no space) must be used to separate the parameters from each other if there are two or more parameters.
Example 4 DEVICE = C:DAQPA_EN.EXE (s0,b300,i5,wCC) Here the Enabler will configure the DAQP card in socket 0 with a base address at 300H and IRQ level 5 using a configuration memory window at CC000H . Example 5 DEVICE = C:DAQPA_EN.EXE (s0,r) DEVICE = C: DAQPA_EN.
3 . Field Wiring The DAQP card is fitted in with a 32-pin 0.8 mm shielded connector. See Figure 3-1 for pin assignments. 33 30 25 20 15 10 5 1 Reserved Ch 0 Ch 0 (-) / Ch 4 Ch 1 (-) / Ch 5 Ch 2 (-) / Ch 6 Ch 3 (-) / Ch 7 DA0 +5V ExtClock ExtOut Ch 1 Ch 2 Ch 3 GND DA1 GND ExtGate GND FullPower SSH (Synch.
3 . 1 CP-DAQ PA Cable Assembly The cable assembly included with your DAQP card, part number CP-DAQPA, converts the card’s 32 pin I/O connector to a standard D37 connector. Figure 3-2 illustrates the D37 connector pin assig n ments for the CP-DAQ PA and the optional screw terminal block UIO-37 .
Table 3-1 lists cable mapping for the CP-DAQPA Hirose-32 to D37 connectors . Table 3-1. DAQP Series Card Cable Mapping Reserved N/C 1 Signal ground (digital) GND 29 2 Signal ground (digital) GND 29 3 .
3 . 2 UIO-37 Screw Terminal Block For applications requiring discrete wiring connections, the UIO-37 terminal block shown in Figure 3-3 provides a simple way of connecting signals to the DAQP card. The D37 connector is available in either male or female and has two rows of screw terminals.
4 . Theory of Operation The DAQP card consists of 4 differential or 8 single-ended analog input channels each with a bipolar input range of ±10v, ±5v, ±2.5v or ±1.25v (programmable gain of 1, 2, 4 or 8) . The A/D converter, either 12 -bit or 16-bit, can be operated at a top speed of 100,000 samples per second (10 µs per sample).
4 . 2 Analog Input Multiplexer Differential or single-ended configuration is determined by bit 6 of the high byte in the scan list register. ‘1’ selects differential input, while a ‘0’ selects single-ended input. Expansion cards will only support single-ended channels.
4 . 4 Scan List Register One entry to the scan list register contains a 16-bit word or two 8-bit bytes. It specifies the internal channel and gain selection in the high byte or MSB, and the external channel and gain selection in the low byte or LSB , in addition to other control and configuration settings.
4 . 5 Trigger Circuit The DAQP card can be triggered by software, an external TTL signal, the analog input passing through the preset threshold or the pacer clock. For the TTL or analog trigger, an active trigger edge can be selected for either the low-to-high or high-to-low transition.
4 . 6 A/D Converter and Data FIFO The DAQP card always assumes a bipolar input range of ±10V if the gain is one. The output data format will always be in 2's complement (and left justified for 12-bit versions). The data acquisition time of the A/D converter is 2 µs while it’s conversion time is no more than 8 µs.
4 . 7 Interrupt and Status The DAQP card has three interrupt sources, the end-of-scan (EOS) interrupt, the FIFO threshold interrupt and the timer interrupt. The control register (base + 2, write only) has two bits to enable or disable the EOS and FIFO interrupts independently.
4 . 9 A/D State Machine The DAQP card has an internal state machine that controls A/D operation, (see Figure 4-1). The state machine defaults to S0 after power up or reset. The normal state flow would be first S0 to S3, initiated by a scan list (queue) flush command (RSTQ).
4 . 10 D/A Circuit The DAQP series PC card is equipped with two D/A channels. The 12-bit D/A converter is a serial converter supporting synchronous update and is configured for a bipolar output range from -5V to +5V.
bit 3 of the command register at base + 7). The integrity of the latched count is guaranteed by the logic design. The timer port is allocated at base + 10 (low byte) and base + 11 (high byte). The 16 bit reload register is accessed when writing to the port, while the read-latch register is accessed when reading the port.
5 . I/O Registers 5 . 1 PCMCIA Interface The information in this section is provided for those who need low level PCMCIA interface details for the DAQP card . The client driver or enabler that comes with the DAQP card will be sufficient for most applications.
5 . 1 . 1 Configuration and Option Register (COR) Bits 7 and 6 of the Configuration Option Register are defined by the PCMCIA standard as the SRESET and the LevlREQ Bits. A “1” written into the SRESET bit puts the card in reset state, while a “0” moves it out of reset state.
5 . 2 Address Map The DAQP card uses eight consecutive I/O locations within the system I/O address space. The base address of the adapter is determined during hardware configuration . The eight I/O locations are used by the DAQP card as summarized in the following table.
5 . 2 . 1 Data FIFO Register (base + 0) The data FIFO register is considered as the access port to the data FIFO, which holds up to 2048 data words from the A/D conversion results. The port is also used for programming the data FIFO thresholds, as explained later in this section.
almost empty thresholds (in bytes). The first word specifies the almost empty threshold, (not used, can be set to anything), while the second word determines the almost full threshold.
The threshold should be set to a value from 1 to FIFO size minus 1. (Default is set to 7 at reset or power up). Refer to Table 5- 7 for FIFO threshold settings .
5 . 2 . 1 . 3 FIFO Flags When reading the register under mode 1 or 3, the first available data byte from the data FIFO will be returned if it is not empty, otherwise the returned byte is not defined.
5.2.2.1 Scan List Queue Programming The scan list queue must be programmed when the A/D circuit card is idle. Each queue entry contains two bytes as described above and the integrity of the entry must be guaranteed. (The scan list queue is write only).
5 . 2 . 2 . 2 Channel Configuration Bits 5 and 4 (LSB) in a queue entry specify the gain of the external expansion card for the external channel selected by bits 0-3 of the same byte.
5.2.2.5 Expansion Mode Bit 5 must be set to “1” if there is an expansion card(s) connected to the DAQP card . All of the digital output lines (bits 0-3) will be used for external channel selection and two of the four digital input lines (bit 1 and 3) will be used for external gain selection.
5 . 2 . 2 . 9 Analog Trigger Threshold The analog trigger threshold can only be set by the output of D/A channel 1, with an equivalent range from -10V to +10V (full A/D converter input range). The threshold level is set at the A/D converter input (after the programmable gain amplifier), not the one at the input connector (before the PGA).
5.2.3 Status Register (base + 2) The status register is read only and shares the same offset as the control register. It reports data FIFO flag, A/D interrupt and A/D conversion status.
5.2.4 Digital I/O Register 5.2.4.1 Digital Output The four digital output lines share the same pins on the interface connector as the four external channel selection bits.
5 . 2 . 5 Pacer Clock (base + 4, + 5, + 6) The pacer clock is actually a 24-bit auto re-load frequency divider. It contains a 24 bit divisor register, a 24 bit counter, an internal clock pre-scaler and a clock source multiplexer . Figure 5 -1 shows the pacer clock block diagram.
5 . 2 . 6 Command Register (base + 7) The command register is used for sending control commands to the DAQP card including arm/trigger (or start A/D), scan list queue and data FIFO flush, stop A/D and timer/counter latch commands. It also sets the data program/access mode for the data FIFO.
5 . 2 . 6 . 3 Flush Data FIFO Command The data FIFO should be flushed before data acquisition is initiated by the trigger/arm command, but not until after the scan list has been configured. The flush command may also be followed by FIFO threshold programming.
After the thresholds are programmed, set the access control bit to “1” by writing a byte of 01H into the auxiliary control register. This will make the following read/write operation access the data bytes in the FIFO instead of it’s thresholds.
5 . 2 . 7 . 2 D/A Port Interface The data link between the D/A data port and the D/A converter is a serial link. The port interface contains a 16 bit buffer register and a 16 bit shift register. On the other side of the link, there are input and output registers in each D/A channel of the D/A converter.
5.2.8 Timer/Counter Port (base + 10, base + 11) The timer/counter port can be accessed as either a 16 bit word at base + 8, or two consecutive bytes at base + 8 (low byte) and base + 9 (high byte). The port contains a 16 bit reload register, a 16 bit up-counter and a 16 bit read latch register and the associated control logic.
5 . 2 . 8 . 2 Timer/Counter Clock Source Bit 2 of the auxiliary control register (base + 15, write) selects the timer/counter clock source. The source can be either the internal 1 MHz clock (bit 2 is “0”) or the external clock (bit 2 is “1”).
5 . 2 . 9 Auxiliary Control Register (base + 15) This register configures the operation of A/D, D/A and the timer counter. It is 8-bit wide and write only. Bit 7 picks between TTL and analog trigger source. Bit 6 sets the pre-trigger option. Bit 5 is for the timer/counter interrupt control.
Table 5-22. Auxiliary Status Register Bit Definition 1 = FIFO empty, 0 = Not empty A/D data FIFO empty flag 0 1 = FIFO almost full, 0 = Not yet A/D data FIFO almost full flag 1 1 = Data lost latched, .
6 . Specifications A/D Converter 12-Bit Version 16-Bit Version Acquisition + Conversion 2 ms + 8 ms 2 ms + 8 ms Monotonicity No missing codes No missing codes Integral linearity error ± 1 LSB ± 3 LSB Differential linearity error ± 1 LSB +3/-2 LSB Full scale error ± 0.
Analog Output Number of output channels 2 (single-ended only) Output Settling Time 10 ms Output range ±5V (bipolar only) Output Current ±2 mA DC Output impedance 0.
DAQP -208/208H/308 Users Manual Version 2. 30 April 12 , 2000 Part No. 940-0092-2 30 DAQP-208/208H/308 Users Manual 61.
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