PanasonicメーカーMN103001G/F01Kの使用説明書/サービス説明書
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MICROCOMPUTER MN1030 MN103001G/F01K LSI User ’ s Manual Pub.N o .23101-050E.
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2. CPU 3. Extension Instruction Specifications 4. Memory Modes 5. Operating Mode 6. Clock Generator 7. Internal Memory 8. Bus Controller (BC) 9. Interrupt Controller 10. 8-bit Timers 11. 16-bit Timers 12. Watchdog Timer Table of Contents/List of Figures and Tables 1 0 3 5 4 7 6 9 8 10 11 12 2 13.
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14. A/D Converter 15. I/O Ports 16. Internal Flash Memory 17. Ordering Mask ROM Appendix 14 15 16 17.
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Table of Contents/List of Figures and Tables 0.
ii Table of Contents 1. General Specifications 1.1 Overview .................................................................................................................... .... 1-2 1.2 Features ....................................................
iii 5. Operating Mode 5.1 Overview .................................................................................................................... .... 5-2 5.2 Reset Mode ...........................................................................
iv 8.13.2 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode ...................................................................... 8-35 8.13.3 16-bit Bus in Asynchronous Mode and in Address/Data Separate Mode .........
v 10.6 Description of Operation ............................................................................................ 10-20 10.6.1 Interval Timers and Timer Output ............................................................ 10-20 10.6.2 Event Counting .
vi 13.4.2 Block Diagram of UART Serial Interface ................................................ 13-37 13.4.3 Description of Registers for the UART Serial Interface ........................... 13-38 13.4.4 Description of Operation ...................
vii 15.9.3 Pin Configurations .................................................................................... 15-44 15.10 Port 8 .................................................................................................................... .
viii List of Figures and Tables List of Figures 1. General Specifications Fig. 1-3-1 MN103001G Block Diagram .................................................................................... 1-4 Fig. 1-4-1 Pin Assignments Diagram ..................
ix Fig. 8-7-1 Address Format When Accessing External Memory .............................................. 8-26 Fig. 8-7-2 Space Partitioning ................................................................................................... .8 - 2 7 Fig.
x Fig. 8-13-21 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2) ................ 8-49 Fig. 8-13-22 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK) .
xi 10. 8-bit Timers Fig. 10-3-1 8-bit Timer Block Diagram (Timers 0 to 3) ............................................................ 10-3 Fig. 10-3-2 8-bit Timer Block Diagram (Timers 4 to B) .........................................................
xii 12. Watchdog Timer Fig. 12-3-1 Block Diagram ....................................................................................................... . 12-3 Fig. 12-5-1 Operation Diagram 1: When Reset Is Released ...................................
xiii Fig. 14-5-2 External Trigger Input Conversion Example (for Channels 0 to 2, One Time Each) ..................................................................... 14-8 Fig. 14-5-3 External Trigger Input Conversion Example ..........................
xiv 17. Ordering Mask ROM Fig. 17-2-1 ROM Ordering Method 1 ........................................................................................ 17-2 Fig. 17-2-2 ROM Ordering Method 2 ...............................................................
xv List of Tables 1. General Specifications Table 1-4-1 Pin Assignments ..................................................................................................... ... 1-6 Table 1-4-2 Pin Function Table (1/2) ................................
xvi 10. 8-bit Timers Table 10-4-1 List of 8-bit Timer Functions .................................................................................. 10-9 Table 10-5-1 List of 8-bit Timer Registers (1/2) ..................................................
xvii Table 15-13-1Port B Configuration ............................................................................................. 1 5-60 Table 15-14-1Port C Configuration .............................................................................
xviii.
1 0 1. General Specifications.
1-2 General Specifications 1.1 Overview The MN1030 Series is a 32-bit microcontroller that maintains the software assets of Matsushita Electronics' 16-bit MN102 Series of microcontrollers by offering ease of use and excellent cost-performance with a simple, high- performance architecture.
1-3 General Specifications High-speed/high-performance bus interface ■ Can select either separate address/data buses or multiplex address/data bus • Address: 24 bits/Data: 8/16 bits ■ External m.
1-4 General Specifications Clock and system controller A/D 10-bit 4 inputs SIF UART x 1 multipurpose x 1 synchronous system x 2 ROM 128 KB (flash memory 256 KB) Data RAM 8 KB 32-bit CPU core I/O ports.
1-5 General Specifications Fig. 1-4-1 Pin Assignments Diagram * "VDD2" in the case of the MN103001G, "VPP" in the case of the MN1030F01K. 1.4 Pin Description 1.4.1 Pin Assignments The pin assignments are shown in Fig. 1-4-1 and Table 1-4-1.
1-6 General Specifications Table 1-4-1 Pin Assignments • Pins for which two or more names are shown are multipurpose pins. * "VDD2" in the case of the MN103001G, "VPP" in the case of the MN1030F01K. Pin No. Pin Name Pin No. Pin Name Pin No.
1-7 General Specifications 1.4.2 Pin Functions Table 1-4-2 shows the function of each pin of this microcontroller. Table 1-4-2 Pin Function Table (1/2) Category Pin name Input/ Number Pin Function Output of pins Power supply VDD 8 Digital system power supply (+3.
1-8 General Specifications Table 1-4-2 Pin Function Table (2/2) Category Pin name Input/ Number Pin Function Output of pins Reset RST I 1 Reset input Interrupts NMIRQ I 1 External non-maskable interru.
2. CPU 2.
2-2 CPU 2.1 Basic Specifications of CPU • Structure Load/store architecture Data/Address/SP Registers x 9 (Data registers: 32-bit x 4, Address registers: 32-bit x 4, SP: 32-bit x 1) Other Registers .
2-3 CPU 2.2 Block Diagram The block diagram for this microcontroller, focusing on the CPU, is shown below. Fig. 2-2-1 CPU Core Block Diagram Instruction queue Interrupt control block Operand address A.
2-4 CPU 31 D0 D1 D2 D3 0 31 A0 A1 A2 A3 0 31 SP 0 31 PC 0 31 MDR 0 15 PSW 0 31 LIR 0 31 LAR 0 Data Register Address Register Stack Pointer Program Counter Multiply/Divide Register Processor Status Word Loop Instruction Register Loop Address Register Fig.
2-5 CPU 0 Z 15 0 0 S1 S0 IE IM2 IM1 0000 IM0 VC N Fig. 2-3-2 Processor Status Word ■ Data Register (32-bit x 4) This register can be used generally for all operations. Operations are performed with a 32-bit length and the data size is converted when sending data to and from the memory or by executing the EXTB or EXTH instructions.
2-6 CPU Z: Zero Flag This flag is set when an operation result is all zeroes, and is cleared by any other result. This flag is also cleared by a reset. N: Negative Flag This flag is set if the MSB of an operation result is "1", and is cleared if the MSB is "0".
2-7 CPU 2.3.2 Control Registers This microcontroller uses the memory-mapped-I/O method and allocates the peripheral circuit registers to the internal I/O space between addresses x'20000000 and x'3FFFFFFF. The registers listed below are described in this section.
2-8 CPU Interrupt Vector Register (IVARn) The interrupt vector register (IVAR0 to IVAR6) contains the lower 16 bits of the start address of the interrupt handler for interrupts of the level accepted by the CPU. IVAR0 corresponds to level 0 interrupts; in similar fashion, IVAR1 to IVAR6 correspond to levels 1 to 6, respectively.
2-9 CPU CPU Mode Register (CPUM) The CPU mode register (CPUM) sets the clock operating mode for the CPU and peripheral blocks. This register is allocated to the internal I/O space at address x'20000040.
2-10 CPU Am/An 0 31 PC 0 31 0 31 0 31 (32-bit address) 0 31 (32-bit address) 0 31 (32-bit address) 0 31 (32-bit address) 0 31 Register direct Immediate value Dm / Dn Am / An imm8 / regs imm16 imm32 im.
2-11 CPU 2.4.2 Data Types Data types can be processed in the four types of bit, byte, halfword and word data. Byte data, halfword data and word data can be handled as signed and unsigned data. The sign bit is MSB. The data in the memory must be aligned data.
2-12 CPU 2.4.3 Instruction Set The instruction set has a simple organization, and features the generation of compact and optimized code through a C compiler.
2-13 CPU • Bit instructions BTST Bit Test BSET Test and set (processing unit: byte) BCLR Test and clear (processing unit: byte) • Shift instructions ASR Shift Right Arithmetic LSR Shift Right Logi.
2-14 CPU 2.5 Interrupts 2.5.1 Overview of Interrupts The most important key to real-time control is the ability to shift quickly to interrupt handler processing.
2-15 CPU 0I D 15 0 1 4 1 3 1 2 1 1 1 0 9876543 21 000000 0000 0 0I D 15 0 1 4 1 3 1 2 1 1 1 0 9876543 21 LV IE IR G0ICR (NMICR) GnICR (n = 2 to 19) 2.5.2 Registers [Flags in the PSW] (CPU) Interrupt-related flags in the processor status word (PSW) include interrupt enable and interrupt mask level.
2-16 CPU LV2 to LV0 (Interrupt Priority Level) R/W • This 3-bit field sets the interrupt priority level. When the interrupt priority level set in LV2 to LV0 is higher than the interrupt mask level set in IM2 to IM0 in the PSW (i.
2-17 CPU [Interrupt Accept Group Register (IAGR)] R halfword/byte access During a register read, the interrupt accept group register (IAGR) indicates the smallest group number of the groups that are generating an interrupt of the interrupt levels accepted by the CPU, which are indicated by IM2 to IM0 of the PSW.
2-18 CPU 2.5.3 Interrupt Types The three types of interrupts are listed below: [Reset interrupt] The reset interrupt is the interrupt with the highest priority level, and is generated by setting the RST pin to "L" level. As a result of the reset interrupt, the registers, etc.
2-19 CPU [Level interrupts] Level interrupts are interrupts for which the interrupt level can be controlled through the interrupt enable (IE) and interrupt mask (IM2 to IM0) bits in the PSW. Level interrupts are interrupts from the interrupt group controllers external to the CPU (in other words, peripheral interrupts).
2-20 CPU (Example of pre-processing by the interrupt handler) 1. The registers are saved. The saved registers are those used by the interrupt handler. 2.
2-21 CPU An even higher interrupt response speed can be realized by assigning only one factor or only a few factors to a single interrupt level. Fig. 2-5-6 shows the interrupt sequence flow when assigning one factor to each interrupt level.
2-22 CPU [Stack Frame] When an interrupt is accepted, a stack frame is allocated and the total 6 bytes of information in the PC and PSW are saved in order to return from the interrupt. However, since the transfer of data across the 32-bit boundary is prohibited, the SP value must constantly be set to a multiple of 4.
3. Extension Instruction Specifications 3.
Extension Instruction Specifications 3-2 3.1 Operation Extension Function The MN1030 series 32-bit microcontrollers are provided with 32 extension instructions which can be defined by users.
Extension Instruction Specifications 3-3 3.2 Extension Instructions 3.2.1 Explanation of Notations The notations used to describe instruction manual are shown below.
Extension Instruction Specifications 3-4 Multiply Register Multiply & Accumulate Register (Higher) Multiply & Accumulate Register (Lower) Multiply & Accumulate Overflow Detect Flag Register Bit 0 MCVF Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 MDRQ MCRH MCRL 3.
Extension Instruction Specifications 3-5 3.2.3 Extension Instruction Details PUTX (Register transfer instruction for high-speed multiplication: Load) [Instruction Format (Macro Name)] PUTX Dm [Assembler Mnemonic] udf20 Dm, Dm [Operation] The contents of Dm are transferred to the high-speed multiply register MDRQ.
Extension Instruction Specifications 3-6 PUTCX (Register transfer instruction for multiply-and-accumulate operation: Load) [Instruction Format (Macro Name)] PUTCX Dm, Dn [Assembler Mnemonic] udf21 Dm, Dn [Operation] This instruction transfers the contents of Dm to the multiply-and-accumulate register MCRH.
Extension Instruction Specifications 3-7 GETX (Register transfer instruction for high-speed multiplication: Store) [Instruction Format (Macro Name)] GETX Dn [Assembler Mnemonic] udf15 Dn, Dn [Operation] The contents of the high-speed multiply register MDRQ are transferred to Dn.
Extension Instruction Specifications 3-8 GETCHX (Register high-order 32-bit transfer instruction for multiply-and-accumulate operation: Store) [Instruction Format (Macro Name)] GETCHX Dn [Assembler Mnemonic] udf12 Dn, Dn [Operation] This instruction transfers the contents of the multiply-and-accumulate register MCRH to Dn.
Extension Instruction Specifications 3-9 GETCLX (Register low-order 32-bit transfer instruction for multiply-and-accumulate operation: Store) [Instruction Format (Macro Name)] GETCLX Dn [Assembler Mnemonic] udf13 Dn, Dn [Operation] This instruction transfers the contents of the multiply-and-accumulate register MCRL to Dn.
Extension Instruction Specifications 3-10 CLRMAC (Register clear instruction for multiply-and-accumulate operation) [Instruction Format (Macro Name)] CLRMAC [Assembler Mnemonic] udf22 D0, D0 [Operation] This instruction clears the contents of the multiply-and-accumulate registers MCRH and MCRL.
Extension Instruction Specifications 3-11 MULQ (Signed high-speed multiplication instruction: between registers) [Instruction Format (Macro Name)] MULQ Dm, Dn [Assembler Mnemonic] udf00 Dm, Dn [Operation] This instruction performs multiplication quickly using the multiplier of the extension function unit.
Extension Instruction Specifications 3-12 MULQI (Signed high-speed multiplication instruction: between immediate value and register) [Instruction Format (Macro Name)] MULQI imm, Dn [Assembler Mnemonic.
Extension Instruction Specifications 3-13 MULQU (Unsigned high-speed multiplication instruction: between registers) [Instruction Format (Macro Name)] MULQU Dm, Dn [Assembler Mnemonic] udf01 Dm, Dn [Operation] This instruction performs multiplication quickly using the multiplier of the extension function unit.
Extension Instruction Specifications 3-14 MULQIU (Unsigned high-speed multiplication instruction: between immediate value and register) [Instruction Format (Macro Name)] MULQIU imm, Dn [Assembler Mnem.
Extension Instruction Specifications 3-15 MAC (Signed multiply-and-accumulate operation instruction: between registers) [Instruction Format (Macro Name)] MAC Dm, Dn [Assembler Mnemonic] udf28 Dm, Dn [Operation] This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit.
Extension Instruction Specifications 3-16 MACH (Signed half word data multiply-and-accumulate operation instruction: between registers) [Instruction Format (Macro Name)] MACH Dm, Dn [Assembler Mnemoni.
Extension Instruction Specifications 3-17 MACB (Signed byte data multiply-and-accumulate operation instruction: between registers) [Instruction Format (Macro Name)] MACB Dm, Dn [Assembler Mnemonic] udf32 Dm, Dn [Operation] This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit.
Extension Instruction Specifications 3-18 MACU (Unsigned multiply-and-accumulate operation instruction: between registers) [Instruction Format (Macro Name)] MACU Dm, Dn [Assembler Mnemonic] udf29 Dm, Dn [Operation] This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit.
Extension Instruction Specifications 3-19 MACHU (Unsigned half word data multiply-and-accumulate operation instruction: between registers) [Instruction Format (Macro Name)] MACHU Dm, Dn [Assembler Mne.
Extension Instruction Specifications 3-20 MACBU (Unsigned byte data multiply-and-accumulate operation instruction: between registers) [Instruction Format (Macro Name)] MACBU Dm, Dn [Assembler Mnemonic.
Extension Instruction Specifications 3-21 SAT16 (16-bit saturation operation instruction) [Instruction Format (Macro Name)] SAT16 Dm, Dn [Assembler Mnemonic] udf04 Dm, Dn [Operation] When Dm is a 16-bit signed number which is the maximum positive value (0x00007fff) or more, the maximum positive value (0x00007fff) is written into Dn.
Extension Instruction Specifications 3-22 SAT24 (24-bit saturation operation instruction) [Instruction Format (Macro Name)] SAT24 Dm, Dn [Assembler Mnemonic] udf05 Dm, Dn [Operation] When Dm is a 24-bit signed number which is the maximum positive value (0x007fffff) or more, the maximum positive value (0x007fffff) is written into Dn.
Extension Instruction Specifications 3-23 MCST (Multiply-and-accumulate operation results 8-, 16-, 32-bit saturation operation instruction) [Instruction Format (Macro Name)] MCST Dm, Dn MCST imm8, Dn .
Extension Instruction Specifications 3-24 [Flag Changes] When multiply-and-accumulate operation overflow was not detected (MCVF = 0) Flag Change Condition V 0 Indicates that the multiply-and-accumulate operation is valid.
Extension Instruction Specifications 3-25 MCST9 (Multiply-and-accumulate operation results 9-bit saturation operation instruction/positive value conversion instruction) [Instruction Format (Macro Name.
Extension Instruction Specifications 3-26 MCST48 (Multiply-and-accumulate operation results 48-bit saturation operation instruction) [Instruction Format (Macro Name)] MCST48 Dn [Assembler Mnemonic] ud.
Extension Instruction Specifications 3-27 Bit 31 Bit 0 1 00 000 000 000 000 00 Dn before execution Dn after execution Search range Search direction MSB LSB BSCH (Bit search instruction) [Instruction F.
Extension Instruction Specifications 3-28 SWAP (Data swapping instruction that swaps bytes [high-order to low-order and vice versa] in four-byte data) [Instruction Format (Macro Name)] SWAP Dm, Dn [As.
Extension Instruction Specifications 3-29 [Flag Changes] Flag Change Condition V * Undefined C * Undefined N * Undefined Z * Undefined [Programming Cautions] PSW updating by flag changes is delayed by one instruction. However, Bcc and Lcc instructions can evaluate flags without waiting for flag reflection to PSW.
Extension Instruction Specifications 3-30 Bit 31 Bit 0 MSB LSB Dm before execution Dn after execution Dm[31:24] Dm[23:16] Dm[15:8] Dm[7:0] Bit 31 Bit 0 MSB LSB Dm[7:0] Dm[15:8] Dm[23:16] Dm[31:24] SWA.
Extension Instruction Specifications 3-31 Multiply-and- accumulate instruction *3 MCRH, MCRL access instruction *4 MCRH, MCRL access instruction *4 Multiply-and- accumulate instruction *3 High-speed multiplication instruction * 5 Multiply-and- accumulate instruction *3 High-speed multiplication instruction *5 3.
Extension Instruction Specifications 3-32 (a ) Note on the description of word/half-word data multiply-and-accumulate instructions and multiply-and- accumulate instructions When executing a word/half-.
Extension Instruction Specifications 3-33 (b) Note on the description of word/half-word data multiply-and-accumulate instructions and MCRH, MCRL access instructions When executing a word/half-word dat.
Extension Instruction Specifications 3-34 (c) Note on the description of byte data multiply-and-accumulate instructions and MCRH, MCRL access instructions When executing a byte data multiply-and-accum.
Extension Instruction Specifications 3-35 (d) Note on the description of multiply-and-accumulate instructions and multiply-and-accumulate instructions or multiply-and-accumulate instructions and quick.
Extension Instruction Specifications 3-36 (e) Note on the description of memory access and multiply-and-accumulate instruction or high-speed multiplication instruction There is an error occasion - CPU.
Extension Instruction Specifications 3-37 If a stack area is in the internal RAM, any error making potential condition shown on the following cases 4 to 12 is not generated.
Extension Instruction Specifications 3-38 <Error actualizing condition> Error actualizing condition is generated by the first extension instruction executed in the interrupt program, or after switching of the task. Error actualizing condition is shown below.
Extension Instruction Specifications 3-39 In addition, please obey the following recommended conditions of 3 points when a program is developed by the assembler so that this error would not occur. As for the program developed by the PanaXSeries C compiler, the following recommended conditions are guaranteed.
Extension Instruction Specifications 3-40.
4. Memory Modes 3 4.
Memory Modes 4-2 4.1 Memory Mode Types and Selection This microcontroller has a 32-bit linear address space of up to 4 Gbytes. The address space is comprised of internal memory space built into the chip and external memory space located outside the chip.
Memory Modes 4-3 4.2 Memory Mode Pin Processing Fix the input levels for the memory mode pins (MMOD0,1) as shown in Table 4-2-1 and Fig. 4-2-1 with pull-up/ pull-down resistors. For details on the pull-up/pull-down resistance, refer to “High-speed Serial Control Card Operation Manual”.
Memory Modes 4-4 4.3 Description of Memory Mode 4.3.1 Memory Extension Mode The memory mode which comprises a system from both internal and external memory is called memory extension mode.
Memory Modes 4-5 4.3.2 Processor Mode The memory mode which executes externally located instructions while using the internal data RAM and I/O ports is called processor mode. The internal instruction ROM and the internal flash memory are not used for this mode.
Memory Modes 4-6.
5. Operating Mode 5.
Operating Mode 5-2 5.1 Overview The 32-bit microcontroller has the following three operating modes. Oscillator start/stop and CPU and peripheral circuit start/stop switching control functions are provided to support low power consumption. Operating modes 1.
Operating Mode 5-3 5.2 Reset Mode • The mode in which the reset (RST) pin is active ( “ L ” level) is called “ Reset Mode ” . • When the reset pin is low, the chip is reset (initialized) internally.
Operating Mode 5-4 5.3 Low Power Mode Low power consumption is achieved by stopping the oscillation of the oscillators and the clock generator (CG) and stopping the clocks supplied to the CPU and peripheral circuits. Low power mode contains the following three modes and transitions to the three modes are made through software.
6. Clock Generator 6 13.
Clock Generator 6-2 6.1 Overview The CG has an internal PLL circuit; in addition to supplying clock pulses to this microcontroller at a frequency that is a multiple of the oscillating frequency of the.
Clock Generator 6-3 6.4 Description of Operation 6.4.1 Input Frequency Setting The CG input frequency range is set by the external input pin CKSEL. When CKSEL is set “H”, use an oscillator or resonator with an input frequency fosci such that 8 MHz ≤ fosci ≤ 18 MHz.
Clock Generator 6-4 The relationship between the input frequency (fosci) and the SYSCLK, MCLK, and IOCLK multiples and frequencies is shown in Table 6-4-2, and the relationship between the input frequency (fosci) and the SYSCLK, MCLK, and IOCLK multiples and frequencies when reset is released is shown in Table 6-4-3.
7. Internal Memory 7.
Internal Memory 7-2 7.1 Overview The MN103001G has 128 Kbytes of instruction ROM and 8 Kbytes of internal data RAM. The MN1030F01K has 256 Kbytes of flash memory and 8 Kbytes of internal data RAM. The instruction ROM/flash memory and data RAM are connected to the CPU core via a 64-bit bus and a 32-bit bus, respectively.
Internal Memory 7-3 7.3 Internal Memory Configuration The internal instruction ROM is located in the internal memory space at address x'40000000 to x'4001FFFF, while the internal flash memory is located at address x'40000000 to x'4003FFFF and the internal data RAM is located at address x'00000000 to x'00001FFF.
Internal Memory 7-4.
8. Bus Controller (BC) 8.
Bus Controller (BC) 8-2 8.1 Overview The bus controller (BC) controls interfacing between the CPU core, internal I/O (peripherals), and devices external to the chip.
Bus Controller (BC) 8-3 8.3 Bus Configuration Fig. 8-3-1 shows the bus configuration. The chip’s internal buses are the ROM bus between the CPU core and internal instruction ROM/internal flash memor.
Bus Controller (BC) 8-4 Fig. 8-4-1 Block Diagram for the Bus Controller BC address bus BC data bus I/O address bus I/O data bus BC internal data bus BC bus interface signals I/O bus interface signals .
Bus Controller (BC) 8-5 8.5 Pin Functions The external pin functions relating to the bus controller are shown in Table 8-5-1. Table 8-5-1 External Pin Functions Relating to the Bus Controller Pin name.
Bus Controller (BC) 8-6 Table 8-5-2 shows the operating status of the external pins concerning BC. Table 8-5-2 Operating Status of Pins Concerning BC Operating status SLEEP mode STOP mode HALT mode Wh.
Bus Controller (BC) 8-7 8.6 Description of Registers Table 8-6-1 lists the bus controller registers. The settings of these registers are used in timing control, DRAM interface control, etc.
Bus Controller (BC) 8-8 ~ ~ ~ ~ ~ ~ ~ ~ 8.6.1 Memory Block 0 Control Register Memory control register 0A/B is used to set the memory block 0 read/write timing and synchronous/asynchronous mode through software. Memory control register 0A Register symbol: MEMCTR0A Address: x’32000030 Purpose: Sets the access timing, etc.
Bus Controller (BC) 8-9 ~ ~ ~ ~ ~ ~ Memory control register 0B Register symbol: MEMCTR0B Address: x’32000020 Purpose: Sets the bus mode, access timing, etc.
Bus Controller (BC) 8-10 8.6.2 Memory Block 1 Control Register Memory control register 1A/B is used to set the memory block 1 read/write timing, synchronous/asynchronous mode, DRAM mode, page mode, and bus width through software. Memory control register 1A Register symbol: MEMCTR1A Address: x’32000032 Purpose: Sets the access timing, etc.
Bus Controller (BC) 8-11 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ When using DRAM (Memory control register 1B B1DRAM = 1) Bit No. Bit name Description Setting conditions 1 to 0 BCS1 to 0 Row address setup timing 00: prohi.
Bus Controller (BC) 8-12 ~ ~ ~ ~ ~ ~ Memory control register 1B Register symbol: MEMCTR1B Address: x ’ 32000022 Purpose: Sets the bus mode, access timing, etc.
Bus Controller (BC) 8-13 When using DRAM (Memory control register 1B B1DRAM = 1) Bit No. Bit name Description Setting conditions 0 DRAM Block 1 DRAM 1: Use as DRAM space.
Bus Controller (BC) 8-14 8.6.3 Memory Block 2 Control Register Memory control register 2A/B is used to set the memory block 2 read/write timing, synchronous/asynchronous mode, fixed wait/handshaking mode, DRAM mode, page mode, and bus width through software.
Bus Controller (BC) 8-15 When using handshaking mode (Memory control register 2B B2DRAM = 0, B2WM = 1) Bit No. Bit name Description Setting conditions 1 to 0 BCS1 to 0 DK detection wait cycle 00: proh.
Bus Controller (BC) 8-16 When using fixed wait mode and not using DRAM (Memory control register 2B B2DRAM = 0, B2WM = 0) Bit No. Bit name Description Setting conditions 0 DRAM Block 2 DRAM 0: Do not use as DRAM space.
Bus Controller (BC) 8-17 ~ ~ ~ ~ ~ ~ ~ ~ When using DRAM (Memory control register 2B B2DRAM = 1 B2WM = 0) Bit No. Bit name Description Setting conditions 0 DRAM Block 2 DRAM 1: Use as DRAM space space.
Bus Controller (BC) 8-18 After the reset is released, block 2 is set as follows: Address output end timing 3MCLK RE negate timing 29MCLK WE negate timing 29MCLK RE/WE assert timing 3MCLK Bus cycle sta.
Bus Controller (BC) 8-19 8.6.4 Memory Block 3 Control Register Memory control register 3A/B is used to set the memory block 3 read/write timing, synchronous/asynchronous mode, fixed wait/handshaking mode, and bus width through software. However, the handshaking mode can only be set when (MCLK frequency/SYSCLK frequency) = 4.
Bus Controller (BC) 8-20 When using handshaking mode (Memory control register 3B B3WM = 1) Bit No. Bit name Description Setting conditions 1 to 0 BCS1 to 0 DK detection wait cycle (used as parameter D.
Bus Controller (BC) 8-21 When using handshaking mode (Memory control register 3B B3WM = 1) Bit No. Bit name Description Setting conditions 1 WM Block 3 wait mode 1: Handshaking mode 2 BM Block 3 bus m.
Bus Controller (BC) 8-22 8.6.5 DRAM control register DRAM control register Register symbol: DRAMCTR Address: x'32000040 Purpose: Stores various DRAM mode settings when DRAM is connected.
Bus Controller (BC) 8-23 ~ ~ 8.6.6 Refresh count register Register symbol: REFCNT Address: x'32000042 Purpose: Sets the DRAM refresh interval when DRAM is connected.
Bus Controller (BC) 8-24 8.6.7 Page Row Address Register Page Row Address Register Register symbol: PRAR Address: x'32000044 Purpose: Sets the row address for DRAM software page mode.
Bus Controller (BC) 8-25 Notes when switching the internal clock multiplier Be aware of the following points when setting the clock control register CKCTR and changing the internal clock multiplier.
Bus Controller (BC) 8-26 8.7 Space Partitioning In extension memory mode (MMOD 1 to 0 = "LH"), the 1 GB memory space from x'80000000 to x'BFFFFFFF becomes external memory space; in processor mode (MMOD 1 to 0 = "HL"), the 2 GB memory space from x'40000000 to x'BFFFFFFF becomes external memory space.
Bus Controller (BC) 8-27 Fig. 8-7-2 Space Partitioning 1 GB Processor mode System reserved 2 GB 1 GB Internal memory space External memory space External memory space that is actually assigned as exte.
Bus Controller (BC) 8-28 8.8 Operation Clocks MCLK, IOCLK, and SYSCLK are used as BC operation clocks. Table 8-8-1 shows the ratio of each clock versus the oscillation input clock (OSCI).
Bus Controller (BC) 8-29 8.10 Bus Cycle Depending on the value of the external input pin CKSEL and the internal registers, the MCLK frequency can be either 1/2, 1, 2, or 4 times the input frequency, and the IOCLK frequency can be either 1/8, 1/4, 1/2, or 1 times the input frequency.
Bus Controller (BC) 8-30 8.11 Store Buffer The bus controller has one store buffer (with a 32-bit data width) built in, and is used to avoid a time penalty when conducting a store operation in internal I/O or external memory.
Bus Controller (BC) 8-31 8.12 Accessing the Internal I/O Space Accesses to the internal I/O space (I/O register) are performed through the I/O bus, with the bus controller controlling the interface for read/write requests from the CPU. Accesses between the bus controller and the internal I/O space are executed in synchronization with IOCLK.
Bus Controller (BC) 8-32 8.13 External Memory Space Access (Non-DRAM Spaces) During an access to external memory, the BC controls the interface for the read/write request from the CPU. Table 8-13-1 lists the transactions that are supported for the external bus.
Bus Controller (BC) 8-33 8. 13. 1 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode Setting of the various parameters for external memory access is performed in memory control registers 0 to 3, corresponding to each block.
Bus Controller (BC) 8-34 An Dn WEn RE CSn EA MCLK SYSCLK BCS BCE BCS BCE REN EA WEN Write Read :Undefined Fig. 8-13-2 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and in A.
Bus Controller (BC) 8-35 8.13.2 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode When using handshaking, bus access starts once synchronization with SYSCLK is achieve.
Bus Controller (BC) 8-36 Fig. 8-13-5 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2) For details on the various timing settings, refer to the description of the memory control register in section 8.
Bus Controller (BC) 8-37 An Dn WEn RE CSn EA MCLK SYSCLK EA Read Write BCE BCE REN WEN : Undefined 8.13.3 16-bit Bus in Asynchronous Mode and in Address/Data Separate Mode Asynchronous mode is used for accessing external memory at high speed; the address signals, CSn signals, etc.
Bus Controller (BC) 8-38 An Dn WEn RE CSn EA MCLK SYSCLK EA Read Write BCE BCE REN WEN : Undefined Fig. 8-13-9 Access Timing on a 16-bit Bus in Asynchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK) For details on the various timing settings, refer to the description of the memory control register in section 8.
Bus Controller (BC) 8-39 8.13.4 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode 8-bit bus mode is set for block 0 by setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, and for blocks 1 to 3 by setting the BnBW bit to "0" in the corresponding memory control register.
Bus Controller (BC) 8-40 An D7-0 WE0 RE CSn MCLK SYSCLK Read low- order side Read high- order side Write low- order side Write high- order side A[0]=0 BCE BCS A[0]=1 BCE BCS A[0]=0 BCE BCS A[0]=1 BCE BCS EA REN EA REN EA WEN WEN EA : Undefined Fig.
Bus Controller (BC) 8-41 8.13.5 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode 8-bit bus mode is set for blocks 2 and 3 by setting the BnBW bit to “ 0 ” in the corresponding memory control register.
Bus Controller (BC) 8-42 (a) Read Timing (b) Write Timing Fig. 8-13-13 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 4) For details on the various timing settings, refer to the description of the memory control register in section 8.
Bus Controller (BC) 8-43 Fig. 8-13-14 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2) For details on the various timing settings, refer to the description of the memory control register in section 8.
Bus Controller (BC) 8-44 (a) Read Timing (b) Write Timing Fig. 8-13-15 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK) For details on the various timing settings, refer to the description of the memory control register in section 8.
Bus Controller (BC) 8-45 8.13.6 8-bit Bus in Asynchronous Mode and in Address/Data Separate Mode 8-bit bus mode is set for block 0 by setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, and for blocks 1 to 3 by setting the BnBW bit to “ 0 ” in the corresponding memory control register.
Bus Controller (BC) 8-46 Fig. 8-13-17 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4) For details on the various timing settings, refer to the description of the memory control register in section 8.
Bus Controller (BC) 8-47 Fig. 8-13-18 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2) For details on the various timing settings, refer to the description of the memory control register in section 8.
Bus Controller (BC) 8-48 8.13.8 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 2 and 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0).
Bus Controller (BC) 8-49 Fig. 8-13-21 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2) For details on the various timing settings, refer to the description of the memory control register in section 8.
Bus Controller (BC) 8-50 Fig. 8-13-22 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK) For details on the various timing settings, refer to the description of the memory control register in section 8.
Bus Controller (BC) 8-51 8.13.9 16-bit Bus in Asynchronous Mode and in Address/Data Multiplex Mode By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 0 to 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0).
Bus Controller (BC) 8-52 8.13.10 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 0 to 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0).
Bus Controller (BC) 8-53 (a) Read Timing Fig. 8-13-24 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4) For details on the various timing settings, refer to the description of the memory control register in section 8.
Bus Controller (BC) 8-54 Fig. 8-13-25 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2) For details on the various timing settings, refer to the description of the memory control register in section 8.
Bus Controller (BC) 8-55 (b) Write Timing Fig. 8-13-26 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK) For details on the various timing settings, refer to the description of the memory control register in section 8.
Bus Controller (BC) 8-56 8.13.11 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 2 and 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0).
Bus Controller (BC) 8-57 Fig. 8-13-27 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in Address/ Data Multiplex Mode (MCLK = SYSCLK multiplied by 4) For details on the various timing settings, refer to the description of the memory control register in section 8.
Bus Controller (BC) 8-58 (a) Read Timing Fig. 8-13-28 Access Timing on a 8-bit Bus with Handshaking in Synchronous Mode and in Address/ Data Multiplex Mode (MCLK = SYSCLK multiplied by 2) For details on the various timing settings, refer to the description of the memory control register in section 8.
Bus Controller (BC) 8-59 (a) Read Timing (b) Write Timing Fig. 8-13-29 Access Timing on a 8-bit Bus with Handshaking in Synchronous Mode and in Address/ Data Multiplex Mode (MCLK = SYSCLK) For details on the various timing settings, refer to the description of the memory control register in section 8.
Bus Controller (BC) 8-60 8.13.12 8-bit Bus in Asynchronous Mode and in Address/Data Multiplex Mode By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 0 to 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0).
Bus Controller (BC) 8-61 (b) Write Timing (a) Read Timing Fig. 8-13-30 Access Timing on a 8-bit Bus in Asynchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4) For details on the various timing settings, refer to the description of the memory control register in section 8.
Bus Controller (BC) 8-62 8.14 External Memory Space Access (DRAM Space) 8.14.1 DRAM Space Blocks 1 and 2 can be used as DRAM space by setting the BnDRAM bits in memory control registers 1B/2B and setting the DRAME bit in DRAM control register.
Bus Controller (BC) 8-63 ■ Minimum value for the RAS Precharge interval When consecutive DRAM accesses are performed, the RAS precharge interval is shortest when performing an access of type (1) or .
Bus Controller (BC) 8-64 ■ 2 WE control/2 CAS control DRAM that permits byte/word control can be supported by selecting either one of the following two methods: • 2 WE control: The two pins WE1 and WE0 are used for byte/word control. • 2 CAS control: The two pins DCAS1 and DCAS0 are used for byte/word control.
Bus Controller (BC) 8-65 8.14.2 DRAM page mode If the PAGE bit in the DRAM control register is set to “1”, page mode access is enabled, making high-speed access in page mode possible for following accesses to DRAM. (1) Word/half-word access when the bus width is set to 8 bits (2) Word access when the bus width is set to 16 bits Fig.
Bus Controller (BC) 8-66 8.14.3 Software Page Mode Software page mode is a mode that forcibly initiates page mode by setting the control register. Operation within software page mode is as described below. Refer to Fig. 8-14-6. • When the mode is initiated, the contents of PRAR are output as the row address.
Bus Controller (BC) 8-67 MCLK Row CAO+1 An CAS RE Dn ASR RASn Column CAS ASC Column CAS Column CAS ASC ASC MCLK Row CAO+1 An CAS WEn Dn ASR RASn Column Column CAS ASC ASC CAS ASC CAS Column (a) Read Timing (b) Write Timing Fig.
Bus Controller (BC) 8-68 [Restrictions on Use] (1) While software page mode is in effect, external access outside of the block in question is prohibited. Cancel software page mode before accessing an external memory space other than the block for which software page mode is set.
Bus Controller (BC) 8-69 Fig. 8-14-8 DRAM Refresh Timing For details on the ASR and RP settings, refer to the explanations in section 8.6.2, “Memory Block 1 Control Register,” and section 8.6.3, “Memory Block 2 Control Register.” For details on the RERS setting, refer to the explanation in section 8.
Bus Controller (BC) 8-70 8.15 Bus Arbitration In this microcontroller, bus arbitration is implemented through the bus authority request signal (BR) and the bus authority release signal (BG).
Bus Controller (BC) 8-71 Fig. 8-15-1 Bus Arbitration Timing 1 (Bus Authority Release/Bus Authority Acquisition, nfr = 4) Fig. 8-15-2 Bus Arbitration Timing 2 (Bus Authority Release/Bus Authority Acqui.
Bus Controller (BC) 8-72 Fig. 8-15-3 Bus Arbitration Timing 3 (Bus Authority Release/Bus Authority Acquisition, n fr = 1) Fig. 8-15-4 Bus Arbitration Timing 4 (Refresh Request Generated While Bus Auth.
Bus Controller (BC) 8-73 8.16 Cautions These cautions concern the BC. These cautions must be heeded, since failure to do so may result in misoperation. 1. Do not change the contents of the relevant memory control register and the DRAM control register while accessing external memory space, except when software page mode is not in effect.
Bus Controller (BC) 8-74 2. _____ Designate the bus authority request pin (BR) as a general-purpose input port, and the bus authority release _____ pin (BG) as a general-purpose output port, for instance, so that bus requests cannot be accepted during execution of a BSET or BCLR instruction.
9. Interrupt Controller 9.
Interrupt Controller 9-2 9.1 Overview The interrupt controller processes non-maskable interrupts and level interrupts (internal interrupts and external interrupts). For external pins, the microcontroller has eight external interrupt pins and one non-maskable interrupt pin.
Interrupt Controller 9-3 9.4 Block Diagram Fig. 9-4-1 Block Diagram 1 Interrupt control register address NMIRQ pin Watchdog timer overflow System error Reserved for system Timer 0 underflow Timer 1 un.
Interrupt Controller 9-4 Interrupt control register address GROUP 9 3 2 1 0 — — GROUP 10 3 2 1 0 — — GROUP 7 3 2 1 0 x'3400011C — — GROUP 8 3 2 1 0 x'34000120 — — GROUP 11 3 .
Interrupt Controller 9-5 Interrupt control register address GROUP 14 3 2 1 0 — — — GROUP 15 3 2 1 0 — — — GROUP 16 3 2 1 0 — — — GROUP 17 3 2 1 0 — — — GROUP 18 3 2 1 0 — —.
Interrupt Controller 9-6 9.5 Description of Registers This interrupt controller includes an interrupt control registers, an interrupt accepted group register, and an external interrupt condition specification register. Table 9-5-1 lists the interrupt controller registers.
Interrupt Controller 9-7 Non-maskable interrupt control register Register symbol: G0ICR (NMICR) Address: x'34000100 Purpose: This register determines whether a non-maskable interrupt has been generated.
Interrupt Controller 9-8 Group n interrupt control register GnICR (n = 2 to 19) Registers G2ICR to G19ICR control level interrupts for groups 2 to 19, respectively. Each register confirms the group interrupt level as well as the enabling, request, and detection of interrupts within the respective group.
Interrupt Controller 9-9 Bit No. Bit name Description 11 to 8 IE3 to 0 Group n interrupt enable register • This register is used to specify whether an interrupt is enabled or not. • When an IEn(n=3 to 0) bit is set to "1", the corresponding interrupt is enabled.
Interrupt Controller 9-10 Group 2 interrupt control register Register symbol: G2ICR Address: x'34000108 Purpose: This register is used to enable group 2 interrupts, and to confirm interrupt requests and detection.
Interrupt Controller 9-11 Group 3 interrupt control register Register symbol: G3ICR Address: x'3400010C Purpose: This register is used to enable group 3 interrupts, and to confirm interrupt requests and detection.
Interrupt Controller 9-12 Group 4 interrupt control register Register symbol: G4ICR Address: x'34000110 Purpose: This register is used to enable group 4 interrupts, and to confirm interrupt requests and detection.
Interrupt Controller 9-13 Group 5 interrupt control register Register symbol: G5ICR Address: x'34000114 Purpose: This register is used to enable group 5 interrupts, and to confirm interrupt requests and detection.
Interrupt Controller 9-14 Group 6 interrupt control register Register symbol: G6ICR Address: x'34000118 Purpose: This register is used to enable group 6 interrupts, and to confirm interrupt requests and detection.
Interrupt Controller 9-15 Group 7 interrupt control register Register symbol: G7ICR Address: x'3400011C Purpose: This register is used to enable group 7 interrupts, and to confirm interrupt requests and detection.
Interrupt Controller 9-16 Group 8 interrupt control register Register symbol: G8ICR Address: x'34000120 Purpose: This register is used to enable group 8 interrupts, and to confirm interrupt requests and detection.
Interrupt Controller 9-17 Group 9 interrupt control register Register symbol: G9ICR Address: x'34000124 Purpose: This register is used to enable group 9 interrupts, and to confirm interrupt requests and detection.
Interrupt Controller 9-18 Group 10 interrupt control register Register symbol: G10ICR Address: x'34000128 Purpose: This register is used to enable group 10 interrupts, and to confirm interrupt requests and detection.
Interrupt Controller 9-19 Group 11 interrupt control register Register symbol: G11ICR Address: x'3400012C Purpose: This register is used to enable group 11 interrupts, and to confirm interrupt requests and detection.
Interrupt Controller 9-20 Group 12 interrupt control register Register symbol: G12ICR Address: x'34000130 Purpose: This register is used to enable group 12 interrupts, and to confirm interrupt requests and detection.
Interrupt Controller 9-21 Group 13 interrupt control register Register symbol: G13ICR Address: x'34000134 Purpose: This register is used to enable group 13 interrupts, and to confirm interrupt requests and detection.
Interrupt Controller 9-22 Group 14 interrupt control register Register symbol: G14ICR Address: x'34000138 Purpose: This register is used to enable group 14 interrupts, and to confirm interrupt requests and detection.
Interrupt Controller 9-23 Group 15 interrupt control register Register symbol: G15ICR Address: x'3400013C Purpose: This register is used to enable group 15 interrupts, and to confirm interrupt requests and detection.
Interrupt Controller 9-24 Group 16 interrupt control register Register symbol: G16ICR Address: x'34000140 Purpose: This register is used to enable group 16 interrupts, and to confirm interrupt requests and detection.
Interrupt Controller 9-25 Group 17 interrupt control register Register symbol: G17ICR Address: x'34000144 Purpose: This register is used to enable group 17 interrupts, and to confirm interrupt requests and detection.
Interrupt Controller 9-26 Group 18 interrupt control register Register symbol: G18ICR Address: x'34000148 Purpose: This register is used to enable group 18 interrupts, and to confirm interrupt requests and detection.
Interrupt Controller 9-27 Group 19 interrupt control register Register symbol: G19ICR Address: x'3400014C Purpose: This register is used to enable group 19 interrupts, and to confirm interrupt requests and detection.
Interrupt Controller 9-28 Interrupt accepted group register Register symbol: IAGR Address: x'34000200 Purpose: This register is used to read the group number that generated the interrupt request.
Interrupt Controller 9-29 External interrupt condition specification register Register symbol: EXTMD Address: x'34000280 Purpose: This register specifies the external interrupt generation conditions. Set the desired level or edge for each pin. B i t N o .
Interrupt Controller 9-30 9.6 Description of Operation The following interrupt processing is performed. • Non-maskable interrupts NMIRQ pin interrupt Watchdog timer overflow interrupt System error i.
Interrupt Controller 9-31 [Cautions] 1. Maintain external pin interrupt signals for at least 10, 5, or 2.5 SYSCLK cycles when n fr = (MCLK frequency/ SYSCLK frequency) = 1, 2, or 4, respectively. The interrupt cannot be detected if the signal is not maintained for at least that long.
Interrupt Controller 9-32.
10. 8-bit Timers 9 10.
8-bit Timers 10-2 10.1 Overview This device has 12 reload timers built in. All are down counters that can be used as interval timers and event counters. Eight of the timers are also capable of PWM output. 10.2 Features The features of the 8-bit timers are described below.
8-bit Timers 10-3 10.3 Block Diagram Fig. 10-3-1 shows a block diagram for timers 0 to 3. Fig. 10-3-2 shows a block diagram for timers 4 to B. Figures 10-3-3 to 10-3-6 show connection diagrams for the 8-bit timers.
8-bit Timers 10-4 Fig. 10-3-2 8-bit Timer Block Diagram (Timers 4 to B) Output waveform control Timer n (n = 4, 5, 6, 7, 8, 9, A, B) Match Output control TMnOUT Compare register Compare register buffe.
8-bit Timers 10-5 Fig. 10-3-3 8-bit Timer Connection Diagram (Overall) TM0IRQ Timer interrupt 0 TMnIN1 TMnIN0 TMnIN2 Block Timer 0 to 3 TM0OUT TM0IRQ TMnIN5 TMnIN4 TMnIN6 Timer 0 Timer 1 Timer 2 Timer.
8-bit Timers 10-6 Fig. 10-3-4 8-bit Timer Connection Diagram (Timer 0 to 3 block) TM0IN1 TM0IN0 TM0IN3 TM0IN2 TM0CI Timer 0 TM0OUT TM0IRQ TM0CO TM0CLK TM0IN5 TM0IN4 TM0IN7 TM0IN6 TM0IRQ Timer interrup.
8-bit Timers 10-7 TM4IRQ Timer interrupt 4 IOCLK/32 TM4IN1 TM4IN0 TM4IN3 TM4IN2 TM4CI Timer 4 TM4OUT TM4IRQ TM4CO TM4CLK TM4IN5 TM4IN4 TM4IN7 TM4IN6 TM5IN1 TM5IN0 TM5IN3 TM5IN2 TM5CI Timer 5 TM5OUT TM.
8-bit Timers 10-8 Fig. 10-3-6 8-bit Timer Connection Diagram (Timer 8 to B block) TM8IRQ Timer interrupt 8 IOCLK/32 TM8IN1 TM8IN0 TM8IN3 TM8IN2 TM8CI Timer 8 TM8OUT TM8IRQ TM8CO TM8CLK TM8IN5 TM8IN4 T.
8-bit Timers 10-9 Note: Because timers 0 and 8, 1 and 9, 2 and A, and 3 and B share multipurpose output pins, only one of either "timer output" or "PWM output" can be selected. 10.4 Functions Table 10-4-1 lists the functions of each 8-bit timer.
8-bit Timers 10-10 10.5 Description of Registers Table 10-5-1 lists the 8-bit timer registers. Table 10-5-1 List of 8-bit Timer Registers (1/2) Address Name Symbol Number of bits Initial value Access .
8-bit Timers 10-11 Address Name Symbol Number of bits Initial value Access size x'34001034 Timer 4 compare register TM4CMP 8 x'00 8, 16, 32 x'34001035 Timer 5 compare register TM5CMP 8 .
8-bit Timers 10-12 Timer n mode register (n = 0, 1, 2, 3) Register symbol: TMnMD Address: x'34001000 (n=0), x'34001001 (n=1), x'34001002 (n=2), x'34001003 (n=3) Purpose: This register controls the operation of timer n.
8-bit Timers 10-13 Timer n mode register (n = 4, 5, 6, 7, 8, 9, A, B) Register symbol: TMnMD Address: x'34001004 (n=4), x'34001005 (n=5), x'34001006 (n=6), x'34001007 (n=7), x'34001008 (n=8), x'34001009 (n=9), x'3400100A (n=A), x'3400100B (n=B) Purpose: This register controls the operation of timer n.
8-bit Timers 10-14 [Note] When setting TMnCNE to "1", do so while TMnLDE is set to "0". When setting TMnLDE to "1", do so while TMnCNE is set to "0". Operation is not guaranteed if TMnCNE and TMnLDE are both set to "1" at the same time.
8-bit Timers 10-15 When using 1/8 IOCLK or 1/32 IOCLK, the prescaler control register (TMPSCNT) must be set. When TMnIO pin input was selected, the rising edge of the pin input signal is counted.
8-bit Timers 10-16 Timer n base register (n = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B) Register symbol: TMnBR Address: x'34001010 (n = 0), x'34001011 (n = 1), x'34001012 (n = 2), x'3400.
8-bit Timers 10-17 Timer n compare register (n = 4, 5, 6, 7, 8, 9, A, B) Register symbol: TMnCMP Address: x'34001034 (n = 4), x'34001035 (n = 5), x'34001036 (n = 6), x'34001037 (n .
8-bit Timers 10-18 Timer output selection register Register symbol: TMOSL Address: x'34001070 Purpose: This register selects the 8-bit timer output signal. B i t N o . 7654321 0 Bit ---- TM TM TM TM name OSL3 OSL2 OSL1 OSL0 Reset 0 0 0 0 0 0 0 0 Access R R R R R/W R/W R/W R/W Bit No.
8-bit Timers 10-19 Prescaler control register Register symbol: TMPSCNT Address: x'34001071 Purpose: This register controls the prescaler operation. B i t N o . 7654321 0 Bit TMPS ---- --- name CNE Reset 0 0 0 0 0 0 0 0 Access R/W R R R R R R R Bit No.
8-bit Timers 10-20 10.6 Description of Operation This section describes the operation of the 8-bit timers. 10.6.1 Interval Timers and Timer Output When using an 8-bit timer as an interval timer, make the appropriate settings according to the procedure described below.
8-bit Timers 10-21 (6) Enable the timer counting operation. Once TMnCNE is set to "1" in the TMnMD register, the counting operation starts. Once the counting operation is enabled, an underflow interrupt request is generated at fixed intervals.
8-bit Timers 10-22 Fig 10-6-1 Interval Timer Operation Fig 10-6-2 Interval Timer Operation (When Clock Source = IOCLK) TMnBC value TMnBR setting value TMnCNE Interrupt request Timer output x'00 x.
8-bit Timers 10-23 Fig. 10-6-3 Interval Timer Operation (Using Prescaler) Timer output (TMnOUT) x'00 x'01 TMnBR value TMnBR value-1 IOCLK TMnBC value Interrupt request signal (TMnIRQ) Counte.
8-bit Timers 10-24 10.6.2 Event Counting When using an 8-bit timer for event counting, make the settings according to the procedure described below. When using the timers as a 16-, 24- or 32-bit timer by means of a cascaded connection, refer to section 10.
8-bit Timers 10-25 [Note] Pin input is sampled according to IOCLK. Input a signal with a pulse width of at least 6, 3, or 1.5 SYSCLK cycles when (MCLK frequency/SYSCLK frequency) = 1, 2, or 4, respectively. Event counting is not possible when IOCLK is stopped (in HALT or STOP mode).
8-bit Timers 10-26 10.6.3 Cascaded Connection The 8-bit timers can be cascaded together in the combinations shown in Fig. 10-6-5. Fig. 10-6-5 Cascaded Connection When using cascaded 8-bit timers as a .
8-bit Timers 10-27 Make the settings described below when cascading 8-bit timers. (1) Set the timer division ratio. Set the timer division ratio in TMnBR.
8-bit Timers 10-28 (4) Enable counting operation Enable the counting operation by either one of the following two methods: 1) Enable the counting operation for each of the cascaded timers one at a time, in order, starting from the highest timer. 2) Enable the counting operation for all of the cascaded timers simultaneously.
8-bit Timers 10-29 Differences between using a timer as a prescaler and when cascaded The following explanation of these differences uses the cases where the clock source for timer 1 is set to "timer 0 underflow" and to "cascaded with timer 0" as examples.
8-bit Timers 10-30 When "cascaded with timer 0" is set, operation is as shown in Fig. 10-6-7. (IOCLK is selected as the clock source for timer 0.) If TM1BC does not equal x'00, then when TM0BC underflows, the value in TM0BC is x'FF and the value in TM1BC is decremented by one.
8-bit Timers 10-31 10.6.4 PWM Output Make the settings as described below when using an 8-bit timer to output a PWM waveform. (Timers 4 to B) The timers cannot be cascaded when outputting a PWM waveform. ■ Procedure for initiating operation (1) Set the PWM output cycle.
8-bit Timers 10-32 Once the counting operation is enabled, the PWM waveform is output and an underflow interrupt request is generated. (Refer to Fig. 10-6-8 and 10-6-9.
8-bit Timers 10-33 TMnBC value Timer output (TMnOUT) TMnBR value x'00 IOCLK Interrupt request signal (TMnIRQ) (TMnBR value +1) x IOCLK TMnBR value x'00 TMnCMP value x IOCLK TMnCMP value Fig. 10-6-8 PWM Output (When Clock Source = IOCLK, and "L" Level Is Output Upon Initialization) Fig.
8-bit Timers 10-34.
11. 16-bit Timers 11.
16-bit Timers 11-2 11.1 Overview This microcontroller has four 16-bit timers built in. Three are reload timers (down-counters) that can be used as interval timers or event counters. The other is an up-counter that has two compare/capture registers built in.
16-bit Timers 11-3 11.3 Block Diagram Fig. 11-3-1 shows the block diagram for timer 10, and Fig. 11-3-2 shows the block diagram for timers 11 to 13. Fig.
16-bit Timers 11-4 Timer n (n = 11, 12, 13) TMnBR TMnBC CK0 CK1 LDE CNE TMnMD Underflow Reload Load TMnIRQ TMnOUT Underflow interrupt Timer output Counting operation enable Reset Mode register Base register Binary counter — — — T R Q CK2 TMnIN0 TMnIN1 TMnIN2 TMnIN5 TMnIN6 TMnIN7 TMnIN4 Fig.
16-bit Timers 11-5 Fig. 11-3-3 16-bit Timer Connection Diagram Timer 10 overflow interrupt TM10IOA I/O port block TM13IO TM13IN1 TM13IN0 TM13IN4 TM13IN2 Timer 13 TM13IN5 TM13IN7 TM13IN6 TM12IO TM12IN1.
16-bit Timers 11-6 Fig. 11-3-4 shows the block diagram for the timer 10 compare/capture registers. Fig. 11-3-4 Timer 10 Compare/Capture Register Block Diagram Fig. 11-3-5 shows the block diagram for the PWM output section when timer 10 is set to PWM mode with additional bits.
16-bit Timers 11-7 11.4 Functions Table 11-4-1 lists the functions of each 16-bit timer. Table 11-4-1 List of 16-bit Timer Functions Down-counting Timer Interval timer Event counting Toggled output PW.
16-bit Timers 11-8 11.5 Description of Registers Table 11-5-1 lists the 16-bit timer registers. Table 11-5-1 List of 16-bit Timer Registers Address Name Symbol Number of bits Initial value Access size.
16-bit Timers 11-9 Timer 10 mode register Register symbol: TM10MD Address: x'34001080 Purpose: This register controls the operation of timer 10. B i t N o .
16-bit Timers 11-10 Bit No. Bit name Description 7 TM10TGE External trigger start enable flag Enables/disables timer start by an external trigger. 0: Disables timer start by an external trigger. (The trigger input is ignored.) 1: Enables timer start by an external trigger.
16-bit Timers 11-11 Timer n mode register (n = 11, 12, 13) Register symbol: TMnMD Address: x'34001082 (n=11), x'34001084 (n=12), x'34001086 (n=13) Purpose: This register controls the operation of timer n.
16-bit Timers 11-12 Timer n base register (n = 11, 12, 13) Register symbol: TMnBR Address: x'34001092 (n=11), x'34001094 (n=12), x'34001096 (n=13) Purpose: This register sets the initial value and the underflow cycle for the timer n binary counter.
16-bit Timers 11-13 Timer 10 compare/capture A mode register Register symbol: TM10MDA Address: x'340010B0 Purpose: This register controls the operation of the timer 10 compare/capture A register. This register also sets the waveform that is output to the TM10IOA pin.
16-bit Timers 11-14 Timer 10 compare/capture B mode register Register symbol: TM10MDB Address: x'340010B1 Purpose: This register controls the operation of the timer 10 compare/capture B register. This register also sets the waveform that is output to TM10IOB pin.
16-bit Timers 11-15 Timer 10 compare/capture A register Register symbol: TM10CA Address: x'340010C0 Purpose: This is the timer 10 compare/capture A register.
16-bit Timers 11-16 Timer 10 compare/capture B register Register symbol: TM10CB Address: x'340010D0 Purpose: This is the timer 10 compare/capture B register.
16-bit Timers 11-17 Prescaler control register Register symbol: TMPSCNT Address: x'34001071 Purpose: This register controls prescaler operations. B i t N o . 7654321 0 Bit TMPS ––––––– name CNE Reset 0 0 0 0 0 0 0 0 Access R/W R R R R R R R Bit No.
16-bit Timers 11-18 11.6 Description of Operation of Timer 10 This section describes the operation of timer 10. Timer 10 includes an up-counter and two compare/capture registers. The compare/capture registers are independent of each other, and can each be used as either a compare register or a capture register.
16-bit Timers 11-19 Fig. 11-6-1 Compare Register Operation (When Clock Source = IOCLK) 11.6.2 Capture Register Settings In order to use either the timer 10 compare/capture A register or B register as a capture register, the following settings must be made according to the procedure described below before timer 10 is initialized.
16-bit Timers 11-20 If dual-edge was selected, the capture operation is performed when either a rising or falling edge is input. It is not possible to determine which edge was input. (The pin input level cannot be read.) The capture operation can be disabled even while counting is in progress by setting TM10ACE to "0".
16-bit Timers 11-21 11.6.3 Pin Output Settings Timer 10 can be used to output a variety of waveforms to the TM10IOA and TM10IOB pins. (1) Setting the output level upon initialization If the TM10LDE fl.
16-bit Timers 11-22 Examples of TM10IOA pin output waveforms are shown below. Output for the TM10IOB pin is similar. Fig. 11-6-3 shows the output waveform for the TM10IOA pin when "Set when TM10BC matches TM10CA, and reset when TM10BC matches TM10CB" is set.
16-bit Timers 11-23 Fig. 11-6-5 shows the output waveform for the TM10IOA pin when "Set when TM10BC matches TM10CA" is set. Fig. 11-6-5 Pin Output Waveform (3) Fig. 11-6-6 shows the output waveform for the TM10IOA pin when "Reset when TM10BC matches TM10CA" is set.
16-bit Timers 11-24 11.6.4 Starting by an External Trigger Timer 10 can be started up by input on the TM10IOB pin. Fig. 11-6-8 illustrates the startup operation. The compare/capture A and B registers can be used as compare registers or as capture registers.
16-bit Timers 11-25 ■ Procedure for ending operation (1) Disable timer startup by an external trigger. Set TM10TGE in the TM10MD register to "0".
16-bit Timers 11-26 11.6.5 One-shot Operation It is possible to stop timer 10 when TM10BC and TM10CA match. Figs. 11-6-9 and 11-6-10 illustrate the operation that stops timer 10. The compare/capture B register can be used as a compare register or as a capture register.
16-bit Timers 11-27 ■ Procedure for ending operation • When the timer was started by a program (TM10TGE = 0) (1) Stop the counting operation. Set TM10CNE in the TM10MD register to "0". • When the timer was started by an external trigger (TM10TGE = 1) (1) Disable timer startup by an external trigger.
16-bit Timers 11-28 11.6.6 Interval Timer When using timer 10 as an interval timer, make the settings according to the procedure described below. This interval timer generates a compare/capture A interrupt request on the cycle that is set. (Refer to Figs.
16-bit Timers 11-29 If the value in the TM10CA register is changed while the counting operation is in progress, the value in the buffer is loaded into the compare register the next time that TM10BC is cleared, and the interrupt cycle is then changed.
16-bit Timers 11-30 x'0000 x'0001 TM10CA value TM10CA value-1 IOCLK TM10BC value x'0000 x'0001 (TM10CA value + 1) x IOCLK Set value 1 Set value 1 Set value 2 Set value 2 If “double-buffer” is set, the set value is loaded from the buffer at the same time that TM10BC is cleared.
16-bit Timers 11-31 11.6.7 Event Counting When using timer 10 as an event counter, make the settings according to the procedure described below. This event counter generates a compare/capture A interrupt when it has counted the specified number of edges.
16-bit Timers 11-32 Once the counting operation is enabled, TM10BC is incremented each time that the specified edge is input to the TM10IOB pin. Once (value in compare/capture A register + 1) edges are counted, TM10BC is cleared and a compare/capture A register interrupt request is generated.
16-bit Timers 11-33 11.7 Description of Operation of Timers 11, 12, and 13 This section describes the operation of timers 11, 12, and 13. Timers 11, 12, and 13 have built-in registers for setting the initial values, and down-counters. These timers can be used as interval timers and as event counters.
16-bit Timers 11-34 Once the counting operation is enabled, an underflow interrupt request is generated on a regular cycle. In addition, with each interrupt the pin output is inverted and the value in TMnBR is loaded into TMnBC.
16-bit Timers 11-35 Fig. 11-7-2 Interval Timer Operation (When Clock Source = IOCLK) Fig. 11-7-3 Interval Timer Operation (When Using the Prescaler) x'0000 x'0001 TMnBR value TMnBR value -1 .
16-bit Timers 11-36 11.7.2 Event Counting When using timer 11, 12, or 13 as an event counter, make the settings according to the procedure described below. ■ Procedure for initiating operation (1) Set the timer division ratio. Set the division ratio in TMnBR.
16-bit Timers 11-37 [Note] The pin input is sampled according to IOCLK. Input a signal with a pulse width of at least 6, 3, or 1.5 SYSCLK cycles when (MCLK frequency/SYSCLK frequency) = 1, 2, or 4, respectively. Also note that event counting is not possible when IOCLK is stopped (in HALT or STOP mode).
16-bit Timers 11-38.
12. Watchdog Timer 11 12.
Watchdog Timer 12-2 12.1 Overview This microcontroller has a 25-bit binary counter built in that can be used as a 16- to 25-bit watchdog timer. A watchdog timer overflow generates a nonmaskable interrupt, enabling the watchdog timer overflow to be identified.
Watchdog Timer 12-3 OSCI RST wdovf S Q R Level output/Pulse output selection Oscillation stabilization wait release, interrupt request Reset 1/2 8 1/2 10 1/2 12 1/2 14 1/2 16 STOP mode WDBC WDCTR CKSE.
Watchdog Timer 12-4 12.4 Description of Registers Table 12-4-1 lists the watchdog timer registers. Table 12-4-1 List of Watchdog Timer Registers Address Name Symbol Number of bits Initial value Access.
Watchdog Timer 12-5 Watchdog timer control register Register symbol: WDCTR Address: x'34004008 Purpose: This register sets the watchdog timer operation control conditions. Bit No. 7 6 543210 Bit WD WD WD WD - WD WD WD name CNE RST OVT OVF CK2 CK1 CK0 Reset 0 0 000001 Access R/W R/W R/W R R R/W R/W R/W Bit No.
Watchdog Timer 12-6 3 — When this bit is read, a "0" is returned. 4 WDOVF The value of the watchdog timer overflow output. 5 WDOVT Watchdog timer overflow output selection 0: Pulse output .
Watchdog Timer 12-7 12.5 Description of Operation Oscillation stabilization wait operation The watchdog timer operates as an oscillation stabilization wait timer after the reset state is released or when the microcontroller recovers from STOP mode (Fig.
Watchdog Timer 12-8 Fig. 12-5-2 Operation Diagram 2: When Recovering from STOP Mode Interrupt Stop mode release request (external pin interrupt) Overflow 4.
Watchdog Timer 12-9 Watchdog operation If the WDCNE flag is set to "1" and the watchdog operation is enabled, a non-maskable interrupt is generated if a watchdog timer overflow occurs. When an overflow occurs, the watchdog timer overflow output is output to the WDOVF flag.
Watchdog Timer 12-10.
13. Serial Interface 13.
Serial Interface 13-2 13.1 Overview This microcontroller has three types of internal serial interfaces. One is a general-purpose serial interface for which clock synchronous mode, UART mode, or I2C mode can be specified; this interface supports one channel.
Serial Interface 13-3 13.2 General-purpose serial interface 13.2.1 Features Serial interface 0 is a general-purpose serial interface for which clock sync mode, UART mode, or I2C mode can be specified.
Serial Interface 13-4 <UART mode> • Parity None, 0 fixed, 1 fixed, even, odd • Character length 7 bits, 8 bits • Transmission and reception bit sequence LSB or MSB selectable • Clock source 1/8 or 1/32 of IOCLK 1/8 of timer 3 or timer 9 underflow 1/8 of external clock • Maximum bit rate 19.
Serial Interface 13-5 13.2.2 Block Diagram of General-Purpose Serial Interface Fig 13-2-1 shows the block diagram for the general-purpose serial interface section.
Serial Interface 13-6 13.2.3 Description of Registers for the General-Purpose Serial Interface The general-purpose serial interface includes the registers listed in Table 13-2-1. These registers are used for settings such as clock source selection, parity bit selection, and protocol selection.
Serial Interface 13-7 6 SC0PB2 Parity bit selection (MSB) 000: None 001, 010, 011: Setting prohibited 100: 0 fixed 101: 1 fixed 110: Even (even number of ones) 111: Odd (odd number of ones) 7 SC0CLN C.
Serial Interface 13-8 Serial 0 interrupt mode register Register symbol: SC0ICR Address: x'34000804 Purpose: This register selects the sources for transmission interrupts and reception interrupts for serial interface 0.
Serial Interface 13-9 Serial 0 reception buffer Register symbol: SC0RXB Address: x'34000809 Purpose: This register reads in the reception data of serial interface 0.
Serial Interface 13-10 13.2.4 Description of Operation <Clock synchronous mode> ■ Clock synchronous mode connection Two different connection methods are possible, one for unidirectional transfer, and the other for bi-directional transfer.
Serial Interface 13-11 ■ Clock synchronous mode timing <Transmission> • One-byte transfer with 8-bit data length and parity on Fig. 13-2-3 Timing Chart (1) • Two-byte transfer with 8-bit data length and parity off Fig. 13-2-4 Timing Chart (2) When transmission is enabled, transmission starts when data is written to SC0TXB.
Serial Interface 13-12 <Reception> • One-byte transfer with 8-bit data length and parity on Fig. 13-2-5 Timing Chart (3) • Two-byte transfer with 8-bit data length and parity off Fig. 13-2-6 Timing Chart (4) After reception end (when the SC0RBF flag is "1"), the received data is fetched by reading the SC0RXB.
Serial Interface 13-13 ■ When a reception error is generated • Transfer in clock synchronous mode with 8-bit data length, parity on. Fig. 13-2-7 Timing Chart (5) When "reception end" is set as the reception interrupt source, an interrupt request is generated when reception ends, regardless of whether or not an error occurred.
Serial Interface 13-14 SBO SBI SBT SBO SBI SBT SBO SBI SBO SBI SBT SBT Reception Transmission Transmission/ reception Transmission/ reception External clock External clock Bi-directional transfer Undi.
Serial Interface 13-15 Table 13-2-2 Bit rates (1) (When IOCLK = 15 MHz) Bit rate (bit/s) When cascaded When using prescalers Timer division ratio Bit rate error Timer division ratio Bit rate error 19 200 98 0.35 % Not using — 9 600 195 0.16 % Not using — 4 800 391 0.
Serial Interface 13-16 ■ UART mode timing <Transmission> • Transfer with 8-bit data length, parity on, and 1 stop bit Fig. 13-2-9 Timing Chart (6) • Two-byte transfer with 7-bit data length, parity on, and 1 stop bit Fig. 13-2-10 Timing Chart (7) When transmission is enabled, transmission starts when data is written to SC0TXB.
Serial Interface 13-17 <Reception> • Transfer with 8-bit data length, parity on, and 1 stop bit Fig. 13-2-11 Timing Chart (8) • Two-byte transfer with 7-bit data length, parity on, and 1 stop bit Fig. 13-2-12 Timing Chart (9) After reception end (when the SC0RBF flag is "1"), the received data is fetched by reading the SC0RXB.
Serial Interface 13-18 ■ When a reception error is generated • Transfer in UART mode with 8-bit data length, parity on, and 1 stop bit Fig. 13-2-13 Timing Chart (10) When "reception end" is set as the reception interrupt source, an interrupt request is generated when reception ends, regardless of whether or not an error occurred.
Serial Interface 13-19 <I2C mode> ■ I2C mode connection It is possible to connect a device that is capable of slave transmission and slave reception. SDA and SCL require pull-up resistors. Connect pull-up resistors externally. The SBO pin is an open-drain input/output, and the SBT pin is an open drain output.
Serial Interface 13-20 ■ I2C mode transmission/reception The transmission/reception procedure in I2C mode is described below. (Refer to Fig. 13-2-15.) • Make the initial settings as described below. (1) I/O port setting Set the SBT and SBO pins as general-purpose input ports.
Serial Interface 13-21 • Perform data transmission/reception (B) according to the procedure described below: (1) Ack setting "Ack" is represented by the parity bits.
Serial Interface 13-22 If the above procedures do not satisfy the AC timing of the device that is connected, send the stop sequence according to the procedure described below. (1)' SBT pin setting Set the SBT pin as a general-purpose input port. When the pin switches to a general-purpose input port, SCL goes high.
Serial Interface 13-23 • Resend the start sequence (D) according to the procedure described below. (Refer to Fig. 13-2-16.) (1) SBO pin setting Set the SBO pin as a general-purpose input port. When the pin switches to a general-purpose input port, SDA goes high.
Serial Interface 13-24 13.3 Clock Synchronous Serial Interface 13.3.1 Features Serial interfaces 1 and 2 are clock synchronous serial interfaces. Their features are described below.
Serial Interface 13-25 13.3.2 Block Diagram of Clock Synchronous Serial Interface Fig 13-3-1 shows the block diagram for the clock synchronous serial interface sections.
Serial Interface 13-26 13.3.3 Description of Registers for the Clock Synchronous Serial Interface The clock synchronous serial interfaces include the registers listed in Table 13-3-1. These registers are used for settings such as clock source selection, parity bit selection, and protocol selection.
Serial Interface 13-27 Serial n control register (n = 1, 2) Register symbol: SCnCTR Address: x'34000810 (n =1), x'34000820 (n =2) Purpose: This register sets the serial interface n operation control conditions.
Serial Interface 13-28 Bit No. Bit name Description 8 SCnTOE SBTn pin output control 0: When the internal clock is selected, the SBTn pin is an output only while transmission is in progress (the SBTn .
Serial Interface 13-29 Serial n interrupt mode register (n = 1, 2) Register symbol: SCnICR Address: x'34000814 (n = 1), x'34000824 (n = 2) Purpose: T his re g ister selects the sources for transmission interrupts and reception interrupts for serial interface n.
Serial Interface 13-30 Serial n transmission buffer (n = 1, 2) Register symbol SCnTXB Address: x'34000818 (n=1), x'34000828 (n=2) Purpose: This register writes the transmission data to serial interface n.
Serial Interface 13-31 Serial n status register (n=1,2) Register symbol: SCnSTR Address: x'3400081C (n=1), x'3400082C (n=2) Purpose: This register indicates the status of serial interface n. B i t N o . 7654321 0 Bit SCn SCn SCn SCn –– SCn SCn name TXF RXF TBF RBF PEF OEF Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit No.
Serial Interface 13-32 SBO SBI SBT Transmission SBO SBI SBT Reception SBO SBI SBT Transmission/ reception SBO SBI SBT Transmission/ reception Unidirectional transfer Bi-directional transfer (SCnMD0 = “0”) n = 1 or 2 SBO SBI SBO SBI Bi-directional transfer (SCnMD0 = “1”) n = 1 or 2 SBT SBT Transmission/ reception Transmission/ reception 13.
Serial Interface 13-33 ■ Clock synchronous serial interface timing <Transmission> • One-byte transfer with 8-bit data length and parity off Fig. 13-3-3 Timing Chart (13) • Two-byte transfer with 7-bit data length and parity on Fig. 13-3-4 Timing Chart (14) When transmission is enabled, transmission starts when data is written to SCnTXB.
Serial Interface 13-34 <Reception> • One-byte transfer with 7-bit data length and parity on Fig. 13-3-5 Timing Chart (15) • Two-byte transfer with 8-bit data length and parity on Fig. 13-3-6 Timing Chart (16) After reception end (when the SCnRBF flag = “1”), the received data is fetched by reading the SCnRXB.
Serial Interface 13-35 ■ When a reception error is generated • Transfer with 7-bit data length, parity on Fig. 13-3-7 Timing Chart (17) When "reception end" is set as the reception interrupt source, an interrupt request is generated when reception ends, regardless of whether or not an error occurred.
Serial Interface 13-36 13.4 Universal Asynchronous Receiver-Transceiver Serial Interface 13.4.1 Features Serial interface 3 is a UART serial interface.
Serial Interface 13-37 13.4.2 Block Diagram of UART Serial Interface Fig 13-4-1 shows the block diagram for the UART serial interface sections. Fig. 13-4-1 Block Diagram Transmission buffer Shift regi.
Serial Interface 13-38 13.4.3 Description of Registers for the UART Serial Interface The UART serial interface includes the registers listed in Table 13-4-1. These registers are used for settings such as clock source selection, parity bit selection, and protocol selection.
Serial Interface 13-39 Serial 3 control register Register symbol: SC3CTR Address: x'34000830 Purpose: This register sets the serial interface 3 operation control conditions.
Serial Interface 13-40 Bit No. Bit name Description 8 SC3TWE Transmission interrupt enable 0: Interrupt disable 1: Interrupt enable 9 SC3OD Transmission and reception bit sequence selection 0: From LS.
Serial Interface 13-41 Serial 3 interrupt mode register Register symbol: SC3ICR Address: x'34000834 Purpose: This register selects the sources for transmission interrupts and reception interrupts for serial interface 3.
Serial Interface 13-42 Serial 3 transmission buffer Register symbol: SC3TXB Address: x'34000838 Purpose: This register writes the transmission data of serial interface 3.
Serial Interface 13-43 Serial 3 status register Register symbol: SC3STR Address: x'3400083C Purpose: This register indicates the status of serial interface 3. Bit No. 7 6 543210 Bit SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 name TXF RXF TBF RBF CTS FEF PEF OEF Reset 0 0 000000 Access RRRRRRRR Bit No.
Serial Interface 13-44 Serial 3 timer register Register symbol: SC3TIM Address: x'3400083D Purpose: This register sets the timer that is used for internal division for serial interface 3.
Serial Interface 13-45 13.4.4 Description of Operation ■ UART Serial Interface connection Two different connection methods are possible, one for unidirectional transfer, and the other for bi-directional transfer. The SBO pin is always an output, and the SBI pin is always an input.
Serial Interface 13-46 Division ratio 1 = INT (IOCLK frequency / bit rate/127) + 1 Division ratio 2 = INT (IOCLK frequency / bit rate/division ratio 1 + 0.5) Subtract 1 from the value for division ratio 2 that was derived through the above equations, and write the result in SC3TIM.
Serial Interface 13-47 Table 13-4-3 Bit Rates (2) (When IOCLK = 12 MHz) Bit rate (bit/s) Division ratio 1 Division ratio 2 Bit rate error 230 400 1 52 0.16 % 115 200 1 104 0.16 % 56 000 2 107 0.13 % 38 400 3 104 0.16 % 19 200 5 125 0.00 % 9 600 10 125 0.
Serial Interface 13-48 [Notes on Usage] 1 Set SC3CTR before setting the other registers, and do not change the setting while transmitting or receiving, or while there is data in the transmission buffer. Operation is not guaranteed if the setting of the SC3CTR register is changed.
Serial Interface 13-49 ■ UART Serial Interface timing <Transmission> • Transfer with 7-bit data length, parity off, and 2 stop bit Fig. 13-4-3 Timing Chart (18) • Two-byte transfer with 8-bit data length, parity off, and 1 stop bit Fig.
Serial Interface 13-50 <Reception> • Transfer with 7-bit data length, parity on, and 2 stop bit Fig. 13-4-5 Timing Chart (20) • Two-byte transfer with 8-bit data length, parity off, and 1 stop bit Fig. 13-4-6 Timing Chart (21) After reception end (when the SC3RBF flag is "1"), the received data is fetched by reading the SC3RXB.
Serial Interface 13-51 ■ When a reception error is generated • Transfer with 7-bit data length, parity on, and 2 stop bit Fig. 13-4-7 Timing Chart (22) When "reception end" is set as the reception interrupt source, an interrupt request is generated when reception ends, regardless of whether or not an error occurred.
Serial Interface 13-52.
14. A/D Converter 14.
A/D Converter 14-2 AN0 AN1 AN2 AN3 S/H AD3BUF AD2BUF AD1BUF AD0BUF VREFH ADTRG 10-bit sequential comparison A/D converter Selector 14.1 Overview The A/D converter is a 10-bit charge redistribution-type A/D converter that can process analog signals on a maximum of four channels.
A/D Converter 14-3 14.2 Features • S/H Built in • Conversion accuracy 10 bits ± 5 LSB (Linearity error) The value of VREFH divided into 1024 steps is stored in AD0BUF to AD3BUF. • Conversion reference clock Selectable from 1/2, 1/4, 1/8, or 1/16 of IOCLK Set this parameter so that one cycle is at least 200 ns.
A/D Converter 14-4 14.3 Block Diagram Fig. 14-3-1 The Block Diagram of A/D Converter VREFH 1 2 4 8 16 32 64 128 256 512 ADCTR ADnBUF INC IOCLK 1 AN0 AN1 AN2 AN3 ADTRG Selector Data buffer 10 bit x 4 c.
A/D Converter 14-5 14.4 Description of Registers Table 14-4-1 lists the registers for this A/D converter. Table 14-4-1 A/D Register List Address Name Symbol Number of bits Initial value Access size x&.
A/D Converter 14-6 7 ADEN Conversion start/execution flag (conversion can be started by writing a "1" to this flag) 0: Conversion stopped 1: Conversion start/in progress 8 ADSC0 Selection of.
A/D Converter 14-7 14.5 Description of Operation ■ Operating mode selection (1) Any one channel/one-time conversion If "any one channel/one-time conversion" is selected as the operating mode (ADMD1 to 0), one AN input is converted one time only.
A/D Converter 14-8 (2) Multiple channels/one-time conversion for each channel If "multiple channels/one-time conversion for each channel" is selected as the operating mode (ADMD1 to 0), a number of AN inputs, starting from AN0, are converted one time only.
A/D Converter 14-9 (3) Any one channel/continuous conversion If "any one channel/continuous conversion" is selected as the operating mode (ADMD1 to 0), one AN input is converted continuously. Set the conversion channel in the conversion channel selection bits (ADSC1 to 0).
A/D Converter 14-10 (4) Multiple channels/continuous conversion If "multiple channels/continuous conversion" is selected as the operating mode (ADMD1 to 0), a number of AN inputs, starting from AN0, are converted continuously.
A/D Converter 14-11 S/H bp9 bp8 bp7 bp6 bp5 bp4 bp3 bp2 bp1 bp0 S/H bp9 bp8 bp7 bp6 bp5 bp4 bp3 bp2 bp1 bp0 S/H 16 (= 12 +4) cycles ADEN flag Conversion reference clock Status One-time conversion Cont.
A/D Converter 14-12 [Notes] If a falling edge is input to the ADTRG pin before the conversion start trigger selection (ADST1 to 0) is switched to "external trigger" ("01"), the ADEN flag is set at the same time that the switch is made, and A/D conversion starts.
15. I/O Ports 15.
I/O Ports 15-2 15.1 Overview The MN103001G and MN1030F01K have a total of 13 internal I/O ports: 0 to 9, A, B and C. These ports can all be accessed by programs as internal I/O memory space.
I/O Ports 15-3 Port 7 (P7) This port is also used for address bus signal A23; DRAM RAS signals RAS2 and RAS1; and chip select signals CS3 to CS0. Port 8 (P8) This port is also used for analog signal inputs AN3 to AN0 and external interrupt inputs IRQ7 to I RQ4.
I/O Ports 15-4 The I/O ports are provided with the registers listed in Table 15-1-1. Table 15-1-1 List of Registers (1/2) Address Name Symbol Number of bits Initial value Access size x'36008000 P.
I/O Ports 15-5 Table 15-1-1 List of Registers (2/2) Address Name Symbol Number of bits Initial value Access size x'36008081 Port 1 pin register P1IN 8 x'XX 8 x'36008084 Port 2 pin regis.
I/O Ports 15-6 15.2 Port 0 15.2.1 Block Diagram Fig. 15-2-1 and Fig 15-2-2 show block diagrams for port 0. Fig. 15-2-1 Port 0 Block Diagram (P02) Internal data bus P02 P0OUT P02O P.
I/O Ports 15-7 Fig. 15-2-2 Port 0 Block Diagram (P01, P00) 15.2.2 Register Descriptions Port 0 is a general-purpose output port that is also used for address bus A [22:20], DRAM CAS signal CAS.
I/O Ports 15-8 Port 0 output mode register Register symbol: P0MD Address: x'36008020 Purpose: This register selects the content output on the port 0 pins with P0SS.
I/O Ports 15-9 15.2.3 Pin Configurations Table 15-2-1 shows the pin configurations for port 0. Table 15-2-1 Port 0 Configuration Port Pin P0n P0nMD = "1" P0nMD = "0" No.
I/O Ports 15-10 15.3 Port 1 15.3.1 Block Diagram Figs. 15-3-1 and 15-3-2 show block diagrams for port 1. Fig. 15-3-1 Port 1 Block Diagram (P17 to P12) Internal data bus M P X P1n (n=7,6,5,4,3,2) P1OUT D7(n=7) to D2(n=2) P1M P1MD P1DIR P1nD P1nO P... Represents one bit of each register.
I/O Ports 15-11 Fig. 15-3-2 Port 1 Block Diagram (P11, and P10) Internal data bus M P X P1OUT P1nO D1(n=1), D0(n=0) P1M P1MD P1DIR P1nD P... Represents one bit of each register.
I/O Ports 15-12 15.3.2 Register Descriptions Port 1 is a general-purpose input/output port that is also used for data bus signals D[7:0], address strobe signal AS, and read/write select RWSEL.
I/O Ports 15-13 Port 1 input/output control register Register symbol: P1DIR Address: x'36008061 Purpose: This register sets the port 1 pins for input or output.
I/O Ports 15-14 15.3.3 Pin Configurations Table 15-3-1 shows the pin configurations for port 1. Table 15-3-1 Port 1 Configuration Port Pin P1n P1M = "1" P1M = "0" No.
I/O Ports 15-15 15.4 Port 2 15.4.1 Block Diagram Figs. 15-4-1 shows a block diagrams for port 2. Fig. 15-4-1 Port 2 Block Diagram (P27 to P20) Internal data bus M P X P2n (n=7,6,5,4,3,2,1,0) P2OUT D15(n=7) to D8(n=0) P2M P2MD P2DIR P2nD P2nO P... Represents one bit of each register.
I/O Ports 15-16 15.4.2 Register Descriptions Port 2 is a general-purpose input/output port that is also used for data bus signals D[15:8]. Each register for port 2 is described below. Port 2 output register Register symbol: P2OUT Address: x'36008004 Purpose: This register sets the data to be output on port 2.
I/O Ports 15-17 Port 2 input/output control register Register symbol: P2DIR Address: x'36008064 Purpose: This register sets the port 2 pins for input or output.
I/O Ports 15-18 15.4.3 Pin Configurations Table 15-4-1 shows the pin configurations for port 2. Table 15-4-1 Port 2 Configuration Port Pin P2n P2M = "1" P2M = "0" No.
I/O Ports 15-19 15.5 Port 3 15.5.1 Block Diagram Fig. 15-5-1 shows a block diagram for port 3. Fig. 15-5-1 Port 3 Block Diagram (P30) Internal data bus M P X P30 P3OUT P3M P3MD P3DIR P30D P30O P.
I/O Ports 15-20 15.5.2 Register Descriptions Port 3 is a general-purpose input/output port that is also used for the bus grant signal BG. Each register for port 3 is described below. Port 3 output register Register symbol: P3OUT Address: x'36008005 Purpose: This register sets the data to be output on port 3.
I/O Ports 15-21 Port 3 output mode register Register symbol: P3MD Address: x'36008025 Purpose: This register selects the content output on the port 3 pin.
I/O Ports 15-22 15.6 Port 4 15.6.1 Block Diagram Figs. 15-6-1 to 15-6-4 show block diagrams for port 4. Fig. 15-6-1 Port 4 Block Diagram (P45 and P43) P4n (n=5,3) Internal data bus P4OUT P4nI P4IN P4nM P4MD P4DIR P4nD P4nO P... Represents one bit of each register.
I/O Ports 15-23 Fig. 15-6-2 Port 4 Block Diagram (P44) Internal data bus P44 P4OUT P44I P4IN P44M P4MD P4DIR P44D P44O P... Represents one bit of each register.
I/O Ports 15-24 Fig. 15-6-3 Port 4 Block Diagram (P42, P40) Fig. 15-6-4 Port 4 Block Diagram (P41) Internal data bus P4n (n=2,0) P4OUT P4DIR P4nD P4nO P... Represents one bit of each register. M P X M P X P4nI P4IN P4nM P4MD SBO0(n=2), SBT0(n=0) SBO0 output enable(n=2), SBT0 output enable (n=0) SBO0(n=2), SBT0(n=0) Internal data bus P.
I/O Ports 15-25 15.6.2 Register Descriptions Port 4 is a general-purpose input/output port that is also used for serial interface input/output signals SBI1, SBO1, SBT1, SBI0, SBO0, and SBT0; the DRAM CAS signals (for 2CAS) DCAS1 and DCAS0; and the DRAM write signal (for 2CAS) DWE.
I/O Ports 15-26 Port 4 input/output control register Register symbol: P4DIR Address: x'36008068 Purpose: This register sets the port 4 pins for input or output.
I/O Ports 15-27 Port 4 dedicated output control register Register symbol: P4SS Address: x'36008048 Purpose: Along with P4MD, this register selects the content output on the port 4 pins.
I/O Ports 15-28 15.6.3 Pin Configurations Table 15-6-1 shows the pin configurations for port 4. Table 15-6-1 Port 4 Configuration Port Pin P4n P4nM = "1" P4nM = "0" No.
I/O Ports 15-29 15.7 Port 5 15.7.1 Block Diagram Figs. 15-7-1 to 15-7-5 show block diagrams for port 5. Fig. 15-7-1 Port 5 Block Diagram (P55) Internal data bus P5OUT P55O TM13IO M P X P55 M P X P.
I/O Ports 15-30 Fig. 15-7-2 Port 5 Block Diagram (P54) Internal data bus P5OUT P54O TM12IO M P X P54 M P X P... Represents one bit of each register. P54I P5IN TM12IO/TM4IO/SBI3 TM4IO P5DIR P54D M P X .
I/O Ports 15-31 Fig. 15-7-3 Port 5 Block Diagram (P53) Internal data bus P5OUT P53O TM11IO M P X P53 M P X P... Represents one bit of each register. P53I P5IN TM11IO/TM3IO/SBT3 TM3IO P5DIR P53D M P X .
I/O Ports 15-32 Fig. 15-7-4 Port 5 Block Diagram (P52, P50) P5n (n=2,0) Internal data bus P5OUT P5DIR P5nD P5nO P... Represents one bit of each register.
I/O Ports 15-33 Fig. 15-7-5 Port 5 Block Diagram (P51) Internal data bus TM1IO P5OUT P51O M P X TM1IO/SBI2 P51 P... Represents one bit of each register.
I/O Ports 15-34 15.7.2 Register Descriptions Port 5 is a general-purpose input/output port that is also used for the serial interface input/output signals SBI3, SBO3, SBT3, SBI2, SBO2, SBT2; and the timer input/output signals TM13IO, TM12IO, TM11IO, TM5IO, TM4IO, TM3IO, TM2IO, TM1IO, and TM0IO.
I/O Ports 15-35 P ort 5 input/output control register Register symbol: P5DIR Address: x'36008069 Purpose: This register sets the port 5 pins for input or output.
I/O Ports 15-36 Port 5 dedicated output control register Register symbol: P5SS Address: x'36008049 Purpose: Along with P5MD, this register selects the content output on the port 5 pins.
I/O Ports 15-37 15.7.3 Pin Configurations Table 15-7-1 shows the pin configurations for port 5. Table 15-7-1 Port 5 Configuration Port Pin P5n P5nM = "1" P5nM = "0" No.
I/O Ports 15-38 15.8 Port 6 15.8.1 Block Diagram Figs. 15-8-1 shows the block diagrams for port 6. Fig. 15-8-1 Port 6 Block Diagram (P63 to P60) Internal data bus P6OUT P6nO M P X P6n (n=3,2,1,0) P6DIR P6nD P.
I/O Ports 15-39 15.8.2 Register Descriptions Port 6 is a general-purpose input/output port that is also used for external interrupt inputs IRQ3 to IRQ0; the timer input/output signals TM6IO, TM7IO, TM10IOA, TM10IOB; and the A/D conversion trigger input ADTRG.
I/O Ports 15-40 Port 6 output mode register Register symbol: P6MD Address: x'3600802C Purpose: This register selects the content output on the port 6 pins. Bit No. 76543210 Bit name ---- P63M P62M P61M P60M Reset 00001111 Access RRRR R / W R / W R / W R / W When P6nM is "0", the timer input/output signal is selected.
I/O Ports 15-41 15.9 Port 7 15.9.1 Block Diagram Fig. 15-9-1 and Fig. 15-9-2 show block diagrams for port 7. Fig. 15-9-1 Port 7 Block Diagram (P73) Fig. 15-9-2 Port 7 Block Diagram (P72 to P70) Internal data bus P7OUT P7nO M P X P7n (n=2,1,0) P7MD P..
I/O Ports 15-42 15.9.2 Register Descriptions Port 7 is a general-purpose output port that is also used for address bus signal A23, DRAM RAS signals RAS2 and RAS1, chip select signals CS3 to CS0.
I/O Ports 15-43 Port 7 dedicated output control register Register symbol: P7SS Address: x'3600804D Purpose: This register selects the content output on the port 7 pins.
I/O Ports 15-44 15.9.3 Pin Configurations Table 15-9-1 shows the pin configurations for port 7. Table 15-9-1 Port 7 Configuration Port Pin P7n P7nM = "1" P7nM = "0" No.
I/O Ports 15-45 15.10 Port 8 15.10.1 Block Diagram Figs. 15-10-1 shows the block diagrams for port 8. Fig. 15-10-1 Port 8 Block Diagram (P83 to P80) Internal data bus P8n (n=3,2,1,0) P.
I/O Ports 15-46 15.10.2 Register Descriptions Port 8 is a general-purpose input port that is also used for analog signal inputs AN3 to AN0 and external interrupt inputs IRQ7 to IRQ4.
I/O Ports 15-47 15.10.3 Pin Configurations Table 15-10-1 shows the pin configurations for port 8. Table 15-10-1 Port 8 Configuration Port Pin No. P8n P8nA = "0" P8nA = "1" Port 8 4.
I/O Ports 15-48 15.11 Port 9 15.11.1 Block Diagram Fig. 15-11-1 to Fig. 15-11-4 show block diagrams for port 9. Fig. 15-11-1 Port 9 Block Diagram (P97) Fig. 15-11-2 Port 9 Block Diagram (P96) Internal data bus P9OUT P97O M P X P97 P... Represents one bit of each register.
I/O Ports 15-49 Fig. 15-11-3 Port 9 Block Diagram (P95, P91, P90) Fig. 15-11-4 Port 9 Block Diagram (P94, P93, P92) Internal data bus P... Represents one bit of each register. P9OUT P9nO P9n (n=5,1,0) P9DIR P9nD P9nI P9IN P9nM P9MD DK (n=5), EXMOD1 (n=1), EXMOD0 (n=0) Internal data bus P9OUT P9nO M P X P9n (n=4,3,2) P9MD P.
I/O Ports 15-50 15.11.2 Register Descriptions Port 9 is also used for extension mode setting signals EXMOD1 and EXMOD0; memory write signals WE1 and WE0; memory read signal RE; bus authority request signal BR; data acknowledge signal DK; and system clock SYSCLK.
I/O Ports 15-51 Port 9 output mode register Register symbol: P9MD Address: x'36008031 Purpose: This register selects the content output on the port 9 pins.
I/O Ports 15-52 15.11.3 Pin Configurations Table 15-11-1 shows the pin configurations for port 9. Table 15-11-1 Port 9 Configuration Port Pin P9n P9nM = "1" P9nM = "0" No.
I/O Ports 15-53 15.12 Port A 15.12.1 Block Diagram Fig. 15-12-1 shows a block diagram for port A. Fig. 15-12-1 Port A Block Diagram (PA7 to PA0) Internal data bus M P X PAn (n=7,6,5,4,3,2,1,0) PAOUT A7(n=7) to A0(n=0) PAM PAMD PADIR PAnD PAnO P... Represents one bit of each register.
I/O Ports 15-54 15.12.2 Register Descriptions Port A is a general-purpose input/output port that is also used for address bus signals A[7:0], and address/ data signals ADM[7:0].
I/O Ports 15-55 Port A input/output control register Register symbol: PADIR Address: x'36008074 Purpose: This register sets the port A pins for input or output.
I/O Ports 15-56 15.12.3 Pin Configurations Table 15-12-1 shows the pin configurations for port A. Table 15-12-1 Port A Configuration Port Pin PAn PAM = "1" PAM = "0" No.
I/O Ports 15-57 15.13 Port B 15.13.1 Block Diagram Fig. 15-13-1 shows a block diagram for port B. Fig. 15-13-1 Port B Block Diagram (PB7 to PB0) Internal data bus M P X PBn (n=7,6,5,4,3,2,1,0) PBOUT A15 (n=7) to A8 (n=0) PBM PBMD PBDIR PBnD PBnO P... Represents one bit of each register.
I/O Ports 15-58 15.13.2 Register Descriptions Port B is a general-purpose input/output port that is also used for address bus signals A[15:8], and address/ data signals ADM[15:8].
I/O Ports 15-59 Port B input/output control register Register symbol: PBDIR Address: x'36008075 Purpose: This register sets the port B pins for input or output.
I/O Ports 15-60 15.13.3 Pin Configurations Table 15-13-1 shows the pin configurations for port B. Table 15-13-1 Port B Configuration Port Pin PBn PBM = "1" PBM = "0" No.
I/O Ports 15-61 15.14 Port C 15.14.1 Block Diagram Fig. 15-14-1 shows a block diagram for port C. Fig. 15-14-1 Port C Block Diagram (PC3 to PC0) Internal data bus M P X PCn (n=3,2,1,0) PCOUT PCnM PCMD PCnO M P X A23 to A16 Output enable signal A19 (n=3) to A16(n=0) P.
I/O Ports 15-62 15.14.2 Register Descriptions Port C is a general-purpose output port that is also used for address bus signals A[19:16]. Each register for port C is described below. Port C output register Register symbol: PCOUT Address: x'36008018 Purpose: This register sets the data to be output on port C.
I/O Ports 15-63 15.14.3 Pin Configurations Table 15-14-1 shows the pin configurations for port C. Table 15-14-1 Port C Configuration Port Pin No. PCn PCnM = "1" PCnM = "0" Port C 5.
I/O Ports 15-64 15.15 Treatment of Unused Pins Unused pins should be treated as shown in Table 15-15-1 below. Table 15-15-1 Treatment of Unused Pins Pin name Treatment Set as port and leave open.
16. Internal Flash Memory 16.
Internal Flash Memory 16-2 16.1 Overview The MN1030F01K has 256 KB of internal flash memory for use as instruction memory in place of instruction ROM. Using flash memory makes it easy to make changes to a stored program, which makes it possible to reduce program development time and permits the creation of a highly flexible system.
Internal Flash Memory 16-3 16.4 Flash Memory Overwrite Mode and Settings There are two flash memory overwrite modes: flash memory mode and on-board write mode. Table 16-4-1 lists the mode settings through the external pins. Flash memory mode is used to overwrite the internal flash memory with a ROM writer.
Internal Flash Memory 16-4 16.5 Flash Memory Mode 16.5.1 Description of External Pins Fig. 16-5-1 and Table 16-5-1 show the pin assignments for the MN1030F01K in flash memory mode.
Internal Flash Memory 16-5 Table 16-5-1 MN1030F01K Pin Assignments I: Input; O: Output; I/O: Input/output; H: High level input; L: Low level input Pin No.
Internal Flash Memory 16-6 Table 16-5-2 lists the functions of the external pins in flash memory mode. Table 16-5-2 Pin Functions When first applying power, it is necessary to input a signal that is low for at least 1 ms to the reset pin NROMRST.
Internal Flash Memory 16-7 16.5.2 Erasure Blocks The flash memory is partitioned into 32 8 KB erasure blocks. Fig. 16-5-2 shows the configuration of the flash memory erasure blocks and their correspondence with each of the bits in the erasure block registers that are used to specify which blocks to erase.
Internal Flash Memory 16-8 16.6 On-board Write Mode In on-board write mode, flash memory is overwritten by manipulating the control registers through software.
17 17. Ordering Mask ROM.
Ordering Mask ROM 17-2 17.1 Overview This chapter describes the procedure for ordering mask ROM. This chapter also describes the difference in programming when using a product that has on-chip flash memory versus a mask product, and explains how to order ROM, etc.
Ordering Mask ROM 17-3 Fig. 17-2-2 ROM Ordering Method 2 x'40000000 x'40000000 x'40002000 User program User program Loader program 8 KB x'40002000 x'40000008 JMP x'400020.
Ordering Mask ROM 17-4.
Appendix.
Appendix Appendix-2 Appendix A. Register Map List 0 IVAR0 MEMCTR0B MEMCTR1B MEMCTR2B MEMCTR3B x'3200004X x'3200400X x'3400010X x'3400011X x'3400012X x'3400014X G3ICR G2IC.
Appendix Appendix-3 TMOSL TM10 MDA TM0 MD TM0 BR TM0 BC SC1CTR SC0CTR x'3400080X x'3400082X x'3400083X x'3400081X SC3CTR SC2CTR SC0 ICR SC1 ICR SC2 ICR SC3 ICR SC0 TXB SC1 TXB SC2 .
Appendix Appendix-4 F E D C B A 9 8 7 6 5 4 3 2 1 0 x'3600800X Address I/O port P1OUT P9OUT P0MD P1MD P8AD P0SS P1DIR P8IN P9IN P9DIR x'3600801X x'3600802X x'3600803X x'360080.
Appendix Appendix-5 Appendix B. Instruction Set List of Instructions ( Code Length, Execution Cycle*) Execution cycle is defined under the following conditions: (1) No pipeline hazard (2) 2-cycle of i.
Appendix Appendix-6 Instruction Source Destination Format Remarks MOVBU MOVBU ( A m ) Dn D0 2 1 MOVBU (d8,Am) D n D 1 3 1 MOVBU (d16,Am) Dn D2 4 1 MOVBU (d32,Am) Dn D4 6 2 MOVBU (d8,SP) Dn D1 3 1 MOVB.
Appendix Appendix-7 Instruction Source Destination Format Remarks MOV M 4 Registers specified by regs = 4 8 Registers specified by regs = 7 9 Registers specified by regs = 8 10 Registers specified by .
Appendix Appendix-8 * Varies according to the state of the instruction buffer. Code length Execution Cycle Instruction Source D estination Format Remarks AND AND D m D n D 0 2 1 A N D im m 8 Dn D1 3 1.
Appendix Appendix-9 Instruction Source Destination Format Remarks SETLB SETLB S 0 1 1 J M P J M P (An) D 0 2 3 J MP (d16,PC) S 2 3 2 J MP (d32,PC) S 4 5 4 CALL CALL (d16,PC) regs,imm8 S 4 5 2 Register.
Appendix Appendix-10 List of Extension Instructions ( Code Length, Execution Cycle) Instruction Source Destination Format Code length Execution cycle Remarks PUTX PUTX Dm D 0 2 2 PUTCX Dm D n D 0 2 2 .
Appendix Appendix-11 Appendix C. Memory Connection Example Fig. C-1 shows a connection example for the memory configuration described below. Block 0: 16-bit bus, 4-Mbit ROM (262 144 words x 16 bits) Block 1: 16-bit bus, 4-Mbit DRAM (262 144 words x 16 bits, 2 CAS control) Block 2: 8-bit bus, 1-Mbit SRAM (131 072 words x 8 bits) Fig.
Appendix Appendix-12 Appendix D. Pins and Their Operating Statuses upon Reset In the address/data separate mode Pin No. Pin name Operating status 1 A19 L 26 PVSS — 51 CS3 H 76 P30 Hi-Z 2 A18 L 27 PV.
Appendix Appendix-13 Note 1) Hi-Z: High impedance H: High level output L: Low level output Pull-up: Pull-up Input: Input an appropriate value. Note 2) The pin marked with an asterisk is VDD2 in the MN103001G, and VPP in the MN1030F01K. In the address/data multiplex mode Pin No.
Appendix Appendix-14 Appendix E. Package Outline The package outline and dimensions of this microcontroller are shown below. Package code : LQFP100-P-1414 Unit: mm Fig.
Errors Page Corrections Page - i - P.1-3 P.1-8 P.2-9 P.2-13 P.2-14 P.2-15 P.2-15 P.2-17 P.2-18 P.2-18 P.2-18 P.2-19 P.2-19 P.2-20 P.3-5 P.3-7 P.1-3 P.1-8 P.
Errors Page Corrections Page - ii - P.3-8 P.3-9 P.3-10 P.3-21 P.3-22 P.3-23 P.3-23 P.3-24 P.3-25 P.3-25 P.3-26 P.3-26 P.3-27 P.3-29 ( Following sentences are added to [Programming Cautions] of GETCHX. ) When "udf12 Dm, Dn" is operated, Dm is ignored.
Errors Page Corrections Page - iii - (Omit) Note that operation is not assured when attempting to access unmounted space. Note that operation is not assured when attempting to access unmounted space. (The 2nd line of " ■ Operation of various peripheral functions in the low power consumption modes".
Errors Page Corrections Page - iv - P.6-3 P.6-3 P.6-4 P.8-5 P.8-11, P.8-15 P.8-15, P.8-20 P.8-35 P.8-35 P.8-36 P.8-41 P.6-3 P.6-3 P.6-4 P.8-5 P.8-11, P.8-15 P.8-15, P.8-20 P.8-35 P.8-35 P.8-36 P.8-41 When the reset state is released, SYSCLK, MCLK, and IOCLK are supplied starting after a certain oscillation stabilization wait time.
Errors Page Corrections Page - v - P.8-42 P.8-43 to P.8-44 P.8-48 P.8-49 P.8-49 P.8-50 P.8-56 P.8-57 P.8-58 P.8-59 - P.8-42 P.8-43 to P.8-44 P.8-48 P.8-49 P.
Errors Page Corrections Page - vi - P.9-3 P.9-7 P.9-7 P.9-7 P.9-7 P.9-7 P.9-8 P.9-30 P.9-30 P.11-6 P.12-2 P.12-2 P.12-2 (In fig. 9-4-1.) (Register's purpose ) This register determines whether an NMI interrupt has been generated.
Errors Page Corrections Page - vii - (In the table of Example.) (The 2nd line from the bottom.) An oscillation stabilization wait time of at least 14 ms is recommended. (In fig.12-5-2.) 4.369 ms to 1118.481 ms <Recommended value is 14 ms or longer.
(All of the series name in this manual is changed as shown below: • "MN10300 Series" is changed the name into "MN1030 Series". • "MN10200 Series" is changed the name into "MN102 Series".
MN103001G/F01K LSI User's Manual February, 2002 5th Edition Issued by Matsushita Electric Industrial Co., Ltd. © Matsushita Electric Industrial Co.
Semiconductor Company, Matsushita Electric Industrial Co., Ltd. Nagaokakyo, Kyoto 617-8520, Japan Tel: (075) 951-8151 http://www.panasonic.co.jp/semicon/ SALES OFFICES ■ NORTH AMERICA ● U.S.A. Sales Office: Panasonic Industrial Company [PIC] • New Jersey Office: Two Panasonic Way Secaucus, New Jersey 07094 U.
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