AtmelメーカーAT91EB42の使用説明書/サービス説明書
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AT91EB42 Evaluation Board ................. .................... ................... ................... .. User Guide.
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i T able of Contents Section 1 Overview .............. .............. .............. .............. .............. .............. ........... 1 -1 1.1 Scope .... .................... ................... ................... .................... .......
Table of Contents ii Section 5 Append ix A – Configura tion Straps ...... .............. .............. .............. ....... 5-1 5.1 Configur ation Straps ( CB1 - 23, J P1 - 8) ............... ................... ............. ... 5-1 5.2 Power Con sumption Me asurement S trap (JP5 ) .
AT91EB42 Evaluation Boa rd User Guide 1-1 Section 1 Ov ervi ew 1.1 Scope The AT91 EB42 Evalua tion Boar d enables real-tim e code de velopment and evalu ation. It suppor ts the AT9 1M42800. This guide foc uses on the AT91EB42 Ev aluation Boar d as an evalua tion and demon- stratio n platform: Section 1 provides an ov er vi ew .
Overview 1-2 AT91E B42 Evaluatio n Board User G uide 2 x 32-p in EBI expansion c onnectors 2 x 32-p in I/O expansion con nectors 20-pin JT AG interface connec tor If r equired , user- defined perip herals ca n also be adde d to t he boa rd. See Section 5 for details .
AT91EB42 Evaluation Boa rd User Guide 2-1 Section 2 Setting Up the AT91EB42 Evaluation Board 2.1 Elect rosta tic Warnin g The AT91EB42 Evaluation Board is shipped in protective anti-static packaging. The board mu st not be subjected to high e lectrostat ic potential s.
Setting Up the AT91EB42 Evaluation Boa rd 2-2 AT91E B42 Evaluatio n Board User G uide 2.4 Jumper S ettings JP1 is us ed to boot standar d or user program s. For st andard op eratio ns, set it in the STD position . JP8 is used to select the core power supp ly of the AT91M4280 0: 3.
AT91EB42 Evaluation Boa rd User Guide 3-1 Section 3 The On-board Software 3.1 AT91EB4 2 Evaluation Board The AT91EB42 Evaluat ion Board embeds an AT 49BV1604 Flash memor y device pro- grammed with default software. Only the lowest 8 x 8 KB sectors are used.
The On-board So ftware 3-2 AT91E B42 Evaluatio n Board User G uide 3.3 Programmed Def ault Me mor y Mapping Table 3 -1 defines t he mappin g defined b y the boot program. The boot software program, FTS and SRAM downloader are in sectors 1 and 2 of the Flash devic e.
AT91EB42 Evaluation Boa rd User Guide 4-1 Section 4 Circuit Description 4.1 AT91M 42800 Processor Figure 6-1 on page 6-2 show s the AT9 1M42800 . The foot print is for a 14 4-pin TQFP package . Strap CB 20 enables the user to choo se between the standard I CE debu g mode and th e JTAG bou ndary sc an mode of o peration .
Circuit Desc ription 4-2 AT91E B42 Evaluatio n Board User G uide 4.3 Me mories The sc hematic ( Figure 6-3 on page 6-4 in Sec tion 6, “ Appendix B – Schemati cs ” ) shows one AT49 BV1604 2 MB 16 -bit Flash, o ne AT45DB321 4 MB serial D ataFlash, one AT24C512 64 KB EEPR OM, one AT252 56 32 KB EEPROM and two 1 28K/512K x 8 SRAM devic es.
Circuit Description AT91EB42 Evaluation Boa rd User Guide 4-3 of watchdog time-out as the pin NWDOV F of the AT9 1M42800 is c onnected to i ts input MR . The asser tion of this rese t signal wil l light up the red RE SET LED (D10). B y pressing the CLEAR RES ET push b utton (S1), the LED ca n be turned of f.
Circuit Desc ription 4-4 AT91E B42 Evaluatio n Board User G uide.
AT91EB42 Evaluation Boa rd User Guide 5-1 Section 5 Appendix A – Configuration Straps 5.1 Configuration Strap s (CB1 - 23, JP1 - 8) By addi ng the I/O an d EBI ex pansion connector s, users can con nect their own peripher- als to the ev aluation boa rd.
Appendix A – Configuration Stra ps 5-2 AT91E B42 Evaluatio n Board User G uide CB7 Standar d P o wer Supply Supervisory Ena bling Clos ed (1) Standard po wer sup ply is sup erv ise d by the ADC (U20) ch annel 2 v ia a resisto r bridge . The rat io is set to 0.
Appendix A – Configuration Straps AT91EB42 Evaluation Boa rd User Guide 5-3 CB15 Serial DataFlash Enabling Clos ed (1) A T91 NPCSA0 se lect sig nal is conn ected to t he serial DataF lash memory . Open A T9 1 NPCSA0 se lect signal is not c onnected to the serial DataFlash memory .
Appendix A – Configuration Stra ps 5-4 AT91E B42 Evaluatio n Board User G uide Note: 1. Hardwired def ault pos ition: T o cancel this def ault config urati on, cut th e wire on the board.
AT91EB42 Evaluation Boa rd User Guide 6-1 Section 6 Appendix B – Sche matics 6.1 Schema tics The foll owing sc hematics a re appended: • Figure 6-1. PCB Lay out • Figure 6- 2. A T91EB42 Blocks Overv iew • Figure 6- 3. EBI Me mories • Figure 6- 4.
Appendix B – Schemati cs 6-2 AT91E B42 Evaluatio n Board User G uide Figure 6-1. PCB Lay out.
Appendix B – Schematics AT91EB42 Evaluation Boa rd User Guide 6-3 Figure 6-2. AT91EB4 2 Blocks Overview INP UT / OUT PU T ON BO ARD Serial Connectors / P.
Appendix B – Schemati cs 6-4 AT91E B42 Evaluatio n Board User G uide Figure 6-3. EBI M emori es VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 512k 512k 128k 128k 128k 512k 512k 128k layout for TSSOP 400mil.
Appendix B – Schematics AT91EB42 Evaluation Boa rd User Guide 6-5 Figure 6-4. I/O and EBI Expans ion Connectors.
Appendix B – Schemati cs 6-6 AT91E B42 Evaluatio n Board User G uide Figure 6-5. Push Butto ns, LEDs and Serial Int erface VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V.
Appendix B – Schematics AT91EB42 Evaluation Boa rd User Guide 6-7 Figure 6-6. AT91M428 00 VDDCORE VDDPLL VCC3V3 VCC3V3 VCC3V3 VDDIO VDDIO VDDCORE JTAG[0..4] NRST NWDOVF JTAGSEL Guard ring PLL filter A PLL filter B Guard ring Default boot Mode : 16 Bits VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO JTAG[0.
Appendix B – Schemati cs 6-8 AT91E B42 Evaluatio n Board User G uide Figure 6-7. Reset an d JTAG Inter face VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 NRST JTAG[0.
Appendix B – Schematics AT91EB42 Evaluation Boa rd User Guide 6-9 Figure 6-8. Power Sup ply and B attery Char ger VCC3V3 VDDCORE VDDIO VDDPLL VCC3V3 Vbatt+ Vps VDDCORE=1.8V VDDCORE=3.3V I Vddcore I Vddio 5 cel. NiCd Timeout 264mn TC in place only if Therm sensor on Batt.
Appendix B – Schemati cs 6-10 AT91E B42 Evaluatio n Board User G uide Figure 6-9. Battery Ty pe and Conn ection T˚C Battery : 6V / 300mAH NiCd SAFT : VRE 1/2 AA Ref 139 663 Wire: gauge 20 AWG Wire: gauge 20 AWG Tmax 45˚C BT1 6V / 300mAH 1 2 J2 con.
Appendix B – Schematics AT91EB42 Evaluation Boa rd User Guide 6-11 Figure 6-10. SPI Me mories, I 2 C Memorie s and SPI AD C VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3.
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