AtmelメーカーATA6264の使用説明書/サービス説明書
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Features • Maxim um Suppl y V oltage 40V • One Programmable/Adjustab le Boost Con verter • T wo Programmable Buc k Con verters • One Programmable Linear Regulator • O TP Customer Mode • 16.
2 4929B–AUTO–01/07 ATA6264 [Preliminary] Figure 1-1. Block Diagram V VCORE V VPERI V VSA T V EVZ CP Logic VCORE- Regulator Internal Supply Reference VPERI- Regulator EVZ- Regulator VSA T - Regulat.
3 4929B–AUTO–01/07 ATA6264 [Preliminary] 1.1 Bloc k Description 1.1.1 Integrated Boos t Con vert er EVZ With an external n-channel FET, the integrated boost converter EVZ provides 3 different volt- ages adjustable via the serial interface for the energy reserve a nd firing capacitors.
4 4929B–AUTO–01/07 ATA6264 [Preliminary] 2. Pin Configuration Figure 2-1. Pinning QFP44 K15 EVZ VSAT GNDD VINT COMSATI SVPERI VPERI GNDA VCORE SVSAT USP K30 K2 IASG1 IASG2 IASG3 ISENS TxD1 IASG5 I.
5 4929B–AUTO–01/07 ATA6264 [Preliminary] 23 VPERI Input f or the VPERI regulator , inter nally used VPERI supply 24 SVPERI Output of VPERI regulator pow er transistor 25 GND A Analog GND 26 VCORE .
6 4929B–AUTO–01/07 ATA6264 [Preliminary] 3. Absolute Maxim um Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause per manent damage to the device.
7 4929B–AUTO–01/07 ATA6264 [Preliminary] ESD classification at pins connected to de vices outside the ECU (IASG1 to IASG5) Human body model (HBM) HBM AEC Q100-002 ±3000 V ESD classification at pi.
8 4929B–AUTO–01/07 ATA6264 [Preliminary] 4. Functional Range Within the function al range, the ATA6264 works as specified. All voltages are r eferenced to the ideal ground level of an ECU connected to the GNDA, GNDB and GNDD pins . At the beginning of each specification table, supply voltage and temp erature conditions are described.
9 4929B–AUTO–01/07 ATA6264 [Preliminary] 4.1 Protection Against Substrate Currents Due to the fact t hat the ATA6264 is conne cted to the wiring ha rness and to componen ts outside of the ECU, neg.
10 4929B–AUTO–01/07 ATA6264 [Preliminary] 5. Supply Currents A minimum current has to fl ow into each pin for proper fun ctioning of the IC. T able 5-1. Electrical Characteristics – Supply currents No. P arameters T est Conditions Pi n Symbo l Min.
11 4929B–AUTO–01/07 ATA6264 [Preliminary] 5.1 Dischar ger Circuit Applications using th e ATA6264 usually use a revers e polarity protecti on diode (D1 in Figure 5-1 ) in the power supply to prev ent any damage if the wrong polarity is app lied to V K30 .
12 4929B–AUTO–01/07 ATA6264 [Preliminary] The following setting s can be made at the initial program ming: MSBit LSBit VR1 VR2 VR3 VR4 EXT ISO/LIN Parity Lock bit T able 5-2. Initial Programming Settings VR1 VR2 VR3 VR4 VCORE VP ERI VSA T 0 0 0 0 All regulators deactivated (def ault) 0 0 0 1 1.
13 4929B–AUTO–01/07 ATA6264 [Preliminary] The IP data is valid only if the parity is odd. If the IP data is not valid, or if the lock b it is not set, the programming will not be executed.
14 4929B–AUTO–01/07 ATA6264 [Preliminary] 5.3 Start-up and P ower -do wn Procedure The ATA6264 is powered via the pin K30 (battery voltage) and via a diode or a resistor it is con- nected to the ignition key line K15. In order to detect an interr uption on one of these pins correctly, resistors are im plemented at these pi ns.
15 4929B–AUTO–01/07 ATA6264 [Preliminary] Depending on t he initial program ming of the ATA6264, the start-u p procedure takes pla ce in dif- ferent phases. 5.3.1 Sta rt-up Procedure if V VCORE is Pr ogrammed to Be 5V or 2.5V Phase1: After switching on the ignition key, K15 voltage will apply at pin K15.
16 4929B–AUTO–01/07 ATA6264 [Preliminary] Figure 5-4. Start-Up a nd Power-Down Procedure if V VCORE Programmed to Be 5V or 2.5V 5.3.3 Sta rt-up Procedure if V VCORE Pr ogrammed to Be 1.88V Phase1: After switching on the ignition key, the K15 voltage will appear at pin K15.
17 4929B–AUTO–01/07 ATA6264 [Preliminary] 5.3.4 The P ower- down Pr ocedure f or V VCORE is Programmed to be 1.88V Phase1: If the ignition key is switched off, the K1 5 voltage will vanish at pin K15. If the serial interface command KEYL ATCH is not set, the EVZ regulator stops wor king.
18 4929B–AUTO–01/07 ATA6264 [Preliminary] 6. P ower Supply Sequencing (Only active when init ial programming sets V VCORE = 1.88V and V VPERI = 3.3V) In order to meet the requirements of several dual-voltage-supply microcontrollers, a power-sequencing function is implemented.
19 4929B–AUTO–01/07 ATA6264 [Preliminary] Figure 6-2. Block Diagram Power Supply Sequencing VEVZ V VSA T V VPERI Comp VEVZ K15GOOD V K15 = 3V to 4.15V (40 mV to 175mV Hysteresis) Serial interface (KEY - LA TCH) VSA T VCP Comp VSA TGOOD V SA T = 6.
20 4929B–AUTO–01/07 ATA6264 [Preliminary] 7. Charge Pump To supply the VSAT and VCORE dr ivers, an external charge pump is provided. Both FETs (1) are driven by the hig h charge pu mp voltage V CP to ensure that they can be switched to a low- ohmic state.
21 4929B–AUTO–01/07 ATA6264 [Preliminary] Necessary for operation: V EVZ = 5.5V to 40V or V K30 = 5.5V to 40V, V K15 > 3V, V VINT = 3.7V to 5.47V Operating condition s of all other supply pins: V VSAT , V VPERI an d V VCORE are within functional rang e limits, T j = –40°C t o 150°C Other pins: As defined in Section 4.
22 4929B–AUTO–01/07 ATA6264 [Preliminary] 8. GKEY Function The GKEY function is used to enab le or disable the ECU via a powerless signal. If the voltage at pin K15 is larger than 3V to 4.15V, the charge pump and the EVZ regulator (for correct EVZ function, the K30 pin has to be connected to the battery) will start operat ing.
23 4929B–AUTO–01/07 ATA6264 [Preliminary] Figure 8-2. Application With Hig h Current Switch (GKEY Function Not Used) Necessary for operation: V K15 = 3V to 40V, V K30 = 3.
24 4929B–AUTO–01/07 ATA6264 [Preliminary] 9. EVZ Step-up Regulator A boost converter generates the supply voltage for energy reserve and firing capacitors in the system. Using a voltage divider at pin FBEVZ, this voltage can be adjusted between 15V and 40V.
25 4929B–AUTO–01/07 ATA6264 [Preliminary] Figure 9-2. EVZ Regulator With Internal Divider A draft formula for calculating t he EVZ voltage, which is programmed by the external voltage divider netw.
26 4929B–AUTO–01/07 ATA6264 [Preliminary] Figure 9-3. Functional Principle of the EVZ Regulat or The output transistor conduction is suppressed immediately if the current through the power FET exceeds a certain le vel, determined by the volt age drop across an external r esistor in the range of 0.
27 4929B–AUTO–01/07 ATA6264 [Preliminary] Necessary for operation: V K15 = 3V to 40V, V K30 = 5V to 40V, C GEVZ = 200 pF to 2 nF, V INT = 3.7V t o 5.47V Operating condition s of all other supply pins: V SAT , V PERI and V CORE are within funct ional range limit s, T j = –40°C t o 150°C Other pins: As defined in Section 4.
28 4929B–AUTO–01/07 ATA6264 [Preliminary] 8.19a Overvoltage at pin EVZ to switch off the regulato r V EVZ1 programmed VEVZ V EVZ 25 28.5 V A 8.19b Overvoltage at pin EVZ to switch off the regulato r V EVZ2 programmed VEVZ V EVZ 35 39.
29 4929B–AUTO–01/07 ATA6264 [Preliminary] Error Amplifier 8.32 Output current at pin COMEVZO sinking to low COMEVZO I COMEVZO 0.4 3 mA A 8.33 Output current at pin COMEVZO drivin g to high COMEVZO I COMEVZO –1000 –150 µA A 8.34 Input offset voltage –10 +10 mV D 8.
30 4929B–AUTO–01/07 ATA6264 [Preliminary] 10. VSA T P o wer Suppl y A stabilized VSAT supply is realized by a buck converter. An external in ductance is PWM-switched with a frequency of 200 kHz via an internal h igh-side DMOS power transistor.
31 4929B–AUTO–01/07 ATA6264 [Preliminary] Necessary for operation: V EVZ = 5.5V to 40V, V CP > V EVZ + 7V, V INT = 3.7V to 5.45V Operating condition s of all other supply pins: V K30 , V PERI an d V CORE are within fu nctional range limits, T j = –40°C to +150°C Other pins: As defined in Section 4.
32 4929B–AUTO–01/07 ATA6264 [Preliminary] 9.15 Overcurrent s witch-on time Time between reaching ov ercurrent and reaching 90% of V SVSA T maximum under on condition SVSA T t SVSA T off 00 . 5 µ s A 9.16 Leakage current at pin SVSA T Output tr ansistor off SVSA T I SVSA T –10 +10 µA A Error Amplifier 9.
33 4929B–AUTO–01/07 ATA6264 [Preliminary] 11. VPERI P ower Supply With the V PERI regulator a stabilized and ripple-free voltage is gene rated out of the VSAT supply voltage. This voltage is intended to be used for sensitive components, for example, sensors or reference inputs of A/D converters from microcontrollers.
34 4929B–AUTO–01/07 ATA6264 [Preliminary] Necessary for operation: V SAT > 7.5V, V INT = 3.7V to 5.47V, V CORE < V PERI + 0.3V Operating condition s of all other supply pins: V K30 , V EVZ and V CORE ar e within functional range limits, T j = –40°C to 150°C Other pins: As defined in Section 4.
35 4929B–AUTO–01/07 ATA6264 [Preliminary] 12. VCORE P ower Suppl y The voltage of the VCORE regulator is gen erated out of the K30 voltage using a step-down reg- ulator as long as the K30 voltage is ava ilable. During times wh en K30 is not present (power-down or sta nd-alone time), the VCORE regulator is supplied out of VEVZ.
36 4929B–AUTO–01/07 ATA6264 [Preliminary] Necessary for operation: V EVZ = 5.5V to 40V or V K30 = 5.5V to 40V, V CP > V EVZ + 7V or V CP > V K3 0 + 7V, V PERI >V CORE – 0.
37 4929B–AUTO–01/07 ATA6264 [Preliminary] 11.12 Output transistor s witch-off time Time between reaching 0.1 × (V K30max – V VCOREmin ) and 0.9 × (V K30max – V VCOREmin ) or 0.1 × (V EVZmax – V VCOREmin ) and 0.9 × (V EVZmax – V VCOREmin ) SVCORE t SVCOREoff 150 ns A 11.
38 4929B–AUTO–01/07 ATA6264 [Preliminary] 11.25 Leading -edge blanking time t bla nk 15 0 200 ns D 11.26 Slope of ar tificial ramp for slope compensation dV/dt 80 (1) 150 (1) mV/µs D 11.27 V oltage lev el at K30 to switch VCORE supply from EVZ to K30 (V VCORE = 1.
39 4929B–AUTO–01/07 ATA6264 [Preliminary] 13. USP Comparator fo r General Purpose The USP comparator is used f or general purposes, for example, low battery det ection. An exter- nal resistive voltage divider provide s the input signal for pin USP.
40 4929B–AUTO–01/07 ATA6264 [Preliminary] 14. Reference V oltage and Reference Current Generation The pin IREF is an output derived direct ly from the chip’s internal reference voltag e. This refer- ence source is a band gap. All internally used precise voltages are derived from this band-gap voltage.
41 4929B–AUTO–01/07 ATA6264 [Preliminary] 15. Reset Function (Pin RESQ and Pin RESQ2) Pins RESQ and RESQ2 are low-active digital out puts of the ATA6264, which provide a digital “low” signal in the case of a missing or incorrect watchdog transm ission or in the case of improper VEVZ, VPERI or VCORE voltage.
42 4929B–AUTO–01/07 ATA6264 [Preliminary] Figure 15-2. F unctional Principle of RESQ, RESQ2 V EVZGOOD SPI communication Re-configure prescaler while 1 st and 2nd trigger watchdog command chip inte.
43 4929B–AUTO–01/07 ATA6264 [Preliminary] The RESQ2 signal results from a logical AND of the Reset signal and an OK signal from the watchdog circuitry, so RESQ2 will go high after the watchdog tr iggers correctly. RESQ and RESQ2 have to be set to low if V VPERI or V EVZ are below the sp ecified thresh old.
44 4929B–AUTO–01/07 ATA6264 [Preliminary] Figure 15-4. Application Example Necessary for operation: V EVZ = 5.5V to 40V, V PERI = 1V to 5.5V , V INT = 3.7V to 5.47 V Operating condition s of all other supply pins: V K30 , V SAT , an d V CORE are within functional range limits, T j = –40 °C to 150°C Other pins: As defined in Section 4.
45 4929B–AUTO–01/07 ATA6264 [Preliminary] T able 15-2. Electrical Characteristics – Res et Fu nction (Pin RESQ and Pin RESQ2) No. P arameters T est Conditions Pin Symbol Min T yp. Max. Unit T ype* 14.1 RESQ and RESQ2 high lev el I RESQ, I RESQ2 = –200 µA to 0 µA RESQ RESQ2 V RESQ V RESQ2 V VPERI – 0.
46 4929B–AUTO–01/07 ATA6264 [Preliminary] 14.15 Delay time for RESQ and RESQ2 to switch to lo w after reaching the reset threshold of V EVZ RESQ RESQ2 t RESQ t RESQ2 10 20 µs A 14.16 Pull-down current at pi n RESQ RESQ is s witched to low (V RESQ = 0.
47 4929B–AUTO–01/07 ATA6264 [Preliminary] 16. W atc hdog Function To verify the proper fu nction of the microcontro ller, watchdog logic is included. As the ATA6264 is powered up, the RESQ2 s ignal stays low until the first valid watchdog trigger is detect ed.
48 4929B–AUTO–01/07 ATA6264 [Preliminary] Requirements for successful trigger: • Minimum one v alid diff er ent serial interf ace command between t wo trigger watchdog commands is necessary . Exception: First trigger watchdog comman d need not be preceded by a d iff erent serial interf ace command .
49 4929B–AUTO–01/07 ATA6264 [Preliminary] The trigger watchdo g cycle can be set to the follow ing retrigger times : •4 m s •8 m s • 16 ms (def ault ) •3 2 m s •6 4 m s •1 2 8 m s Cyclic phase: Between two trigger commands a different SPI command must be seen by th e SPI decoder Figure 16-3.
50 4929B–AUTO–01/07 ATA6264 [Preliminary] Figure 16-4. Watchdog Trigger Functional Principle (Unsucce ssful Watchdog Trigger) Serial interface communication chip internal trigger window Serial int.
51 4929B–AUTO–01/07 ATA6264 [Preliminary] Configuration of wat chdog trigger: For the configuration of the watchdog prescaler, a special serial interface command is necessary. Note: a, b , and c to be set as defined in Table 16-1 The status of th e watchdog prescaler is indicated in the status register.
52 4929B–AUTO–01/07 ATA6264 [Preliminary] Necessary for operation: V PERI > Reset thresho ld, V CORE > Reset th reshold Operating condition s of all other supply pins: V K30 , V EVZ and V VSA T are within functional rang e limits, T j = –40°C t o 150°C Other pins: As defined in Section 4.
53 4929B–AUTO–01/07 ATA6264 [Preliminary] Figure 16-5. Watchdog Trigger Re-configure prescaler during 1 st and 2nd trigger watchdog command VCC 15.
54 4929B–AUTO–01/07 ATA6264 [Preliminary] 17. LIN/ISO 9141 Interfaces The ATA6264 includes two complete ISO 9141 int erfaces. Interfa ce #1 is controlled via the pins RxD1 and TxD1, int erface #2 is controlled via the pins RxD2 and TxD2.
55 4929B–AUTO–01/07 ATA6264 [Preliminary] T able 17-1. Electr ical Characterist ics – LIN/IS O 9141 Inter faces No. P arameters T est Conditions Pin Symbol Min T yp. Ma x. Unit T ype* General (V alid for All Modes) 16.1 Pull-up current to VPERI at pin TxD x (x = 1, 2) TxD x I TxDx –35 –50 –65 µA A 16.
56 4929B–AUTO–01/07 ATA6264 [Preliminary] ISO 9141 Mode 16.23 Maximum baud rate K x f Kx 62.5 kBd A 16.24 Propagation delay TxD x = low to K x =l o w (x = 1, 2), measured f rom TxD x H to L to K x = 0.9 × V K30 R Kx = 510 Ω to K30, C Kx = 470 pF to GNDB K x t PDtL 1µ s A 16.
57 4929B–AUTO–01/07 ATA6264 [Preliminary] Figure 17-2. Timing LIN/ISO 9141 Interface 16.37 Propagation delay K 1 high to RxD 1 =h i g h Measured f rom K 1 =0 . 6 × V K30 to RxD 1 =Lt oH K 1 t PDkH 4µ s A 16.38 Symmetr y of transmitter delay t SYM_T1 =t PDtL –t PDtH K 1 t SYM_T1 –1 1 µs A 16.
58 4929B–AUTO–01/07 ATA6264 [Preliminary] 18. V oltage/Current Sour ces ( IASG x Sources) For a variable resistan ce measurement and especia lly fo r buckle-switch dete ction, five constant voltage sources, switchable between two different voltage s (V1 and V2) are implemented.
59 4929B–AUTO–01/07 ATA6264 [Preliminary] Figure 18-1. F unctional Principl e of the IASG Interface Necessary for operation: V VCORE and V VPERI > Reset threshold, V EVZ = 9V to 40V for operation with IASGx switched to 5V V VCORE and V VPERI > Reset threshold, V EVZ = 15V to 40V fo r operation with IASGx switched to 10V V INT = 3.
60 4929B–AUTO–01/07 ATA6264 [Preliminary] T able 18-1. Electrical Characteristics – Voltag e/Current S ources (IASG x Sources) No. P arameters T est Conditions Pin Symbol Min T yp. Max. Unit T ype* 17.1 Output voltage (V1) (x = 1 to 5), –40 mA < I IASGx < –0.
61 4929B–AUTO–01/07 ATA6264 [Preliminary] 17.11 Output voltage clamping (V ISENS ≤ V VPERI ) I IASGx >C R Y × V VPERI /R ISEN S (x = 1 to 5), (Y = 1, 2) (V ISENS ≤ V VPERI regulator active ) ISENSE V ISENSE 0.96 × V VPERI 1.05 × V VPERI VA 17.
62 4929B–AUTO–01/07 ATA6264 [Preliminary] 19. AMUX (Analog Multiplex er f or V oltage Measurements) Various voltages and the chip temperature inside of the ATA62 64 can be measured at the ana- log measurement output UZP. Different volta ge dividers en sure that t he values of the m easured voltages at UZP are in t he range of 0V to V PERI .
63 4929B–AUTO–01/07 ATA6264 [Preliminary] T able 19-1. Electrical Characteristics – AMUX (Analog Multiplexer for Voltage Me asurements) No. Parameters T est Conditions Pi n Symbol Min T yp. Max. Unit T yp e* 18.1 Output offset error Has to be calculated from the values of the diff erential measurement UZP V UZPoffset –5 +15 mV A 18.
64 4929B–AUTO–01/07 ATA6264 [Preliminary] 18.15 Ratio V USP /V UZP Fo r V VPERI = 5V (1.5V to 3V) Fo r V VPERI = 5V (> 3V to 25V) UZP Ratio 6.02 ± 6% 6.02 ± 2.3% A A 18.15a Ratio V USP /V UZP Fo r V VPERI = 3.3V (1.5V to 3V) Fo r V VPERI = 3.
65 4929B–AUTO–01/07 ATA6264 [Preliminary] 20. UZP Buffer The pin UZP is an analog output pin of the ATA62 64. Th e UZP buffer is realized as a trista te out- put with the ability to drive to VPERI as well as to GNDA.
66 4929B–AUTO–01/07 ATA6264 [Preliminary] T able 20-1. Electrical Characte ristics – UZP Buffer No. P arameters T est Conditions Pin Symbol Min T yp. Max. Unit T ype* 19.1 Output current high side, driving curre nt with measurement activated V UZP = 0V , UZP connected to GND UZP I UZP –8 –2 mA A 19.
67 4929B–AUTO–01/07 ATA6264 [Preliminary] 21. Chip T emperature Measurement A serial interface command allows measur ing a chip-temperature–dep endent voltage which is generated by tw o diodes connected in ser ies. Three 2-diode sen sors are connected in pa rallel and located in the following blocks: VPERI, VCORE, and VS AT.
68 4929B–AUTO–01/07 ATA6264 [Preliminary] 22. Serial Interface Commands 22.1 Overview All functions of the ATA6264 are triggered b y 16-bit serial interface commands. Some of these commands are latched because their actions have to continue for a longer time.
69 4929B–AUTO–01/07 ATA6264 [Preliminary] 21.7 Time from SSQ f alling edg e to MISO MSB v alid (2) MISO t MISOMSB_V 0 400 ns A 21.8 Time from SCLK rising edge to MISO va lid (2) MISO t MISO V 04 0 n s A 21.9 Time from SSQ rising edge to MISO trista te condition (2) MISO t MISOhiZ 04 0 n s A 21.
70 4929B–AUTO–01/07 ATA6264 [Preliminary] Figure 22-1. T iming Serial In terface 22.2 Set Commands After a reset due t o the watchdog or undervoltag e, all internal control registe rs and decoded sig- nals are set to their de fault values.
71 4929B–AUTO–01/07 ATA6264 [Preliminary] Because the K1 and K2 interfaces are by default switched to ISO (LIN) mode, the commands 9CF0, 9CFF, 9C00, and 9C0F defau lt to invalid commands.
72 4929B–AUTO–01/07 ATA6264 [Preliminary] The initial programming comm and is only available in T est mode. For more inform ation about the programmin g flow and the re gister contents, see Section 5.2 ”Initial Prog ramming of the ATA6264” on pag e 11 .
73 4929B–AUTO–01/07 ATA6264 [Preliminary] Because the diagnosis commands are non- latchi ng commands, any new serial interface com- mands, except watchdog triggering (6A55) an d the Kx switching commands (9Cxx), interrupt the diagnosis.
74 4929B–AUTO–01/07 ATA6264 [Preliminary] 22.3 Serial Interface Status Register For all serial int erface commands except the test-mode co mmands (55AAh, AA55h, 5500h), the ATA6264 status is available at the MISO line. Fo r the status register a 16-bit structure is used, one bit for each information.
75 4929B–AUTO–01/07 ATA6264 [Preliminary] The overtempe rature bits a5, a6 and a 7 are latched when ove rtemperature is det ected. These bits will be reset with the next SPI co mmand, unless overtemperature still exists. In the case of a reset , bits b4 and b5 ar e not set to their def ault state.
76 4929B–AUTO–01/07 ATA6264 [Preliminary] 23. T est Mode For better testability of the ATA6264, a test mode is implemented. This mode is activated if the pins RESQ and TxD1 are connected to GND, the pins RESQ2 and TxD2 are connected to VPERI, and the serial interf ace command 5A5Ah is sent to the ATA6264.
77 4929B–AUTO–01/07 ATA6264 [Preliminary] 24. Application Circuits Figure 24-1. O verview of a Typical Airb ag System COMSA TO SVSA T COMEVZ FBEVZ VPERIFB VPERI VSA T COMSA TI EVZ GNDB OCEVZ GEVZ .
78 4929B–AUTO–01/07 ATA6264 [Preliminary] Figure 24-2. Typical Application Circuit KL15 RESQ2 MISO RESQ MOSI KL30 K1 RxD1 TxD1 RxD2 TxD2 RESQ2 VINT MISO RESQ SSQ SCLK SSQ SCLK Cp K30 USP MOSI RxD1.
79 4929B–AUTO–01/07 ATA6264 [Preliminary] 26. P ac kage Inf ormation 25. Ordering Inf ormation Extended T y pe Number P ac kage Remarks A T A6264-AL TW P-TQFP44 T ra y A T A6 264-ALQW P-TQFP44 T aped and reeled specifications according to DIN technical drawings 10 ±0.
80 4929B–AUTO–01/07 ATA6264 [Preliminary] 27. Revision History Please note that the follo wing page numbers referred to in this section refer to the specific revision mentioned, not to this document.
81 4929B–AUTO–01/07 ATA6264 [Preliminary] 28. T able of Contents Features ................ ................ .............. ............... .............. .............. ............ 1 1 Description ............ ............................ .......
82 4929B–AUTO–01/07 ATA6264 [Preliminary] 17 LIN/ISO 9141 Interfaces ......... ........................................................ ........ 54 18 Voltage/Current Sources (I ASGx Sources) ................. .............. .......... 58 19 AMUX (Analog Multiplexer for Voltage Measurements) .
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