QuatechメーカーRS-422/485の使用説明書/サービス説明書
ページ先へ移動 of 44
MPA-200/300 RS-422/485 SYNCHRONOUS ADAPTER CARD for ISA compatible machines User's Manual QUATECH, INC. TEL: (330) 655-9000 5675 Hudson Industrial Parkway FAX: (330) 655-9010 Hudson, Ohio 44236 http://www.
.
Warranty Information Quatech Inc. warrants the MPA-200/300 to be free of defects for one (1) year from the date of purc hase. Quatech I nc. will repair or replace any adapter that fails to perform under nor mal operating conditions and in accordance with the procedures outlined in this document during the warranty period.
The information contained in this doc ument cannot be reproduced in any form without the written consent of Quatech, In c. L ikewise, any software programs that might accompany this document can be used only in accordance with any license agreement(s) bet ween the purchaser and Quatech, Inc.
Compliances - Electromagnetic Emissions EC - Council Directive 89/336/EEC This equipment has been tested and found to comply with the limits of the following standards for a digital device: EN5008.
TABLE OF CONTENTS 37 13 SPECIFICATIONS ................................... 33 12 DEFINITION OF INTERFACE SIGNALS ........... 32 11.2 Null-Modem Cables ................................... 32 11.1 MPA-200 and EIA-530 Compatibility .................... 29 11 EXTERNAL CONNECTIONS .
3 Quatech Inc., MPA-200/300 Manual.
1 INTRODUCTION The Quatech MPA-200/300 is a single ch annel, sy nchronous serial communica- tion port for sy stems utilizing the architec ture of the I BM AT personal or compati- ble computers. The MPA-200 is RS-422 compatible. The MPA-300 has RS-485 data line driv ers and receivers in place of the MPA-200's RS-422 drivers and receivers.
Figure 1 MPA-200 board drawing Quatech, Inc. MPA-200 U1 U2 SW 1 SW 2 U3 U4 U5 U6 U7 U8 X1 U16 U9 U10 U11 U12 U13 U14 U15 U21 U17 J10 J11 J5 J6 J4 CN2 CN1 U22 U23 U26 U18 U19 U20 U25 J8 J7 U29 U24 U28 3 Quatech Inc.
2 HARDWARE INSTALLATION I f the default address a nd interrupt settings are sufficient, the MPA-200 can be quickly installed and put to use. The fa ctory default settings ar e listed below in Table 1. Table 1 Default Board Confi guration DMA/DRQ 1 DMA/DRQ 3 IRQ 5 300 hex RxDMA TxDMA Interrupt Address 1.
3 SCC GENERAL INFORMATION The Serial Communications Controlle r (SCC) is a dual channe l, multi-protocol data communications peripheral. The MPA-200 provides a sing le channel for communications, howeve r, to provide full DMA capabilitie s, both channels of the SCC can be utilized.
3.1 Accessing the registers The mode of communication desired is es tablished and monitored through the bit values of the internal read and writ e registers.
Example 3: Write data into the transmit buffer of channel A. mov dx,base ; load base address out dx,al ; write data in ax to buffer Example 4: Read data from the receive buffer of channel A. mov dx,base ; load base address in al,dx ; write data in ax to buffer Table 2 SCC read register description.
clock (TCLK) and the RTXC pin for its receive clock (RCL K). Programming of the clocks should be done before enab ling the receiver, transmitter, BRG, or DPLL.
3.2 Baud Rate Generator Programming The baud rate generator (hereafter referred to as t he BRG) of the SCC consist s of a 16-bit down counter, two 8-b it time constant registers, and an output divide-by - two. The time constant f or the BRG is prog rammed into WR12 (lea st signific ant by te) a nd WR13 (most sig nificant by te).
3.3 SCC Data Encoding Methods The SCC provides four differe nt data encoding methods, selected by bits D6 and D5 in WR10. These four include NRZ, NRZI , FM1 and FM0. The SCC also features a digital phase-loc ked loop (DPL L) that can be prog rammed to operate in NRZI or FM mode.
4 JUMPER BLOCK CONFIGURATIONS The MPA-200 utilizes seven user-selectable jumper blocks , that allow the user more flexibility when configuring the board.
5&10 IRQ15 4&9 IRQ14 3&8 IRQ12 2&7 IRQ11 1&6 IRQ10 4.3 J10 - Transmit DMA Channel Selection J10 selects the DMA channel to be used f or transmit DMA.
4.4 J11 - Receive DMA Channel Selection J11 selects t he DMA channel to be used for receive DMA. Three channels (1 - 3) are available on the MPA-200 for DMA. When selecting a DMA channel, both the DMA acknowledge (DACK) and the DM A request (DRQ) for the appropriate channel need to be selected.
Table 10 Jumper block J7 connections 5&6 Receiver controlled by Comm. Register 4&5 Receiver Always Enabled 2&3 Transmitter controlled by Comm.
5 ADDRESSING The MPA-200 occupies a continuous 8 byte block of I /O addresses. For ex ample, if the base address is set to 300H, then the MPA-200 will occupy address locations 300H-307H.
The first four by tes, Base+0 throug h Base+3, of address space on the MPA-200 contain the internal registers of the SCC. The nex t two locations Base+4 and Base+5 contain t he communica tions register and the conf ig uration register. The last two address port locat ions are reserved for future use.
6 INTERRUPTS The MPA-200 supports eleven interrupt leve ls: IRQ2 -7, I RQ10 - 12, and I RQ14 - 15. The interrupt level is selected th rough jumper blocks J5 and J6 ( see JUMPER BLOCK CONFIGURATI ONS on page 11). The interrupt source is selected by bits D4 and D5 of the c onfiguration register.
7 DIRECT MEMORY ACCESS Direct Memory Access (DMA) is a way of directly transferring data to and from memory , resulting in hig h data transf er r ates with very low CPU overhead. The MPA-200 allows the user to perform DM A transfers when data is received (DMARRQ) or when da ta is transmitted (DMATRQ).
of the SCC, a DMA reque st is ge nerated. The DMA contr oller then writes the data from the SCC into memory. Programming for DMA request on both trans mit and receive is simply a combina- tion of the two. There are three possible c onfigurations that can be used, depend- ing on the sources selected.
Figure 3 Block diagram of DMA on MPA-200. W/ R E Q A DTR/REQA W/ R E Q B SCC DMATRQ DRMRRQ J10 J11 PAL 7.1 Using Terminal Count to Generate an Interrupt The MPA-200 allows the option of generatin g an interrupt whenever the Terminal Count (TC) signal is asserted.
8 CONFIGURATION REGISTER The MPA-200 is equipped with an onboard re gister used for configuring informa- tion such as DMA enables, DMA sources, in terrupt enables, and interrupt sources. Below is a detailed descr ipti on of the configuration regi ster.
D1 -RXSRC, RECEIVE DMA SOURCE: When set (logic 1), this bit allows the source for receive DMA to come from the W/REQB pin of channel B on the SCC. When cleared (logic 0), the source for receive DMA comes from the W/REQA pin of channel A on the SCC.
9 COMMUNICATIONS REGISTER The MPA-200 is equipped with an onboard communications register which gives the user options pertaining to the clocks and testing. The user can specify the source and type of clock to be transmitted or received. Te st mode bits pertain only to the DTE versions and can be ignored if using a MPA-200 configured DCE.
D3 -RECEIVE CLOCK ENABLE (DCE only): When set (logic 1), this bit allows the DCE to transmit its receive clock (RCLK). When cleared (logic 0), the DCE receives its RCLK. Since a DTE can only receive its RCLK, writing to this bit has no effect on a DTE.
10 DTE / DCE Configuration The MPA-200 can be purchased in either Data Terminal Equipment (DTE) or Data Communications Equipment (DCE) configuration. The two config urations share some important features, but have si gnificant differences whi ch need to be mentioned.
10.1 DTE Configuration The control signals that the DTE can generate are the Request To Send (RTS) and Data Terminal Ready (DTR). I t can receive the signals Carrier Detect (CD), Clear to Send (CTS) , and Data Set Re ady (DSR).
10.2 DCE Configuration On the MPA-200, the difference between th e DTE and DCE signals is that, with the except ion of a few control signals, the pins used for signal transmission on the DTE are used for signal reception on the DCE and vice versa.
Figure 3 DCE Clock Configuration TRX CA RTXCA RTXCB RRCLK RTCLK TRX CB RCKEN TTCLK TCKEN (RCLK) (TCLK ) The Test Mode (TM) signal is always in the OFF condition and cannot be changed by the user. The L o cal Loopback (L L) and Remote L oopback (RL) test sig nals are not implemented on the DCE.
11 EXTERNAL CONNECTIONS When configured as a DTE, the MPA- 200 uses a D-25 short body male connector (labeled CN2). When configured as a DCE, the MPA-200 uses a D-25 long body female connector (labeled CN1).
Table 16 DCE Connector Pin Definitions Always Zero TEST MODE 25 TRXC +RRCLK 24 DCDA -DSR 23 DTR/REQA -DTR 22 No Connect 21 DCDA +DSR 20 CTSA -CTS 19 No Connect 18 TRXCA +TTCLK 17 TXDA -TXD 16 TRXCB +R.
Figure 4 MPA-200 DTE Output Connector 25 TEST MODE 24 +TTCLK 23 -DTR 22 -DSR 21 RLBK 20 +DTR 19 -RTS 18 LLBK 17 +RRCLK 16 -RX D 15 +RTCLK 14 -TXD CGND 1 +TXD 2 +RXD 3 +RTS 4 +CTS 5 +DSR 6 DGND 7 +CD 8.
11.1 MPA-200 and EIA-530 Com patibility I f the MPA-200 is to be connected with an EI A-530 device, it may be necessary to swap the +/- conductors on the TXD and RXD signals. 11.2 Null-Modem Cables The MPA-200 does not use a standard asyn chronous PC serial port connector pin out.
12 DEFINITION OF INTERFACE SIGNALS CIRCUIT AB - SIGNAL GROUND CONNECTOR NOTATION: DGND DIRECTION: Not applicable This conductor directly connects the DTE circuit ground to the DCE circuit ground.
CIRCUIT DB - TRANSMIT ELEMENT TIMING (TxClk - DCE Source) CONNECTOR NOTATION: +RTCLK,-RTCLK DIRECTION: From DCE This signal, generated by the DCE, provides the DTE with element timing information pertaining to the data transmitted to the DCE.
CIRCUIT CD - DTE READY (DTR) CONNECTOR NOTATION: +DTR,-DTR DIRECTION: To DCE This signal controls the switching of the DCE to the communication channel. The DTE will generate this signal to prepare the DCE to be connected to or removed from the communication channel.
CIRCUIT TM - TEST MODE (TM) CONNECTOR NOTATION: TEST MODE DIRECTION: From DCE This signal indicates to the DTE that the DCE is in a test condition. The DCE generates this signal when it has received a local loopback or remote loopback signal from the DTE.
13 SPECIFICATIONS Bus interface: IBM AT 16-bit bus Controller: Serial Communications Controller, 6 MHz (determined by user, typically an Intel 82530). Physical Dimensions: 7.
MPA-200/300 User's Manual Version 5.31 March 2004 Part No. 940-0038-531.
デバイスQuatech RS-422/485の購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
Quatech RS-422/485をまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはQuatech RS-422/485の技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Quatech RS-422/485の取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Quatech RS-422/485で得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Quatech RS-422/485を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はQuatech RS-422/485の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Quatech RS-422/485に関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちQuatech RS-422/485デバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
