RenesasメーカーH8S/2111Bの使用説明書/サービス説明書
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Revision Date: Ma y . 14 , 2004 16 H8S/2111B Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series H8S/2111B HD64F2111B Rev.
Rev. 1.00, 05/04, page ii of xxxiv.
Rev. 1.00, 05/04, page iii of xxxiv 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
Rev. 1.00, 05/04, page iv of xxxiv General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not con nect anythin g to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pi ns or to red uce noise.
Rev. 1.00, 05/04, page v of xxxiv Configuration of This Manual This manual comprises th e following items: 1. General Precautions on Handling of Product 2.
Rev. 1.00, 05/04, page vi of xxxiv Preface The H8S/2111B is a microcomputer (MCU) made up of the H8S/200 0 CPU employing Renesas Technology's o riginal archite cture as it s core, and the peripheral functions r equired to c onfigure a system.
Rev. 1.00, 05/04, page vii of xxxiv Rules: Register name: The following notatio n is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more tha n one cha nnel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right.
Rev. 1.00, 05/04, page viii of xxxiv.
Rev. 1.00, 05/04, page ix of xxxiv Contents Section 1 Overview ............................................................................................1 1.1 Features .................................................................................
Rev. 1.00, 05/04, page x of xxxiv 2.8 Processing States.............................................................................................................. .4 6 2.9 Usage Notes ................................................................
Rev. 1.00, 05/04, page xi of xxxiv 5.4.1 Exter nal Interrupts ............................................................................................... 76 5.4.2 Inter nal Interrupts ...............................................................
Rev. 1.00, 05/04, page xii of xxxiv 7.4 Port 4......................................................................................................................... ........ 107 7.4.1 Port 4 Data Direction Register (P 4DDR).........................
Rev. 1.00, 05/04, page xiii of xxxiv 7.12.5 Pin F unctions ....................................................................................................... 135 7.12.6 Input Pull-Up MOS in Ports C and D ..........................................
Rev. 1.00, 05/04, page xiv of xxxiv 9.3.7 Timer C ontrol/Status Re gister (TCSR)................................................................ 163 9.3.8 Timer C ontrol Regi ster (TCR) .................................................................
Rev. 1.00, 05/04, page xv of xxxiv 10.5.1 TCNT Count Timing ........................................................................................... 207 10.5.2 Timing of CMFA and CMFB Setting at Co mpar e-Match ................................... 207 10.
Rev. 1.00, 05/04, page xvi of xxxiv 11.6.5 System Reset by RESO Signal ............................................................................ 233 11.6.6 Counter Val ues during Transiti ons between Hi gh-Speed, Sub-Active, and Watch Modes .......
Rev. 1.00, 05/04, page xvii of xxxiv 12.8.6 SCI Operations during Mode Trans itions ............................................................ 273 12.8.7 Switching from SCK Pi ns to Port Pins .........................................................
Rev. 1.00, 05/04, page xviii of xxxiv 14.4.6 KBF Setting Timing a nd KCLK C ontrol ............................................................. 362 14.4.7 Receive Ti ming................................................................................
Rev. 1.00, 05/04, page xix of xxxiv 16.4.2 Scan Mode ........................................................................................................... 419 16.4.3 Input Sampling and A/D C onversion Time .......................................
Rev. 1.00, 05/04, page xx of xxxiv 19.2 Duty C orrection Circuit .................................................................................................... 459 19.3 Medium-Spee d Cloc k Divi der ..............................................
Rev. 1.00, 05/04, page xxi of xxxiv 22.5 Flash Memory Char acteristic s .......................................................................................... 527 22.6 Usage Note.....................................................................
Rev. 1.00, 05/04, page xxii of xxxiv.
Rev. 1.00, 05/04, page xxiii of xxxiv Figures Section 1 Overview Figure 1.1 Int ernal Block Di agram ............................................................................................ ..... 2 Figure 1.2 Pin Arrangement.......................
Rev. 1.00, 05/04, page xxiv of xxxiv Section 8 8-Bit PW M Timer (PWM) Figure 8.1 Block Diag ram of PWM Tim er ................................................................................. 147 Figure 8.2 Ex ample of Ad ditional Pulse Timi ng (When Upper 4 Bits of PWDR = B'1000) .
Rev. 1.00, 05/04, page xxv of xxxiv Figure 10.13 Timing of Input Cap ture Signal (Input capture si gnal is input during TI CRR a nd TICRF read) ............................. 213 Figure 10.14 Conflict betw een TC NT Write and Clear ....................
Rev. 1.00, 05/04, page xxvi of xxxiv Figure 12.20 Sample Flowc hart of Simulta neous Serial Transmi ssion and Reception .............. 270 Figure 12.21 Sample Flowc hart for M ode Transition duri ng Tra nsmission ............................... 274 Figure 12.
Rev. 1.00, 05/04, page xxvii of xxxiv Figure 13.25 IRIC Setting Ti m ing and SCL Control (1) ............................................................ 331 Figure 13.26 IRIC Setting Ti m ing and SCL Control (2) ......................................
Rev. 1.00, 05/04, page xxviii of xxxiv Section 16 A/D Converter Figure 16.1 Block Diag ram of A/D C onver ter ........................................................................... 414 Figure 16. 2 Exampl e of A/D Co nverter Op eration ( Scan Mode, Cha nnels AN0 t o AN2 Selected) .
Rev. 1.00, 05/04, page xxix of xxxiv Figure 22.4 Connectio n of VCL Capacitor ................................................................................. 529 Figure 22.5 Sy stem Clock Tim ing .....................................................
Rev. 1.00, 05/04, page xxx of xxxiv.
Rev. 1.00, 05/04, page xxxi of xxxiv Tables Section 1 Overview Table 1.1 Pin Functions i n Each Operatin g Mode .................................................................... 4 Table 1.2 Pin Fu nctions ...........................................
Rev. 1.00, 05/04, page xxxii of xxxiv Table 7.4 Input Pull-Up MOS St ates (P ort 3) ....................................................................... 106 Table 7.5 Input Pull-Up MOS St ates (P ort 6) .............................................
Rev. 1.00, 05/04, page xxxiii of xxxiv Table 12.7 Maxim um Bit Rate with External Clock Input (Clocked Sy nchronous Mode) .... 248 Table 12.8 Serial Transfer Formats (Asynchronous M ode) .................................................... 250 Table 12.
Rev. 1.00, 05/04, page xxxiv of xxxiv Section 19 Clock Pulse Generator Table 19.1 Dam ping Resistan ce Values ................................................................................. 456 Table 19.2 Crystal Resonator Parameters ...............
Rev. 1.00, 05/04, page 1 of 544 Section 1 Overview 1.1 Features • High-speed H8S/2000 cent ral processing un it with an internal 16-bit arch itecture Upward-com patible wi th H8/300 a nd H8/ 300H CP.
Rev. 1.00, 05/04, page 2 of 544 1.2 Internal Block Diagram P17/PW7 P16/PW6 P15/PW5 P14/PW4 P13/PW3 P12/PW2 P11/PW1 P10/PW0 P27 P26 P25 P24 P23 P22 P21 P20 PA7/ KIN15 /PS2CD PA6/ KIN14 /PS2CC PA5/ KIN1.
Rev. 1.00, 05/04, page 3 of 544 1.3 Pin Description 1.3.1 Pin Arrangement 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 11.
Rev. 1.00, 05/04, page 4 of 544 1.3.2 Pin Functions in Each O perating Mode Table 1.1 Pin Functions in Each Operatin g Mode Pin Name Pin No. Single-Chip Modes Flash Memory TFP-144 Mode 2, Mode 3 (EXPE.
Rev. 1.00, 05/04, page 5 of 544 Pin Name Pin No. Single-Chip Modes Flash Memory TFP-144 Mode 2, Mode 3 (EXPE = 0) Programmer Mode 31 PE1 NC 32 PE0 NC 33 (B) PA7/ KIN15 /PS2CD NC 34 (B) PA6/ KIN14 /PS2.
Rev. 1.00, 05/04, page 6 of 544 Pin Name Pin No. Single-Chip Modes Flash Memory TFP-144 Mode 2, Mode 3 (EXPE = 0) Programmer Mode 61 PD5 NC 62 PD4 NC 63 PD3 NC 64 PD2 NC 65 PD1 NC 66 PD0 NC 67 AVSS VS.
Rev. 1.00, 05/04, page 7 of 544 Pin Name Pin No. Single-Chip Modes Flash Memory TFP-144 Mode 2, Mode 3 (EXPE = 0) Programmer Mode 91 PC3 NC 92 PC2 NC 93 PC1 NC 94 PC0 NC 95 VSS VSS 96 P27 CE 97 P26 FA.
Rev. 1.00, 05/04, page 8 of 544 Pin Name Pin No. Single-Chip Modes Flash Memory TFP-144 Mode 2, Mode 3 (EXPE = 0) Programmer Mode 121 P30/LAD0 FO0 122 P31/LAD1 FO1 123 P32/LAD2 FO2 124 P33/LAD3 FO3 12.
Rev. 1.00, 05/04, page 9 of 544 1.3.3 Pin Functions Table 1.2 Pin Functions Pin No. Type Symbol TFP-144 I/O Name and Function VCC 1, 86 Input Power su pply pin. Connect the pin to the system power supply. VCL 13 Input Power supply pin. Connect the pin to VCC.
Rev. 1.00, 05/04, page 10 of 544 Pin No. Type Symbol TFP-144 I/O Name and Function FTCI 78 Input The counter cl ock input pin. FTOA 79 Output The output co mpare A output pin. FTOB 84 Output The output co mpare B output pin. FTIA 80 Input The input capture A input pin.
Rev. 1.00, 05/04, page 11 of 544 Pin No. Type Symbol TFP-144 I/O Name and Function LAD3 to LAD0 124 to 121 Input/ Output LPC command, address, and data input/output pins. LFRAME 125 Input Input pin that indicat es the start of an LPC cycle or forced terminat ion of an abnormal LPC cycle.
Rev. 1.00, 05/04, page 12 of 544 Pin No. Type Symbol TFP-144 I/O Name and Function I 2 C bus interface (IIC) SCL0 SCL1 ExSCLA * ExSCLB * 14 135 53 51 Input/ Output I 2 C clock I/O pins. The output type is NMOS open-drain output. SDA0 SDA1 ExSDAA * ExSDAB * 17 138 54 52 Input/ Output I 2 C data I/O pins.
CPU210A_0200 20040200 Rev. 1.00, 05/04, page 13 of 544 Section 2 CPU The H8S/2000 CPU is a hi gh-speed ce ntral processin g unit with an internal 32-bit architecture that is upward-c ompatible wit h the H8/3 00 and H8/30 0H CPUs.
Rev. 1.00, 05/04, page 14 of 544 • Two CPU operat ing modes Normal mode Advanced mod e • Power- down state Transition t o power-dow n state by SLEEP i nstruction Selectable CPU clock speed 2.1.1 Differences between H8S/ 2600 CPU and H8S/2000 CP U The differences bet ween the H8S/2600 CPU an d the H8S/ 2000 CPU are as shown below.
Rev. 1.00, 05/04, page 15 of 544 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8 S/2000 CPU has the following en hancements. • More general registers a nd cont rol regist ers Eight 16-bit extended registers and o ne 8-bit cont rol register have been ad ded.
Rev. 1.00, 05/04, page 16 of 544 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: n ormal and advanced. Normal mod e supports a maximum 64-Kbyte address sp ace. Advanced mode supports a maximum 16-Mbyte a ddress space. The mode is selected by the LSI's mode pins.
Rev. 1.00, 05/04, page 17 of 544 H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) Exception vector 1 Exception vector 2 Exception vector table (Reserved for system use) Figure 2.
Rev. 1.00, 05/04, page 18 of 544 2.2.2 Adva nced Mode • Address space Linear access to a maximum address sp ace of 16 Mbytes is possible. • Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit regi sters. They can also be used as the upper 16-bit segments of 32-b it registers or address registers.
Rev. 1.00, 05/04, page 19 of 544 The memory indirect addressing mode (@ @aa:8) employed in the JMP and JSR instructions uses an 8-bit abso lute address included in th e instruction code to sp ecify a memo ry operand that contains a branch a ddress. In advance d mode, the operand is a 32-bit longw ord operand, providing a 32- bit branch address.
Rev. 1.00, 05/04, page 20 of 544 2.3 Address Space Figure 2.5 shows a memo ry map of the H8S/2000 CPU . The H8S/2000 CPU provides linear access to a maximum 64-Kbyte address space in normal mode, an d a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode.
Rev. 1.00, 05/04, page 21 of 544 2.4 Register Configuration The H8S/2000 CPU has the internal registers show n in figure 2.6. There are two types of registers: general regist ers and cont rol registers. Control re gisters are a 24-bit progra m counter (PC ), an 8-bi t extended control register (EXR), and an 8-bit condition code register (CCR).
Rev. 1.00, 05/04, page 22 of 544 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit ge neral registers . These general registers a re all funct ionally alike and can be used as both address re gisters and data regi sters. When a general regist er is used as a data regist er, it can be ac cessed as a 3 2-bit, 16-bit, or 8-bit re gister.
Rev. 1.00, 05/04, page 23 of 544 SP (ER7) Free area Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of t he ne xt instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored.
Rev. 1.00, 05/04, page 24 of 544 2.4.4 Conditi on-Code Re gister (CCR ) This 8-bit re gister co ntains internal CPU status i nformation , including a n interrupt mask bit (I) a nd half-carry (H), negative (N), z ero (Z), o verflow (V), and ca rry (C) flags .
Rev. 1.00, 05/04, page 25 of 544 Bit Bit Name Initial Value R/W Desc ription 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise.
Rev. 1.00, 05/04, page 26 of 544 2.5 Data Formats The H8S/2000 C PU can process 1-bi t, 4-bit BCD, 8- bit (byte), 16-bi t (word), and 32-bit (longword) data. Bit -manipulati on instructio ns operate on 1-bit data b y accessing bit n (n = 0, 1, 2, …, 7) of byte operand data .
Rev. 1.00, 05/04, page 27 of 544 15 0 MSB LSB 15 0 MSB LSB 31 16 MSB 15 0 LSB En Rn ERn: En: Rn: RnH: RnL: MSB: LSB : General register ER General register E General register R General register RH Gene.
Rev. 1.00, 05/04, page 28 of 544 2.5.2 Memory Data Formats Figure 2.10 s hows the dat a formats in mem ory . The H8S/2000 CPU can access word data and longword dat a in memory , but wor d or long word data m ust begin at a n even a ddress.
Rev. 1.00, 05/04, page 29 of 544 2.6 Instruction Set The H8S/2000 CPU ha s 65 types of in structions. Th e instructions are classi fied by functi on as shown in ta ble 2.
Rev. 1.00, 05/04, page 30 of 544 2.6.1 Table of Instructions Cl assi fied by Function Tables 2.3 to 2.10 summarize th e instructi ons in each functional cate gory.
Rev. 1.00, 05/04, page 31 of 544 Table 2.3 Data Transfer Instructions Instruction Size * 1 Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers o r between a general register and memory, or moves immediate data to a genera l register.
Rev. 1.00, 05/04, page 32 of 544 Table 2.4 Arithmetic Operations Instructions (1) Instruction Size * Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on da ta in t wo general registers, or on immediate data and data in a gen eral register.
Rev. 1.00, 05/04, page 33 of 544 Table 2.4 Arithmetic Operations Instructions (2) Instruction Size * 1 Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two gene ral registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
Rev. 1.00, 05/04, page 34 of 544 Table 2.5 Logic Oper ati ons Instructions Instruction Size * Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation o n a general register and anoth er general register or immediate data.
Rev. 1.00, 05/04, page 35 of 544 Table 2.7 Bit Manipulation Instructions (1) Instruction Size * Function BSET B 1 → (<bit-No.> of <EAd>) Sets a specified bit in a general regist er or memory operand to 1. The bit number is specified by 3-bit immediate data or the l ower three bits of a general register.
Rev. 1.00, 05/04, page 36 of 544 Table 2.7 Bit Manipulation Instructions (2) Instruction Size * Function BXOR B C ⊕ (<bit-No.> of <EAd>) → C Logically exclusive-ORs the carry flag with a specifie d bit in a general register or memory operand and stores the result in the ca rry flag.
Rev. 1.00, 05/04, page 37 of 544 Table 2.8 Branch Instructions Instruction Size Function Branches to a specified address if a specified condition is tr ue.
Rev. 1.00, 05/04, page 38 of 544 Table 2.9 System Control Instructions Instruction Size * Function TRAPA — Starts trap-instruct ion excepti on handling. RTE — Returns from an exception-handli ng routine. SLEEP — Causes a transition to a power-down state.
Rev. 1.00, 05/04, page 39 of 544 2.6.2 Basic Instruction Formats The H8S/2000 CPU instruct ions consis t of 2-byte (1-word) uni ts. An i nstruction consist s of an operation fi eld (op) , a register field (r), a n eff ective address extensi on (EA), and a condition field (cc).
Rev. 1.00, 05/04, page 40 of 544 2.7 Addressing Modes and Effective Address Calculation The H8S/2000 CPU support s the eight addres sing modes listed in t able 2.11. Each instruct ion uses a subset of these addressing m odes. Arithmetic and logic operations instru ctions can use the register direct and immediate a ddressing modes.
Rev. 1.00, 05/04, page 41 of 544 2.7.3 Register Indirect with Displacem ent—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement cont ained in the instruction code is added to an address register (ERn) specified by the register field of the instru ct ion, and t he sum gives t he address of a memory operand.
Rev. 1.00, 05/04, page 42 of 544 2.7.6 Immediate—#xx:8, #x x:16, or # xx:32 The 8-bit (# xx:8), 16 -bit (#xx: 16), or 32-bi t (#xx:32) imme diate data co ntained in an i nstruction code can be us ed directly as an opera nd. The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in th eir instruction codes.
Rev. 1.00, 05/04, page 43 of 544 2.7.8 Memory Indirect —@@aa:8 This mode can be used by the JMP and JSR instructions . The instructi on code cont ains an 8- bit absolute address specifying a memo r y operand which cont ains a bra nch addres s.
Rev. 1.00, 05/04, page 44 of 544 2.7.9 Effective Address Calculation Table 2.13 indicates how effec tive addresses are calculated in each addressing mode. In normal mode, the uppe r 8 bits of the effecti ve address are i gnored in or der to gene rate a 16-bit address.
Rev. 1.00, 05/04, page 45 of 544 Table 2.13 Effective Ad dress Calculation (2) No 5 op 31 23 31 0 Don't care abs @aa:8 7 H'FFFF op 31 23 31 0 Don't care @aa:16 op @aa:24 @aa:32 abs 15 1.
Rev. 1.00, 05/04, page 46 of 544 2.8 Processing States The H8S/2000 CPU ha s four main processing stat es: the reset state, exception ha ndling state, program execu tion state, an d prog ram stop state.
Rev. 1.00, 05/04, page 47 of 544 Program execution state Sleep mode Exception-handling state Software standby mode RES = high Reset state * 1 STBY = high, RES = low Hardware standby mode * 2 Power-down state * 3 Notes: 1. 2. 3. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low.
Rev. 1.00, 05/04, page 48 of 544 2.9 Usage Notes 2.9.1 Note on TAS Instructi on Usage When using t he TAS instructi on, use register s ER0, ER1, ER 4 and ER5. The TAS instructi on is not generated by the Renesas Tech nology H8S an d H8/300 series C/C++ compilers.
Rev. 1.00, 05/04, page 49 of 544 2.9.4 EE PMOV Instruction 1. EEPMOV is a block-transfer in struction and tran sfers the byte size of da ta indicated by R4L, which starts from the address indicated by R5, to the address indicated by R6. R6 R6 + R4L R5 R5 + R4L 2.
Rev. 1.00, 05/04, page 50 of 544.
Rev. 1.00, 05/04, page 51 of 544 Section 3 MCU Operating Modes 3.1 MCU Operating Mode Selection This LSI has two operating modes (mode s 2 and 3). The operatin g mode is dete rmined by t he setting of t he mode pins (MD1 and M D0). Tabl e 3.1 sho ws the MCU operating m ode sel ection.
Rev. 1.00, 05/04, page 52 of 544 3.2 Register Descriptions The following registers are related to th e operating mode. Mode contr ol register (MDCR) System control register (SYSCR) Serial timer control register (STCR) 3.2.1 Mode Control Re gi ster ( MD CR ) MDCR is used to monitor th e current operating mode.
Rev. 1.00, 05/04, page 53 of 544 3.2.2 System C ontrol Register (SYS CR) SYSCR selects a s ystem pin funct ion, moni tors a reset source, selects the interrupt control mode and the detection edge for .
Rev. 1.00, 05/04, page 54 of 544 Bit Bit Name Initial Value R/W Description 1 HIE 0 R/W Host Interface Enab le Controls CPU access to the keyboard matr ix interrupt, input pull-up MOS control register.
Rev. 1.00, 05/04, page 55 of 544 3.2.3 Serial Timer Co ntrol Register (STCR) STCR enables or disables regi ster access, IIC operating mode, and on-c hip flash memory, and selects the input clock of the timer counter.
Rev. 1.00, 05/04, page 56 of 544 Bit Bit Name Initial Value R/W Description 3 FLSHE 0 R/W Flash Memory Control R egister Enable Enables or disables CPU acc ess for flash memory registers (FLMCR1, FLMC.
Rev. 1.00, 05/04, page 57 of 544 3.4 Address Map Figures 3.1 and 3.2 sh ow the address map in each operating mode. Mode 2 (EXPE = 0) Advanced mode Single-chip mode On-chip ROM Internal I/O registers 2.
Rev. 1.00, 05/04, page 58 of 544 Mode 2 (EXPE = 0) Advanced mode Single-chip mode On-chip ROM Internal I/O registers 2 On-chip RAM Internal I/O registers 1 On-chip RAM (128 bytes) Internal I/O registe.
Rev. 1.00, 05/04, page 59 of 544 Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 i ndicates, except ion handl ing may be caused b y a reset, interr upt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.
Rev. 1.00, 05/04, page 60 of 544 4.2 Exception Sources and Exception Vector Table Different vector a ddresses are assigned to differen t exception sources.
Rev. 1.00, 05/04, page 61 of 544 4.3 Reset A reset has the highest exceptio n priority. When the RES pin goes low, al l processing hal ts and this LSI enters the reset. To ensure that th is LSI is reset, hold the RES pin low for at least 20 ms at power-on.
Rev. 1.00, 05/04, page 62 of 544 4.3.2 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a prog ram crash. To prevent this, all interrupt requests, including NM I, are disa bled immediat ely after a re set.
Rev. 1.00, 05/04, page 63 of 544 4.4 Interrupt Exception Handling Interrupts are controlled by the interrupt contro ller. The sources to start interrupt exception handling are extern al interrupt sources (NMI, IRQ7 to IRQ0, KIN15 to KIN 0, and WU E7 to WUE0) and i nternal i nterrupt sources from t he on-c hip periphe ral modules .
Rev. 1.00, 05/04, page 64 of 544 4.6 Stack Status after Exception Handling Figure 4.2 s hows the stack after completion of trap instruction exception handling and interrupt exception hand ling. CCR CCR * PC (16 bits) Note: Ignored on return. Normal mode Advanced mode CCR PC (24 bits) SP SP Figure 4.
Rev. 1.00, 05/04, page 65 of 544 4.7 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwo rds, an d the value of the stac k pointer (SP: ER7) should al ways be kept e ven.
Rev. 1.00, 05/04, page 66 of 544.
Rev. 1.00, 05/04, page 67 of 544 Section 5 Interrupt Controller 5.1 Features • Two interrupt control mo des Any of two i nterrupt c ontrol modes can be s et by mea ns of the INTM 1 and INTM0 bit s in the system control register (SYSC R).
Rev. 1.00, 05/04, page 68 of 544 SYSCR NMI input IRQ input Internal interrupt request WOVI0 to IBFI3 NMIEG INTM1, INTM0 NMI input IRQ input ISR ISCR IER ICR Interrupt controller Priority check Interru.
Rev. 1.00, 05/04, page 69 of 544 5.3 Register Descriptions The interrupt controller has the follo wing register s. For details on the system contro l register (SYSCR), refer to section 3.
Rev. 1.00, 05/04, page 70 of 544 Table 5.2 Corre sponde nce between Interrupt Source and ICR Register Bit Bit Name ICRA ICRB ICRC 7 ICRn7 IRQ0 — — 6 ICRn6 IRQ1 FRT SCI_1 5 ICRn5 IRQ2, IRQ3 — —.
Rev. 1.00, 05/04, page 71 of 544 5.3.3 Break Addres s Registers A to C (BAR A to BAR C) The BAR registers specify an addres s that is to be a break address. An ad dress in whic h the first byte of an instruction exists shou ld be set as a break address.
Rev. 1.00, 05/04, page 72 of 544 5.3.4 IRQ Sense Control Register s (ISCRH, ISCRL ) The ISCR registers select the source that generates an inte rrupt re quest at pins IR Q7 to IRQ0 .
Rev. 1.00, 05/04, page 73 of 544 5.3.5 IRQ Enable Register (IE R) IER control s the ena bling and di sabling of interrupt requests IRQ7 to IR Q0. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2.
Rev. 1.00, 05/04, page 74 of 544 • KMIMRA Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10 KMIMR9 KMIMR8 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Keyboard Matrix In terrupt Mask 15 to 8 These bits enable or disable a key-sensing in put interrupt request (KIN15 to KIN8).
Rev. 1.00, 05/04, page 75 of 544 Figure 5.2 s hows the rela tionship between inte rrupts IR Q7 and IRQ 6, interrupt s KIN15 to KIN0, interrupts WUE7 to WUE0, and registers KMIMRA, KM IMR, and WUEMRB .
Rev. 1.00, 05/04, page 76 of 544 5.4 Interrupt Sources 5.4.1 Extern al Interrupts There a re four typ es of externa l interrupts: NMI, IRQ7 to IRQ0, KIN15 to KIN0 and WU E7 to WUE0. WUE7 to WUE0 and KIN15 to KIN8 share the IRQ7 interrupt sou rce, and KIN7 to KIN0 share the IRQ6 interr upt source.
Rev. 1.00, 05/04, page 77 of 544 When pin IRQ7 is used as an IRQ7 inte rrupt pin , set all of bits KMIM R15 to KM IMR8 and WUEMR7 to WUEMR0 to 1. If any of these bits is cleared to 0, IRQ7 interrupt input from the IRQ7 pin will b e ignored.
Rev. 1.00, 05/04, page 78 of 544 5.5 Interrupt Exception Handling Vector Table Table 5.3 lists interr upt excepti on handling sources, vect or addresses, and int errupt priori ties. For default priorities, the lower the vector number, th e higher the priority.
Rev. 1.00, 05/04, page 79 of 544 Vector Address Origin of Interrupt Source Name Vector Number Normal Mode Advanced Mode ICR Priority TMR_0 CMIA0 (Compare match A) CMIB0 (Compare match A) OVI0 (Overflo.
Rev. 1.00, 05/04, page 80 of 544 5.6 Interrupt Control Modes and Interrupt Opera tion The interru pt cont roller has two mode s: Interr upt contr ol mode 0 and int errupt co ntrol mo de 1. Interrupt operations differ de pending o n the inte rrupt contr ol mode.
Rev. 1.00, 05/04, page 81 of 544 7. The CPU generates a vector address for the accepted interrupt and starts e xecution of the interrupt ha ndling routine at t he address indi cated by the co ntents of the vector ad dress in the vector table.
Rev. 1.00, 05/04, page 82 of 544 5.6.2 Interrupt Control Mode 1 In interrupt control mod e 1, mask control is app lied to three levels fo r IRQ and on -chip periphe ral module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting .
Rev. 1.00, 05/04, page 83 of 544 Figure 5.6 shows a flowchart of the i nterrupt acceptance operation. 1. If an int errupt so urce occurs when the c orrespon ding interr upt enabl e bit is set to 1, an interrupt request is sent to the in terrupt controller.
Rev. 1.00, 05/04, page 84 of 544 Program excution state Interrupt generated? NMI An interrupt with interrupt control level 1? IRQ0 IRQ1 IFBFI3 IRQ0 IRQ1 IFBFI3 UI = 0 Save PC and CCR I 1, UI 1 Read ve.
Rev. 1.00, 05/04, page 85 of 544 5.6.3 Interrupt Exception Handling Sequence Figure 5.7 s hows the inter rupt exceptio n handling sequence. T he example shown is f or the case where inte rrupt contr ol mode 0 is set in a dvan ced mode, an d the program area and stack area are in on-chip memory.
Rev. 1.00, 05/04, page 86 of 544 5.6.4 Interrupt Response Times Table 5.5 sho ws interrupt re sponse times − the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling rou tine. The execution statu s symbols used i n table 5.
Rev. 1.00, 05/04, page 87 of 544 5.7 Address Break 5.7.1 Features This LSI can determine t he specific address prefet ch by the CPU to ge ne rate an address break interrupt b y setting ABRKCR an d BAR. If a n address brea k interrupt is generate d, the add ress break interrupt excep tion handling is performed.
Rev. 1.00, 05/04, page 88 of 544 5.7.3 Operatio n If the CPU prefetches an a ddress specified in BAR by setting ABRKCR and BAR, an address break interr upt can be ge nerated. This a ddress break f unction gene rates an i nterrupt re quest to the interrupt controller at pr efetch, and determines the priority by the interrupt co ntroller.
Rev. 1.00, 05/04, page 89 of 544 Figure 5.9 s hows an exam ple of add ress timing. Instruction fetch Address bus Break request signal Break point NOP instruction is executed at break point address H'0312 and following address H'0314. Fetching is performed from address H'0316 after exception handling ends.
Rev. 1.00, 05/04, page 90 of 544 5.8 Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an inte rrupt enabl e bit is cleared to 0 to di sable interr upt requests , the disabl ing becomes effective after execution of the inst ruction.
Rev. 1.00, 05/04, page 91 of 544 5.8.2 Instructions th at Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After an y of these instructions are executed , all interrupts including NMI are disabled and the n ext instruction is always executed.
Rev. 1.00, 05/04, page 92 of 544.
Rev. 1.00, 05/04, page 93 of 544 Section 6 Bus Controller (BSC) Since this LSI does not have an ext ernally exten ded function, i t does not have an on-chi p bus controller (BSC). Considering the softw are compatibility with similar products, you must b e careful to set appropriate values to the cont rol registers for the bu s controller.
Rev. 1.00, 05/04, page 94 of 544 6.1.2 Wait Sta te Control Re gister (W SCR) Bit Bit Name Initial Value R/W Desc ription 7 6 — — 0 0 R/W R/W Reserved The initial value should not be chan ged. 5 ABW 1 R/W Bus Width Cont rol The initial value should not be chan ged.
Rev. 1.00, 05/04, page 95 of 544 Section 7 I/O Ports This LSI has fifteen I/O ports (ports 1 to 6, 8, 9, and A to G), and one input-only port (port 7 ). Table 7.1 is a summary of the port f unctions. The pins of eac h port also have othe r functio ns.
Rev. 1.00, 05/04, page 96 of 544 Table 7.1 Port Functions Port Description Mode 2and Mode 3 I/O Status Port 1 General I/O port also functioning as PWM output pins P17/PW7 P16/PW6 P15/PW5 P14/PW4 P13/P.
Rev. 1.00, 05/04, page 97 of 544 Port Description Mode 2and Mode 3 I/O Status Port 6 General I/O port also functioning as interrupt input, FRT input/output, TMR_X and TMR_Y input/output, and key- sens.
Rev. 1.00, 05/04, page 98 of 544 Port Description Mode 2and Mode 3 I/O Status Port A General I/O port also functioning as key-sense interrupt input and keyboard buffer controller input/output pins PA7.
Rev. 1.00, 05/04, page 99 of 544 Port Description Mode 2and Mode 3 I/O Status Port E General I/O port PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 On-chip input pull- up MOSs Port F General I/O port also functioni.
Rev. 1.00, 05/04, page 100 of 544 7.1 Port 1 Port 1 is an 8-bit I/ O port. Po rt 1 pins also funct ion as PWM output pi ns. Port 1 has the followi ng registers. • Port 1 data direct ion register ( P1DDR) • Port 1 data register (P1DR) • Port 1 pull-up MOS control register (P1PCR) 7.
Rev. 1.00, 05/04, page 101 of 544 7.1.3 Port 1 Pull-U p MOS Con trol Regi ster (P1P CR) P1PCR cont rols the on/ off state of the port 1 on-chip i nput pul l-up MOSs .
Rev. 1.00, 05/04, page 102 of 544 7.1.5 Port 1 Input Pull-Up MOS Port 1 has an on-chip i nput pu ll-up MOS f unction t hat can be controlled by software. T his input pull-up MOS funct ion can be specified as on or off on a bit-by-bit basis. Table 7.2 summarizes the input pull-up MOS states.
Rev. 1.00, 05/04, page 103 of 544 7.2.2 Port 2 Da ta Register (P 2DR)) P2DR stores outpu t data for por t 2. Bit Bit Name Initial Value R/W Description 7 P27DR 0 R/W 6 P26DR 0 R/W 5 P25DR 0 R/W 4 P24D.
Rev. 1.00, 05/04, page 104 of 544 7.2.5 Port 2 Input Pull-Up MOS Port 2 has an on-chip i nput pu ll-up MOS f unction t hat can be controlled by software. T his input pull-up MOS funct ion can be specified as on or off on a bit-by-bit basis. Table 7.3 summarizes the input pull-up MOS states.
Rev. 1.00, 05/04, page 105 of 544 7.3.2 Port 3 Da ta Register (P 3DR) P3DR stores outpu t data of port 3 . Bit Bit Name Initial Value R/W Description 7 P37DR 0 R/W 6 P36DR 0 R/W 5 P35DR 0 R/W 4 P34DR .
Rev. 1.00, 05/04, page 106 of 544 7.3.4 Pin Functions • P37/SERIRQ, P36/LCLK, P35/ LRESET , P34/ LFRAME , P 33/LA D3, P32/ LAD2, P31/L AD1, P30/LAD0 The pin functi on is swi tched as shown below according t o the combin ation of the LPC3E to LPC1E bits in HICR0 of the host interface (LPC) and the P3nDDR bit.
Rev. 1.00, 05/04, page 107 of 544 7.4 Port 4 Port 4 is an 8 -bit I/ O port. Po rt 4 pins also functi on as TMR_0 an d TMR_1 I/O pins, a nd the IIC _1 I/O pin. T he output type of P 42 is NM OS push- pull out put. The out put t ype of SDA 1 is NMO S open-drain o utput.
Rev. 1.00, 05/04, page 108 of 544 7.4.3 Pin Functions • P47 The pin functi on is swi tched as shown below accor ding to the c ombination of t he P47DDR bit. P47DDR 0 1 Pin Function P47 input pin P47 output pin • P46 The pin function is switched as shown bel ow acc ording t o the com bination of t he P46DDR bit.
Rev. 1.00, 05/04, page 109 of 544 • P43/TMCI1 The pin functi on is swi tched as shown below accor ding to t he state of the P43DDR bit . P43DDR 0 1 P43 input pin P43 output pin Pin Function TMCI1 input pin * Note: * When the external clock is selected by the bi ts CKS2 to CKS0 in TCR1 of TMR_1, this pin is used as the TMCI1 input pin.
Rev. 1.00, 05/04, page 110 of 544 7.5 Port 5 Port 5 is a 3-bit I/O port. Port 5 pins also funct ion as SCI_ 1 extended I/ O pins, a nd the I IC_0 I/O pin. P52 an d ExSCK1 are NMOS p ush-pull outputs, a nd SCL0 is an NMOS o pen-drain o utput. Port 5 has t he followi ng registers.
Rev. 1.00, 05/04, page 111 of 544 7.5.3 Pin Functions • P52/ExSCK1*/SCL0 The pin functi on is swi tched as shown below accor ding to t he combination of t he C/ A bit in SMR of SCI_1, the CKE0 and CKE1 bits in SCR, the SPS1 bit* 1 in SPSR, the ICE bit in ICCR of IIC_0, t he IIC0AS a nd the IIC 0BS bits in PGCTL* 2 , and the P52DDR bit.
Rev. 1.00, 05/04, page 112 of 544 • P50/ExTxD1 The pin function is switched as shown bel ow acc ording to the combination of the TE b it in SCR of SCI_ 1, the SPS 1 bit* in SP SR, and t he P50DDR bit.
Rev. 1.00, 05/04, page 113 of 544 7.6.2 Port 6 Data Register (P6DR) P6DR stores outpu t data for por t 6. Bit Bit Name Initial Value R/W Description 7 P67DR 0 R/W 6 P66DR 0 R/W 5 P65DR 0 R/W 4 P64DR 0.
Rev. 1.00, 05/04, page 114 of 544 7.6.4 System C ontrol Register 2 (SYSC R2) SYSCR2 is not available in this LSI although origin ally designed to control the por t 6 operations. Bit Bit Name Initial Value R/W Description 7 to 0 — All 0 R/W Reserved The initial value should not be chan ged.
Rev. 1.00, 05/04, page 115 of 544 • P66/FTOB/ KIN6 / IRQ6 The pin functi on is swi tched as shown below accor ding to t he combination o f the OEB bi t in TOCR of the F RT and the P 66DDR bi t.
Rev. 1.00, 05/04, page 116 of 544 • P61/FTOA/ KIN1 The pin function is switched as shown bel ow acc ording to the combination of the OEA bit in TOCR of the F RT, and the P6 1DDR bit . OEA 0 1 P61DDR 0 1 — P61 input pin P61 output pin FTOA input pin Pin Function KIN1 input pin * Note: * This pin can always be used as the KIN1 in put pin.
Rev. 1.00, 05/04, page 117 of 544 7.7 Port 7 Port 7 is an 8 -bit i nput only p ort. Port 7 pins al so function as the A/D c onverter a nalog input pins. Port 7 has t he followi ng register. • Port 7 input data register (P7PI N) 7.7.1 Port 7 Input Data Regis ter (P7P IN ) P7PIN reflects the pin states of port 7.
Rev. 1.00, 05/04, page 118 of 544 7.8 Port 8 Port 8 is an 8-bit I/O port. P ort 8 pins also f unction as SCI_1 I/ O pins, the IIC_1 I/O pins, LPC I/O pins, and interrupt input pins. The output t ype of P8 6 and SC K1 is NMOS push-pul l outp ut. The output type of SCL1 i s NMOS open-drai n output an d direct bu s driving is enable d.
Rev. 1.00, 05/04, page 119 of 544 7.8.3 Pin Functions • P86/ IRQ5 /SCK1/SCL1 The pin functi on is swi tched as shown below accor ding to t he combination of t he C/ A bit in SMR of SCI_1, the CKE0 and CKE1 bits in SCR, the SPS1 bit* 2 in SPSR, the ICE bit in ICCR of IIC_1, t he IIC1AS a nd the IIC 1BS bits in PGCTL* 3 , and the 86DDR bit.
Rev. 1.00, 05/04, page 120 of 544 • P84/ IRQ3 /TxD1 The pin function is switched as shown bel ow acc ording to the combination of the TE b it in SCR of SCI_1, the SPS1 bit* 2 in SPSR, and t he P84DDR bit.
Rev. 1.00, 05/04, page 121 of 544 • P81/GA20 The pin function is switched as shown b elow according to the combin ation of the FGA20E bit in HICR0 an d the P81D DR bit.
Rev. 1.00, 05/04, page 122 of 544 7.9 Port 9 Port 9 is an 8-bit I/ O port. Po rt 9 pins also fu nction as the i nterrupt in put pins, IIC_0 I/ O pin, subclock inp ut pin, an d system cloc k ( φ ) ou tput pin. P97 is an NMOS p ush-pull output. SDA0 is an NMOS open- drain output, and has direct bus drive capability.
Rev. 1.00, 05/04, page 123 of 544 7.9.3 Pin Functions • P97/SDA0 The pin functi on is swi tched as shown below accor ding to t he combination o f the ICE bi t in ICCR of IIC_0, the IIC0AS and the IIC0BS bits in PGCTL*, and the P97DDR bit.
Rev. 1.00, 05/04, page 124 of 544 • P92/ IRQ0 The pin functi on is swi tched as shown below according t o the state of the P92DDR bit. P92DDR 0 1 P92 input pin P92 outp ut pin Pin Function IRQ0 input pin * Note: * When bit IRQ0E in IER is set to 1, this pin is used as the IRQ0 input pin.
Rev. 1.00, 05/04, page 125 of 544 7.10 Port A Port A is an 8-bit I/ O port. P ort A pi ns also funct ion as keyboard buffer cont roller I/O pins, and key-sense interr upt input pins. Port A inpu t/output operates by V ccB power independen t from the Vcc power.
Rev. 1.00, 05/04, page 126 of 544 7.10.3 Port A Input Data Regis ter (PA P IN ) PAPIN indicates the port A state. Bit Bit Name Initial Value R/W Description 7 PA7PIN Undefined * R 6 PA6PIN Undefined *.
Rev. 1.00, 05/04, page 127 of 544 • PA5/ KIN13 /PS2 BD The pin functi on is swi tched as shown below accor ding to t he combination o f the KBIOE bit in KBCRH_1 of the keyboard buffer controller, and the PA5DDR bit.
Rev. 1.00, 05/04, page 128 of 544 • PA2/ KIN10 /PS2A C The pin functi on is swi tched as shown below accor ding to t he combination o f the KBIOE bit in KBCRH_0 of the keyboard buffer controller, and the PA2DDR bit.
Rev. 1.00, 05/04, page 129 of 544 7.11 Port B Port B is a n 8-bit I/O port. Port B pi ns also h ave LPC in put/out put pins , and wake up event interrupt i nput pi ns functi on. Port B has the followi ng regist ers. • Port B data direction register (PBD DR) • Port B output data register (PBODR) • Port B input data register (PBPIN) 7.
Rev. 1.00, 05/04, page 130 of 544 7.11.3 Port B Input Data Regis ter (PBPIN) PBPIN indicates the port B state. Bit Bit Name Initial Value R/W Description 7 PB7PIN Undefined * R 6 PB6PIN Undefined * R .
Rev. 1.00, 05/04, page 131 of 544 • PB0/ WUE0 / LSMI The pin functi on is swi tched as shown below accor ding to t he combination of t he LSMIE bit in HICR0 of the host interface (LPC) and the PB0DDR bit. LSMIE 0 1 PB0DDR 0 1 0 * 1 PB0 input pin PB0 output p in LSMI output pin Pin Function WUE0 input pin * 2 , LSMI input pin * 2 Notes: 1.
Rev. 1.00, 05/04, page 132 of 544 7.12 Ports C, D Port C and p ort D are t wo sets of 8-bit I/O p orts. Port C and port D have th e followi ng registers.
Rev. 1.00, 05/04, page 133 of 544 7.12.2 Port C and Port D Output D ata Registers (PCODR, P DODR) PCODR and P DODR store output data for the pins on p orts C and D.
Rev. 1.00, 05/04, page 134 of 544 Bit Bit Name Initial Value R/W Description 7 PD7PIN Undefi ned * R 6 PD6PIN Undefi ned * R 5 PD5PIN Undefi ned * R 4 PD4PIN Undefi ned * R 3 PD3PIN Undefi ned * R 2 PD2PIN Undefi ned * R 1 PD1PIN Undefi ned * R 0 PD0PIN Undefi ned * R PDPIN indicates the port D state.
Rev. 1.00, 05/04, page 135 of 544 7.12.5 Pin Functions DDR 0 1 NOCR — 0 1 ODR 0 1 0 1 0 1 N-ch. driver OFF ON OFF ON OFF P-ch. driver OFF OFF ON OFF Input pull-up MOS OFF ON OFF Pin function Input pin Output pin 7.
Rev. 1.00, 05/04, page 136 of 544 7.13 Ports E, F Ports E and F are two sets of 8-bit I/O port s. Port F als o functions as I/O pi ns for TMR_X *, TMR_Y*, TMR_A, and TMR_B.
Rev. 1.00, 05/04, page 137 of 544 7.13.2 Port E and Port F Output Data Registers (PEODR, PFODR) PEODR and PFODR store output data fo r the pins on ports E and F.
Rev. 1.00, 05/04, page 138 of 544 7.13.3 Port E and Port F Inpu t Data Registers (PEPIN, PFPIN) Reading PEPIN and PFPIN al wa ys retur ns the pin states.
Rev. 1.00, 05/04, page 139 of 544 • PF6/ExTMOX The pin functi on is swi tched as shown below accor ding to t he combination o f the IOSX bi t* in TCRXY of TMR_X, the OS3 to OS0 bits in TCSR_X, and the PF6DDR bit.
Rev. 1.00, 05/04, page 140 of 544 • PF2/TMOA The pin function is switched as shown bel ow acc ording t o the com bination of t he OS3 t o OS0 bits in TCSR_A of TMR_A and the PF2DDR bit.
Rev. 1.00, 05/04, page 141 of 544 Bit Bit Name Initial Value R/W Description 7 PF7NOCR 0 R/W 6 PF6NOCR 0 R/W 5 PF5NOCR 0 R/W 4 PF4NOCR 0 R/W 3 PF3NOCR 0 R/W 2 PF2NOCR 0 R/W 1 PF1NOCR 0 R/W 0 PF0NOCR 0 R/W 0: CMOS (p-channel driver enabled) 1: N-channel open drain (p-ch annel driver disabled) 7.
Rev. 1.00, 05/04, page 142 of 544 7.14 Port G Port G is an 8-bit I/O port. Po rt G pins als o function a s IIC_0 an d IIC_1 I/ O pins . The output type of port G is NMOS p ush-pull output. T he output t ype of E xSCLB*, ExS DAB*, ExSC LA*, and ExSDAA* is NMOS ope n-drain o utput and t he pins can di rectly drive the bus.
Rev. 1.00, 05/04, page 143 of 544 7.14.2 Port G Outpu t Data Re gister (PGO DR) PGODR stores output data for th e pins on port G. Bit Bit Name Initial Value R/W Description 7 PG7ODR 0 R/W 6 PG6ODR 0 R.
Rev. 1.00, 05/04, page 144 of 544 7.14.4 Pin Functions • PG7/ExSCLB The pin function is switched as shown bel ow acc ording t o the combinat ion of the IIC1BS and the IIC0BS bits in PGCTL of the IIC* and the PG7 DDR bit.
Rev. 1.00, 05/04, page 145 of 544 • PG3, PG2, PG1, PG0 The pin functi on is swi tched as shown below accor ding to t he state of the PGnDDR bi t. PGnDDR 0 1 Pin Function PGn input pin PGn output pin [Legend] n = 3 to 0 7.
Rev. 1.00, 05/04, page 146 of 544.
PWM0800B_0001 20040200 Rev. 1.00, 05/04, page 147 of 544 Section 8 8-Bit PWM Timer (PWM) This LSI has an on-c hip pul se width m odulati on (PWM) ti mer with ei ght out puts. Eig ht output waveforms are generated f rom a commo n time base, ena bling PWM o utput with a high carrier frequency t o be produced using pulse di vision.
Rev. 1.00, 05/04, page 148 of 544 8.2 Input/Output Pins Table 8.1 shows the PWM o utput pins. Table 8.1 Pin Configuration Name Abbreviation I/O Function PWM output 7 to 0 PW 7 to PW0 Output PWM timer pulse output 7 to 0 8.3 Register Descriptions The PWM has the following registers.
Rev. 1.00, 05/04, page 149 of 544 8.3.1 PWM Registe r Select (PWS L) PWSL is use d to select the input clock and t he PWM data re gister. Bit Bit Name Initial Value R/W Description 7 6 PWCKE PWCKS 0 0.
Rev. 1.00, 05/04, page 150 of 544 Table 8.2 Internal Cloc k Selection PWSL PCSR PWCKE PWCKS PWCKC PWCKB PWCKA Description 0 — — — — Clock input is d isabled (Initial val ue) 1 0 — — — φ.
Rev. 1.00, 05/04, page 151 of 544 8.3.2 PWM Data Registers 7 to 0 (PW DR 7 t o PWD 0) PWDR are 8-bit readable/writab le registers. The PWM has eight PWM dat a registers. Each PWDR specifi es the duty cyc le of the basic pulse to be output, and t he number of additi onal pulses.
Rev. 1.00, 05/04, page 152 of 544 8.3.4 PWM Output E nable Regi ster A (PWOE RA) PWOERA switches betw een PWM output and port output. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 OE7 OE6.
Rev. 1.00, 05/04, page 153 of 544 8.4 Operation The upper fo ur bits of PWDR specif y the duty c ycle of the basi c pulse as 0/16 to 15/16 with a resolution o f 1/16.
Rev. 1.00, 05/04, page 154 of 544 The lower four bits of PW DR specify the posit ion of pulses added to the 16 basic pul ses. An additional pul se adds a hi gh period (w hen OS = 0) wi th a width equal to t he resolution bef ore the rising edge o f a basic pulse.
Rev. 1.00, 05/04, page 155 of 544 8.4.1 PWM Setting Example : Pulse added 1-conv ersion cycle Combination of the basic pulse and added pulse outputs 0/256 to 255/256 of dudty cycle as low ripple wave form.
Rev. 1.00, 05/04, page 156 of 544 8.5 Usage Notes 8.5.1 Module Stop Mode Setting PWM operation ca n be enabl ed or disa bled by the mo dule stop co ntrol regist er. In the i nitial st ate, PWM operation i s disable d. Access to PWM registers is e nabled when module st op mode is cancelled.
TIM8FR1A_0100200 20700 Rev. 1.00, 05/04, page 157 of 544 Section 9 16-Bit Fr ee-Running Timer (FRT) This LSI has an on-c hip 16-b it free-runnin g timer (F RT). The FRT ope rates on the basis of the 16- bit free-run ning counter (F RC), and outputs tw o independent w aveforms, and measures the inpu t pulse wi dth and e xternal cloc k periods .
Rev. 1.00, 05/04, page 158 of 544 Figure 9.1 s hows a bl ock diagra m of the FR T. Clock selector Clock Compare-match A OCRA Comparator A Internal data bus FRC Comparator B OCRB ICRA ICRB ICRC ICRD TC.
Rev. 1.00, 05/04, page 159 of 544 9.2 Input/Output Pins Table 9.1 list s the FRT inp ut and output pins. Table 9.1 Pin Configuration Name Abbreviation I/O Function Counter clock input pin FTCI Input F.
Rev. 1.00, 05/04, page 160 of 544 9.3.1 Free-Running Counter (FRC) FRC is a 16-bit readable/writable up-counter. Th e clock source is selected by bits CKS1 and CKS0 in TCR. FRC can be cleared by compar e-match A. When FRC overf lows from H'FFFF to H'0000, the overflow flag bit (OVF) in TCSR is set to 1.
Rev. 1.00, 05/04, page 161 of 544 9.3.4 Output Com pare Regis ters AR and AF (OCRAR, O CRAF) OCRAR and OCRAF are 16-bit readab le/writable registers. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use of OCRAR a nd OCR AF.
Rev. 1.00, 05/04, page 162 of 544 9.3.6 Timer Interrupt En able Register (TIER) TIER enables and disables interrupt request s. Bit Bit Name Initial Value R/W Description 7 ICIAE 0 R/W Input Capture Interrupt A Enable Selects whether to enable input capture interr upt A request (ICIA) when input capture flag A (ICFA) in TCSR is set to 1.
Rev. 1.00, 05/04, page 163 of 544 Bit Bit Name Initial Value R/W Description 2 OCIBE 0 R/W Output Compare Interrupt B Enable Selects whether to enable output compar e interrupt B request (OCIB) when output compare flag B (OCFB) in TCSR is set to 1.
Rev. 1.00, 05/04, page 164 of 544 Bit Bit Name Initial Value R/W Description 6 ICFB 0 R/(W) * Input Capture Flag B This status flag indicates that the FRC value has been transferred to ICRB by means of an input capture signal.
Rev. 1.00, 05/04, page 165 of 544 Bit Bit Name Initial Value R/W Description 3 OCFA 0 R/(W) * Output Compare Flag A This status flag indicates that the FRC value matches the OCRA value.
Rev. 1.00, 05/04, page 166 of 544 9.3.8 Timer Contr ol Register (T CR) TCR selects the rising or falling edge of the inpu t cap ture signals, enables the inpu t capture buffer mode, and selects the FRC clock source.
Rev. 1.00, 05/04, page 167 of 544 Bit Bit Name Initial Value R/W Description 1 0 CKS1 CKS0 0 0 R/W Clock Sel ect 1, 0 Select clock source for FRC. 00: φ /2 internal clock source 01: φ /8 internal clock source 10: φ /32 internal clock source 11: External clock source (counting at FTCI rising edge) 9.
Rev. 1.00, 05/04, page 168 of 544 Bit Bit Name Initial Value R/W Description 4 OCRS 0 R/W Output Compare Register Select OCRA and OCRB share the same address. When this address is accessed, the OCRS bit selects which register is accessed. The operation of OCRA or OCRB is not affected.
Rev. 1.00, 05/04, page 169 of 544 9.4 Operation 9.4.1 Pulse Output Figure 9.2 sho ws an example of 50% -duty p ulses output wi th an arbitrary pha se differenc e. When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and OLVLB bits are inverted by softwa re.
Rev. 1.00, 05/04, page 170 of 544 9.5 Operation Timing 9.5.1 FRC Increment T iming Figure 9.3 s hows the FRC i ncrement t iming with a n internal cl ock source. Fig ure 9.4 sh ows the increment timing with an extern al clock source. The pulse width of the external cloc k signal must be at least 1.
Rev. 1.00, 05/04, page 171 of 544 9.5.2 Output Compare Output Timing A compare-match signal occurs at the last st ate when the FRC and OCR values matc h (at the timing when the FRC updates the counter value). Whe n a compare-match signal occurs, the level selected by the OLVL bit in TOCR i s output at the output compare pi n (FTOA or FTOB).
Rev. 1.00, 05/04, page 172 of 544 9.5.4 Input Capture Input Timin g The rising or falling edge can be selected for the input capture inpu t timing by the IEDGA to IEDGD bits i n TCR. Figure 9.7 shows the usual i nput captu re timing whe n the rising ed ge is selected.
Rev. 1.00, 05/04, page 173 of 544 9.5.5 Buffered Input Capture Input Timing ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 9.
Rev. 1.00, 05/04, page 174 of 544 9.5.6 Timing of Input C apture Flag (I CF) Setti ng The input capture flag, ICFA, ICFB , ICFC, or ICFD, is set to 1 by the input cap ture signal. The FRC value is simultaneously transferred to the co rresponding input capture register (ICRA, ICRB, ICRC, or ICRD).
Rev. 1.00, 05/04, page 175 of 544 9.5.8 Timing of FRC Overflow Flag Set t ing The FRC overf low flag (OV F) is set t o 1 when FRC overflows (c hanges fro m H'FFFF to H'0000). Figure 9.13 shows the timing of setting th e OVF flag. Overflow signal FRC H'FFFF H'0000 OVF φ Figure 9.
Rev. 1.00, 05/04, page 176 of 544 9.5.10 Mask Signal Generati o n Timi ng When the ICRDMS bit in TOCR is set to 1 and th e contents of OCRDM are other than H'0000, a signal that masks t he ICRD input ca pture signal i s generated. The mask signal is set by the i nput capture signal.
Rev. 1.00, 05/04, page 177 of 544 9.6 Interrupt Sources The free-runni ng timer ca n reque st seven i nterrupts: ICIA to IC ID, OCIA, OC IB, and FOVI. Eac h interrupt ca n be enabled or disabled b y an enable bi t in TIER. I ndependent signals are se nt to the interrupt controller for each interrupt.
Rev. 1.00, 05/04, page 178 of 544 9.7.2 Conflict between FRC Write and Increment If an FRC i ncrement pul se is gene rated duri ng the state after an FRC writ e cycle, the wri te takes priority and FRC is not in cremented. Figure 9.18 shows the timing for this type of conflict.
Rev. 1.00, 05/04, page 179 of 544 φ Address OCR address Internal write signal Compare-match signal FRC Write data Disabled OCR N M N N + 1 T 1 T 2 Write cycle of OCR Figure 9.
Rev. 1.00, 05/04, page 180 of 544 9.7.4 Switching o f Internal Clock and FRC Operati on When the inte rnal clock i s changed, the changeo ver may cause FRC to in crement. This depends on the time at which the clock is switched (b its CKS1 and CKS0 are rewr itten), as shown in table 9.
Rev. 1.00, 05/04, page 181 of 544 No. Timing of Switchover by Means of CKS1 and CKS0 Bits FRC Operation 3 Switching from high to low Clock before switchover Clock after switchover FRC clock FRC CKS bi.
Rev. 1.00, 05/04, page 182 of 544.
TIMH265B_00002 0040200 Rev. 1.00, 05/04, page 183 of 544 Section 10 8-Bit Timer (TMR) This LSI has an on-c hip 8-bit timer modul e (TMR_0, TM R_1, TMR_Y, TMR_X, TMR _B, an d TMR_A) with six channels operating o n the basis of a n 8-bit cou nter.
Rev. 1.00, 05/04, page 184 of 544 Table 10.1 TMR Function Item TMR_0 TMR_1 TMR_ Y TMR_X TMR_B TMR_A Count clock φ /2 φ /8 φ /32 φ /64 φ /256 φ /1024 φ /2 φ /8 φ /64 φ /128 φ /1024 φ /2048 .
Rev. 1.00, 05/04, page 185 of 544 Figures 10. 1 to 10.3 sh ow block diagrams of 8-bit timers . External clock sources Internal clock sources TMR_0 φ /2, φ /8, φ /32, φ /64, φ /256, φ /1024 Clock.
Rev. 1.00, 05/04, page 186 of 544 External clock sources Internal clock sources TMR_X φ , φ /2, φ /4, φ /2048 * , φ /4096 * , φ /8192 * Clock X Clock Y Compare-match AX Compare-match A Y Clear X.
Rev. 1.00, 05/04, page 187 of 544 External clock sources Internal clock sources TMR_A φ , φ /2, φ /4, φ /2048, φ /4096, φ /8192 Clock A Clock B Compare-match AA Compare-match AB Clear A CMIAAB C.
Rev. 1.00, 05/04, page 188 of 544 10.2 Input/Output Pins Table 10.2 summarizes the input and output pin s of the TMR. Table 10.2 Pin Configuration Channel Name Sy mbol I/O Function Timer output TMO0 O.
Rev. 1.00, 05/04, page 189 of 544 10.3 Register Descriptions The TMR has the following re gisters. For det ails on the seri al timer contro l register, see section 3.
Rev. 1.00, 05/04, page 190 of 544 For both TM R_Y and TM R_X Timer XY control register (TCRXY) TMR_B Timer counter_B (TCNT_B) Time constant register A_B (TCORA_B) Time constant register B_B (TCORB_B) .
Rev. 1.00, 05/04, page 191 of 544 10.3.1 Timer Counter (TCNT) Each TCNT is an 8-bit rea dable/writabl e up-counter. TC NT_0 and TCNT_1 com prise a singl e 16- bit register, so they can be accessed toget her by word access. The clock s ource is selected by the CKS2 to CKS0 bits in TCR.
Rev. 1.00, 05/04, page 192 of 544 10.3.4 Timer Control Register (TCR) TCR selects the TCNT clock source and the conditio n by which TCNT is cleared, and enables/disables interrupt requests. TCR_Y can be accessed when the HI E bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 1.
Rev. 1.00, 05/04, page 193 of 544 Table 10.3 Clock Input to T CNT and Count Co nditi on (1) TCR STCR Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description 0 0 0 — — Disables clock input 0 0 1 — 0 Incre.
Rev. 1.00, 05/04, page 194 of 544 Table 10.3 Clock Input to T CNT and Coun t Conditi on (2) TCR TCRXY * 2 Channel CKS2 CKS1 CKS0 CKSX CKSY Description TMR_Y 0 0 0 — 0 Disables clock input 0 0 1 — .
Rev. 1.00, 05/04, page 195 of 544 Table 10.3 Clock Input to T CNT and Co un t Co ndi ti on (3) TCR TCRAB Channel CKS2 CKS1 CKS0 CKSA CKSB Description TMR_B 0 0 0 — 0 Disables clock input 0 0 1 — 0.
Rev. 1.00, 05/04, page 196 of 544 10.3.5 Timer Control/S tatus Register (TCSR) TCSR indicates t he status fla gs and contr ols compare-mat ch output . TCSR_0 Bit Bit Name Initial Value R/W Description.
Rev. 1.00, 05/04, page 197 of 544 TCSR_1 Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/(W ) * Compare-Match Flag B [Setting condition] When the values of TCNT_1 and TCORB_1 match [Clearing con.
Rev. 1.00, 05/04, page 198 of 544 TCSR_Y Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/(W ) * 1 Compare-Match Flag B [Setting condition] When the values of TCNT_Y and TCORB_Y match [Clearing c.
Rev. 1.00, 05/04, page 199 of 544 TCSR_X Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/(W ) * Compare-Match Flag B [Setting condition] When the values of TCNT_X and TCORB_X match [Clearing con.
Rev. 1.00, 05/04, page 200 of 544 TCSR_B Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/(W ) * Compare-Match Flag B [Setting condition] When the values of TCNT_B and TCORB_B match [Clearing con.
Rev. 1.00, 05/04, page 201 of 544 TCSR_A Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/(W ) * Compare-Match Flag B [Setting condition] When the values of TCNT_A and TCORB_A match [Clearing con.
Rev. 1.00, 05/04, page 202 of 544 10.3.6 Time Constant Register (TCORC) TCORC is an 8-bit rea dable/writabl e register. The sum of conte nts of TCORC and TIC R is always compared with TCNT. When a match is detect ed , a compare-match C signal is generated.
Rev. 1.00, 05/04, page 203 of 544 10.3.9 Timer Connection Register I (TCONRI) TCONRI cont rols the input ca pture functi on. Bit Bit Name Initial Value R/W Description 7 to 5 — All 0 R/W Reserved The initial value should not be chan ged. 4 ICST 0 R/W Input Capture Start Bit TMR_X has input captur e registers (TICRR and TICRF).
Rev. 1.00, 05/04, page 204 of 544 Table 10.4 Registers Accessible by TMR_X/TMR_Y TMRX/Y H'FFF 0 H'FFF1 H'FFF2 H' FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7 0 TMR_X TCR_X .
Rev. 1.00, 05/04, page 205 of 544 10.3.12 Timer AB Control Register (TCRAB) TCRAB selects the internal clock or controls the input capture function in the TMR_A and TMR_B. Bit Bit Name Initial Value R/W Description 7, 6 All 0 R/W Reserved The initial value should not be modifi ed.
Rev. 1.00, 05/04, page 206 of 544 10.4 Operation 10.4.1 Pulse Output Figure 10.4 s hows an exam ple for ou tputting an arbitrary duty pulse. 1. Clear the CCLR1 bit in TCR to 0 so th at TCNT is clea red according to the compa re match of TCORA, and then set the CCLR0 bit to 1.
Rev. 1.00, 05/04, page 207 of 544 10.5 Operation Timing 10.5.1 TCNT Count Timing Figure 10. 5 shows the TCNT count t iming wit h an interna l clock source . Figure 10.6 show s the TCNT count ti ming with an external clock source. The pulse wi dth of the external cloc k signal must be at least 1.
Rev. 1.00, 05/04, page 208 of 544 φ TCNT N N + 1 TCOR N Compare-match signal CMF Figure 10.7 Timing of CMF Setting at C ompare- M atc h 10.5.3 Timing of Timer Output at Compare -Match When a compare-match si gnal occurs, the timer ou tput changes as specified by the OS3 to OS0 bits in TCSR.
Rev. 1.00, 05/04, page 209 of 544 10.5.5 TCNT Extern al Re set Timing TCNT is cleare d at the risin g edge of an ext ernal reset i nput, depen ding on the set tings of the CCLR1 and CCLR0 bits in TCR. The width of the cl earing pulse must be at least 1.
Rev. 1.00, 05/04, page 210 of 544 10.6 TMR_0 and TMR_1 Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set t o B'100, the 8-bit t imers of the two channels are cascaded. With t his configuration, the 16-bit count mod e or compare- match count mode is available.
Rev. 1.00, 05/04, page 211 of 544 10.7 TMR_Y and TMR_X Cascaded Connection If bits CKS2 to CKS0 in either TCR_Y or TCR_X are set to B'100, the 8-bit timers of the two channels are cascaded. With t his configuration, 16-bit count mode or compare-match count mode can be selected by the setting s of the CKSX and CKSY bits in TCRXY.
Rev. 1.00, 05/04, page 212 of 544 10.7.3 Input Capture Operation TMR_X has input cap ture registers (TICRR and TI CRF). A narrow pulse width can be measured with TICRR and TICRF, using a single capture.
Rev. 1.00, 05/04, page 213 of 544 10.8.3 Input Capture Operation TMR_A has input cap ture registers (TICRR_A an d TICRF_A). A narrow pulse width can be measured with TICRR and TICRF, using a single ca pture.
Rev. 1.00, 05/04, page 214 of 544 Selection of Inp ut Capture Signa l Input: TMRIX (input c apture input signal of TMR _X) is selected according to the setting of the IC ST bit in TCONR I. The input capture signal selection is shown in ta ble 10.5. Table 10.
Rev. 1.00, 05/04, page 215 of 544 10.9 Interrupt Sources TMR_0, TMR_1 , and TMR_Y ca n generate three types of interr upts: CMIA , CMIB, and OVI. TMR_X can ge nerate an ICI X interrupt . TMR_A ca n gen erate four t ypes of inte rrupts, CMIA, CMIB, OVI and ICIA.
Rev. 1.00, 05/04, page 216 of 544 10.10 Usage Notes 10.10.1 Co nflict between TCNT Write and Counter Clear If a counter clear signal is ge nerated during the T 2 state of a TCNT write cycle as shown in figure 10.14, clearin g takes pri ority and the counte r write i s not pe rformed.
Rev. 1.00, 05/04, page 217 of 544 10.10.3 Co nflict betw een TCOR Write and Compare-Match If a compare-match occurs duri ng the T 2 state of a TC OR write cycle as show n in figu re 10.16, t he TCOR write t akes priorit y and the compa re-match signal is disa bled.
Rev. 1.00, 05/04, page 218 of 544 10.10.5 Switching of Interna l Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switch ed over. Table 10.9 shows the relationship between the timing at wh ich the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation.
Rev. 1.00, 05/04, page 219 of 544 No. Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation 3 Clock switchin g from high to low level ∗ 3 Clock before switchover Clock after switc.
Rev. 1.00, 05/04, page 220 of 544.
WDT0102A_0200200 40200 Rev. 1.00, 05/04, page 221 of 544 Section 11 Watchdog Timer (WDT) This LSI incorporates two watchdog timer channe ls (WDT_0 and WDT_1).
Rev. 1.00, 05/04, page 222 of 544 WOVI0 (Interrupt request signal) Internal NMI (Interrupt request signal * 2 ) RESO signal * 1 Internal reset signal * 1 TCNT_0 TCSR_0 φ /2 φ /64 φ /128 φ /512 φ .
Rev. 1.00, 05/04, page 223 of 544 11.2 Input/Output Pins The WDT has t he pins listed i n table 11. 1. Table 11.1 Pin Configuration Name Symbol I/O Function Reset output pin RESO Output Outputs the co unt er overflow signal in watchdog timer mode External sub-clock input pin EXCL Input Inputs the clock pulses to the W DT_1 prescaler counter 11.
Rev. 1.00, 05/04, page 224 of 544 11.3.2 Timer Control/St atus Regist er (TCSR ) TCSR selects the clock source to be input to TCNT , and the ti mer mode. • TCSR_0 Bit Bit Name Initial Value R/W Description 7 OVF 0 R/(W) * 1 Overflow Flag Indicates that TCNT has overflowed (change s from H'FF to H'00).
Rev. 1.00, 05/04, page 225 of 544 Bit Bit Name Initial Value R/W Description 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 Selects the clock source to be input to. The overflow frequency for φ = 10 MHz is enclosed in parentheses. 000: φ /2 (frequency: 51.
Rev. 1.00, 05/04, page 226 of 544 Bit Bit Name Initial Value R/W Description 4 PSS 0 R/W Prescaler S elect Selects the clock source to be input to TCNT.
Rev. 1.00, 05/04, page 227 of 544 11.4 Operation 11.4.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/ IT bit and the TME bit in TCSR to 1.
Rev. 1.00, 05/04, page 228 of 544 TCNT value H'00 Time H'FF WT/ IT = 1 TME = 1 Write H'00 to TCNT WT/ IT = 1 TME = 1 Write H'00 to TCNT 518 system clocks Internal reset signal [Leg.
Rev. 1.00, 05/04, page 229 of 544 11.4.2 Interval Ti mer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows, as shown in figure 11.3 . Therefore, an interrupt can be generated at intervals.
Rev. 1.00, 05/04, page 230 of 544 11.4.3 RESO Signal Output Timing When TCNT overflows in watchdog timer mode, the OV F bit in TCSR is set to 1. When the RST/ NMI bit is 1 here, the internal reset signal is ge nerated for the entire L SI. At the same time, the low level signal is ou tput from the RESO pin.
Rev. 1.00, 05/04, page 231 of 544 11.6 Usage Notes 11.6.1 Notes on Register Access The watchdog timer's regist ers, TCNT and T CSR differ f rom other re gisters in bei ng more difficult to w rite to. The proced ures for writing to and reading from these registers are given below.
Rev. 1.00, 05/04, page 232 of 544 11.6.2 Conflict between Timer Co unter (TCNT ) Write and Increment If a timer c ounter cl ock pulse is generate d during the T2 state of a TCNT write cycle, the write takes priori ty and the ti mer count er is not increme nted.
Rev. 1.00, 05/04, page 233 of 544 11.6.5 System Reset by RESO Signal Inputting the RE SO output signal to the RESO pin of this L SI prevents the LSI from being initialized correctly; th e RESO signal must not be logical ly connected to the RES pin of the LSI.
Rev. 1.00, 05/04, page 234 of 544.
SCI0022C_00002 0020800 Rev. 1.00, 05/04, page 235 of 544 Section 12 Serial Co mmunication Interface (SCI) This LSI has a serial communication interface (S CI).
Rev. 1.00, 05/04, page 236 of 544 ExRxD * /RxD ExTxD * /TxD ExSCK * /SCK Clock φ φ /4 φ /16 φ /64 TEI TXI RXI ERI SCMR SSR SCR SMR Transmission/ reception control Baud rate generator BRR Module da.
Rev. 1.00, 05/04, page 237 of 544 12.3 Register Descriptions The SCI has the followi ng registers. • Receive shift register (RSR) • Receive data register (RDR) • Transmit data register (TDR) •.
Rev. 1.00, 05/04, page 238 of 544 12.3.4 Transmit Shi ft Register (T SR) TSR is a shift register that transmits serial data. To perform serial data transmissi on, the SCI first transfers transmit data fr om TDR to TSR, then se nds the dat a to the TxD pi n.
Rev. 1.00, 05/04, page 239 of 544 Bit Bit Name Initial Value R/W Description 2 MP 0 R/W Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE b it and O/ E bit settings are invalid in multiprocessor mod e.
Rev. 1.00, 05/04, page 240 of 544 Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiprocessor Interrupt Enabl e (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled.
Rev. 1.00, 05/04, page 241 of 544 12.3.7 Serial Status Register (SS R ) SSR is a regi ster containi ng status fl ags of th e SCI a nd multiprocessor bi ts for transfer.
Rev. 1.00, 05/04, page 242 of 544 Bit Bit Name Initial Value R/W Description 3 PER 0 R/(W) * Parity Error [Setting condition] • When a parity error is detected during rece ption [Clearing condition].
Rev. 1.00, 05/04, page 243 of 544 12.3.8 Serial Interfa ce Mode Register (SCMR) SCMR selects SCI functions and its format. Bit Bit Name Initial Value R/W Description 7 to 4 — All 1 R Reserved These bits are always read as 1 and cannot be modified. 3 SDIR 0 R/W Data Transfer Direction Selects the serial/parallel con version format.
Rev. 1.00, 05/04, page 244 of 544 12.3.9 Bit Rate Re gister (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independentl y for each c hannel, differe nt bit rates ca n be set fo r each channel.
Rev. 1.00, 05/04, page 245 of 544 Table 12.3 BRR Settings for Various Bit Ra tes (A sy n c hron ou s Mode) (1) Operating Frequency φ (MHz) 4 4.9152 5 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 207 0.
Rev. 1.00, 05/04, page 246 of 544 Table 12.3 BRR Settings for Various Bit Ra tes (A sy n c hron ou s Mode) (2) Operating Frequency φ (MHz) 6 6.144 7.3728 8 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.
Rev. 1.00, 05/04, page 247 of 544 Table 12.4 Maximum Bit R ate for Ea c h Frequency (Asynchr onous Mode) φ (MHz) Maximum Bit Rate (bit/s) n N φ (MHz) Maximum Bit Rate (bit/s) n N 4 125000 0 0 9.8304 307200 0 0 4.9152 153600 0 0 10 312500 0 0 5 156250 0 0 6 187500 0 0 6.
Rev. 1.00, 05/04, page 248 of 544 Table 12.6 BRR Settings fo r Various Bit Rates (Clocked Synchrono us Mode) Operating Frequency φ (MHz) 4 8 10 Bit Rate (bit/s) n N n N n N 110 — — 250 2 249 3 124 — — 500 2 124 2 249 — — 1k 1 249 2 124 — — 2.
Rev. 1.00, 05/04, page 249 of 544 12.3.10 Serial Pin Select Register (SPSR) SPSR selects the serial I/O pins. SPSR should be set before initialization. Do not set during communication. Bit Bit Name Initial Value R/W Description 7 SPS1 0 R/W Serial Port Select Selects the serial I/O pins.
Rev. 1.00, 05/04, page 250 of 544 12.4.1 Data Transfer Format Table 12.8 shows the data transfer formats that can b e used in asynchronous mode. Any of 12 transfer formats can be selected acc ording to the SMR sett ing. For detai ls on the m ultiprocessor bit, refer to section 12.
Rev. 1.00, 05/04, page 251 of 544 12.4.2 Receive Data Samplin g Timing and Reception Marg in in Asynchronous Mode In asynchronous mode, the SCI operates on a basic cl ock with a freque ncy of 16 times t he bit rate. In reception, the SCI samples the falling edge of the start bit usi ng the basic cl ock, and perf orms internal synchronization.
Rev. 1.00, 05/04, page 252 of 544 12.4.3 Clock Either an inte rnal clock generated b y the on- chip baud rate generato r or an exte rnal clock input at the SCK pin can be selected as the SCI's tran sfer clock, acc ording t o the setti ng of the C/ A bi t in SMR and the CKE1 and CKE0 bits in SCR.
Rev. 1.00, 05/04, page 253 of 544 12.4.4 SCI Initializatio n (Asynchronous Mode) Before transmitting and recei ving da ta, you shoul d first clear the TE a n d RE bits in SCR to 0, then initialize the SCI as shown in figure 12.5 . When the operating mode, transfer format, etc.
Rev. 1.00, 05/04, page 254 of 544 12.4.5 Data Transmi ssion (Asy nchronous M ode) Figure 12.6 sho ws an example of the op eration for transmissio n in asynchronous mode .
Rev. 1.00, 05/04, page 255 of 544 No <End> [1] Yes Initialization Start transmission Read TDRE flag in SSR [2] Write transmit data to TDR and clear TDRE flag in SSR to 0 No Yes No Yes Read TEND .
Rev. 1.00, 05/04, page 256 of 544 12.4.6 Serial Data Recep tion (Asynchronous Mode) Figure 12.8 s hows an exam ple of the operat ion for rece ption in as ynchronou s mode.
Rev. 1.00, 05/04, page 257 of 544 Table 12.9 SSR Status Flag s and Receive Data Handling SSR Status Flag RDRF * ORER FER PER Receive Data Receive Error Type 1 1 0 0 Lost Overrun error 0 0 1 0 Transfer.
Rev. 1.00, 05/04, page 258 of 544 <End> [3] Error processing Parity error processing Yes No Clear ORER, PER, and FER flags in SSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER = 1 FER = 1 Break? PER = 1 Clear RE bit in SCR to 0 Figure 12.
Rev. 1.00, 05/04, page 259 of 544 12.5 Multiprocessor Communication Function Use of the multiprocessor communicat ion function enab les data transfer to be performed among a number of p rocessors shar.
Rev. 1.00, 05/04, page 260 of 544 12.5.1 Multiprocessor Seri al Data Transmissi on Figure 12.11 shows a sample flowch art for multiprocessor serial data transmission . For an ID transmission cycle, set the MPBT bit in SSR to 1 before t ransmission. F or a data tra nsmission cycle, clear the MPBT b it in SSR to 0 before transmission.
Rev. 1.00, 05/04, page 261 of 544 12.5.2 Multiprocessor S erial Data Reception Figure 12.13 shows a sam ple flowchart for multiprocess or serial data reception. If t he MPIE bit in SCR is set to 1, data is ski pped until data with a 1 multiprocessor bit is sent.
Rev. 1.00, 05/04, page 262 of 544 Yes <End> [1] No Initialization Start reception No Yes [4] Clear RE bit in SCR to 0 Error processing (Continued on next page) [5] No Yes FER ∨ ORER = 1 RDRF =.
Rev. 1.00, 05/04, page 263 of 544 <End> Error processing Yes No Clear ORER, PER, and FER flags in SSR to 0 No Yes No Yes Framing error processing Overrun error processing ORER = 1 FER = 1 Break? Clear RE bit in SCR to 0 [5] Figure 12.
Rev. 1.00, 05/04, page 264 of 544 12.6 Operation in Clocked Synchronous Mode Figure 12.14 s hows the ge neral format for clocked synchro nous communi cation. In cloc ked synchronous mode, data is transmitted or receiv ed in synchronization w ith clock pulses.
Rev. 1.00, 05/04, page 265 of 544 12.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and recei ving da ta, you shoul d first clear the TE a n d RE bits in SCR to 0, then initialize the SCI as described in a sample flowch art in figure 12.
Rev. 1.00, 05/04, page 266 of 544 12.6.3 Serial Data Transmission (Clocked Sync hronous Mod e) Figure 12.16 s hows an exa mple of SCI operation fo r transmissi on in cloc ked synchro nous mode. In serial transmission, the SCI operates as described below.
Rev. 1.00, 05/04, page 267 of 544 No <End> [1] Yes Initialization Start transmission Read TDRE flag in SSR [2] Write transmit data to TDR and clear TDRE flag in SSR to 0 No Yes No Yes Read TEND .
Rev. 1.00, 05/04, page 268 of 544 12.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 12.18 shows an example of SCI operation for reception in clocked synchronous mode .
Rev. 1.00, 05/04, page 269 of 544 Yes <End> [1] No Initialization Start reception [2] No Yes Read RDRF flag in SSR [4] [5] Clear RE bit in SCR to 0 Error processing (Continued below) [3] Read re.
Rev. 1.00, 05/04, page 270 of 544 Yes <End> [1] No Initialization Start transmission/reception [5] Error processing [3] Read receive data in RDR, and clear RDRF flag in SSR to 0 No Yes ORER = 1 .
Rev. 1.00, 05/04, page 271 of 544 12.7 Interrupt Sources Table 12.10 shows the interrupt sources in se rial communication interface. A different interrupt vector is assig ned to each inte rrupt source , and indivi dual interr upt sources can be enabl ed or disabled using the enable b its in SCR.
Rev. 1.00, 05/04, page 272 of 544 12.8 Usage Notes 12.8.1 Module Stop Mode Setting SCI operati on can be di sabled or enabled us ing the mo dule stop c ontrol re gister. The initial setting is for SCI operation to be halt ed. Register ac cess is enabled by clearing module stop mode.
Rev. 1.00, 05/04, page 273 of 544 12.8.6 SCI Operations du ring Mode Transitions Transmission: Before making a transition to module stop, software standby, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset.
Rev. 1.00, 05/04, page 274 of 544 Start transmission Transmission [1] No No No Yes Yes Yes Read TEND flag in SSR Make transition to software standby mode etc. Cancel software standby mode etc. TE = 0 Initialization TE = 1 [2] [3] All data transmitted? Change operating mode? TEND = 1 [1] Data being transmitted is lost halfway.
Rev. 1.00, 05/04, page 275 of 544 TE bit SCK output pin TxD output pin Port input/output Port input/output Port input/output High output * Marking output Transmission start Transmission end Transition.
Rev. 1.00, 05/04, page 276 of 544 12.8.7 Switching from SCK Pins to Port Pins When SCK pi ns are swit ched to p ort pins a fter transmissi on has compl eted, pi ns are enabl ed for port output a fter outputti ng a low pulse of hal f a cycle as shown in figure 12.
IFIIC60B_0100200 40200 Rev. 1.00, 05/04, page 277 of 544 Section 13 I 2 C Bus Interface (IIC) This LSI has a two-channel I 2 C bus interface. The I 2 C bus i nterface confor ms to and pro vides a subset of the Philips I 2 C bus (inter- IC bus) int erface functi ons.
Rev. 1.00, 05/04, page 278 of 544 • Selectable in put/output pins* Pins , PG4/ExSD AA, PG5/ExSC LA, PG6/Ex SDAB, and PG 7/ExSCLB, ar e selectable for the I 2 C bus inp ut/output pin in each c hannel. Note: * Th e program development tool (emulator) do es not support this function.
Rev. 1.00, 05/04, page 279 of 544 SCL in SCL out SDA in SDA out (Slave 1) SCL SDA SCL in SCL out SDA in SDA out (Slave 2) SCL SDA SCL in SCL out SDA in SDA out (Master) This LSI SCL SDA V CC V CC SCL SDA V DD Figure 13.
Rev. 1.00, 05/04, page 280 of 544 13.2 Input/Output Pins Table 13.1 summari zes the input/ output pin s used by the I 2 C bus interface . The serial clock I/O pin for each channel can be select ed from the three pi ns*. The serial data I/O pin for each channel can be selected form t he three pin s*.
Rev. 1.00, 05/04, page 281 of 544 13.3 Register Descriptions The I 2 C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessi ble regist ers differ depending on the ICE bit in ICCR.
Rev. 1.00, 05/04, page 282 of 544 13.3.1 I 2 C Bus Data Re gister (ICDR) ICDR is an 8-bit readable/writable reg ister that is used as a transmit data register when transmitting and a receive data re gister when recei ving. ICDR is inte rnally divided i nto a shift register (ICDRS), receive buffer (IC DRR), and transmit buffer (ICDRT).
Rev. 1.00, 05/04, page 283 of 544 13.3.2 Slave Address Register (S AR) SAR sets the slave address and selects the communicat ion format. If the LSI is in slav e mode with the I 2 C bus format selected.
Rev. 1.00, 05/04, page 284 of 544 13.3.3 Second Slave Addre ss Regi s ter (SA R X) SARX sets the second slave address and selects th e c ommunication format.
Rev. 1.00, 05/04, page 285 of 544 Table 13.2 Communication Format SAR SARX FS FSX Operating Mode 0 0 I 2 C bus format • SAR and SARX slave addresses recognize d • General call address recogniz ed .
Rev. 1.00, 05/04, page 286 of 544 13.3.4 I 2 C Bus Mode Register (ICMR) ICMR sets the communication form at and transfe r rate. It c an only be accessed when t he ICE bit in ICCR is set to 1.
Rev. 1.00, 05/04, page 287 of 544 Bit Bit Name Initial Value R/W Description 2 1 0 BC2 BC1 BC0 0 0 0 R/W R/W R/W Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. Bit BC2 to BC0 settings should be made during an interval between transfer frames.
Rev. 1.00, 05/04, page 288 of 544 Table 13.3 I 2 C Transfer Rate STCR ICMR Bits 5 and 6 Bit 5 Bit 4 Bit 3 Transfer Rate IICX CKS2 CKS1 CKS0 Clock φ = 5 MHz φ = 8 MHz φ = 10 MHz 0 0 0 0 φ /28 179 kHz 286 kHz 357 kHz 0 0 0 1 φ /40 125 kHz 200 kHz 250 kHz 0 0 1 0 φ /48 104 kHz 167 kHz 208 kHz 0 0 1 1 φ /64 78.
Rev. 1.00, 05/04, page 289 of 544 13.3.5 I 2 C Bus Control Register (ICCR) ICCR controls the I 2 C bus interface and performs in terrupt flag c onfirmation. Bit Bit Name Initial Value R/W Description 7 ICE 0 R/W I 2 C Bus Interface Enable 0: I 2 C bus interface modules are stopped and I 2 C bus interface module internal state is initial ized.
Rev. 1.00, 05/04, page 290 of 544 Bit Bit Name Initial Value R/W Description 5 4 MST TRS 0 0 R/W [MST clearing conditions] 1. When 0 is written by software 2. When lost in bus contention in I 2 C bus format master mode [MST setting conditions] 1. When 1 is written by software (for MST clearing condition 1) 2.
Rev. 1.00, 05/04, page 291 of 544 Bit Bit Name Initial Value R/W Description 2 0 BBSY SCP 0 1 R/W * W Bus Busy Start Condition/Stop Condition Prohibit In master mode: • Writing 0 in BBSY and 0 in SC.
Rev. 1.00, 05/04, page 292 of 544 Bit Bit Name Initial Value R/W Description 1 IRIC 0 R/(W) * I 2 C Bus Interface Interrupt Request Flag Indicates that the I 2 C bus interface has issue d an interrupt request to the CPU. IRIC is set at different times depending on the FS bit in SAR, the FSX bit in SARX, and the WAIT bit in ICMR.
Rev. 1.00, 05/04, page 293 of 544 Bit Bit Name Initial Value R/W Description 1 IRIC 0 R/(W) * Clocked synchrono us serial format mode: • At the end of data transfer (rise of the 8th transmit/receive.
Rev. 1.00, 05/04, page 294 of 544 Table 13.4 Flags and Transfer States (Master Mode) MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDRE State 1 1 0 0 0 0 0 ↓ 0 0 ↓ 0 ↓ 0 — 0 Idle sta.
Rev. 1.00, 05/04, page 295 of 544 Table 13.5 Flags and Tra nsfer States (S lave Mode ) MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDRE State 0 0 0 0 0 0 0 0 0 0 0 — 0 Idle state (flag c.
Rev. 1.00, 05/04, page 296 of 544 Table 13.5 Flags and Tra nsfer States ( Slave Mode ) (cont) MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDRE State 0 0 1 0 0 — — — — — — 1 —.
Rev. 1.00, 05/04, page 297 of 544 13.3.6 I 2 C Bus Status Register (I CSR) ICSR consist s of status flags. Also see t ables 13.4 a nd 13.5. Bit Bit Name Initial Value R/W Description 7 ESTP 0 R/(W) * Error Stop Condition Detection Flag This bit is valid in I 2 C bus format slave mode.
Rev. 1.00, 05/04, page 298 of 544 Bit Bit Name Initial Value R/W Description 4 AASX 0 R/(W) * Second Slave Address Recognitio n Flag In I 2 C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX.
Rev. 1.00, 05/04, page 299 of 544 Bit Bit Name Initial Value R/W Description 2 AAS 0 R/(W) * Slave Address Recognition Fl ag In I 2 C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected.
Rev. 1.00, 05/04, page 300 of 544 Bit Bit Name Initial Value R/W Description 0 ACKB 0 R/W Acknowledge Bit Stores acknowledge data. Transmit mode: [Setting condition] When 1 is received as the acknowle.
Rev. 1.00, 05/04, page 301 of 544 13.3.7 DDC Switch Register (DDCSWR) DDCSWR controls IIC i nternal latch clearance. Bit Bit Name Initial Value R/W Description 7 to 5 — All 0 R/W Reserved The initial value should not be chan ged.
Rev. 1.00, 05/04, page 302 of 544 13.3.8 I 2 C Bus Extended Cont rol Register (ICXR) ICXR ena bles or disa bles the I 2 C bus interface interrupt genera tion a nd continuous receive operation, and indicates the status of receive/t ransmit operations.
Rev. 1.00, 05/04, page 303 of 544 Bit Bit Name Initial Value R/W Description 5 ICDRF 0 R Receive Data Read Request Flag Indicates the ICDR (ICDRR) st atus in receive mode. 0: Indicates that the data has been already r ead from ICDR (ICDRR) or ICDR is initialized.
Rev. 1.00, 05/04, page 304 of 544 Bit Bit Name Initial Value R/W Description 4 ICDRE 0 R Transmit Data Write Request Flag Indicates the ICDR (ICDRT) st atus in transmit mode. 0: Indicates that the data has been already w ritten to ICDR (ICDRT) or ICDR is initialized.
Rev. 1.00, 05/04, page 305 of 544 Bit Bit Name Initial Value R/W Description 3 ALIE 0 R/W Arbitration Lost Interrupt Enable Enables or disables IRIC flag setting and i nterrupt generation when arbitration is lost. 0: Disables interrupt request when arbitrati on is lost.
Rev. 1.00, 05/04, page 306 of 544 13.3.9 Port G Control Register (P GCTL) PGCTL selects the input/output pin for IIC. Bit Bit Name Initial Value R/W Description 7 6 IIC1BS IIC1AS 0 0 R/W R/W IIC_1 Inp.
Rev. 1.00, 05/04, page 307 of 544 13.4 Operation The I 2 C bus interface has an I 2 C bus format a nd a serial format. 13.4.1 I 2 C Bus Data Forma t The I 2 C bus format is an addressing format with an acknow ledge bit. This is shown in figure 13.3. The first frame following a start condition always consists of 9 bits.
Rev. 1.00, 05/04, page 308 of 544 SDA SCL S SLA R/ W A 9 8 1 to 7 9 8 1 to 7 9 8 1 to 7 DATA A DATA A/ A P Figure 13.5 I 2 C Bus Timing Table 13.6 I 2 C Bus Data Fo rmat Symbols Legend S Start condition. The master device drives SDA from high to low while SCL is high.
Rev. 1.00, 05/04, page 309 of 544 13.4.2 Initialization Initialize the IIC by the pro cedure shown in figure 13.6 before starting transmission/reception of data.
Rev. 1.00, 05/04, page 310 of 544 Start Initialize IIC Set MST = 1 and TRS = 1 in ICCR Set BBSY =1 and SCP = 0 in ICCR Write transmit data in ICDR Clear IRIC flag in ICCR No No Yes Yes Yes Yes No No [1] Initialization [3] Select master transmit mode. [4] Start condition issuance [6] Set transmit data for the first byte (slave address + R/ W ).
Rev. 1.00, 05/04, page 311 of 544 The transmissi on procedure a nd operati ons by which data is sequentially transmitted in synchronizatio n with ICDR (ICDR T) write operations, are described belo w. 1. Initialize the IIC as described in section 13.4.
Rev. 1.00, 05/04, page 312 of 544 12. Clear the IRIC flag to 0. Write 0 to ACKE in ICCR, to clear received ACKB c ontents to 0. Write 0 to BBSY and SCP in ICCR.
Rev. 1.00, 05/04, page 313 of 544 SDA (master output) SDA (slave output) 2 14 36 58 79 89 A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 0 ICDRE IRTR ICDR SCL (master output) Start condition is.
Rev. 1.00, 05/04, page 314 of 544 13.4.4 Master Receive Operation In I 2 C bus format master rec eive mode, the master device outputs the receive clock, recei ves data, and returns an acknow ledge signal.
Rev. 1.00, 05/04, page 315 of 544 The reception procedure and operations using the HNDS function, by which the data reception process is pr ovided in 1- byte unit s with SC L fixed l ow at each data recept ion, are desc ribed bel ow. 1. Clear the TRS bit in I CCR to 0 to switch from transmit mode to receive mode.
Rev. 1.00, 05/04, page 316 of 544 SDA (master output) SDA (slave output) 2 1 4 3 6 5 8 7 1 2 9 9 A A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 IRTR ICDRF ICDRR SCL (master output) Ma.
Rev. 1.00, 05/04, page 317 of 544 Receive Operation Usin g the Wai t Function: Figures 13.13 and 13.14 s how the sample flowcharts for the op erations in master receive mode (WAIT = 1).
Rev. 1.00, 05/04, page 318 of 544 End Set HNDS = 0 in ICXR Set WAIT = 0 in ICMR Set WAIT = 0 in ICMR Set ACKB = 0 in ICSR Set ACKB = 1 in ICSR Read ICDR Clear IRIC flag in ICCR Clear IRIC flag in ICCR Clear IRIC flag in ICCR Read IRIC flag in ICCR Read ICDR Read IRIC flag in ICCR IRIC = 1? Yes No No IRIC = 1? Yes [1] Select receive mode.
Rev. 1.00, 05/04, page 319 of 544 The reception procedure and operations using the wait function (WAIT bit), by which data is sequentially re ceived in sync hronization with ICDR (ICDRR ) read operation s, are described below. The following describes the multip le-byte reception procedure.
Rev. 1.00, 05/04, page 320 of 544 12. The IRIC flag is set to 1 in either of the fo llowing cases. At the fall of the 8th receive clock pulse for one frame SCL is automatically fixed low in synchronization with th e internal clock until the IRIC flag is cleared.
Rev. 1.00, 05/04, page 321 of 544 SDA (master output) SDA (slave output) 2 1 4 3 6 5 8 7 9 9 8 A A Bit 7 Bit 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 IRIC IRTR ICDR SCL (master output) Data 3 Data 2 Data.
Rev. 1.00, 05/04, page 322 of 544 Slave receive mode End Read IRIC flag in ICCR Clear IRIC flag in ICCR Read IRIC flag in ICCR Read AASX, AAS and ADZ in ICSR Read TRS in ICCR Read IRIC flag in ICCR Cl.
Rev. 1.00, 05/04, page 323 of 544 The reception procedure and operations using the HNDS bit function, by which data reception process is pr ovided in 1- byte unit with SCL being fi xed low at e very data rece ption, are described below. 1. Initialize the IIC as described in section 13.
Rev. 1.00, 05/04, page 324 of 544 SDA (master output) SDA (slave output) 2 1 2 1 4 36 58 79 Bit 7 Bit 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICDRF IRIC ICDRS ICDRR SCL (master output) SCL (.
Rev. 1.00, 05/04, page 325 of 544 Continuous Receive Operation: Figure 13.20 shows the sample fl owchart for the operat ions in sla ve receive mode (HNDS = 0).
Rev. 1.00, 05/04, page 326 of 544 The reception procedure and operations in slave receive a re described below. 1. Initialize the IIC as described in section 13.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS a nd ACKB bits to 0.
Rev. 1.00, 05/04, page 327 of 544 SDA (master output) SDA (slave output) 2 14 32 14 3 6 58 79 Bit 7 Bit 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICDRF ICDRS ICDRR IRIC SCL (master.
Rev. 1.00, 05/04, page 328 of 544 13.4.6 Slave Transm it Operati on If the slave address matches t o the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (R/ W ) is 1 (read), the TRS bit in ICCR is automatically set to 1 and the mode changes to slave transmit mode.
Rev. 1.00, 05/04, page 329 of 544 In slave transmit mode, the sla ve device outputs the transmit data, while the master device outputs the receive clock and returns an ac knowledge signal. The transmission pro cedure and operations in slave transmit mode are described belo w.
Rev. 1.00, 05/04, page 330 of 544 10. When the stop condition is detected, that is, when SDA is chang ed from low to high when SCL is high, the BBSY flag in ICCR is cleared to 0 an d the STOP flag in ICSR is set to 1. When the STOPIM bit in ICXR is 0, the IRIC flag is set to 1.
Rev. 1.00, 05/04, page 331 of 544 13.4.7 IRIC Setting Ti ming and SCL Control The interrupt request flag (IRIC) is set at differ ent times depending on the WA IT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX.
Rev. 1.00, 05/04, page 332 of 544 SCL SDA IRIC User processing Clear IRIC 2 13 A 8 123 9 8 Clear IRIC When WAIT = 1, and FS = 0 or FSX = 0 (I 2 C bus format, wait inserted) SCL SDA IRIC User processin.
Rev. 1.00, 05/04, page 333 of 544 SCL SDA IRIC User processing Clear IRIC 1 8 7 4 12 3 8 7 When FS = 1 and FSX = 1 (clocked synchronous serial format) (a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception.
Rev. 1.00, 05/04, page 334 of 544 13.4.8 Noise Canceller The logic levels at the SCL and SDA pin s are routed through noise can cellers before being latched internally. Fi gure 13.2 8 shows a bloc k diagram o f the noise canceller. The noise canceller consists of two cascaded latc hes and a match detect or.
Rev. 1.00, 05/04, page 335 of 544 13.4.9 Initialization of Internal State The IIC has a function for forcible initializat ion of its internal state if a deadlock occurs during communication. Initialization is execu ted in accordance with the setting of bits CLR3 to CLR0 in DD CSWR or clearing ICE bit.
Rev. 1.00, 05/04, page 336 of 544 The value of th e BBSY bit ca nnot be m odified di rectly by t his module cle ar function , but since t he stop conditi on pin wavef orm is ge nerated accor ding to the st ate and release ti ming of the S CL and SDA pins, the BB SY bit may be cleared as a result.
Rev. 1.00, 05/04, page 337 of 544 13.6 Usage Notes 1. In master m ode, if an inst ruction to gene rate a start condition is issued and then an inst ruction to generat e a stop con dition is i ssued before the start co ndition is output t o the I 2 C bus , neither condition will be outpu t correctly.
Rev. 1.00, 05/04, page 338 of 544 5. The I 2 C bus interface specific ation for the SCL rise time t sr is 1000 ns or less ( 300 ns f or high- speed mode). I n master mode, the I 2 C bus interface monitors the SCL line and synchronizes one bit at a ti me during communicatio n.
Rev. 1.00, 05/04, page 339 of 544 Table 13.10 I 2 C Bus Timing (with Maximum Influence of t Sr /t Sf ) Time Indication (at Maximu m Transfer Rate) [ns] Item t cyc Indication t Sr /t Sf Influence (Max.) I 2 C Bus Specifi- cation (Min.) φ = 5 MHz φ = 8 MHz φ = 10 MHz Standard mode –1000 4000 4000 4000 4000 t SCLHO 0.
Rev. 1.00, 05/04, page 340 of 544 7. Notes on ICDR read at end of maste r reception To halt reception at the end of a receive operation in master r eceive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop cond ition.
Rev. 1.00, 05/04, page 341 of 544 8. Notes on start conditio n issuance for retransmission Figure 13.30 shows the timing of start condition issuance fo r retransmission, and the timing for subsequently writing data to ICDR, together with the correspond ing flowchart.
Rev. 1.00, 05/04, page 342 of 544 9. Note on whe n I 2 C bus interface stop condition in struction is issued In cases where the rise time of the 9th cl ock of SCL excee ds the stipulated value because.
Rev. 1.00, 05/04, page 343 of 544 10. Note on IRIC flag clear wh en the wait function is used If the rise time of SCL excee ds the stipulated va lue or a slave device in which a wait can be inserted b.
Rev. 1.00, 05/04, page 344 of 544 11. Note on ICDR read and I CCR access in slave transmit mode In I 2 C bus interface slave tra nsmit mode, do not read ICDR or do not rea d/write from/to ICCR during the ti me shaded i n figure 13.
Rev. 1.00, 05/04, page 345 of 544 12. N ote on TRS bit setting in slav e mode In I 2 C bus interface slave mode, if t he TRS bit valu e in ICCR is set after detecting the rising edge of the 9th clock pul se or the st op condit ion befo re detecting the next r ising edge on the SCL pin (the t ime indicat ed as (a) in figure 13.
Rev. 1.00, 05/04, page 346 of 544 13. No te on ICDR read in transmit mode and ICDR write in receive mod e If ICDR is read in tra nsmit mode (TRS = 1) or ICDR is wri tten to in receive mode (TRS = 0), .
Rev. 1.00, 05/04, page 347 of 544 SA SLA R/ W SA SLA R/ W A DATA2 SA SLA R/ W A SLA R/ W A DATA3 A DATA4 DATA1 I 2 C bus interf ace (Master transmit mode) T ransmit data match T ransmit timing match .
Rev. 1.00, 05/04, page 348 of 544.
IFKEY10A_000020 020700 Rev. 1.00, 05/04, page 349 of 544 Section 14 Keyboard Buffer Contr oller This LSI has three on-chi p keyb oard buffer controll er channel s. The keyb oard buffer c ontroll er is provided with function s conforming to the PS/2 interface specifications.
Rev. 1.00, 05/04, page 350 of 544 Figure 14.2 s hows how t he keyboa rd buffer contr oller is con nected. Vcc KCLK in KCLK out KD in KD out Keyboard buffer controller (This LSI) System side KCLK in KCLK out KD in KD out I/F Keyboard side Vcc Clock Data Figure 14.
Rev. 1.00, 05/04, page 351 of 544 14.3 Register Descriptions The keyboard buffe r controll er has the followi ng registers fo r each channel. • Keyboard control register H (KBCRH) • Keyboard control register L (KBCRL) • Keyboard data buffer register (KBBR) 14.
Rev. 1.00, 05/04, page 352 of 544 Bit Bit Name Initial Value R/W Description 3 KBIE 0 R/W Keyboard Interrupt Enable Enables or disables interrupts from the keyboar d buffer controller to the CPU.
Rev. 1.00, 05/04, page 353 of 544 14.3.2 Keyboard Control Re gister L (KB CRL) KBCRL enables the receive c ounte r count and controls the keyboa rd buffer c ontroller pin out put. Bit Bit Name Initial Value R/W Description 7 KBE 0 R/W Keyboard Enable Enables or disables loading of receive data into KBBR.
Rev. 1.00, 05/04, page 354 of 544 14.3.3 Keyboard Data B uffer Regi ster (KBBR ) KBBR stores receive data. Its value is valid only when KB F = 1. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0 0 0 0 0 0 0 0 0 R R R R R R R R Keyboard Data 7 to 0 8-bit read only data.
Rev. 1.00, 05/04, page 355 of 544 14.4 Operation 14.4.1 Receive Operation In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and inputs on thi s LSI chip (s ystem) side. KD recei ves a start bit , 8 data bits (LSB-first ), an odd parity bit, and a stop bit, in that or der.
Rev. 1.00, 05/04, page 356 of 544 12 3 KCLK (pin state) KD (pin state) KCLK (input) KCLK (output) KB7 to KB0 PER KBS KBF Start bit Parity bit Stop bit Receive processing/ error handling Automatic I/O inhibit Previous data Receive data Flag cleared 9 10 11 7 01 KB0 KB1 [1] [2] [3] [4] [5] [6] Figure 14.
Rev. 1.00, 05/04, page 357 of 544 Start Set KBIOE bit KCLKI = 0? Read KBCRH KCLKI and KDI bits both 1? Set I/O inhibit (KCLKO = 0) KBE = 0 (KBBR reception prohibited) KDO remains at 1 Wait Set start b.
Rev. 1.00, 05/04, page 358 of 544 Read KBCRH Transmit end state (KCLK = high, KD = high) Yes Note: * To switch to reception after transmission, set KBE to 1 (KBBR receive enable) while KCLKI is low.
Rev. 1.00, 05/04, page 359 of 544 14.4.3 Receive Abort This LSI (system side) can forcibly abort transm ission from the device co nnected to it (keyboard side) in the eve nt of a prot ocol error, et c.
Rev. 1.00, 05/04, page 360 of 544 Receive data processing Clear KBF flag (KCLK = High) Processing 1 Receive operation ends normally [1] On the system side, drive the KCLK pin low, setting the I/O inhibit state. [1] Transmit enabled state. If there is transmit data, the data is transmitted.
Rev. 1.00, 05/04, page 361 of 544 14.4.4 KCLKI and KDI Read Timing Figure 14. 9 shows the KCLKI a nd KDI rea d timing. T 1 T 2 φ * Internal read signal KCLK, KD (pin state) KCLKI, KDI (register) Internal data bus (read data) Note: * The φ clock shown here is scaled b y 1/N in medium-speed mode when the operating mode is activ e mode.
Rev. 1.00, 05/04, page 362 of 544 14.4.6 KBF Setting Timi ng and KCLK Control Figure 14.11 sh ows the KBF setting timing and th e KCLK pin states. KCLK (pin) φ * Internal KCLK Falling edge signal RXC.
Rev. 1.00, 05/04, page 363 of 544 14.4.7 Receive Timing Figure 14.12 shows the receive timing. N + 1 N + 2 N KCLK (pin) Note: * The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. KD (pin) Internal KCLK (KCLKI) Falling edge signal RXCR3 to RXCR0 Internal KD (KDI) KBBR7 to KBBR0 φ * Figure 14.
Rev. 1.00, 05/04, page 364 of 544 14.4.8 KCLK Fall Interrupt Operation In this device, clearin g the KBFSEL bit to 0 in KBCRH enables th e KBF bit in KBCRL to be used as a flag for the interrupt generated by the fall of KCLK input. Figure 14.13 shows th e setting method and an ex ample of operation.
Rev. 1.00, 05/04, page 365 of 544 14.5 Usage Notes 14.5.1 KBIOE Setting and KC LK Falling Edge Detection When KBIOE is 0, the internal KCLK and internal KD settings are fixe d at 1. The refore, i f the KCLK pin is l ow when the KBIOE bi t is set to 1, the edge detection ci rcuit operate s and the KCLK falling edge is detected.
Rev. 1.00, 05/04, page 366 of 544 14.5.2 Module Stop Mode Setting Keyboard b uffer contr oller operat ion can be enabled or disabled using the module sto p control register. The initial setting is fo r keyboard buffer c ontroller opera tion to be halted.
IFHSTL0A_020020 040200 Rev. 1.00, 05/04, page 367 of 544 Section 15 Host In terface (LPC) This LSI has an on-c hip LPC interface. The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz PCI clock. It uses four signal lines for addr ess/data, and one for host interrup t requests.
Rev. 1.00, 05/04, page 368 of 544 Figure 15.1 show s a block diagra m of the LPC. TWR1–15 IDR3 IDR2 IDR1 H'0060/64 H'0062/66 LADR3 SIRQCR0 SIRQCR1 TWR0MW TWR1–15 ODR3 ODR2 ODR1 STR3 STR2.
Rev. 1.00, 05/04, page 369 of 544 15.2 Input/Output Pins Table 15.1 li sts the input and output pi ns of the L PC modul e. Table 15.1 Pin Configuration Name Abbreviation Port I/O Function LPC address/.
Rev. 1.00, 05/04, page 370 of 544 15.3 Register Descriptions The LPC has the following registers. • Host interface control register 0 (HICR0) • Host interface control register 1 (HICR1) • Host i.
Rev. 1.00, 05/04, page 371 of 544 15.3.1 Host Interface Control Registers 0 an d 1 (HICR0, HICR1) HICR0 and H ICR1 contai n control bits that enabl e or disab le host inter face functions, control bit s that determine pin output and the internal state of the host interface, and st atus fla gs that monitor the internal state of the host interface.
Rev. 1.00, 05/04, page 372 of 544 R/W Bit Bit Name Initial Value Slave Host Description 4 FGA20E 0 R/W — Fast A20 Gate Function Enable Enables or disables the fast A20 gate functi on. When the fast A20 gate is disa bled, the normal A20 gate can be implemented by firmware oper ation of the P81 output.
Rev. 1.00, 05/04, page 373 of 544 R/W Bit Bit Name Initial Value Slave Host Description 2 PMEE 0 R/W — PME output En able Controls PME output in co mbination with the PMEB bit in HICR1.
Rev. 1.00, 05/04, page 374 of 544 • HICR1 R/W Bit Bit Name Initial Value Slave Host Description 7 LPCBSY 0 R/W — LPC Busy Indicates that the host interface is processing a transfer cycle.
Rev. 1.00, 05/04, page 375 of 544 R/W Bit Bit Name Initial Value Slave Host Description 5 IRQBSY 0 R — SERIRQ Busy Indicates that the host interface's SERIRQ signal is engaged in transfer processing.
Rev. 1.00, 05/04, page 376 of 544 R/W Bit Bit Name Initial Value Slave Host Description 3 SDWNB 0 R/W — LPC Software Shutdown Bit Controls host interface shutdown. For details of the LPC shutdown function, and the scope of in itialization by an LPC reset and an LPC shutdown, see section 15.
Rev. 1.00, 05/04, page 377 of 544 15.3.2 Host Interface Con trol Re gisters 2 and 3 (HICR 2, HICR3 ) Bits 6 to 0 in HICR2 control interrupts from the ho st interface (LPC) module to the slave processor (this LSI). Bit 7 in HICR 2 and HICR3 monitor host interface pin states.
Rev. 1.00, 05/04, page 378 of 544 R/W Bit Bit Name Initial Value Slave Host Description 3 IBFIE3 0 R/W — IDR3 and TWR Receive Completio n Interrupt Enable Enables or disables IBFI3 interrupt to the slave processor (this LSI).
Rev. 1.00, 05/04, page 379 of 544 15.3.3 LPC C hannel 3 Address Register (LADR3) LADR3 comprises two 8-b it readable/writable regi sters that perform LPC channel-3 host address setting and co ntrol the o peration of t he bidirect ional data re gisters.
Rev. 1.00, 05/04, page 380 of 544 Table 15.2 Register Selection I/O Address Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer Cycle Host Register Selection Bit 4 Bit 3 0 Bit 1 0 I/O write IDR3 write, C/ D 3 ← .
Rev. 1.00, 05/04, page 381 of 544 15.3.5 Output Data Regis ters 1 to 3 (ODR1 to ODR 3 ) The ODR registers are 8-bit readab le/writable registers for the slav e processor (this LSI), and 8-bit read-only registers for the host pr ocessor. Th e registers selected fr om the host according to the I/O address are shown in the following table.
Rev. 1.00, 05/04, page 382 of 544 I/O Address Bits 15 to 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer Cycle Host Register Selection 0000 0000 0110 0 1 0 0 I/O read STR1 read 0000 0000 0110 0 1 1 0 I/O read STR2.
Rev. 1.00, 05/04, page 383 of 544 • STR2 R/W Bit Bit Name Initial Va lue Slave Host Description 7 6 5 4 DBU27 DBU26 DBU25 DBU24 0 0 0 0 R/W R/W R/W R/W R R R R Defined by User The user can use these bits as necessary.
Rev. 1.00, 05/04, page 384 of 544 • STR3 (TWRE = 1 or SELSTR3 = 0) R/W Bit Bit Name Initial Value Slave Host Description 7 IBF3B 0 R R Bidirectional Data Register Input Buffer Full Set to 1 when the host processor writes to TWR15. This is an internal interrupt source t o the slave processor (this LSI).
Rev. 1.00, 05/04, page 385 of 544 R/W Bit Bit Name Initial Value Slave Host Description 3 C/D3 0 R R Command/Data When the host processor writes to an IDR register, bit 2 of the I/O address is written into this bit to indicate whether IDR contains data or a command.
Rev. 1.00, 05/04, page 386 of 544 • STR3 (TWRE = 0 and SELSTR3 = 1) R/W Bit Bit Name Initial Value Slave Host Description 7 6 5 4 DBU37 DBU36 DBU35 DBU34 0 0 0 0 R/W R/W R/W R/W R R R R Defined by User The user can use these bits as necessary.
Rev. 1.00, 05/04, page 387 of 544 15.3.8 SERIRQ Control Registers 0 and 1 (SIR Q CR0, SIRQC R1 ) The SIRQCR re gisters contai n status bit s that indi cate the SERIRQ o perating m ode and bi ts that specify SERIRQ interrupt sources.
Rev. 1.00, 05/04, page 388 of 544 R/W Bit Bit Name Initial Value Slave Host Description 4 SMIE3B 0 R/W — Host SMI Interrupt Enable 3B Enables or disables a host SMI interrupt request whe n OBF3B is set by a TWR15 write.
Rev. 1.00, 05/04, page 389 of 544 R/W Bit Bit Name Initial Value Slave Hos t Description 2 SMIE2 0 R/W — Host SMI Interrupt Enab le 2 Enables or disables a host SMI interrupt request whe n OBF2 is set by an ODR2 write.
Rev. 1.00, 05/04, page 390 of 544 R/W Bit Bit Name Initial Value Slave Host Desc ription 0 IRQ1E1 0 R/W — Host IRQ1 Interrupt Enable 1 Enables or disables a host IRQ1 interrupt request wh en OBF1 is set by an ODR1 write.
Rev. 1.00, 05/04, page 391 of 544 R/W Bit Bit Name Initial Value Slave Host Desc ription 6 IRQ10E3 0 R/W — Host IRQ10 Interrupt Enable 3 Enables or disables a host IRQ10 interrupt requ est when OBF3A is set by an ODR3 write.
Rev. 1.00, 05/04, page 392 of 544 R/W Bit Bit Name Initial Value Slave Host Desc ription 4 IRQ6E3 0 R/W — Host IRQ6 Interrupt Enable 3 Enables or disables a host IRQ6 interrupt request wh en OBF3A is set by an ODR3 write.
Rev. 1.00, 05/04, page 393 of 544 R/W Bit Bit Name Initial Value Slave Host Description 2 IRQ10E2 0 R/W — Host IRQ10 Interrupt Ena ble 2 Enables or disables a host IRQ10 interrupt requ est when OBF2 is set by an ODR2 write.
Rev. 1.00, 05/04, page 394 of 544 R/W Bit Bit Name Initial Value Slave Host Description 0 IRQ6E2 0 R/W — Host IRQ6 Interrupt Enable 2 Enables or disables a host IRQ6 interrupt request wh en OBF2 is set by an ODR2 write.
Rev. 1.00, 05/04, page 395 of 544 15.3.9 Host Interface Select Re gister (HISE L) HISEL selects the f unction of bi ts 7 to 4 i n STR3 and s pecifies the out put of the host interrupt request signal of each frame.
Rev. 1.00, 05/04, page 396 of 544 15.4 Operation 15.4.1 Host Interface Activation The host interface is activated by setting one of bits LPC3E to LPC1E i n HICR0 to 1 in single- chip mode. When the host interface is activated, the related I/O po rts (ports 37 t o 30, ports 83 and 82) functio n as dedicat ed host interface input /output pi ns.
Rev. 1.00, 05/04, page 397 of 544 15.4.2 LPC I/O Cycles There a re ten kind s of LPC tran sfer cyc le: memo ry read, memory write, I/O read, I/O wri te, DMA read, DMA write, bus master memory read, bus ma ster memory write, bus master I/O read, and bus master I/O write.
Rev. 1.00, 05/04, page 398 of 544 The timing of the LFRAME , LCLK, and LAD si gnals is show n in fig ures 15.2 an d 15.3. ADDR Start LFRAME LAD3–LAD0 Number of clocks LCLK T AR Sync Data T AR Start Cycle type, direction, and size 11 4 1 22 2 1 Figure 15.
Rev. 1.00, 05/04, page 399 of 544 Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1 command followed by data. When the slave processor (this LSI) r eceives data, it normally uses an interrupt routine activated by the IBF1 interrup t to read IDR1.
Rev. 1.00, 05/04, page 400 of 544 Table 15.4 Fast A20 Gate Output Sign als HA0 Data/Command Internal CPU Interrupt Flag (IBF) GA20 (P81) Remarks 1 H'D1 comman d 0 Q 0 1 data * 1 0 1 1 H'FF c.
Rev. 1.00, 05/04, page 401 of 544 15.4.4 Host Interface Shutdo wn Function (LPCP D) The host interface can be plac ed in the shutdown state acco rding to the state of the LPCPD pin. There are tw o kinds of h ost interface s hutdown st ate: LPC hard ware shutdown a nd LPC s oftware shutdown.
Rev. 1.00, 05/04, page 402 of 544 Table 15.5 shows the scope of the host interface pin shut down. Table 15.5 Scope of Host Interface Pin Shutdown Abbreviation Port Scope of Shutdown I/O Notes LAD3 to .
Rev. 1.00, 05/04, page 403 of 544 The scope of the initialization in each mode is shown in table 15.6. Table 15.6 Scope of Initi alization in Each Host Interface Mode Items Initialized System Reset LP.
Rev. 1.00, 05/04, page 404 of 544 Figure 15. 5 shows the timing of t he LPCPD and LRESET signals. LPCPD LRESET LAD3–LAD0 LFRAME LCLK At least 30 µ s At least 100 µ s At least 60 µ s Figure 15.
Rev. 1.00, 05/04, page 405 of 544 15.4.5 Host Interface Serialized Interrupt Operation (SERIRQ) A host interrupt request can be issued from the host interface by means of th e SERIRQ pin.
Rev. 1.00, 05/04, page 406 of 544 Serial Interrupt Transfer Cycle Frame Count Contents Drive Source Number of States Notes 0 Start Slave Host 6 In quiet mode only, slave drive possible in first state,.
Rev. 1.00, 05/04, page 407 of 544 15.4.6 Host Interface Clock S tart Request ( CLKRUN) A request to restart the clock (LCLK) can be sent to the host pr o cessor by m eans of the CLKRUN pin. With LPC data tra nsfer and SER IRQ in cont inuous m ode, a cloc k restart is ne ver req uested since the transfer cycles are initiated b y the host.
Rev. 1.00, 05/04, page 408 of 544 15.5 Interrupt Sources 15.5.1 IBFI1, IBFI2, IBFI3, and E RRI The host interface has four interr upt re quests for the slave processo r (this LSI): IBF1, IB F2, IBF3, and ERRI. IBFI1, IBFI2, and IBFI3 a re IDR r eceive complete interrupts for IDR 1, IDR2, and IDR3 and TWR, respectively.
Rev. 1.00, 05/04, page 409 of 544 Table 15.8 summari zes the methods o f setting a nd clearing the se bits, and figure 15.8 shows th e processing flo wchart.
Rev. 1.00, 05/04, page 410 of 544 Slav e CPU Master CPU ODR1 write Write 1 to IRQ1E1 OBF1 = 0? Yes No No Yes All bytes transf erred? SERIRQ IRQ1 output SERIRQ IRQ1 source clearance Interrupt initiation ODR1 read Hardware operation Software operation Figure 15.
Rev. 1.00, 05/04, page 411 of 544 15.6 Usage Notes 15.6.1 Module Stop Mode Setting LPC operation can be enab led or disabled using the modu le stop control reg ister. The initial setting is for LPC operation to be halted. Regist er access is enabled by canceling modul e stop mode.
Rev. 1.00, 05/04, page 412 of 544 Table 15.9 Host Address Example Register Host Address when LADR3 = H'A 24F Host Address when LADR3 = H'3FD0 IDR3 H'A24A an d H'A24E H'3FD0 an.
ADCMS33B_010020 040200 Rev. 1.00, 05/04, page 413 of 544 Section 16 A/D Converter This LSI includes a succe ssive-approximation-type 10-bit A/D converter that allows up t o six analog input c hannels to be s elected. A/D c onversion for digit al input is e ffective as a c omparator in multiple inpu t testing.
Rev. 1.00, 05/04, page 414 of 544 A block diagram of the A/D conv erter is shown in figur e 16.1. Module data bus Control circuit Internal data bus 10-bit D/A Comparator + Sample-and-hold circuit φ /.
Rev. 1.00, 05/04, page 415 of 544 16.2 Input/Output Pins Table 16.1 summari zes the pins used by the A/ D converter. T he 6 analog input pins a re divided into two groups consisting of four channels and two ch annels. Analog input pins 0 to 3 (AN0 to AN3) compr ising group 0 and analog in put pins 4 and 5 (AN4 and AN5) comprising group 1.
Rev. 1.00, 05/04, page 416 of 544 16.3 Register Descriptions The A/D converter has the following reg isters. • A/D data register A (ADDRA ) • A/D data reg ister B (ADDRB) • A/D data reg ister C (ADDRC) • A/D data register D (ADDRD ) • A/D con trol/status register (ADCSR) • A/D control regist er (ADCR) 16.
Rev. 1.00, 05/04, page 417 of 544 16.3.2 A/D Control/Status Register ( ADCSR) ADCSR controls A/D conversion operations. Bit Bit Name Initial Value R/W Description 7 ADF 0 R/(W) * A/D End Flag A status flag that indicates the end of A/D conversion.
Rev. 1.00, 05/04, page 418 of 544 Bit Bit Name Initial Value R/W Description Channel Select 2 to 0 Select analog input channels. The input channel settin g must be made when conversi on is halted (ADST = 0).
Rev. 1.00, 05/04, page 419 of 544 16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating m odes: single mode and sca n mode. When cha nging the o perating mode or analog i nput channel, to prevent incorrect operation, first cl ear the ADST bit to 0 in ADCSR to halt A/D conversion.
Rev. 1.00, 05/04, page 420 of 544 Figure 16.2 shows the op eration timing. 1. Scan mode is selected (SCAN = 1), scan grou p 0 is selected (CH2 = 0), analog input channels AN0 to AN 2 are selected (C H1 = 1, C H0 = 0), a nd A/D con version is st arted (ADS T = 1).
Rev. 1.00, 05/04, page 421 of 544 16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in samp le-and-hold circuit. The A/D converter samp les the analog input when th e A/D conversion start delay time (t D ) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversi on.
Rev. 1.00, 05/04, page 422 of 544 Table 16.3 A/D Conversio n Time (Single Mode) CKS = 0 CKS = 1 Item Symbol Min. Typ. Max. Min. Typ. Max. A/D conversion start delay time t D 10 — 17 6 — 9 Input sampling time t SPL — 63 — — 31 — A/D conversion time t CONV 259 — 266 131 — 134 Note: * Valu es in the table indicate the number of states.
Rev. 1.00, 05/04, page 423 of 544 16.5 Interrupt Sources The A/D converter generates an A/D con version end interrupt (ADI ) at the end of A/D conversion. Setting the ADIE bit to 1 enab les ADI interrupt requests while th e ADF bit in ADCSR is set to 1 after A/D conversion is completed.
Rev. 1.00, 05/04, page 424 of 544 H'001 H'000 1 1024 2 1024 1022 1024 1023 1024 FS Quantization error Digital output Ideal A/D conversion characteristic Analog input voltage H'002 H'003 H'004 H'3FD H'3FE H'3FF Figure 16.
Rev. 1.00, 05/04, page 425 of 544 16.7 Usage Notes 16.7.1 Permissible Si gnal Source Impedance This LSI's anal og input (3-V versi on) is desi gned so that the conversion a ccu racy is guaranteed for an input sig nal for whic h the si gnal source i mpedance is 5 k Ω or less.
Rev. 1.00, 05/04, page 426 of 544 16.7.3 Setting Range of Analog Power Supply and Other Pins If conditions shown below are not met, the reliab ility of this LSI may be adversely affected.
Rev. 1.00, 05/04, page 427 of 544 AV CC * 1 AN0 to AN5 AV SS Notes: Values are reference values. 2. R in : Input impedance 1. * 1 R in * 2 100 Ω 0.1 µF 0.01 µF 10 µF AV ref Figure 16.8 Example of Anal o g Inp ut P r otec tion Circuit 20 pF To A/D converter AN0 to AN5 10 k Ω Note: * Values are reference values.
Rev. 1.00, 05/04, page 428 of 544.
Rev. 1.00, 05/04, page 429 of 544 Section 17 RAM This LSI has an on-c hip high-spee d static R AM. The RAM is connected to the CPU by a 16-bit data bus, enabl ing one-stat e access by the C PU to both byte data a nd word dat a. The on-chip RAM ca n be enabled or disabl ed by means of the RAME bit in the system cont rol register (SYSC R).
Rev. 1.00, 05/04, page 430 of 544.
ROMF360A_010020 040200 Rev. 1.00, 05/04, page 431 of 544 Section 18 ROM This LSI has an on-c hip RO M (flash me mory). T h e features of the flas h memory are summarized below.
Rev. 1.00, 05/04, page 432 of 544 • Programmer mode In addition to on-boar d progra mming mode, programmer m ode is sup ported to program o r erase the flash memory using a PROM programmer.
Rev. 1.00, 05/04, page 433 of 544 18.2 Mode Transitions When the mode pins are set in the reset state an d a reset-start is exec uted, this LSI enters an operating m ode as sho wn in figu re 18.2. In user mode, flash memory ca n be rea d but not programmed or era sed.
Rev. 1.00, 05/04, page 434 of 544 <Flash memory> <This LSI> <RAM> <Host> Programming control program SCI Application program (old version) Boot program New application program .
Rev. 1.00, 05/04, page 435 of 544 <Flash memory> <This LSI> <RAM> <Host> Programming/ erase control program SCI Boot program New application program <Flash memory> <Th.
Rev. 1.00, 05/04, page 436 of 544 18.3 Block Configuration Figure 18.5 s hows the bl ock config uration of flas h memory . The thick li nes indicate erasi ng units, the narrow lines indicate programming units, and th e values are addresses.
Rev. 1.00, 05/04, page 437 of 544 18.4 Input/Output Pins The flash memory i s controll ed by means of the pins s hown in ta ble 18.2. Table 18.2 Pin Configuration Pin Name I/O Function RES Input Reset.
Rev. 1.00, 05/04, page 438 of 544 18.5.1 Flash Memory Contr ol Reg ister 1 (FL M CR 1 ) FLMCR1, used together with FLMCR2 , makes the flash memory transit to program mode, program-veri fy mode, erase mode, or erase-verify mode. F or detail s on regist er setting, re fer to section 18.
Rev. 1.00, 05/04, page 439 of 544 18.5.2 Flash Memory Control Reg i ster 2 (FL M CR 2 ) FLMCR2 monitors the state of flash memory programming/erasing protection (error pro tection) and sets up the flash memory to transit to programming/erasin g mode. FLMCR2 is initialized to H'00 by a reset or in hardwa re standb y mode.
Rev. 1.00, 05/04, page 440 of 544 18.5.3 Erase Block Registers 1 and 2 (E BR1, EBR2 ) EBR1 and EBR2 are used to specify the flash memory eras e bloc k.
Rev. 1.00, 05/04, page 441 of 544 18.6 Operating Modes The flash memory is connected to the C PU via a 16-bit data bus, en ablin g byte data and wor d data to be accessed in a si ngle state. Even addres ses ar e connected to the uppe r 8 bits and odd addresses are connected to the low er 8 bits.
Rev. 1.00, 05/04, page 442 of 544 18.7.1 Boot Mode Table 18.5 sho ws the boot m ode operati ons between reset end and branching to t he programmi ng control pro gram. 1. When boot mode is use d, the flash memory pr ogramming cont rol progra m must be prepared in the host beforehand.
Rev. 1.00, 05/04, page 443 of 544 7. Boot mode can be cleared by a reset. Ca ncel the reset* 2 after driving the reset pin low, waiting at least 20 states, and then setting the mode pins. B oot mode is also cleared when a WDT overflow occurs. 8. Do not c hange the mode pin i nput levels in boot mo de.
Rev. 1.00, 05/04, page 444 of 544 Table 18.6 System Clock Frequencies for whic h Aut omatic Adjust ment of LSI Bit Rate is Possible Host Bit Rate System Cloc k Frequency Range of LSI 19200 bps 8 to 10.
Rev. 1.00, 05/04, page 445 of 544 18.7.2 User Program Mode On-board p rogramming/ erasing of a n indi vidual flash me mory bl ock can also be performe d in user program mode by bra nching to a use r progra m/erase contro l program. T he user m ust set branc hing conditions an d provide on-bo ard means of supplying p rogramming data.
Rev. 1.00, 05/04, page 446 of 544 18.8 Flash Memory Programming/Erasing A software method, using the CPU, is emp loyed to program and erase flash me mory in the on- board prog ramming mode s.
Rev. 1.00, 05/04, page 447 of 544 START End of programming Set SWE bit in FLMCR1 Start of programming Write pulse application subroutine Wait (x) µ s Sub-Routine Write Pulse End Sub Set PSU bit in FL.
Rev. 1.00, 05/04, page 448 of 544 18.8.2 Erase/Er ase-Verify When erasing flash memory, t he erase/erase-veri fy flowchart show n in figure 18.10 should be followed. 1. Prewriting (setting erase block da ta to all 0) is not necessary. 2. Erasing is performed i n block uni ts.
Rev. 1.00, 05/04, page 449 of 544 End of erasing START Set SWE bit in FLMCR1 Set ESU bit in FLMCR2 Set E bit in FLMCR1 Wait (x) µ s Wait (y) µ s n = 1 Set EBR1 and EBR2 Enable WDT * 4 * 2 * 2 * 2 * .
Rev. 1.00, 05/04, page 450 of 544 18.9 Program/Erase Protection There are three kinds of flash memory program/erase protecti on: hardwa re protectio n, software protection, a nd error protection.
Rev. 1.00, 05/04, page 451 of 544 The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is abort ed at the p oint at whic h the error occ urred. Pr ogram mode or erase mode ca nnot be entered by setting the P or E bit to 1.
Rev. 1.00, 05/04, page 452 of 544 18.11 Programmer Mode In programmer mode, the on-ch ip flash memory can be programmed/erased by a PROM programmer via a socket adapter, just like for a discrete flas h memory. Use a PROM pr ogrammer that supports the Renesas 64-Kby te flash memory on-chip MCU device*.
Rev. 1.00, 05/04, page 453 of 544 18.12 Usage Notes The following li sts notes on the use of on-board pr ogramming modes and program mer mode. 1. Perform programming/erasing with the specified voltage and timing . If a voltage higher tha n the rate d voltage is applie d, the pr oduct may be fatall y damaged.
Rev. 1.00, 05/04, page 454 of 544.
Rev. 1.00, 05/04, page 455 of 544 Section 19 Clock Pulse Generator This LSI incorporates a clock pulse genera tor, which generates the system clock ( φ ), bus master clock, and internal clock.
Rev. 1.00, 05/04, page 456 of 544 19.1 Oscillator Clock pulses can be suppl ied either by conn ecting a crystal resonat or, or by providin g external clock input. 19.1.1 Connecting Crystal Resonator Figure 19.2 s hows a typical method of c onnecting a cryst al resonator.
Rev. 1.00, 05/04, page 457 of 544 19.1.2 External Clock Input Me thod Figure 19.4 shows a typical method of connecting an external clock signal. To leave the XTAL pin open, incide ntal capacit ance should be 10 pF or less.
Rev. 1.00, 05/04, page 458 of 544 Table 19.3 External Clock Input Conditions V CC =3.0 to 3.6 V Item Symbol Min Max Unit Test Conditions External clock input pulse width low level t EXL 40 — ns Exte.
Rev. 1.00, 05/04, page 459 of 544 t DEXT * RES (Internal and external) EXTAL STBY V CC 3.0 V V IH φ Note: * The external clock output stabilization delay time (t DEXT ) includes a RES pulse width (t RESW ). Figure 19.6 Timing of External Cl ock Output Stabili zati on Delay Time 19.
Rev. 1.00, 05/04, page 460 of 544 19.5 Subclock Input Circuit The subclock i nput circuit controls subcl ock input fr om the EXCL pin. To use the subclo ck, a 32.768-k Hz external cl ock shoul d be inp ut from the EXCL pin. At this ti me, the P96 DDR bit in P9DDR should be cleared to 0, and the EX CLE bit in LPWRCR should be set to 1.
Rev. 1.00, 05/04, page 461 of 544 19.7 Clock Select Circuit The clock select circuit selects the syst em clock that is used in this LSI. A clock generated by an oscillator to which the EXTAL and XTAL pins are input is selected as a system clock whe n returni ng from hi gh-speed m ode, medium -speed mode, sl eep mode, reset state, or standby mo de.
Rev. 1.00, 05/04, page 462 of 544.
Rev. 1.00, 05/04, page 463 of 544 Section 20 Power-Down Modes For operati ng modes afte r the reset stat e is cancelled, t his LSI has not only t he normal pr ogram execution stat e but also seve n power-d own modes i n which po wer consu mption is si gnificantl y reduced.
Rev. 1.00, 05/04, page 464 of 544 20.1.1 Standby Control Re gister (SBY CR) SBYCR cont rols powe r-down mo des. Bit Bit Name Initial Value R/W Description 7 SSBY 0 R/W Software Standby Specifies the operating mode to be entered a fter executing the SLEEP instruction.
Rev. 1.00, 05/04, page 465 of 544 Table 20.1 Operating Fr equency and Wait Time ST S 2 STS1 STS0 Wai t T ime 10 MHz 8 MHz 6 MH z 4 MH z Un it 0 0 0 8192 states 0.8 1.0 1.3 20. 0 0 1 16384 states 1.6 2.0 2.7 4.1 0 1 0 32768 states 3.3 4.1 5.5 8.2 0 1 1 65536 states 6.
Rev. 1.00, 05/04, page 466 of 544 Bit Bit Name Initial Value R/W Description 6 LSON 0 R/W Low-Speed On Flag Specifies the operating mode to be entered a fter executing the SLEEP instruction. This bit als o controls whether to shift to high-speed mode or subac tive mode when watch mode is cancelle d.
Rev. 1.00, 05/04, page 467 of 544 20.1.3 Module Stop Control Regi sters H and L (MSTPCRH, MSTPCRL ) MSTPCRH an d MSTPCRL s pecify on-chi p periphe ral modules t o shift to module sto p mode in module units. Each module c an enter mo dule stop mo de by setting t he correspondi ng bit to 1.
Rev. 1.00, 05/04, page 468 of 544 20.2 Mode Transitions and LSI States Figure 20.1 s hows the ena bled mode t ransition dia gram. The mo de transition from progra m execution state to program halt state is performed by the SLEEP i nstruction. The mode transition from program halt state to program exec ution state is pe rformed by a n interru pt.
Rev. 1.00, 05/04, page 469 of 544 Table 20.2 LSI Internal States in Each Oper ating M ode Function High- Speed Medium- Speed Sleep Module Stop Watch Sub- Active Sub- Sleep Software Standby Hardware St.
Rev. 1.00, 05/04, page 470 of 544 20.3 Medium-Speed Mode The CPU makes a transition to medium-sp eed mo de as soon as the cu rrent bus cycle end s according to the setting of the SCK2 t o SCK0 b its in SBYC R. In medium-speed mode, t he CPU operates on the operati ng clock ( φ /2, φ /4, φ /8, φ /16, o r φ /32).
Rev. 1.00, 05/04, page 471 of 544 20.4 Sleep Mode The CPU makes a transition to sleep mo de if th e SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU operation stops but th e peripheral modules do not stop.
Rev. 1.00, 05/04, page 472 of 544 When the RES pin is driven low, system clock oscillation is started. At the same time as system clock oscillation starts, th e system clock is supplied to the entire LSI. Note th at the RES pin must be held low until clock oscillatio n stabilizes.
Rev. 1.00, 05/04, page 473 of 544 20.6 Hardware Standby Mode The CPU makes a transition to hardware standby mode from any mode when the STBY pin is driven low. In hardware st andby mode, al l functions enter the re set state. As long as t he prescribed voltage is supplied, on-chip RAM data is retained.
Rev. 1.00, 05/04, page 474 of 544 20.7 Watch Mode The CPU makes a transition to watch mode wh en the SLEEP instruction is executed in high-speed mode or subactive mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1.
Rev. 1.00, 05/04, page 475 of 544 20.8 Subsleep Mode The CPU makes a transition to subsleep mode when the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR clear ed to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1.
Rev. 1.00, 05/04, page 476 of 544 20.9 Subactive Mode The CPU makes a transition to su bactive mode when t he SLEEP in struction is executed in hi gh- speed mode with th e SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1.
Rev. 1.00, 05/04, page 477 of 544 20.10 Module Stop Mode Module stop mode can be individually set for each on-chip peripheral module. When the cor respondin g MSTP bit in MSTPCR is set to 1, m odule ope ration st ops at the en d of the bus cycle and a tran sition is made to module stop mode.
Rev. 1.00, 05/04, page 478 of 544 20.12 Usage Notes 20.12.1 I/ O Port Statu s The status of the I/O ports is retained in software standby mode. Therefo re, when a high level is output, the c urrent co nsumptio n is not re duced by t he amount o f current to support the high l evel output.
Rev. 1.00, 05/04, page 479 of 544 Section 21 List of Registers The register li st gives info rmation on the on-chip I/O regist er addresses, h ow the regi ster bits are configured, an d the regist er states in eac h operating m ode. The inf ormation is given as s hown below.
Rev. 1.00, 05/04, page 480 of 544 21.1 Register Addresses (Address Order) The data bus width indi cates the numbers of bit s by which the register is accessed. The number of access states indicates t he number of states based on the sp ecified reference clock.
Rev. 1.00, 05/04, page 481 of 544 Register Name Abbreviation Number of Bits Address Module Data Bus Width Number of Access States Bidirectional data register 1 TWR1 8 H'FE21 LPC 8 3 Bidirectional.
Rev. 1.00, 05/04, page 482 of 544 Register Name Abbreviation Number of Bits Address Module Data Bus Width Number of Access States Wakeup event interrupt mask register B WUEMRB 8 H'FE44 INT 8 3 Po.
Rev. 1.00, 05/04, page 483 of 544 Register Name Abbreviation Number of Bits Address Module Data Bus Width Number of Access States Keyboard control registe r H_1 KBCRH_1 8 H'FEDC Keyboa rd buffer .
Rev. 1.00, 05/04, page 484 of 544 Register Name Abbreviation Number of Bits Address Module Data Bus Width Number of Access States Low power control register LPWRCR 8 H'FF85 SYSTEM 8 2 Module stop.
Rev. 1.00, 05/04, page 485 of 544 Register Name Abbreviation Number of Bits Address Module Data Bus Width Number of Access States Output control register AFL OCRAFL 8 H'F F9B FRT 8 2 Input captur.
Rev. 1.00, 05/04, page 486 of 544 Register Name Abbreviation Number of Bits Address Module Data Bus Width Number of Access States Port 8 data direction register P8DDR 8 H'FFBD (write) PORT 8 2 Po.
Rev. 1.00, 05/04, page 487 of 544 Register Name Abbreviation Number of Bits Address Module Data Bus Width Number of Access States I 2 C bus mode register_0 ICMR_0 8 H'FFDF IIC_0 8 2 Slave address.
Rev. 1.00, 05/04, page 488 of 544 Register Name Abbreviation Number of Bits Address Module Data Bus Width Number of Access States Input capture register F TICRF 8 H'FFF3 TMR_X 16 2 Time constant .
Rev. 1.00, 05/04, page 489 of 544 21.2 Register Bits Register addre sses and bit names of t he on-chip peripheral mo dules are descri bed below . Each line covers 8 bits, and 16-bit registers are shown as 2 lines.
Rev. 1.00, 05/04, page 490 of 544 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi t 1 Bit 0 Module TWR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TWR2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 .
Rev. 1.00, 05/04, page 491 of 544 Register Abbreviation Bit 7 Bit 6 Bi t 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module WUEMRB WUEMR7 WUEMR6 WUEMR5 WUEMR4 WUEMR3 WUEMR2 WUEMR1 WUEMR0 INT PGODR PG7ODR PG6ODR P.
Rev. 1.00, 05/04, page 492 of 544 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi t 1 Bit 0 Module ICRA ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 I CRA2 ICRA1 ICRA0 ICRB ICRB7 ICRB6 ICRB5 ICRB4 ICRB3.
Rev. 1.00, 05/04, page 493 of 544 Register Abbreviation Bit 7 Bit 6 Bi t 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TIER ICIAE ICIBE ICICE ICIDE OCI AE OCIBE OVIE — TCSR ICFA ICFB ICFC ICFD OCFA OCFB OV.
Rev. 1.00, 05/04, page 494 of 544 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi t 1 Bit 0 Module PAODR PA7ODR PA6ODR PA5ODR PA4O DR PA3ODR PA2ODR PA1ODR PA0ODR PAPIN PA7PIN PA6PIN PA5 P.
Rev. 1.00, 05/04, page 495 of 544 Register Abbreviation Bit 7 Bit 6 Bi t 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCR_0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TCR_1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS.
Rev. 1.00, 05/04, page 496 of 544 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi t 1 Bit 0 Module TCR_X CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_X TCR_Y CMIEB CMIEA OVIE CCLR1 CCL.
Rev. 1.00, 05/04, page 497 of 544 21.3 Register States in Each Operating Mode Register Abbrevia- tion Reset High-Speed/ Medium- Speed Watch Sleep Sub- Active Sub-Sleep Module Stop Software Standby Har.
Rev. 1.00, 05/04, page 498 of 544 Register Abbrevia- tion Reset High-Speed/ Medium- Speed Watch Sleep Sub- Active Sub-Sleep Module Stop Software Standby Hardware Standby Module TWR6 — — — — .
Rev. 1.00, 05/04, page 499 of 544 Register Abbrevia- tion Reset High-Speed/ Medium- Speed Watch Sleep Sub- Active Sub-Sleep Module Stop Software Standby Hardware Standby Module WUEMRB Initialized — .
Rev. 1.00, 05/04, page 500 of 544 Register Abbrevia- tion Reset High-Speed/ Medium- Speed Watch Sleep Sub- Active Sub-Sleep Module Stop Software Standby Hardware Standby Module ICRA Initialized — .
Rev. 1.00, 05/04, page 501 of 544 Register Abbrevia- tion Reset High-Speed/ Medium- Speed Watch Sleep Sub- Active Sub-Sleep Module Stop Software Standby Hardware Standby Module TIER Initialized — .
Rev. 1.00, 05/04, page 502 of 544 Register Abbrevia- tion Reset High-Speed/ Medium- Speed Watch Sleep Sub- Active Sub-Sleep Module Stop Software Standby Hardware Standby Module PAODR Initialized — .
Rev. 1.00, 05/04, page 503 of 544 Register Abbrevia- tion Reset High-Speed/ Medium- Speed Watch Sleep Sub- Active Sub-Sleep Module Stop Software Standby Hardware Standby Module TCR_0 Initialized — .
Rev. 1.00, 05/04, page 504 of 544 Register Abbrevia- tion Reset High-Speed/ Medium- Speed Watch Sleep Sub- Active Sub-Sleep Module Stop Software Standby Hardware Standby Module TCR_X Initialized — .
Rev. 1.00, 05/04, page 505 of 544 21.4 Register Select Conditions Lower Address Register Name Regist er Select Condition Module Name H'FE00 TCR_B H'FE01 TCR_A H'FE02 TCSR_B H'FE03 .
Rev. 1.00, 05/04, page 506 of 544 Lower Address Register Name Regist er Select Condition Module Name TWR0MW H'FE20 TWR0SW H'FE21 TWR1 H'FE22 TWR2 H'FE23 TWR3 H'FE24 TWR4 H&apo.
Rev. 1.00, 05/04, page 507 of 544 Lower Address Register Name Regist er Select Condition Module Name H'FE44 WUEMRB No condition INT H'FE46 PGODR H'FE47 PGPIN (read) PGDDR (write) H&apos.
Rev. 1.00, 05/04, page 508 of 544 Lower Address Register Name Regist er Select Condition Module Name H'FEE8 ICRA H'FEE9 ICRB H'FEEA ICRC H'FEEB ISR H'FEEC ISCRH H'FEED IS.
Rev. 1.00, 05/04, page 509 of 544 Lower Address Register Name Regist er Select Condition Module Name OCRAH OCRS = 0 in TOCR H'FF94 OCRBH OCRS = 1 in TOCR OCRAL OCRS = 0 in TOCR H'FF95 OCRBL .
Rev. 1.00, 05/04, page 510 of 544 Lower Address Register Name Regist er Select Condition Module Name H'FFAA PAODR No condition PORT H'FFAB PAPIN (read) PADDR (write) H'FFAC P1PCR H&apos.
Rev. 1.00, 05/04, page 511 of 544 Lower Address Register Name Regist er Select Condition Module Name H'FFC8 TCR_0 MSTP12 = 0 TMR_0, TMR_1 H'FFC9 TCR_1 H'FFCA TCSR_0 H'FFCB TCSR_1 H.
Rev. 1.00, 05/04, page 512 of 544 Lower Address Register Name Regist er Select Condition Module Name H'FFEA TCSR_1 No condition WDT_1 TCNT_1 (write) H’FFEB TCNT_1 (read) H'FFF0 TCR_X TMRX/.
Rev. 1.00, 05/04, page 513 of 544 Section 22 Electrical Charact eristics 22.1 Absolute Maximum Ratings Table 22.1 lists the absolute max imum ratings. Table 22.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage V CC , V CL –0.3 to +4.
Rev. 1.00, 05/04, page 514 of 544 22.2 DC Charac teristics Table 22.2 lists the DC characteristics. Permitted output current values and bus drive characteristics are shown in tables 22.3 and 22.4, respectively. Table 22.2 DC Charac teristics ( 1) Conditions : V CC = 3.
Rev. 1.00, 05/04, page 515 of 544 Item Symbol Min. Typ. Max. Unit Test Conditions All output pins (except RESO ) * 5 — — 0.4 V I OL = 1.6 mA Ports 1 to 3 — — 1.0 V I OL = 5 mA Output low voltage RESO V OL — — 0.4 V I OL = 1.6 mA Notes: 1. Do not leave the AV cc , AV ref , and AV ss pins open even if the A/D converter is not used.
Rev. 1.00, 05/04, page 516 of 544 Table 22.2 DC Characteri stics (2) Conditions : V CC = 3.0 V t o 3.6 V* 5 , V CC B = 3.0 V to 5.5 V, AV CC * 1 = 3.0 V to 3.6 V , AV ref * 1 = 3.0 V to AV CC , V SS = AV SS * 1 = 0 V, T a = –20 to +7 5°C Item Symbol Min.
Rev. 1.00, 05/04, page 517 of 544 Item Symbol Min. Typ. Max. Unit Test Conditions 3.0 — 3.6 Operating Analog power supply voltag e * 1 AV CC 2.0 — 3.6 V Idle/not used RAM standby voltage V RAM 2.0 — — V Notes: 1. Do not leave the AV CC , AV ref , and AV SS pins open even if the A/D converter is not used.
Rev. 1.00, 05/04, page 518 of 544 Table 22.3 Permissible Output Currents Conditions : V CC = 3.0 V to 3.6 V, V CC B = 3.0 V to 5.5 V, V SS = 0 V, T a = –20 to +75°C Item Symbol Min.
Rev. 1.00, 05/04, page 519 of 544 600 Ω This LSI Ports 1 to 3 LED Figure 22.2 LED Drive Circuit (Example) Table 22.4 Bus Drive Characteristics Conditions : V CC = 3.0 V to 3.6 V, V SS = 0 V, Ta = –20 to +75°C Applicable Pins: SCL1, SCL0, SDA1, SDA0 ExSDAA, ExSCLA, ExSDAB, ExSCLB (bus drive function selected) Item Symbol Min.
Rev. 1.00, 05/04, page 520 of 544 Conditions : V CC = 3.0 V to 3.6 V, V CC B = 3.0 V to 5.5 V, V SS = 0 V, Ta = –20 to +75°C Applicable Pins: PS2AC, PS2AD, PS2BC, PS 2 BD, PS2CC, PS2CD , PA7 to PA4 (bu s drive function selected) Item Symbol Min. Typ.
Rev. 1.00, 05/04, page 521 of 544 22.3.1 Clock Timing Table 22.5 sho ws the clock ti ming. The cl ock timi ng specified he re covers cl ock ( φ ) outp ut and clock pulse generator (cry stal) and external clock input (EXTAL pin) oscillat ion settling times.
Rev. 1.00, 05/04, page 522 of 544 22.3.2 Control Signal Timing Table 22.6 sho ws the control signal timi ng. The o nly external interrupts th at can operate on the subclock ( φ = 32.7 68 kHz) a re NMI and IRQ0, 1, 2, 6, an d 7. Table 22.6 Control Signal Timing Conditions : V CC = 3.
Rev. 1.00, 05/04, page 523 of 544 22.3.3 Timing of On-Chip Peripheral Modules Tables 22.7 to 22.10 show the on- chip peripheral module timing. Th e only on-chip peripheral modules that c an operate in subclock operation ( φ = 32.
Rev. 1.00, 05/04, page 524 of 544 Condition 10 MHz Item Symbol Min. Max. Unit Test Conditions Transmit data delay time (synchronous) t TXD — 100 ns Receive data setup time (synchronous) t RXS 100 — ns SCI Receive data hold time (synchronous) t RXH 100 — ns Figure 22.
Rev. 1.00, 05/04, page 525 of 544 Table 22.9 I 2 C Bus Timing Conditions : V CC = 3.0 V to 3.6 V, V SS = 0 V, φ = 5 MHz t o maximum o perating freq uency, T a = –20 to + 75°C Ratings Item Symbol Min.
Rev. 1.00, 05/04, page 526 of 544 Table 22.10 LPC Module Timing Conditions : V CC = 3.0 V to 3.6 V, V SS = 0 V, φ = 4 MHz t o maximum operating f requency, T a = –20 to + 75°C Item Symbol Min.
Rev. 1.00, 05/04, page 527 of 544 22.5 Flash Memory Characteristics Table 22.12 s hows the flas h memory chara cteristic s. Table 22.12 Flash Memory Characteristi cs Conditions : V CC = 3.0 V to 3.6 V, V SS = 0 V, T a = –20 to +75°C Item Symbol Min.
Rev. 1.00, 05/04, page 528 of 544 Item Symbol Min. Typ. Max. Unit Test Conditions Wait time after SWE-bit setting * 1 x 1 — — µs Wait time after ESU-bit setting * 1 y 100 — — µs Wait time af.
Rev. 1.00, 05/04, page 529 of 544 22.6 Usage Note The method of connecting an ex ternal capacitor is shown in fi gure 22.4. Connect th e system power sup ply to the VCL pin together with the VCC pins. VCL VSS 0.01 µF 10 µF Bypass capacitor Vcc power supply < Vcc = 3.
Rev. 1.00, 05/04, page 530 of 544 t OSC1 t OSC1 EXTAL V CC STBY RES φ t DEXT t DEXT Figure 22.6 Oscilla tion Settling Timing φ NMI IRQi (i = 0, 1, 2, 6, 7) t OSC2 Figure 22.
Rev. 1.00, 05/04, page 531 of 544 22.7.2 Control Signal Timing The control signal timings ar e shown below. t RESW t RESS φ t RESS RES Figure 22.8 Reset Input Timing t IRQS φ t NMIS t NMIH IRQi Edge input (i = 7 to 0) NMI t IRQS t IRQH IRQi (i = 7 to 0) IRQi Level input (i = 7 to 0) t NMIW t IRQW Figure 22.
Rev. 1.00, 05/04, page 532 of 544 22.7.3 On-Chip Peripheral Module Timing The on-chip peri pheral modul e timings are shown bel ow. φ Ports 1 to 9, and A to G (read) T 2 T 1 t PWD t PRH t PRS Ports 1 to 6, 8, 9, and A to G (write) Figure 22.10 I/O Port Inpu t/Output Timing φ t FTIS t FTOD FTOA, FTOB FTIA, FTIB, FTIC, FTID Figure 22.
Rev. 1.00, 05/04, page 533 of 544 φ TMO0, TMO1 TMOX, ExTMOX, TMOY, TMOA, TMOB t TMOD Figure 22.13 8-Bit Timer Output Timing φ TMCI0, TMCI1 TMIX, TMIY, ExTMIX, ExTMIY, TMIA, TMIB t TMCS t TMCS t TMCWH t TMCWL Figure 22.14 8-Bit Timer Clock Input Ti ming φ t TMRS TMRI0, TMRI1 TMIX, TMIY, ExTMIX, ExTMIY, TMIA, TMIB Figure 22.
Rev. 1.00, 05/04, page 534 of 544 SCK1, ExSCK1 t SCKW t SCKr t SCKf t Scyc Figure 22.17 SCK Cl ock Input Timing TxD1, ExTxD1 (transmit data) RxD1, ExRxD1 (receive data) SCK1, ExSCK1 t RXS t RXH t TXD Figure 22.18 SCI Input/Output Timing (Synchronous Mode) φ ADTRG t TRGS Figure 22.
Rev. 1.00, 05/04, page 535 of 544 1. Reception φ KCLK/KD * KCLK/KD * t KBIS t KBIH Transmission (b) t KBF 2. Transmission (a) φ KCLK/KD * T 1 T 2 t KBOD Note: φ shown here is the clock scaled by 1/N when the operating mode is active medium-speed mode.
Rev. 1.00, 05/04, page 536 of 544 LCLK LAD3 to LAD0, SERIRQ, CLKRUN (Transmit signal) LAD3 to LAD0, SERIRQ, CLKRUN LFRAME (Receive signal) t TXD t RXH t RXS t OFF LAD3 to LAD0, SERIRQ, CLKRUN (Transmit signal) t Lcyc t LCKH LCLK t LCKL Figure 22.23 Host I nterface (LPC) Timing Testing voltage: 0.
Rev. 1.00, 05/04, page 537 of 544 Appendix A. I/O Port States in Each Processin g State Table A.1 I/O Port States in Each Proc essing State Port Name Pin Name Reset Hardware Standby Mode Software Stan.
Rev. 1.00, 05/04, page 538 of 544 B. Product Codes Product Type Product Co de Mark Code Package (Package Code) H8S/2111B-B HD64F2111BVB F2111BVTE10B H8S/2111B-C Flash memory version (3 V version) HD64.
Rev. 1.00, 05/04, page 539 of 544 C. Package Dimensions For package dimensi ons, dimensi ons described in Renesas Semiconducto r Packages Data Book have priority. Package Code JEDEC EIAJ Weight (reference value) TFP-144 — Conforms 0.6 g Unit: mm * Dimension including the plating thickness Base material dimension 108 73 1 36 0 ˚ – 8 ˚ 0.
Rev. 1.00, 05/04, page 540 of 544.
Rev. 1.00, 05/04, page 541 of 544 Index 16-bit count mode ................................... 210 16-bit free-running timer (FRT) ............. 157 8-bit PWM timer ( PWM)........................ 147 8-bit timer (T MR) .................................
Rev. 1.00, 05/04, page 542 of 544 ICIX ........................................................ 215 IICI ......................................................... 337 Immediate ................................................. 42 Increment tim ing ...
Rev. 1.00, 05/04, page 543 of 544 ICXR....................302, 482, 491, 499, 507 IDR ...................... 380, 481, 490, 498, 506 IER .........................73, 486, 494, 502, 510 ISCR ......................72, 483, 492, 500, 508 ISR ............
Rev. 1.00, 05/04, page 544 of 544 TCONRI .............. 203, 488, 496, 504, 512 TCONRS ............. 203, 488, 496, 504, 512 TCOR .................. 191, 486, 495, 503, 511 TCORC ................ 202, 488, 496, 504, 512 TCR .................... 166, 192, 484, 486, 493, .
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2111B Publication Date: Rev.1.00, May 14, 2004 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co.
Colophon 1.0 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited.
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H8S/2111B Hardware Manual.
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