SamsungメーカーS3C84E5の使用説明書/サービス説明書
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USER'S MANUAL ERRATA This document contains the corrections of errors, typos and omissions in the following document. Samsung 8 - bit CMOS S3C84E5/C84E9/P84E9 Microprocessor User's Manual Document Number: 21 .
S3C84E5/C84E9/P84E9 USER’S MA NUA L ERRA TA 1 ERRATA ( VER 1.1) Samsung 8-bit CMOS S3C84E5/C84E9/P 84E9 Microprocessor User’s Manual Document Number: 21.1- S3-C84E5/C84E9/P84E9-082005 Publication: August 2005 1. Features (PAGE 1-2) Built-in RESET circuit (LVR) • Low-Voltage reset (LVR value: 2.
USER’S MANUA L ERRA TA S3C84E5/C84E9/P84E9 2 3. Low Voltage Reset (PAGE 16-2) + - V REF BGR V DD V REF V IN VDD Longger than 1us N.F Internal System RESET W hen the V DD level is lower than 2.9V Comparator NOTES: 1. The target of voltage detection level is 2.
S3C84E5/C84E9/P84E9 USER’S MANUA L ERRA TA 3 4. Table 17-3. D.C. Electrical Characteristics (PAGE 17-3) (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.5 V) Parameter Symbol Conditions Min Ty p. Max Unit Input high voltage V IH1 V DD = V LVR to 5.
USER’S MANUA L ERRA TA S3C84E5/C84E9/P84E9 4 5. Table 17-3. D.C. Electri cal Characteristics (PAGE 17-4) (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.
S3C84E5/C84E9/P84E9 USER’S MANUA L ERRA TA 5 6. Table 17-4. A.C. Electri cal Characteristics (PAGE 17-5) (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.5 V) 7. Table 17-5. Main Oscillator Frequency (PAGE 17-6) (T A = – 25 ° C + 85 ° C, V DD = V LVR to 5.
USER’S MANUA L ERRA TA S3C84E5/C84E9/P84E9 6 10. Table 17-8. Subsystem Oscillator (c ry stal) Stabilization Time (PAGE 17-7) (T A = 25 ° C) Oscillator Test Condition Min Typ. Max Unit Normal mode V DD = 4.5 V to 5.5 V – 800 1600 ms V DD = V LVR to 3.
S3C84E5/C84E9/P84E9 USER’S MANUA L ERRA TA 7 13. Table 17-11. A/D Converter Elect rical Characteristics (PAGE 17-11) (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.
S3C84E5/C84E9/P84E9 8 - BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 1 .1.
Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibi lity, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.
S3C84E5/C84E9/P84E9 MICROCONTROLLER iii Preface The S3C84E5/C84E9/P84E9 Microcontroller User's Manual is designed for application designers and programmers who are using the S3C84E5/C84E9/P84E9 microcontr oller for application development.
S3C84E5/C84E9/P84E9 MICROCONTROLLER v Table of Contents Part I — Programming Model Chapter 1 Product Overview S3C8 - SERIES Microcontrollers ............................................................................................................
vi S3C84E5/C84E9/P84E9 MICROCONTROLLER Table of Contents (Continued) Chapter 4 Control Registers Overview ............................................................................................................................................. 4 - 1 Chapter 5 Interrupt Structure Overview .
S3C84E5/C84E9/P84E9 MICROCONTROLLER vii Table of Contents (Continued) Part II Hardware Descriptions Chapter 7 Clock Circuit Overview ......................................................................................................................
viii S3C84E5/C84E9/P84E9 MICROCONTROLLER Table of Contents (Continued) Chapter 11 8 - bit Timer A/B 8 - Bit Timer A .......................................................................................................................................
S3C84E5/C84E9/P84E9 MICROCONTROLLER ix Table of Contents (Continued) Chapter 15 8 - bit Analog - to - Digital Converter Overview ..........................................................................................................................
S3C84E5/C84E9/P84E9 MICROCONTROLLER xi List of Figures Figure Title Page Number Number 1 - 1 S3C84E5/C84E9/P84E9 Block Diagram ................................................................ 1 - 3 1 - 2 S3C84E5/C84E9/P84E9 Pin Assignment (44 - pin QFP) .
xii S3C84E5/C84E9/P84E9 MICROCONTROLLER List of Figures (Continued) Figure Title Page Number Number 5 - 1 S3C8 - Series Interrupt Types ................................................................................. 5 - 2 5 - 2 S3C84E5/C84E9/P84E9 Interrupt Structure .
S3C84E5/C84E9/P84E9 MICROCONTROLLER xiii List of Figures (Concluded) Page Title Page Number Number 12 - 1 Timer 1(0,1) Cont rol Register (T1CON0, T1CON1) ................................................... 12 - 4 12 - 2 Timer A, Timer 1(0,1) Pending Register (TINTPND) .
S3C84E5/C84E9/P84E9 MICROCONTROLLER xv List of Tables Table Title Page Number Number 1 - 1 S3C84E5/C84E9/P84E9 Pin Descriptions .............................................................. 1 - 6 2 - 1 S3C84E5/C84E9/P84E9 Register Type Summary ......
xvi S3C84E5/C84E9/P84E9 MICROCONTROLLER List of Tables (Continued) Table Title Page Number Number 19 - 1 Descriptions of Pins Used to Read/Writ e the OTP .................................................. 19 - 3 19 - 2 Comparison of S3P84E9 and S3C84E5/C84E9 Features .
S3C84E5/C84E9/P84E9 MICROCONTROLLER xvii List of Programming Tips Description Page Number Chapter 2: Address Spaces Using the Page Pointer for RAM clear (Page 0, Page 1) .......................................................................... 2 - 6 Setting the Register Pointers .
S3C84E5/C84E9/P84E9 MICROCONTROLLER xix List of Register Desc riptions Register Full Register Name Page Identifier Number ADCON A/D Converter Control Register F7H Set 1, Bank 0 ................................................. 4 - 5 BTCON Basic Timer Control Register H Set 1 .
S3C84E5/C84E9/P84E9 MICROCONTROLLER xxi List of Instruction Descriptions Instruction Full Register Name P age Mnemonic Number ADC Add with Carry .................................................................................................... 6 - 14 ADD Add .
xxii S3C84E5/C84E9/P84E9 MICROCONTROLLER List of Instruction Descriptions (Continued) Instruction Full Register Name Page Mnemonic Nu mber LDC/LDE Load Memory ............................................................................................
S3C84E5/C84E9/P84E9 PRODUCT OVERVIEW 1-1 1 PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8-series of 8-bit single-chip CMOS microc ontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programm able ROM sizes.
PRODUCT OVERVIEW S3 C84E5/C84E9/P84E9 1-2 FEATURES CPU • SAM88RC CPU core Memory • 528-bytes internal register file • 16K/32Kbytes internal program memory (S3C84E5/C84E9:Mask ROM) (S3P84E9:OTP) .
S3C84E5/C84E9/P84E9 PRODUCT OVERVIEW 1-3 BLOCK DIAGRAM ADC0~ ADC7/ P3. 0~P3. 7 I/O P o rt a n d In te rru p t C o n tro l SAM 88RC CPU 16K/32K-Byt e ROM 528-Byt e RAM OSC/nRESET 8-Bi t Basic Ti m er 8- Bi t Ti mer / Count er A, B 16-Bi t Ti mer / Count er 10, 11 Por t 0 Por t 1 Por t 2 P2.
PRODUCT OVERVIEW S3 C84E5/C84E9/P84E9 1-4 PIN ASSIGNMENT TBPWM/ P4. 3 INT10/ P4.2 VDD VSS Xout Xin TEST S3C84E5 S3C84E9 S3P84E9 Top View (44-QFP) 1 2 3 4 5 6 7 8 9 10 11 P4.4 P0.2/T1CAP1 P0.3/T1CK1 P0.4/T1OUT 1 P0.5/T1CAP0 P0.6/TACK P0.7/TACAP P1.0/TAOUT P1.
S3C84E5/C84E9/P84E9 PRODUCT OVERVIEW 1-5 PIN ASSIGNMENT TACAP/P0.7 TACK/P0.6 T1CAP0/P0.5 T1OUT1/P0.4 T1CK1/P0.3 T1CAP1/P0.2 XTout/ P0.1 XTin/ P0.0 TBPWM/P4.3 INT10/P4. 2 VDD VSS Xout Xin TEST INT9/P4.1 INT8/P4.0 nRESET INT0/P2.0 INT1/P2 .1 INT2/P2.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 P1.
PRODUCT OVERVIEW S3 C84E5/C84E9/P84E9 1-6 PIN DESCRIPTIONS Table 1-1. S3C84E5/C84E 9/P84E9 Pin Descriptions Pin Name Pin Type Pin Description Circuit Type Pin Number Share Pins P0.0–P0.7 I/O Bit programmable port; input or output mode selected by software; input or push-pull output.
S3C84E5/C84E9/P84E9 PRODUCT OVERVIEW 1-7 Table 1-1. S3C84E5/C84E9/P84E 9 Pin Descriptions (Continued) Pin Name Pin Type Pin Description Circuit Type Pin Number Share Pins INT0–INT10 I Input pins for external interrupt. Alternatively used as general-purpose digital input/output port 2,4.
PRODUCT OVERVIEW S3 C84E5/C84E9/P84E9 1-8 PIN CIRCUITS Schmitt Trigger In V DD Pull-Up Resistor Figure 1-4. Pin Circuit Type B (nRESET) P-Channel N-Channel V DD Out Output Disable Data Figure 1-5.
S3C84E5/C84E9/P84E9 PRODUCT OVERVIEW 1-9 I/O Output Disa ble Data Pin Circuit Type C Pull-up Enable V DD Figure 1-6. Pin Circuit Type D (P0.2-P0.7, P1, P4.3–P4.5) I/O Output Disa ble Data Pin Circuit Typ e C Pull-up Enable V DD Nois e Filter Ext.INT Input Normal V DD Figure 1-7.
PRODUCT OVERVIEW S3 C84E5/C84E9/P84E9 1-10 V DD Pull-up Resistor (Typical Value: 47k Ω ) V DD Pull-up Enable Data Normal Input Output DIsable In/Out Analog Input Figure 1-8.
S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 1 2 ADDRESS SPACES OVERVIEW The S3C84E5/C84E9/P84E9 microcontroller has two types of address space: — Internal program memory (ROM) — Internal register file (RAM) A 16 - bit address bus supports program memory operations.
ADDRESS SPACES S3C8 4E5/C84E9/P84E9 2 - 2 PROGRAM MEMORY (ROM) Program memory (ROM) stores program codes or table data. The S 3C84E5/84E9 has 16Kbytes and 32Kbytes of internal mask programmable program memory. The program memory address range is therefore 0H – 3FFFH and 0H - 7FFFH (see Figure 2 - 1).
S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 3 REGISTER ARCHITECTUR E In the S3C84E5/C84E9/P84E9 implementation, the upper 64 - byte area of register files is expanded two 64 - byte areas, called set 1 and set 2 .
ADDRESS SPACES S3C8 4E5/C84E9/P84E9 2 - 4 Bank 1 FFH E0H 32 Bytes E0H DFH D0H CFH C0H 64 Bytes System and Peripheral Control Registers (Register Addressing Mode) System and Peripheral Control Register.
S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 5 REGISTER PAGE POINTE R (PP) The S3C8 - series architecture supports the logical expansion of the physical 512 - byte internal register file (using an 8 - bit data bus) into as many as 2 separately addressa ble register pages.
ADDRESS SPACES S3C8 4E5/C84E9/P84E9 2 - 6 F PROGRAMMING TIP — Using the Page Pointer for RAM clear (Page 0, Page 1) LD PP,#00H ; Destination ← 0, Source ← 0 SRP #0C0H LD R0,#0FFH ; Page 0 RAM cl.
S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 7 REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H – FFH. The upper 32 - byte area of this 64 - byte space (E0H – FFH) is expanded two 32 - byte register banks, bank 0 and bank 1 .
ADDRESS SPACE S S3C84E5/C84E9/P84 E9 2 - 8 PRIME REGISTER SPACE The lower 192 bytes (00H – BFH) of the S3C84E5/C84E9/P84E9's two 256 - byte register pages is called prime register area. Prime registers can be accessed using any of the seven addressing modes (see Chapter 3, "Addressing Modes.
S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 9 WORKING REGISTERS Instructions can access specif ic 8 - bit registers or 16 - bit register pairs using either 4 - bit or 8 - bit address fields.
ADDRESS SPACE S S3C84E5/C84E9/P84 E9 2 - 10 USING THE REGISTER P OINTERS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1 , are used to select two movable 8 - byte working register slices in the register file.
S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 11 16-byte Non- contiguous working register block Register File Contains 32 8-Byte Slices 8-Byte Slice 0H (R8) 7H (R15) F0H (R0) F7H (R7) RP1 RP0 1 1 1 1 0 X X X 0 0 0 0 0 X X X 8-Byte Slice Figure 2 - 7.
ADDRESS SPACE S S3C84E5/C84E9/P84 E9 2 - 12 REGISTER ADDRESSING The S3C8 - series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time.
S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 13 RP1 RP0 Register Pointers 00H All Addressing Modes Page 0-1 Indirect Register, Indexed Addressing Modes Page 0-1 Register Addressing Only Can be pointed by Re.
ADDRESS SPACE S S3C84E5/C84E9/P84 E9 2 - 14 COMMON WORKING REGIS TER AREA (C0H – CFH) After a reset, register pointers RP0 and RP1 automatically select two 8 - byte register slices in set 1, locatio.
S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 15 F PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access wo rking registers in the common area, locations C0H – CFH, using working register addressing mode only.
ADDRESS SPACE S S3C84E5/C84E9/P84 E9 2 - 16 Together they create an 8-bit register address Register pointer provides five high-order bits Address OPCODE Selects RP0 or RP1 RP1 RP0 4-bit address provides three low-order bits Figure 2 - 11.
S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 17 8 - BIT WORKING REGIST ER ADDRESSING You can also use 8 - bit working register addressing to access registers in a selected working register area. To initiate 8 - bit working regi ster addressing, the upper four bits of the instruction address must contain the value "1100B.
ADDRESS SPACE S S3C84E5/C84E9/P84 E9 2 - 18 8-bit address form instruction 'LD R11, R2' RP0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 Selects RP1 R11 Register address (0ABH) RP1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 Specifies working register addressing Figure 2 - 14.
S3C84E5/C84E9/P84E9 ADDRESS SPACES 2 - 19 SYSTEM AND USER STACK The S3C8 - series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH and POP instructions are used to control system stack operations. The S3C84E5/C84E9/P84E architecture supports stack operations in th e internal register file.
ADDRESS SPACE S S3C84E5/C84E9/P84 E9 2 - 20 F PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register .
S3C84E5/C84E9/P84E9 ADDRESSING MODES 3 - 1 3 ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operate d on.
ADDRESSING MODES S3 C84E5/C84E9/P84E9 3 - 2 REGISTER ADDRESSING MODE (R) In Register addressing mode (R), the operand value is the content of a specified register or register pair (see Figur e 3 - 1).
S3C84E5/C84E9/P84E9 ADDRESSING MODES 3 - 3 INDIRECT REGISTER AD DRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand.
ADDRESSING MODES S3 C84E5/C84E9/P84E9 3 - 4 INDIRECT REGISTER AD DRESSING MODE (C ontinued ) dst OPCODE PAIR Points to Register Pair Example Instruction References Program Memory Sample Instructions: .
S3C84E5/C84E9/P84E9 ADDRESSING MODES 3 - 5 INDIRECT REGISTER ADDRESSING MODE (C ontinued ) dst OPCODE ADDRESS 4-bit Working Register Address Point to the Working Register (1 of 8) Sample Instruction: .
ADDRESSING MODES S3 C84E5/C84E9/P84E9 3 - 6 INDIRECT REGISTER AD DRESSING MODE (C ontinued ) dst OPCODE 4-bit Working Register Address Sample Instructions: LCD R5,@RR6 ; Program memory access LDE R3,@.
S3C84E5/C84E9/P84E9 ADDRESSING MODES 3 - 7 INDEXED ADDRESSING M ODE (X) Inde xed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3 - 7). You can use Indexed addressing mode to access locations in the internal register file or in ex ternal memory.
ADDRESSING MODES S3 C84E5/C84E9/P84E9 3 - 8 INDEXED ADDRESSING M ODE (C ontinued ) Register File OPERAND Program Memory or Data Memory Point to Working Register Pair (1 of 4) LSB Selects 16-Bit addres.
S3C84E5/C84E9/P84E9 ADDRESSING MODES 3 - 9 INDEXED ADDRESSING M ODE (C ontinued ) Register File OPERAND Program Memory or Data Memory Point to Working Register Pair LSB Selects 16-Bit address added to.
ADDRESSING MODES S3 C84E5/C84E9/P84E9 3 - 10 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16 - bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16 - bit destination address that is loaded into the PC whenever a JP or CALL i nstruction is executed.
S3C84E5/C84E9/P84E9 ADDRESSING MODES 3 - 11 DIRECT ADDRESS MODE (C ontinued ) OPCODE Program Memory Lower Address Byte Memory Address Used Upper Address Byte Sample Instructions: JP C,JOB1 ; Where JOB1 is a 16-bit immediate address CALL DISPLAY ; Where DISPLAY is a 16-bit immediate address Next OPCODE Figure 3 - 11.
ADDRESSING MODES S3 C84E5/C84E9/P84E9 3 - 12 INDIRECT ADDRESS MOD E (IA) In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memor y. The selected pair of memory locations contains the actual address of the next instruction to be executed.
S3C84E5/C84E9/P84E9 ADDRESSING MODES 3 - 13 RELATIVE ADDRESS MOD E (RA) In Relative Address (RA) mode, a twos - complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value.
ADDRESSING MODES S3 C84E5/C84E9/P84E9 3 - 14 IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used.
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 1 4 CONTROL REGISTERS OVERVIEW Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual.
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 2 Table 4 - 2. Set 1, Bank 0 Registers Register Name Mnemonic Decimal Hex R/W Port 0 data register P0 224 E0H R/W Port 1 data register P1 225 E1H R/W Port 2 .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 3 Table 4 - 3. Set 1, Bank 1 Registers Register Name Mnemonic Decimal Hex R/W Timer A, Timer 1 interrupt pending register TINTPND 224 E0H R/W Timer A control r.
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 4 FLAGS - System Flags Register .7 Carry Flag (C) .6 Zero Flag (Z) .5 Bit Identifier RESET Value Read/Write Bit Addressing Mode R = Read-only W = Write-only .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 5 ADCON — A/D Converter Control Register F7H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 R ead/Write – R/W R/W R/W R R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 6 BTCON — Basic Timer Control Register D3 H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register address ing mode only .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 7 CLKCON — System Clock Control Register D4H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write – – – R/W R/W – – – Addressing Mode Register addressing mode only .
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 8 FLAGS — System Flags Register D5H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x 0 0 Read/Write R/W R/W R/W R/W R/W R/W R R/W Addressing Mode Register addressing mode only .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 9 IMR — Interrupt Mask Register DDH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Interrupt Level 7 (IRQ7) Enab le Bit 0 Disable (mask) 1 Enable (un - mask) .
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 10 IPH — Instr uction Pointer (High Byte) DAH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 11 IPR — Interrupt Priority Register FFH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 12 IRQ — Interrupt Request Register DCH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Addressing Mode Register addressing mode only .7 Interrupt L evel 7 (IRQ7) Request Pending Bit 0 Not pending 1 Pending .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 13 OSCCON — Oscillator Control Register FBH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write – – – R/W R/W R/W – R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 14 P0CONH — Port 0 Control Register (High Byte) E6H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 15 P0CONL — Port 0 Control Register (Low Byte) E7H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 1 .0 Reset Value 0 0 0 0 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 16 P1CONH — Port 1 Control Re gister (High Byte) E8H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 17 P1CONL — Port 1 Control Register (Low Byte) E9H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 18 P2CONH — Port 2 Control Register (High Byte) EAH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 . 3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 19 P2CONL — Port 2 Control Register (Low Byte) EBH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 20 P2INT — Port 2 Interrupt Control Register ECH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 21 P2INTPND — Port 2 Interrupt Pending Register EDH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Wr ite R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 22 P3CONH — Port 3 Control Register (High Byte) EEH Set 1, Bank 0 Bit Identifi er .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 23 P3CONL — Port 3 Control Register (Low Byte) EFH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 24 P4CONH — Port 4 Control Register (High Byte) F0H Set 1, Ba nk 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 25 P4CONL — Port 4 Control Register (Low Byte) F1H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 26 P4INT — Port 4 Interrupt Control Register F2H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write – – – – – R/W R/W R/W Addressing Mode Register addressing mode only .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 27 P4INTPND — Port 4 Interrupt Pending Register F3H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e 0 0 0 0 0 0 0 0 Read/Write – – – – – R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 28 PP — Register Page Pointer DFH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register add ressing mode only .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 29 RP0 — Register Pointer 0 D6H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 1 1 0 0 0 – – – Read/Write R/W R/W R/W R/W R/W – – – Addressing Mode Register addressing only .
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 30 SPH — Stack Pointer (High Byte) D8H Se t 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 31 STPCON — Stop Control Register E5H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 32 SYM — System Mode Register DEH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 x x x 0 0 Read/Write – – – R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .5 Not used, But you must keep always 0 .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 33 T1CON0 — Timer 1(0) Control Register E8H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 34 T1CON1 — Timer 1(1) Control Register E9H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressin g Mode Register addressing mode only .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 35 TACON — Timer A Control Register E1H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 36 TBCON — Timer B Control Register D0H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 . 0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 37 TINTPND — Timer A, Timer 1 Inte rrupt Pending Register E0H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write – – R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 38 UARTCON — UART Control Register F6H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 39 NOTES: 1. In mode 2, if the MCE (UARTCON.5) bit is set to "1", then the receive interrupt will not be activated if the received 9th data bit is "0". In mode 1, if MCE = "1”, then the receive interrupt will not be activated if a valid stop bit was not received.
CONTROL REGISTERS S 3C84E5/C84E9/P84E9 4 - 40 UARTPND — UART Pending and parity contr ol F4H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write – – R/W R/W – – R/W R/W .7 – .6 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0) .
S3C84E5/C84E9/P84E9 CONTROL REGISTER 4 - 41 WTCON — Watch Timer Control Register FAH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R /W R/W Addressing Mode Register addressing mode only .
S3C84E5/C84E9/P84E9 INTERRUPT STRUCTUR E 5 - 1 5 INTERRUPT STRUCTURE OVERVIEW The S3C8 - series interrupt structure has three basic components: levels, vectors, and sources. The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors.
INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9 5 - 2 INTERRUPT TYPES The three components of the S3C8 interrupt structure described before — levels, vectors, and sources — are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic.
S3C84E5/C84E9/P84E9 INTERRUPT STRUCTUR E 5 - 3 S3C84E5/C84E9/P84E9 INTERRUPT STRUCTURE The S3C84E5/C84E9/P84E9 microcontroller supports twenty - one interrupt s ources.
INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9 5 - 4 Vectors Sources Levels Reset(Clear) Timer A match/capture IRQ1 Timer A overflow H/W, S/W H/W, S/W C0H C2H C4H C6H C8H CAH IRQ2 Timer 1(0) match/capture Ti.
S3C84E5/C84E9/P84E9 INTERRUPT STRUCTUR E 5 - 5 INTERRUPT VECTOR ADD RESSES All interrupt vector addresses for the S3C84E5/C84E9/P84E9 interrupt structure are stored in the vector address area of the internal 16/32 - Kbyte ROM, 0H – 3FFFH/0H – 7FFFH (see Figure 5 - 3).
INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9 5 - 6 Table 5 - 1. Interrupt Vectors Vector Address Interrupt Source Request Reset/Clear Decimal Value Hex Value Interrupt Level Priority in Level H/W S/W 256 100H Basic timer (WDT) overflow nRESET – √ 230 E6H UART transmit IRQ7 1 √ 228 E4H UART receive 0 √ 226 E2H P4.
S3C84E5/C84E9/P84E9 INTERRUPT STRUCTUR E 5 - 7 ENABLE/DISABLE INTER RUPT INSTRUCTIONS (E I, DI) Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then serviced as they occur according to the established priorities.
INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9 5 - 8 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source.
S3C84E5/C84E9/P84E9 INTERRUPT STRUCTUR E 5 - 9 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see Table 5 - 3).
INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9 5 - 10 SYSTEM MODE REGISTER (SYM) The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing (see Figure 5 - 5).
S3C84E5/C84E9/P84E9 INTERRUPT STRUCTUR E 5 - 11 INTERRUPT MASK REGIS TER (IMR) The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine.
INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9 5 - 12 INTERRUPT PRIORITY R EGISTER (IPR) The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in the microcontroller’s interrupt structure.
S3C84E5/C84E9/P84E9 INTERRUPT STRUCTUR E 5 - 13 Group A 0 = IRQ0 > IRQ1 1 = IRQ1 > IRQ0 Subgroup B 0 = IRQ3 > IRQ4 1 = IRQ4 > IRQ3 Group C 0 = IRQ5 > (IRQ6, IRQ7) 1 = (IRQ6, IRQ7) > .
INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9 5 - 14 INTERRUPT REQUEST RE GISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure.
S3C84E5/C84E9/P84E9 INTERRUPT STRUCTUR E 5 - 15 INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine.
INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9 5 - 16 INTERRUPT SOURCE POL LING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that source.
S3C84E5/C84E9/P84E9 INTERRUPT STRUCTUR E 5 - 17 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H – FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 1 6 INSTRUCTION SET OVERVIEW The instruction set is specifically designed to support large register files that are typical of most S3C8 - series microcontrollers.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 2 Table 6 - 1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst,src Load LDB dst,src Load bit LDE dst,src Load ex.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 3 Table 6 - 1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Instructions ADC dst,src Add with carry ADD dst,src Add CP dst,src.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 4 Table 6 - 1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions BTJRF dst,src Bit test and jump relative on fal.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 5 Table 6 - 1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instructions RL dst Rotate left RLC dst Rotate left through .
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 6 FLAGS REGISTER (FLAG S) The flags register FLAGS contains eight bits which describe the current status of CPU operations. Four of these bits, FLAGS.7 – FLAGS.4, can be tested and used with conditional jump instructions.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 7 FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry - out from or a borrow to the bit 7 position (MSB).
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 8 INSTRUCTION SET NOTA TION Table 6 - 2. Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign flag V Overflow flag D Decimal - adjust fla.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 9 Table 6 - 4. Instruction Notation Conventions Notation Description Actual Operand Range cc Condition code See list of condition codes in Table 6 - 6. r Working register only Rn (n = 0 – 15) rb Bit (b) of working register Rn.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 10 Table 6 - 5. OPCODE Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – 0 1 2 3 4 5 6 7 U 0 DEC R1 DEC IR1 ADD r1,r2 ADD r1,Ir2 ADD R2,R1 ADD IR2,R1 ADD R1,IM BOR r0 – Rb P 1 RLC R1 RLC IR1 ADC r1,r2 ADC r1,Ir2 ADC R2,R1 ADC IR2,R1 ADC R1,IM BCP r1.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 11 Table 6 - 5. OPCODE Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – 8 9 A B C D E F U 0 LD r1,R2 LD r2,R1 DJNZ r1,RA JR cc,RA LD r1,IM JP cc,DA.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 12 CONDITION CODES The opcode of a conditional jump always contains a 4 - bit field called the condition code (cc).
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 13 INSTRUCTION DESCRIPT IONS This Chapter contains detailed information and programming examples for each instruction in the S3C8 - series instruction set. Information is arranged in a consistent format for improved readability and for quick reference.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 14 ADC — Add with Carry ADC dst,src Operation: dst ← dst + src + c The source operand, along with the carry flag setting, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 15 ADD — Add ADD dst,src Operation: dst ← dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaf fected. Two's - complement addition is performed.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 16 AND — Logical AND AND dst,src Operation: dst ← dst AND src The source operand is logically ANDed with the destination operand.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 17 BAND — Bit AND BAND dst,src.b BAND dst.b,src Operation: dst(0) ← dst(0) AND src(b) or dst(b) ← dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or the source).
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 18 BCP — Bit Compare BCP dst,src.b Operation: dst(0) – src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 19 BITC — Bit Complement BITC dst.b Operation: dst(b) ← NOT dst(b) This instruction complements the specified bit within the destination without affecting any other bit in the destination. Flags: C: Unaffected.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 20 BITR — Bit Reset BITR dst.b Operation: dst(b) ← 0 The BITR instruction clears the specified bit within the destination without affecting any other bit in the destination.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 21 BITS — Bit Set BITS dst.b Operation: dst(b) ← 1 The BITS instruction sets the specified bit within the destination without affecting any other bit in the destination.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 22 BOR — Bit OR BOR dst,src.b BOR dst.b,src Operation: dst(0) ← dst(0) OR src(b) or dst(b) ← dst(b) OR src(0) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source).
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 23 BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b Operation: If src(b) is a "0", then PC ← PC + dst The specified bit within the source operand is tested.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 24 BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b Operation: If src(b) is a "1", then PC ← PC + dst The specified bit within the source operand is tested.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 25 BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src Operation: dst(0) ← dst(0) XOR src(b) or dst(b) ← dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive - ORed with bit zero (LSB) of the destination (or the source).
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 26 CALL — Call Procedure CALL dst Operation: SP ← SP –1 @SP ← PCL SP ← SP –1 @SP ← PCH PC ← dst The contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 27 CCF — Complement Carry Flag CCF Operation: C ← NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero. If C = "0", the value of the carry flag is changed to logic one.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 28 CLR — Clear CLR dst Operation : dst ← "0" The destination location is cleared to "0".
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 29 COM — Complement COM dst Operation: dst ← NOT dst The contents of the destination location are complemented (one's complement). All "1s" are changed to "0s", and vice - versa. Flags: C: Unaffected.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 30 CP — Compare CP dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 31 CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA Operation: If dst – src = "0", PC ← PC + RA Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 32 CPIJNE — Compare, Increment, and Jump on Non - Equal CPIJNE dst,src,RA Operation: If dst – src ¡ "0", PC ← PC + RA Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 33 DA — Decimal Adjust DA dst Operation: dst ← DA dst The destination operand is adjusted to form two 4 - bit BCD digits following an addition or subtraction operation.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 34 DA — Decimal Adjust DA (Continued) Example: Given: The working register R0 contains the value 15 (BCD), the working register R1 contains 27 (BCD), and the.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 35 DEC — Decrement DEC dst Operation: dst ← dst –1 The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 36 DECW — Decrement Word DECW dst Operation: dst ← dst – 1 The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16 - bit value that is decremented b y one.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 37 DI — Disable Interrupts DI Operation: SYM (0) ← 0 Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 38 DIV — Divide (Unsigned) DIV dst,src Operation: dst ÷ src dst (UPPER) ← REMAINDER dst (LOWER) ← QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 39 DJNZ — Decrement and Jump if Non - Zero DJNZ r,dst Operation: r ← r – 1 If r ≠ 0, PC ← PC + dst The working register being used as a counter is decremented.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 40 EI — Enable Interrupts EI Operation: SYM (0) ← 1 The EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have the highest priority).
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 41 ENTER — Enter ENTER Operation: SP ← SP – 2 @SP ← IP IP ← PC PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded - code languages. The contents of the instruction pointer are pushed to the stack.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 42 EXIT — Exit EXIT Operation: IP ← @SP SP ← SP + 2 PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded - code languages. The stack value is popped and loaded into the instruction pointer.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 43 IDLE — Idle Operation IDLE Operation: (See description) The IDLE instruction stops the CPU clock while allowing the system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 44 INC — Increment INC dst Operation: dst ← dst + 1 The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 45 INCW — Increment Word INCW dst Operation: dst ← dst + 1 The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16 - bit value that is incremented by one.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 46 IRET — Interrupt Return IRET IRET (Normal) RET (Fast) Operation: FLAGS ← @SP PC ↔ IP SP ← SP + 1 FLAGS ← FLAGS' PC ← @SP FIS ← 0 SP ← SP + 2 SYM(0) ← 1 This instruction is used at the end of an interrupt service routine.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 47 JP — Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC ← dst The conditional JUMP instruction transfers program control to.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 48 JR — Jump Relative JR cc,dst Operat ion: If cc is true, PC ← PC + dst If the condition specified by the condition code (cc) is true, the relative addres.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 49 LD — Load LD dst,src Operation: dst ← src The contents of the source are loaded into the destination. The source's contents are unaffected.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 50 LD — Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 51 LDB — Load Bit LDB dst,src.b LDB dst.b,src Operation: dst(0) ← src(b) or dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 52 LDC/LDE — Load Memory LDC dst,src LDE dst,src Operation: dst ← src This instruction l oads a byte from program or data memory into a working register or vice - versa. The source values are unaffected. LDC refers to program memory and LDE to data memory.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 53 LDC/LDE — Load Memory LDC/LDE (Continued) E xamples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 54 LDCD/LDED — Load Memory and Decrement LDCD dst,src LDED dst,src Operation: dst ← src rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 55 LDCI/LDEI — Load Memory and Increment LDCI dst,src LDEI dst,src Operation: dst ← src rr ← rr + 1 These instructions are used f or user stacks or block transfers of data from program or data memory to the register file.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 56 LDCPD/LDEPD — Load Memory with Pre - Decrement LDCPD dst,src LDEPD dst,src Operation: rr ← rr – 1 dst ← src These instructions are used for block transfers of data from program or data memory to the register file.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 57 LDCPI/LDEPI — Load Memo ry with Pre - Increment LDCPI dst,src LDEPI dst,src Operation: rr ← rr + 1 dst ← src These instructions are used for block transfers of data from program or data memory to the register file.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 58 LDW — Load Word LDW dst,src Operation: dst ← src The contents of the source (a word) are loaded into the destination.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 59 MULT — Multiply (Unsigned) MULT dst,src Operation: dst ← dst × src The 8 - bit d estination operand (the even numbered register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 60 NEXT — Next NEXT Operation: PC ← @IP IP ← IP + 2 The NEXT instruction is useful when implementing threaded - code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 61 NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to affect a timing delay of variable duration. Flags: No flags are affected.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 62 OR — Logical OR OR dst,src Operation: dst ← dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 63 POP — Pop from Stack POP dst Operation: dst ← @SP SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags are affected.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 64 POPUD — Pop User Stack (Decrementing) POPUD dst,src Operation: dst ← src IR ← IR – 1 This instruction is used for user - defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 65 POPUI — Pop User Stack (Incrementing) POPUI dst,src Operation: dst ← src IR ← IR + 1 The POPUI instruction is used for user - defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 66 PUSH — Push to Stack PUSH src Operation: SP ← SP – 1 @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 67 PU SHUD — Push User Stack (Decrementing) PUSHUD dst,src Operation: IR ← IR – 1 dst ← src This instruction is used to address user - defined stacks in the register file.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 68 PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src Operation: IR ← IR + 1 dst ← src This instruction is used fo r user - defined stacks in the register file.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 69 RCF — Reset Carry Flag RCF RCF Operation: C ← 0 The carry flag is cleared to logic zero, regardless of its previous value.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 70 RET — Return RET Operation: PC ← @SP SP ← SP + 2 The RET instruction is normally used to return to the previously executed procedure at the end of the procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 71 RL — Rotate Left RL dst Operation: C ← dst (7) dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0 –6 The contents of the destination operand are rotated left one bit position.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 72 RLC — Rotate Left through Carry RLC dst Operation: dst (0) ← C C ← dst (7) dst (n + 1) ← dst (n), n = 0 –6 The contents of the destination operand with the carry flag are rotated left one bit position.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 73 RR — Rotate Right RR dst Operation: C ← dst (0) dst (7) ← dst (0) dst (n) ← dst (n + 1), n = 0 –6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 74 RRC — Rotate Right through Carry RRC dst Operation: dst (7) ← C C ← dst (0) dst (n) ← dst (n + 1), n = 0 –6 The contents of the destination operand and the carry flag are rotated right one bit position.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 75 SB0 — Select Bank 0 SB0 Operation: BANK ← 0 The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0 ) to logic zero, selecting the bank 0 register addressing in the set 1 area of the register file.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 76 SB1 — Select Bank 1 SB1 Operation: BANK ← 1 The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting the bank 1 register addressing in the set 1 area of the register file.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 77 SBC — Subtract with Carry SBC dst,src Operation: dst ← dst – src – c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 78 SCF — Set Carry Flag SCF Operation: C ← 1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags ar e affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 DF Example: The statement SCF sets the carry flag to “1”.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 79 SRA — Shift Right Arithmetic SRA dst Operation: dst (7) ← dst (7) C ← dst (0) dst (n) ← dst (n + 1), n = 0 –6 An arithmetic shift - right of one bit position is performed on the destination operand.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 80 SRP/SRP0/SRP1 — Set Register Pointer SRP src SRP0 src SRP1 src Operation: If src (1) = 1 and src (0) = 0 the n: RP0 (3 – 7) ← src (3 – 7) If src (1).
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 81 STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on - chip CPU registers, peripheral registers, and I/O port control and data registers are retained.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 82 SUB — Subtract SUB dst,src Operation: dst ← dst – src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 83 SWAP — Swap Nibbles SWAP dst Operation: dst (0 – 3) ↔ dst (4 – 7) The contents of the lower four bits and the upper four bits of the destination operand are swapped. 7 0 4 3 Flags: C: Undefined. Z: Set if the result is "0"; cleared otherwise.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 84 TCM — Test Complement under Mask TCM dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested a re specified by setting a "1" bit in the corresponding position of the source operand (mask).
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 85 TM — Test under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value.
INSTRUCTION SET S3C 84E5/C84E9/P84E9 6 - 86 WFI — Wate for Interrupt WFI Operation: The CPU is effectively halted before an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrup t.
S3C84E5/C84E9/P84E9 INSTRUCTION SET 6 - 87 XOR — Logical Exclusive OR XOR dst,src Operation: dst ← dst XOR src The source operand is logically exclusive - ORed with the destination operand and the result is stored in the destination.
S3C84E5/C84E9/P84E9 CLOCK CIRCUIT 7 - 1 7 CLOCK CI RCUIT OVERVIEW The clock frequency generated for the Main clock of S3C84E5/C84E9/P84E9 by an external crystal can range from 1 MHz to 12 MHz. The maximum CPU clock frequency is 12 MHz. The X IN and X OUT pins connect the external oscillator or clo ck source to the on - chip clock circuit.
CLOCK CIRCUIT S3C84 E5/C84E9/P84E9 7 - 2 CLOCK STATUS DURING POWER - DOWN MODES The t wo power - down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted.
S3C84E5/C84E9/P84E9 (REV.0) CLOCK CIRCU IT 7 - 3 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in set 1, address D4H.
CLOCK CIRCUIT S3C84 E5/C84E9/P84E9 7 - 4 Oscillator Control Register (OSCCON) FBH, Set 1, Bank 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Not used (must keep always 0) System clock selection bit: 0 = Main.
S3C84E5/C84E9/P84E9 RESET and POWER - DOWN 8 - 1 8 RESET and POWER - DOWN SYSTEM RESET OVERVIEW During a power - on Reset, the voltage at VDD goes to High level and the nRESET pin is forced to Low level. The nRESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock.
RESET and POWER - DOWN S3C84E5 /C84E9/P84E9 8 - 2 HARDWARE RESET VALUE S Table 8 - 1, 8 - 2, and 8 - 3 list the re set values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation.
S3C84E5/C84E9/P84E9 RESET and POWER - DOWN 8 - 3 Table 8 - 2. S3C84E5/C84E9/P84E9 Set 1, Bank 0 Register Values After RESET Register Name Mnemonic Address Bit Values After RESET Dec Hex 7 6 5 4 3 2 1 .
RESET and POWER - DOWN S3C84E5 /C84E9/P84E9 8 - 4 Table 8 - 3. S3C84E5/C84E9/P84E9 Set 1, Bank 1 Register Values After RESET Register Name Mnemonic Address Bit Values After RESET Dec Hex 7 6 5 4 3 2 1.
S3C84E5/C84E9/P84E9 RESET and POWER - DOWN 8 - 5 POWER - DOWN MODES STOP MODE Stop mode is invok ed by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all peripherals is halted.
RESET and POWER - DOWN S3C84E5 /C84E9/P84E9 8 - 6 How to Enter into Stop Mode There are two steps to enter into Stop mode: 1. Handling OSCCON register. 2. Handling STPCON register then writing Stop instruction (keep the order). IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH).
S3C84E5/C84E9/P84E9 I/O PORTS 9 - 1 9 I/O PORTS OVERVIEW The S3C84E5/C84E9/P84E9 microcontroller has seven bit - programmable I/O ports, P0 – P4. This gives a total of 36 I/O pins. Each port can be flexibly configured to meet application design requirements.
I/O PORTS S3C84E5/C 84E9/P84E9 9 - 2 PORT DATA REGISTERS Table 9 - 2 gives yo u an overview of the register locations of all seven S3C84E5/C84E9/P84E9 I/O port data registers. Data registers for ports 0, 1, 2, 3 and 4 have the general format shown in Table 9 - 2.
S3C84E5/C84E9/P84E9 I/O PORTS 9 - 3 PORT 0 Port 0 is an 8 - bit I/O port that you can use two ways: — General - purpose digital I/O — Alternative function: TACAP, TACK, T1CAP0, T1OUT1, T1CK1, T1CAP1, XT IN , XT OUT Port 0 is accessed directly by writing or reading the port 0 data register, P0 at location E0H in set 1, bank 0.
I/O PORTS S3C84E5/C 84E9/P84E9 9 - 4 Port 0 Control Register, Low Byte (P0CONL) E7H, Set1, Bank0, R/W, Reset value="0FH" .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB [.7-.6] P0.3/T1CK1 Configuration Bits 0 0 = Input mode with pull-up; T1CK1 input 0 1 = Input mode; T1CK1 input 1 X = Push-pull output mode [.
S3C84E5/C84E9/P84E9 I/O PORTS 9 - 5 PORT 1 Port 1 is a 6 - bit I/O port with individually configurable pins that you can use two ways: — General - purpose digital I/O — Alternative function: TAOUT, T1OUT0, T1CK0, BZOUT, TXD, RXD Port 1 is accessed directly by writing or reading the port 1 data register, P1 at location E1H in set 1, bank 0.
I/O PORTS S3C84E5/C 84E9/P84E9 9 - 6 Port 1 Control Register, Low Byte (P1CONL) E9H, Set1, Bank0, R/W, Reset value="00H" .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB [.7-.6] P1.3/BZOUT Configuration Bits 0 0 = Input mode with pull-up 0 1 = Input mode 1 0 = Push-pull output mode 1 1 = Alternative function mode: BZOUT output [.
S3C84E5/C84E9/P84E9 I/O PORTS 9 - 7 PORT 2 Port 2 is an 8 - bit I/O port with in dividually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location E2H in set 1, bank 0.
I/O PORTS S3C84E5/C 84E9/P84E9 9 - 8 Port 2 Control Register, High Byte (P2CONH) EAH, Set1, Bank0, R/W, Reset value="00" .7 .6 .5 .4 .3 .2 .1 .
S3C84E5/C84E9/P84E9 I/O PORTS 9 - 9 Port 2 Control Register, Low Byte (P2CONL) EBH, Set1, Bank0, R/W, Reset value="00" .7 .6 .5 .4 .3 .2 .1 .
I/O PORTS S3C84E5/C 84E9/P84E9 9 - 10 Port 2 Interrupt Pending Register (P2INTPND) EDH, Set1, Bank0, R/W, Reset value="00" .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB [.7] P2.7/PND7, Interrupt Pending Bit 0 = No interrupt pending (when read) / Pending bit clear (when write) 1 = Interrupt is pending (when read) / No effect (when write) [.
S3C84E5/C84E9/P84E9 I/O PORTS 9 - 11 Port 2 Interrupt Control Register (P2INT) ECH, Set1, Bank0, R/W, Reset value="00" .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB [.7] P2.7 External Interrupt (INT7) Enable Bit 0 = Disable interrupt 1 = Enable interrupt [.
I/O PORTS S3C84E5/C 84E9/P84E9 9 - 12 PORT 3 Port 3 is an 8 - bit I/O port that can be used for general - purpose digital I/O. The pins are accessed directly by writing or reading the port 3 data register, P3 at location E3H in set 1, bank 0. P3.0 – P3.
S3C84E5/C84E9/P84E9 I/O PORTS 9 - 13 Port 3 Control Register, Low Byte (P3CONL) EFH, Set1, Bank0, R/W, Reset value="00" .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB [.7-.6] P3.3/ADC3 Configuration Bits 0 0 = Input mode with pull-up 0 1 = Input mode 1 0 = Push-pull output mode 1 1 = Alternative function mode: ADC3 input [.
I/O PORTS S3C84E5/C 84E9/P84E9 9 - 14 PORT 4 Port 4 is a 6 - bit I/O port that you can use two ways: — General - purpose digital I/O — Alternative function: INT8 – INT10, TBPWM Port 4 is accessed directly by writing or reading the port 4 data register, P4 at location E4H in set 1, bank 0.
S3C84E5/C84E9/P84E9 I/O PORTS 9 - 15 Port 4 Control Register, High Byte (P4CONH) F0H, Set1, Bank0, R/W, Reset value="00" .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB [.7-.4] Not used (must keep always 0) [.3-.2] P4.5 Configuration Bits 0 0 = Input mode with pull-up 0 1 = Input mode 1 X = Push-pull output mode [.
I/O PORTS S3C84E5/C 84E9/P84E9 9 - 16 Port 4 Interrupt Pending Register (P4INTPND) F3H, Set1, Bank0, R/W, Reset value="00" .7 .6 .5 .4 .3 .2 .
S3C84E5/C84E9/P84E9 BASIC TIMER 10 - 1 10 BASIC TIMER OVERVIEW BASIC TIMER (BT) You can use the basic timer (BT) in two different ways: — As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. — To signal the end of the required oscillation stabiliza tion interval after a reset or a Stop mode release.
BASIC TIMER S3C84E5 /C84E9/P84E9 10 - 2 Basic Timer Control Register (BTCON) D3H, Set 1, R/W LSB MSB .7 .6 .5 .4 .3 .2 .1 .0 Divider clear bit: 0 = No effect 1 = Clear divider Basic timer counter clea.
S3C84E5/C84E9/P84E9 BASIC TIMER 10 - 3 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7 – BTCON.4 to any value other than "1010B". (The "1010B" value disables the watchdog function.
BASIC TIMER S3C84E5 /C84E9/P84E9 10 - 4 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows).
S3C84E5/C84E9/P84E9 8 - BIT TIMER A/B 11 - 1 11 8 - BIT TIMER A/B 8 - BIT TIMER A OVERVIEW The 8 - bit timer A is an 8 - bit general - purpose timer/counter.
8 - BIT TIMER A/B S3C 84E5/C84E9/P84E9 11 - 2 FUNCTION DESCRIPTION Timer A Interrupts (IRQ1, Vectors C0H and C2H) The timer A module can generate two interrupts: the timer A overflow interrupt (TAOVF), and the timer A match/ capture interrupt (TAINT).
S3C84E5/C84E9/P84E9 8 - BIT TIMER A/B 11 - 3 TIMER A CONTROL REGI STER (TACON) You use the timer A control register, TACON, to: — Select the timer A operating mode (interval timer, capture mode and .
8 - BIT TIMER A/B S3C 84E5/C84E9/P84E9 11 - 4 BLOCK DIAGRAM NOTES: 1. When PWM mode, match signal cannot clear counter. 2. Pending bit is located at TINTPND register. Clear Match TACON.7-.6 f xx/1024 f xx/256 f xx/64 TACK TACON.2 Pending TACON.3 Overflow TAOVF TACAP TAOUT(TAPWM) TINTPND.
S3C84E5/C84E9/P84E9 8 - BIT TIMER A/B 11 - 5 8 - BIT TIMER B OVERVIEW The S3C84E5/C84E9/P84E9 micro - controller has an 8 - bit timer called timer B. Timer B, which can be used to generate the carrier frequency of a remote controller signal.
8 - BIT TIMER A/B S3C 84E5/C84E9/P84E9 11 - 6 TIMER B CONTROL REGI STER (TBCON) Timer B Control Register (TBCON) D0H, Set 1, Bank 0, R/W LSB MSB .7 .6 .
S3C84E5/C84E9/P84E9 8 - BIT TIMER A/B 11 - 7 TIMER B PULSE WIDTH CALCULATIONS t LOW t LOW t HIGH To generate the above repeated waveform consisted of low period time, t LOW , and high period time, t HIGH . When T - FF = 0, t LOW = (TBDATAL + 1) x 1/fx, 0H < TBDATAL < 100H, where fx = The selected clock.
8 - BIT TIMER A/B S3C 84E5/C84E9/P84E9 11 - 8 Timer B Clock 0H T-FF = '0' TBDATAL = 01-FFH TBDATAH = 00H T-FF = '0' TBDATAL = 00H TBDATAH = 01-FFH T-FF = '0' TBDATAL = 00.
S3C84E5/C84E9/P84E9 8 - BIT TIMER A/B 11 - 9 F PROGRAMMING TIP — To Gen erate 38 kHz, 1/3duty signal through P4.3 This example sets Timer B to the repeat mode, sets the oscillation frequency as the Timer B clock source, and TBDATAH and TBDATAL to make a 38 kHz, 1/3 Duty carrier frequency.
8 - BIT TIMER A/B S3C 84E5/C84E9/P84E9 11 - 10 F PROGRAMMING TIP — To generate a one pulse signal through P4.3 This example sets Timer B to the one shot mode, sets the oscillation frequency as the Timer B clock source, and TBDATAH and TBDATAL to make a 40 µ s width pulse.
S3C84E5/C84E9/P84E9 8 - BIT TIMER A/B 11 - 11 F PROGRAMMING TIP — Using the Timer A ORG 0000h VECTOR 0C0h,TAMC_INT VECTOR 0C2h,TAOV_INT ORG 0100h INITIAL: LD SYM,#00h ; Disable Global/Fast interrupt.
8 - BIT TIMER A/B S3C 84E5/C84E9/P84E9 11 - 12 F PROGRAMMING TIP — Using the Timer B ORG 0000h VECTOR 0BEh,TBUN_INT ORG 0100h INITIAL: LD SYM,#00h ; Disable Global/Fast interrupt LD IMR,#00000001b ;.
S3C84E5/C84E9/P84E9 16 - BIT TIMER 1(0,1 ) 12 - 1 12 16 - BIT TIMER 1(0,1) OVERVIEW The S3C84E5/C84E9/P84E9 has two 16 - bit timer/counters. The 16 - bit timer 1(0,1) is an 16 - bit general - purpose timer/counter.
16 - BIT TIMER 1(0,1) S3C84E5/C84E9/P84E9 12 - 2 FUNCTION DESCRIPTION Timer 1 (0,1) Interrupts (IRQ2, Vectors C4H, C6H, C8H and CAH) The timer 1(0) module can generate two interrupts, the timer 1(0) overflow interrupt (T1OVF0), and the timer 1(0) match/capture interrupt (T1INT0).
S3C84E5/C84E9/P84E9 16 - BIT TIMER 1(0,1 ) 12 - 3 PWM Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T1OUT0, T1OUT1 pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 1(0,1) data registers.
16 - BIT TIMER 1(0,1) S3C84E5/C84E9/P84E9 12 - 4 NOTE: Interrupt pending bits are located in TINTPND register. Timer 1 Control Register (T1CON0) E8H, Set 1, Bank 1, R/W (T1CON1) E9H, Set 1, Bank 1, R/W LSB MSB .
S3C84E5/C84E9/P84E9 16 - BIT TIMER 1(0,1 ) 12 - 5 Timer A, Timer 1 Pending Register (TINTPND) E0H, Set 1, Bank 1, R/W LSB MSB .7 .6 .5 .4 .3 .2 .1 .0 Timer A overflow interrupt pending bit 0 = No inte.
16 - BIT TIMER 1(0,1) S3C84E5/C84E9/P84E9 12 - 6 BLOCK DIAGRAM f xx/1 f xx/64 f xx/8 V S S T1CK f xx/256 f xx/1024 NOTES: 1. When PWM mode, match signal cannot clear counter. 2. Pending bit is located at TINTPND register. Clear Match T1CON.7-.5 T1CON.
S3C84E5/C84E9/P84E9 16 - BIT TIMER 1(0,1 ) 12 - 7 F PROGRAMMING TIP — Using the Timer 1(0) ORG 0000h VECTOR 0C4h,TIM1_INT ORG 0100h INITIAL: LD SYM,#00h ; Disable Global/Fast interrupt LD IMR,#00001.
S3C84E5/C84E9/P84E9 UART 13 - 1 13 UART OVERVIEW The UART block has a full - duplex serial port with programmable operating modes: There is one synchronous mode and three UART (Universal Asynchronous .
UART S3C84E5/C84E9/ P84E9 13 - 2 UART CONTROL REGISTE R (UARTCON) The control register for the UART is called UARTCON at address F6H. It has the following control functions: — Operating mode and bau.
S3C84E5/C84E9/P84E9 UART 13 - 3 If parity disable mode (PEN = 0), location of the 9th data bit that was received in UART mode 2 ("0" or "1"). If parity enable mode (PEN = 1), Even/odd parity selection bit for receive data in UART mode 2.
UART S3C84E5/C84E9/ P84E9 13 - 4 UART INTERRUPT PENDI NG REGISTER (UARTPND ) The UART interrupt pending register, UARTPND is located at address F4H. It contains the UART data transmit interrupt pending bit (UARTPND.0) and the receive interrupt pending bit (UARTPND.
S3C84E5/C84E9/P84E9 UART 13 - 5 In mode 2 (9 - bit UART data), by setting the parity enable bit (PEN) of UARTPND register t o '1', the 9 th data bit of transmit data will be an automatically generated parity bit. Also, the 9 th data bit of the received data will be treated as a parity bit for checking the received data.
UART S3C84E5/C84E9/ P84E9 13 - 6 UART BAUD RATE DATA REGISTER (BRDATAH, B RDATAL) The value stored in the UART baud rate register, (BRDATAH, BRDATAL), lets you determine the UART clock rate (baud rate). UART Baud Rate Data Register (BRDATAH) EEH, Set1, Bank 0, R/W, Reset Value: FFH (BRDATAL) EFH, Set1, Bank 0, R/W, Reset Value: FFH .
S3C84E5/C84E9/P84E9 UART 13 - 7 Table 13 - 1. Commonly Used Baud Rates Generated by 16 - bit BRDATA Baud Rate Oscillation Clock BRDATAH BRDATAL Decimal Hex Decimal Hex 230,400 Hz 11.0592 MHz 0 0H 02 02H 115,200 Hz 11.0592 MHz 0 0H 05 05H 57,600 Hz 11.
UART S3C84E5/C84E9/ P84E9 13 - 8 BLOCK DIAGRAM Zero Detector UDATA RxD (P1.4) TIE RIE Interrupt 1-to-0 Transition Detector RE RIE Bit Detector Shift Value MS0 MS1 MS0 MS1 RxD (P1.
S3C84E5/C84E9/P84E9 UART 13 - 9 UART MODE 0 FUNCTION DESCRIPTION In mode 0, UART is input and output through the RxD (P1.4) pin and TxD (P1.5) pin outputs the shift clock. Data is transmitted or received in 8 - bit units only. The LSB of the 8 - bit value is transmitted (or received) first.
UART S3C84E5/C84E9/ P84E9 13 - 10 UART MODE 1 FUNCTION DESCRIPTION In mode 1, 10 - bits are transmitted (through the TxD (P1.5) pin) or received (through the RxD (P1.
S3C84E5/C84E9/P84E9 UART 13 - 11 UART MODE 2 FUNCTION DESCRIPTION In mode 2, 11 - bits are transmitted (through the TxD pin) or received (through the RxD pin).
UART S3C84E5/C84E9/ P84E9 13 - 12 Transmit TIP Write to Shift Register (UARTDATA) Start Bit TxD Stop Bit D0 D1 D2 D3 D4 D5 D6 D7 Shift Tx Clock Receive RIP Start Bit Rx Clock Stop Bit RxD D0 D1 D2 D3 D4 D5 D6 D7 Bit Detect Sample Time Shift TB8 or Parity bit RB8 or Parity bit Figure 13 - 8.
S3C84E5/C84E9/P84E9 UART 13 - 13 SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS The S3C9 - series multiprocessor communication features let a "master" S3C84E5/C84E9/P84E9 send a multiple - frame serial message to a "slave" device in a multi - S3C84E5/C84E9/P84E9 configuration.
UART S3C84E5/C84E9/ P84E9 13 - 14 Setup Procedure for Multiprocessor Com munications Follow these steps to configure multiprocessor communications: 1. Set all S3C84E5/C84E9/P84E9 devices (masters and slaves) to UART mode 2 with parity disable. 2. Write the MCE bit of all the slave devices to "1".
S3C84E5/C84E9/P84E9 WATCH TIMER 14 - 1 14 WATCH TIMER OVERVIEW Watch timer functions include real - time and watch - time measurement and interval timing for the system clock. To start watch timer operation, set bit1 and bit 6 of the watch timer mode register, WTCON.
WATCH TIMER S3C84E5 /C84E9/P84E9 14 - 2 WATCH TIMER CONTROL REGISTER (WTCON: R/W ) FAH WTCON.7 WTCON.6 WTCON.5 WTCON.4 WTCON.3 WTCON.2 WTCON.1 WTCON.0 RESET "0" "0" "0" "0" "0" "0" "0" "0" Table 14 - 1.
S3C84E5/C84E9/P84E9 WATCH TIMER 14 - 3 WATCH TIMER CIRCUIT DIAGRAM WTCON.1 WTCON.2 WTCON.3 WTCON.4 WTCON.5 Enable/Disable Selector Circuit MUX WTCON.0 WTINT WTCON.6 BUZZER Output (BZOUT) f W2 6 1 Hz f X = Main System Clock (9.8304MHz) f XT = Subsystem Clock (32768 Hz) f W = Watch timer Clock Selector WTCON.
WATCH TIMER S3C84E5 /C84E9/P84E9 14 - 4 F PROGRAMMING TIP — Using the Watch Timer ORG 0000h VECTOR 0CCh,WT_INT ORG 0100h INITIAL: LD SYM,#00h ; Disable Global/Fast interrupt LD IMR,#00010000b ; Enable IRQ3 interrupt LD SPH,#00000000b ; Set stack area LD SPL,#0FFh LD BTCON,#10100011b ; Disable Watch - dog LD WTCON,#11001110b ; 0.
S3C84E5/C84E9/P84E9 A/D CONVERTER 15 - 1 15 A/D CONVERTER OVERVIEW The 10 - bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10 - bit digital values. T he analog input level must lie between the AV REF and AV SS values.
A/D CONVERTER S3C84 E5/C84E9 /P84E9 15 - 2 A/D CONVERTER CONTRO L REGISTER (ADCON) The A/D converter control register, ADCON, is located in set1, bank 0 at address F7H. ADCON is read - write addressable using 8 - bit instructions only. But, the EOC bit, ADCON.
S3C84E5/C84E9/P84E9 A/D CONVERTER 15 - 3 Conversion Data Register High Byte (ADDATAH) F8H, Set 1, Bank 0, Read only LSB MSB .7 .6 .5 .4 .3 .2 .1 .0 Conversion Data Register Low Byte (ADDATAL) F9H, Set 1, Bank 0, Read only LSB MSB xxxxxx .1 .0 Figure 15 - 2.
A/D CONVERTER S3C84 E5/C84E9 /P84E9 15 - 4 INTERNAL REFERENCE V OLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range AV SS to AV REF (AV REF = V DD ).
S3C84E5/C84E9/P84E9 A/D CONVERTER 15 - 5 INTERNAL A/D CONVERS ION PROCEDURE 1. Analog input must remain between the voltage range of AV SS and AV REF . 2. Configure P3.0 – P3.7 for analog input before A/D convers ions. To do this, you load the appropriate value to the P3CONH and P3CONL (for ADC0 – ADC7) registers.
A/D CONVERTER S3C84 E5/C84E9 /P84E9 15 - 6 F PROGRAMMING TIP — Configuring A/D Converter • • LD P3CONH, #11111111B ; P3.7 – P3.4 A/D Input MODE LD P3CONL, #11111111B ; P3.
S3C84E5/C84E9/P 84E9 LOW VOLTAGE R ESET 16 - 1 16 LOW VOLTAGE RESET OVERVIEW The S3C84E5/C84E9/P84E9 can be reset in four ways: — by external power - on - Reset — by the external nReset input pin .
LOW VOLTAGE RESET S 3C84E5/C84E9/P84E9 16 - 2 + - V REF BGR V IN V DD Longger than 1us N.F Internal System RESET When the V DD level is lower than 2.9V Comparator NOTES: 1. The target of voltage detection level is 2.9 V at V DD = 5 V 2. BGR is Band Gap voltage Reference Longger than 1us N.
S3C84E5/C84E9/P84E9 ELECTRICAL DA TA 17-1 17 ELECTRICAL DATA OVERVIEW In this chapter, S3C84E5/C84E9/P 84E9 electrical characteristics ar e presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — Input/output capacitance — D.
ELECTRICAL DA TA S3C84E5/C84E9/P84E9 17-2 Table 17-1. Absolute Maximum Ratings (T A = 25 ° C) Parameter Symbol Conditions Rating Unit Supply voltage V DD – – 0.3 to + 6.5 V Input voltage V I All input ports – 0.3 to VDD + 0.3 Output voltage V O All output ports – 0.
S3C84E5/C84E9/P84E9 ELECTRICAL DA TA 17-3 Table 17-3. D.C. Electrical Characteristics (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.5 V) Parameter Symbol Conditions Min Ty p. Max Unit Input high voltage V IH1 V DD = V LVR to 5.5V All port and nRESET 0.
ELECTRICAL DA TA S3C84E5/C84E9/P84E9 17-4 Table 17-3. D.C. Electrical Characteristics (Continued) (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.5 V) Parameter Symbol Conditions Min Typ.
S3C84E5/C84E9/P84E9 ELECTRICAL DA TA 17-5 Table 17-4. A.C. Electrical Characteristics (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.5 V) Parameter Symbol Conditions Min Ty p. Max Unit Interrupt input high, low width (Ports 4) t INTH , t INTL V DD = 5 V 180 – – ns nRESET input low width t RSL Input 1.
ELECTRICAL DA TA S3C84E5/C84E9/P84E9 17-6 Table 17-5. Main Oscillator Frequency (f OSC1 ) (T A = – 25 ° C + 85 ° C, V DD = V LVR to 5.5 V) Oscillator Clock Circuit Test Condition Min Typ. Max Unit Main crystal or ceramic X IN C1 C2 X OUT V DD = V LVR to 5.
S3C84E5/C84E9/P84E9 ELECTRICAL DA TA 17-7 X IN t XH t XL 1/f OSC1 V DD - 0.5 V 0.4 V Figure 17-3. Clock Timing Measurement at X IN Table 17-7. Sub Oscillator Frequency (f OSC2 ) (T A = –25 ° C + 85 ° C, V DD = V LVR to 5.5 V) Oscillator Clock Circuit Test Condition Min Typ.
ELECTRICAL DA TA S3C84E5/C84E9/P84E9 17-8 Table 17-9. Data Retention Supply Voltage in Stop Mode (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage V DDDR Stop mode 2 – 5.
S3C84E5/C84E9/P84E9 ELECTRICAL DA TA 17-9 Execution of STOP Instruction ~ ~ V DDDR ~ ~ Stop Mode Idle Mode Data Retention Mode t WAIT V DD Interrupt Normal Operating Mode Oscillation Stabilization Time 0.2 V DD NOTE: When the case of select the fxx/128 for basic timer input clock before enter the stop mode.
ELECTRICAL DA TA S3C84E5/C84E9/P84E9 17-10 Table 17-10. UART Timing Characteristics in Mode 0 (10 MHz) (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.
S3C84E5/C84E9/P84E9 ELECTRICAL DA TA 17-11 Table 17-11. A/D Converter Electrical Characteristics (T A = – 25 ° C to + 85 ° C, V DD = V LVR to 5.5 V, V SS = 0 V) Parameter Symbol Test Conditions Min Ty p. Max Unit Resolution – 10 – bit Total accuracy V DD = 5.
ELECTRICAL DA TA S3C84E5/C84E9/P84E9 17-12 Table 17-12. LVR (Low Voltage Reset) Circuit Characteristics (T A = 25 ° C) Parameter Symbol Test Condition Min Typ Max Unit LVR voltage level V LVR T A = 25 ° C 2.6 2.9 3.2 V CPU Clock 1 MH z Main O scillator Frequency 1234567 Supply Voltage (V) 8 MH z 12 MH z V LVR 5.
S3C84E5/C84E9/P84E9 MECHANICAL DATA 18 - 1 18 MECHANICAL DATA OVERVIEW The S3C84E5/C84E9/P84E9 microcontrollers are available in a 42 - SDIP - 600, 44 - QFP - 1010 package. NOTE : Dimensions are in millimeters. 39.50 MAX 39.10 ?0 .20 0.50 ? 0.10 1.78 (1.
MECHANICAL DATA S3C 84E5/C84E9/P84E9 18 - 2 NOTE : Dimensions are in millimeters. 44-QFP-1010 13.20 ± 0.3 #44 (1.00) #1 13.20 ± 0.3 10.00 ± 0.2 0.35 +0.10 - 0.05 0.10 MAX 0.15 +0.10 - 0.05 0-8° 0.05 MIN 2.05 ± 0.10 2.30 MAX 0.80 ±0.20 0.80 10.00 ± 0.
S3C84E5/C84E9/P84E9 OTP VERSION 19-1 19 S3P84E9 OTP VERSION OVERVIEW The S3P84E9 single-chip CMOS microcontro ller is the OTP (One Time Programmable) version of the S3C84E5/C84E9 microcontroller. It has an on-chip EPROM instead of a masked ROM. The EPROM is accessed by serial data format.
OTP VERSION S3C84E5/C84E9/P84E9 19-2 SDAT /TBPW M /P4.3 SCLK /INT10/P4.2 VDD VSS Xout Xin VPP /TEST S3P84E9 Top View (44-Q FP) 1 2 3 4 5 6 7 8 9 10 11 P4.4 P0.2/T1CAP1 P0.3/T1CK1 P0.4/T1OUT1 P0.5/T1CAP0 P0.6/TACK P0.7/TACAP P1.0/TAOUT P1.1/T1CK0 44 43 42 41 40 39 38 37 36 35 34 P4.
S3C84E5/C84E9/P84E9 OTP VERSION 19-3 Table 19-1. Descriptions of Pins Used to Read/Write the OTP Main Chip Pin Name During Programming Pin Name Pin No. I/O Function P4.3 SDAT 9(3) I/O Serial data pin. Output port when reading and input port when writing.
OTP VERSION S3C84E5/C84E9/P84E9 19-4 NOTES.
S3C84E5/C84E9/P84E9 DEVELOPMENT TOOLS 20 - 1 20 DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy - to - use development support system on a turnkey basis. The development support system is composed of a host system, debugging tools, and supp orting software.
DEVELOPMENT TOOLS S 3C84E5/C84E9/P84E9 20 - 2 TARGET BOARDS Target boards are available for all the S3C8 - series microcontrollers. All the required target system cables and adapters are included on the device - specific target board . TB84E5/84E9 is a specific target board for the S3C84E5/C84E9 and S3P84E9 development.
S3C84E5/C84E9/P84E9 DEVELOPMENT TOOLS 20 - 3 TB84E5/84E9 TARGET B OARD The TB84E5/84E9 target board is used for the S3C84E5/C 84E9 and the S3P84E9 microcontroller. It is supported by the SMDS2+ or SK - 1000 development system (In - Circuit Emulator). Figure 20 - 2.
DEVELOPMENT TOOLS S 3C84E5/C84E9/P84E9 20 - 4 Table 20 - 1. Power Selection Settings for TB84E5/84E9 To User_Vcc' Settings Operating Mode Comments To User_V DD Off On Target System SMDS2+ or SK-1000 TB84E5/E9 V DD V SS V DD SMDS2+ or SK - 1000 supplies V DD to the target board (evaluation chip) and the target system.
S3C84E5/C84E9/P84E9 DEVELOPMENT TOOLS 20 - 5 Table 20 - 3. The Port 0.0 and Port 0.1 selection setting “Sub - OSC” Setting Description XTin P0.0 XTout P0.1 If you set the Sub - OSC to the XTin and XTout side, 32,768Hz - subsystem crystal will be connected to P0.
DEVELOPMENT TOOLS S 3C84E5/C84E9/P84E9 20 - 6 Target Board 44-Pin Connector Target System J101 1 2 43 44 Part Name: AS20D Order Cods: SM6304 1 2 43 44 44-Pin Connector Figure 20 - 4.
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.
デバイスSamsung S3C84E5の購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
Samsung S3C84E5をまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはSamsung S3C84E5の技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Samsung S3C84E5の取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Samsung S3C84E5で得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Samsung S3C84E5を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はSamsung S3C84E5の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Samsung S3C84E5に関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちSamsung S3C84E5デバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
