SamsungメーカーS3C9228/P9228の使用説明書/サービス説明書
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21 - S3 - C9228/P9228-112002 USER'S M ANUAL S3C9228/P9228 8 -Bit CMOS Microcontroller Revision 1.
S3C9228/P9228 8-BIT CMOS MICROCONTROLLER S USER'S MANUAL Revision 1.
Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.
S3C9228/P9228 MICROCONTROLLER S iii Preface The S3C9228/P9228 Microcontroller s User's Manual is designed for application designers and programmers who are using the S3C9228/P9228 microcontroller s for application development.
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S3C9228/P9228 MICROCONTROLLER S v Table of Contents Part I — Programming Model Chapter 1 Product Overview SAM88RCRI Product Family ................................................................................................................... 1-1 S3C9228/P9228 Microcontroller .
vi S3C9228/P9228 MICROCONTROLLER S Table of Contents (Cont inued ) Chapter 4 Control Registers Overview ................................................................................................................................................. 4-1 Chapter 5 Interrupt Structure Overview .
S3C9228/P9228 MICROCONTROLLER S vii Table of Contents (Cont inued ) Part II — Hardware Descriptions Chapter 7 Clock Circui t Overview ...................................................................................................................
viii S3C9228/P9228 MICROCONTROLLER S Table of Contents (Con tinued ) Chapter 11 Timer 1 One 16-Bit Timer Mode (Timer 1) ............................................................................................................ 11-1 Overview ........
S3C9228/P9228 MICROCONTROLLER S ix Table of Contents (Con cluded ) Chapter 1 6 Electrical Data Overview ................................................................................................................................................. 16-1 Chapter 1 7 Mechanical Data Overview .
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S3C9228/P9228 MICROCONTROLLER S xi List of Figures Figure Title Page Number Number 1-1 Block Diagram .................................................................................................................... 1-3 1-2 S3C9228 44-QFP Pin Assignments .
xii S3C9228/P9228 MICROCONTROLLER S List of Figures (Cont inued ) Figure Title Page Number Number 5-1 S3C9-Series Interrupt Type ................................................................................................ 5-1 5-2 Interrupt Function Diagram .
S3C9228/P9228 MICROCONTROLLER S xiii List of Figures (Con tinued ) Figure Title Page Number Number 10-1 Basic Timer Control Register (BTCON) .............................................................................. 10-2 10-2 Basic Timer Block Diagram .
xiv S3C9228/P9228 MICROCONTROLLER S List of Figures (Con cluded ) Figure Title Page Number Number 16-1 Stop Mode Release Timing When Initiated by an External Interrupt .................................... 16-5 16-2 Stop Mode Release Timing When Initiated by a RESET .
S3C9228/P9228 MICROCONTROLLER S xv List of Tables Table Title Page Number Number 1-1 Pin Descriptions ................................................................................................................. 1-6 6-1 Instruction Group Summary .
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S3C9228/P9228 MICROCONTROLLER S xvii List of Programming Tips Description Page Number Chapter 2: Address Spaces Addressing the Common Working Register Area ..................................................................................... 2-4 Standard Stack Operations Using PUSH and POP .
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S3C9228/P9228 MICROCONTROLLER S xix List of Register Descriptions Register Full Register Name Page Identifier Number ADCON A/D Converter Co ntrol Register .............................................................................. 4-5 BTCON Basic Timer Control Register .
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S3C9228/P9228 MICROCONTROLLER S xxi List of Instruction Descriptions Instruction Full Instruction Name Page Mnemonic Number ADC Add With Carry ...................................................................................................... 6 - 11 ADD Add .
S3C9228/P9228 PRODUCT OVERVIEW 1- 1 1 PRODUCT OVERVIEW SAM8 8RC RI PRODUCT FAMILY Samsung's SAM88RCRI family of 8-bit single-chi p CMOS microcontrollers offer fast and efficient CPU, a wide range of integrated peripherals, and supports OTP device .
PRODUCT OVERVIEW S3C9228/P9228 1- 2 FEATURES CPU • SAM88RCRI CPU core Memory • 8192 × 8 bits program memory (ROM) • 264 × 8 bits data memory (RAM) (Including LCD data memory) Instruction Set .
S3C9228/P9228 PRODUCT OVERVIEW 1- 3 BLOCK DIAGRAM 8-Bit Timer/ CounterA Port I/O and Interrupt Control SAM88RCRI CPU RESET X IN XT IN I/O Port 0 8-Kbyte ROM 264-Byte Register File X OUT XT OUT 16-Bit Timer/ Counter1 8-Bit Timer/ CounterB TAOUT/ P0.0 T1CLK/ P0.
PRODUCT OVERVIEW S3C9228/P9228 1- 4 PIN ASSIGNMENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 S3C9228 (44-QFP) P1.0/AD0/INT P1.1/AD1/INT P1.2/AD2/INT P1.3/AD3/INT V DD V SS X OUT X IN TEST XT IN XT OUT RESET P2.3 P2.2/SI SEG0/P2.1/SO SEG1/P2.
S3C9228/P9228 PRODUCT OVERVIEW 1- 5 COM1/P6.2 COM0/P6.3 P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P1.0/AD0/INT P1.1/AD1/INT P1.2/AD2/INT P1.3/AD3/INT V DD V SS X OUT X IN TEST XT IN XT OUT RESET P2.3 P2.2/SI SEG0/P2.1/SO S3C9228 (42-SDIP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 COM2/P6.
PRODUCT OVERVIEW S3C9228/P9228 1- 6 PIN DESCRIPTIONS Table 1- 1 . Pin Descriptions Pin Names Pin Type Pin Description Circuit Number Pin Numbers Share Pins P0.0 P0.1 P0.2 P0.3 I/O 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups.
S3C9228/P9228 PRODUCT OVERVIEW 1- 7 Table 1- 1 . Pin Descriptions (Continued) Pin Names Pin Type Pin Description Circuit Number Pin Numbers Share Pins V DD , V SS – Power input pins for internal pow.
PRODUCT OVERVIEW S3C9228/P9228 1- 8 PIN CIRCUIT DIAGRAMS RESET V DD Pull-Up Resistor Noise Filter Figure 1-4. Pin Circuit Type B V DD Output Output Disable Data V SS Figure 1-5.
S3C9228/P9228 PRODUCT OVERVIEW 1- 9 V DD Pull-up Enable V DD I/O Pull-up Resistor Output Disable Data External Interrupt Input Open-Drain Figure 1-7. Pin Circuit Type E-4 V DD I/O Pull-up Resistor Circuit Type E To ADC Data ADEN ADSELECT Open-Drain EN Data Output Disable Pull-up Enable Figure 1-8.
PRODUCT OVERVIEW S3C9228/P9228 1- 10 Out SEG/COM V LC3 Output Disable V LC2 V LC1 V SS V LC4 V LC5 Figure 1-9. Pin Circuit Type H-23.
S3C9228/P9228 PRODUCT OVERVIEW 1- 11 V DD Pull-up Enable V DD I/O Pull-up Resistor Data Open-Drain EN Circuit Type H-23 LCD Out EN COM/SEG Output Disable Figure 1-10. Pin Circuit Type H-32 V DD Pull-up Enable V DD I/O Pull-up Resistor Data Open-Drain EN Circuit Type H-23 LCD Out EN COM/SEG Output Disable Figure 1-11.
PRODUCT OVERVIEW S3C9228/P9228 1- 12 V DD Pull-up Enable V DD I/O Pull-up Resistor Data Open-Drain EN Circuit Type H-23 LCD Out EN COM/SEG Output Disable Port Enable (LMOD.
S3C9228/P9228 ADDRESS SPACES 2- 1 2 ADDRESS SPACES OVERVIEW The S3C9228/P9228 microcontroller has three kinds of address space: — Program memory (ROM) — Internal register file — LCD display register file A 16 -bit address bus supports program memory operations.
ADDRESS SPACES S3C9228/P9228 2- 2 PROGRAM MEMORY (ROM) Program memory (ROM) stores program code or table data. The S3C9228 has 8K bytes of mask- programable program memory. The program memory address range is therefore 0H-1FFFH. The first 2 bytes of the ROM (0000H– 0001H) are an interrupt vector address.
S3C9228/P9228 ADDRESS SPACES 2- 3 REGISTER ARCHITECTURE The upper 72 bytes of the S3C9228/P9228 's internal register file are addressed as working registers, system cont r ol registe r s and periphe r al control registers. The lower 184 bytes of internal register file (00H– B7 H) is called the general purpose register space .
ADDRESS SPACES S3C9228/P9228 2- 4 COMMON WORKING REGISTER AREA (C0H–CFH) The SAM88RCR I register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time.
S3C9228/P9228 ADDRESS SPACES 2- 5 SYSTEM STACK S 3C9 -series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3C9228/P9228 architecture supports stack operations in the internal register file.
ADDRESS SPACES S3C9228/P9228 2- 6 + + PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file usi.
S3C9228/P9228 ADDRESSING MODES 3- 1 3 ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand.
ADDRESSING MODES S3C9228/P9228 3- 2 REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register (see Figure 3- 1).
S3C9228/P9228 ADDRESSING MODES 3- 3 INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand.
ADDRESSING MODES S3C9228/P9228 3- 4 INDIRECT REGISTER ADDRESSING MODE ( C ontinued ) dst OPCODE PAIR Points to Rigister Pair Example Instruction References Program Memory Sample Instructions: CALL @RR2 JP @RR2 Program Memory Register File Value used in Instruction OPERAND REGISTER Program Memory 16-Bit Address Points to Program Memory Figure 3- 4 .
S3C9228/P9228 ADDRESSING MODES 3- 5 INDIRECT REGISTER ADDRESSING MODE (C ontinued ) dst OPCODE OPERAND 4-Bit Working Register Address Point to the Woking Register (1 of 16) Sample Instruction: OR R6, @R2 Program Memory Register File src 4 LSBs Value used in Instruction OPERAND CFH C0H .
ADDRESSING MODES S3C9228/P9228 3- 6 INDIRECT REGISTER ADDRESSING MODE (C oncluded ) dst OPCODE 4-Bit Working Register Address Sample Instructions: LCD R5,@RR6 ; Program memory access LDE R3,@RR14 ; Ex.
S3C9228/P9228 ADDRESSING MODES 3- 7 INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3- 7). You can use Indexed addressing mode to access locations in the internal register file or in external memory.
ADDRESSING MODES S3C9228/P9228 3- 8 INDEXED ADDRESSING MODE (C ontinued ) Point to Working Register Pair (1 of 8) LSB Selects 16-Bit address added to offset dst OPCODE Program Memory XS (OFFSET) 4-Bit Working Register Address Sample Instructions: LDC R4, #04H[RR2] ; The values in the program address (RR2 + #04H) are loaded into register R4.
S3C9228/P9228 ADDRESSING MODES 3- 9 INDEXED ADDRESSING MODE (C oncluded ) Point to Working Register Pair (1 of 8) LSB Selects 16-Bit address added to offset Program Memory 4-Bit Working Register Address Sample Instructions: LDC R4, #1000H[RR2] ; The values in the program address (RR2 + #1000H) are loaded into register R4.
ADDRESSING MODES S3C9228/P9228 3- 10 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
S3C9228/P9228 ADDRESSING MODES 3- 11 DIRECT ADDRESS MODE (C ontinued ) OPCODE Program Memory Upper Address Byte Program Memory Address Used Lower Address Byte Sample Instructions: JP C,JOB1 ; Where JOB1 is a 16-bit immediate address CALL DISPLAY ; Where DISPLAY is a 16-bit immediate address Next OPCODE Figure 3- 11 .
ADDRESSING MODES S3C9228/P9228 3- 12 RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value.
S3C9228/P9228 CONTROL REGISTERS 4- 1 4 CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3C9228/P9228 control registers are presented in an easy-to-read format. These descriptions will help familiarize you with the mapped locations in the register file.
CONTROL REGISTERS S3C9228/P9228 4- 2 Table 4-1. Sys tem and Peripheral C ontrol Registers (Page 0) Register Name Mnemonic Address (Page 0) R/W Decimal Hex Port 0 Control Register P0CON 235 EBH R/W Por.
S3C9228/P9228 CONTROL REGISTERS 4- 3 Table 4- 1. Sys tem and Peripheral C ontrol Registers (Page 0) Register Name Mnemonic Address (Page 0) R/W Decimal Hex Locations D8H-B9H are not mapped.
CONTROL REGISTERS S3C9228/P9228 4- 4 FLAGS - System Flags Register .7 .6 .5 Bit Identifier RESET RESET Value Read/Write R = Read-only W = Write-only R/W = Read/write ' - ' = Not used Bit num.
S3C9228/P9228 CONTROL REGISTERS 4- 5 AD C ON — A/D Converter Co ntrol Register D 0 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––000000 Read/Write – – R/W R/W R R/W R/W R/W .7-.6 Not used for the S3C9228/P9228 .5- . 4 A/D Input Pin Selection Bits 0 0 AD0 (P1.
CONTROL REGISTERS S3C9228/P9228 4- 6 BTC ON — Basic Timer Co ntrol Register DCH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7- .4 Watchdog Timer En able Bits 1010 Disable watchdog function Any other value Enable watchdog function .
S3C9228/P9228 CONTROL REGISTERS 4- 7 CLKCON — System Clock Control Register D4H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .
CONTROL REGISTERS S3C9228/P9228 4- 8 FLAGS — System Flags Register D5H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value xxxx –––– Read/Write R/W R/W R/W R/W –––– .7 Carry Flag (C) 0 Operation does not generate a carry or borrow condition .
S3C9228/P9228 CONTROL REGISTERS 4- 9 INTPND1 — Interrupt Pending Register 1 D6 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 P1.3's Interrupt Pending Bit 0 No interrupt pending (when read), clear pending bit (when write) 1 Interrupt is pending (when read) .
CONTROL REGISTERS S3C9228/P9228 4- 10 INTPND2 — Interrupt Pending Register 2 D7 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––000000 Read/Write – – R/W R/W R/W R/W R/W R/W .
S3C9228/P9228 CONTROL REGISTERS 4- 11 LMOD — LCD Mode Control Register FE H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value –0000000 Read/Write – R/W R/W R/W R/W R/W R/W R/W .7 Not used for S3C9228/P9228 .6 COM Pins High Impedance Control Bit 0 Normal COMs signal output 1 COM pins are at high impedance .
CONTROL REGISTERS S3C9228/P9228 4- 12 LPOT — LCD Port Control Register D8 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value –0000000 Read/Write – R/W R/W R/W R/W R/W R/W R/W .7 Not used for S3C9228/P9228 .6-.4 SEG4-SEG19 and COM0-COM3 Selection Bit SEG4-7 SEG8-11 SEG12-15 SEG16-19/ COM7-COM4 COM0-3 P4.
S3C9228/P9228 CONTROL REGISTERS 4- 13 OSCCON — Oscillator Control Register D3 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––00–0 Read/Write –––– R/W R/W – R/W .7 -.4 Not used for S3C9228/P9228 .3 Main Oscillator Control Bit 0 Main oscillator RUN 1 Main oscillator STOP .
CONTROL REGISTERS S3C9228/P9228 4- 14 P0CON – Port 0 Control Register EBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P0.3/BUZ/INT Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Alternative function (BUZ output) .
S3C9228/P9228 CONTROL REGISTERS 4- 15 P0INT –Port 0 Interrupt Enable Register EDH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P0.3's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt .
CONTROL REGISTERS S3C9228/P9228 4- 16 P0PUR –Port 0 Pull-up Resistors Enable Register ECH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P0.3's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor .
S3C9228/P9228 CONTROL REGISTERS 4- 17 P0EDGE –Port 0 Interrupt Edge Selection Register EEH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P0.3's Interrupt Edge Setting Bit 0 Falling edge interrupt 1 Rising edge interrupt .
CONTROL REGISTERS S3C9228/P9228 4- 18 P1CON – Port 1 Control Register EFH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P1.3/AD3/INT Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Alternative function (ADC mode) .
S3C9228/P9228 CONTROL REGISTERS 4- 19 P1INT –Port 1 Interrupt Enable Register F1H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P1.3's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt .
CONTROL REGISTERS S3C9228/P9228 4- 20 P1PUR –Port 1 Pull-up Resistors Enable Register F0H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P1.3's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor .
S3C9228/P9228 CONTROL REGISTERS 4- 21 P1EDGE –Port 1 Interrupt Edge Selection Register F2H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P1.3's Interrupt Edge Setting Bit 0 Falling edge interrupt 1 Rising edge interrupt .
CONTROL REGISTERS S3C9228/P9228 4- 22 P2CON – Port 2 Control Register F3H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P2.3 Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Not available .
S3C9228/P9228 CONTROL REGISTERS 4- 23 P2PUR –Port 2 Pull-up Resistors Enable Register F4H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P2.3's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor .
CONTROL REGISTERS S3C9228/P9228 4- 24 P3CON – Port 3 Control Register F5H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .
S3C9228/P9228 CONTROL REGISTERS 4- 25 P3INT –Port 3 Interrupt Enable Register F7H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––––00 Read/Write –––––– R/W R/W .7-.2 Not used for S3C9228/P9228 .1 P3.1's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt .
CONTROL REGISTERS S3C9228/P9228 4- 26 P3PUR –Port 3 Pull-up Resistors Enable Register F6H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––––00 Read/Write –––––– R/W R/W .7-.2 Not used for S3C9228/P9228 .1 P3.1's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor .
S3C9228/P9228 CONTROL REGISTERS 4- 27 P3EDGE –Port 3 Interrupt Edge Selection Register F8H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––––00 Read/Write –––––– R/W R/W .7-.4 Not used for S3C9228/P9228 .1 P3.1's Interrupt State Setting Bit 0 Falling edge interrupt 1 Rising edge interrupt .
CONTROL REGISTERS S3C9228/P9228 4- 28 P4CONH – Port 4 Control Register High Byte F9H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P4.7/SEG11 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .
S3C9228/P9228 CONTROL REGISTERS 4- 29 P4CONL –Port 4 Control Register Low Byte FAH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P4.3/SEG7 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .
CONTROL REGISTERS S3C9228/P9228 4- 30 P5CONH – Port 5 Control Register High Byte FBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 -.6 P5.7/SEG19/COM4 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .
S3C9228/P9228 CONTROL REGISTERS 4- 31 P5CONL – Port 5 Control Register Low Byte FCH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 -.6 P5.3/SEG15 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .
CONTROL REGISTERS S3C9228/P9228 4- 32 P6CON – Port 6 Control Register High Byte FDH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 -.6 P6.3/COM0 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .
S3C9228/P9228 CONTROL REGISTERS 4- 33 SIOCON — SIO Control Register E1 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 0000000– Read/Write R/W R/W R/W R/W R/W R/W R/W – .7 SIO Shift Clock Selection Bit 0 Internal clock ( P.S clock) 1 External clock (SCK) .
CONTROL REGISTERS S3C9228/P9228 4- 34 STPCON – Stop Control Register E0H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .
S3C9228/P9228 CONTROL REGISTERS 4- 35 SYM — System Mode Register DFH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .
CONTROL REGISTERS S3C9228/P9228 4- 36 T A CON — Timer 1/A Control Register BBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 0 000000– Read/Write R/W R/W R/W R/W R/W R/W R/W – .7 Timer 1 Mode Selection Bit 0 Two 8-bit timers mode (Timer A/B) 1 One 16-bit timer mode (Timer 1) .
S3C9228/P9228 CONTROL REGISTERS 4- 37 T B CON — Timer B Control Register BA H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value –000000– Read/Write – R/W R/W R/W R/W R/W R/W – .7 Not used for S3C9228/P9228 .6-.4 Timer B Clock Selection Bits 000 fxx/512 001 fxx/256 010 fxx/64 011 fxx/8 100 fxx (system clock) 101 fxt (sub clock) .
CONTROL REGISTERS S3C9228/P9228 4- 38 WTCON — Watch Timer Control Register DA H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 0000000– Read/Write R/W R/W R/W R/W R/W R/W R/W – .7 Watch Timer Clock Selection Bit 0 Select main clock divided by 2 7 (fx/128) 1 Select sub clock ( fxt) .
S3C9228/P9228 INTERRUPT STRUCTURE 5- 1 5 INTERRUPT STRUCTURE OVERVIEW The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through a interrupt vector which is assigned in ROM address 0000H–0001H.
INTERRUPT STRUCTURE S3C9228/P9228 5- 2 INTERRUPT PENDING FUNCTION TYPES When the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (IRET) occurs.
S3C9228/P9228 INTERRUPT STRUCTURE 5- 3 INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request pending bit to "1". 2. The CPU generates an interrupt acknowledge signal.
INTERRUPT STRUCTURE S3C9228/P9228 5- 4 S3C9228/P9228 INTERRUPT STRUCTURE The S3C9228/P9228 microcontroller has fourteen peripheral interrupt sources: — Timer 1/A interr upt — Timer B interrupt —.
S3C9228/P9228 INTERRUPT STRUCTURE 5- 5 SYM.3 (EI, DI) P0INT.0 P0.0 External Interript P0INT.1 P0.1 External Interript P0.3 External Interript P0.2 External Interript P0INT.2 P0INT.3 INTPND1.0 INTPND1.1 INTPND1.2 INTPND1.3 P1.0 External Interript P1INT.
INTERRUPT STRUCTURE S3C9228/P9228 5- 6 Programming Tip — How to clear an interrupt pending bit As the following examples are shown, a load instruction should be used to clear an interrupt pending bit. Examples: 1. LD INTPND1, #11111011B ; Clear P0.2's interrupt pending bit • • • IRET 2.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 1 6 SAM8 8RC R I INSTRUCTION SET OVERVIEW The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8- bit arithmetic and logic operations. There are 41 instructions.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 2 Table 6- 1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst,src Load LDC dst,src Load program memory LDE ds.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 3 Table 6- 1 . Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions CALL dst Call procedure IRET Interrupt re.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 4 FLAGS REGISTER (FLAGS) The FLAGS register contains eight bits that describe the current status of CPU operations.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 5 INSTRUCTION SET NOTATION Table 6- 2 . Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign flag V Overflow flag 0 Cleared to logic zero 1 Set to logic one * Set or cleared according to operation – Value is unaffected x Value is undefined Table 6- 3 .
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 6 Table 6- 4 . Instruction Notation Conventions Notation Description Actual Operand Range cc Condition code See list of condition codes in Table 6- 6. r Working register only Rn (n = 0–15) rr Working register pair RRp (p = 0, 2, 4, .
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 7 Table 6- 5 . Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – 0123456 7 U 0 DEC R1 DEC IR1 ADD r1,r2 ADD r1,Ir2 ADD R2,R1 ADD IR2,R1 ADD R1,IM .
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 8 Table 6- 5 . Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – 8 9 A B C D E F U 0 LD r1,R2 LD r2,R1 JR cc,RA LD r1,IM JP cc,DA INC r1 .
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 9 CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc).
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 10 INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM88RCRI instruction set. Information is arranged in a consistent format for improved readability and for fast referencing.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 11 ADC — Add With Carry ADC dst,src Operation: dst ¨ dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 12 ADD — Add ADD dst,src Operation: dst ¨ dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 13 AND — Logical AND AND dst,src Operation: dst ¨ dst AND src The source operand is logically ANDed with the destination operand.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 14 CALL — Call Procedure CALL dst Operation: SP ¨ SP – 1 @SP ¨ PCL SP ¨ SP –1 @SP ¨ PCH PC ¨ dst The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 15 CCF — Complement Carry Flag CCF Operation: C ¨ NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 16 CLR — Clear CLR dst Operation: dst ¨ "0" The destination location is cleared to "0".
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 17 COM — Complement COM dst Operation: dst ¨ NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 18 CP — Compare CP dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 19 DEC — Decrement DEC dst Operation: dst ¨ dst – 1 The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 20 DI — Disable Interrupts DI Operation: SYM (2) ¨ 0 Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt processing.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 21 EI — Enable Interrupts EI Operation: SYM (2) ¨ 1 An EI instruction sets bit 2 of the system mode register, SYM.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 22 IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 23 INC — Increment INC dst Operation: dst ¨ dst + 1 The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 24 IRET — Interrupt Return IRET IRET Operation: FLAGS ¨ @SP SP ¨ SP + 1 PC ¨ @SP SP ¨ SP + 2 SYM(2) ¨ 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 25 JP — Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC ¨ dst The conditional JUMP instruction transfers program cont.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 26 JR — Jump Relative JR cc,dst Operation: If cc is true, PC ¨ PC + dst If the condition specified by the condition code (cc) is true, the relative addre.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 27 LD — Load LD dst,src Operation: dst ¨ src The contents of the source are loaded into the destination.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 28 LD — Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH .
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 29 LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst ¨ src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 30 LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 31 LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src Operation: dst ¨ src rr ¨ rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 32 LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src Operation: dst ¨ src rr ¨ rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 33 NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typic ally, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 34 OR — Logical OR OR dst,src Operation: dst ¨ dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 35 POP — Pop From Stack POP dst Operation: dst ¨ @SP SP ¨ SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 36 PUSH — Push To Stack PUSH src Operation: SP ¨ SP – 1 @SP ¨ src A PUSH instruction decrements the stack pointer value and loads the contents of the source ( src) into the location addressed by the decremented stack pointer.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 37 RCF — Reset Carry Flag RCF RCF Operation: C ¨ 0 The carry flag is cleared to logic zero, regardless of its previous value.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 38 RET — Return RET Operation: PC ¨ @SP SP ¨ SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 39 RL — Rotate Left RL dst Operation: C ¨ dst (7) dst (0) ¨ dst (7) dst (n + 1) ¨ dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value o f bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 40 RLC — Rotate Left Through Carry RLC dst Operation: dst (0) ¨ C C ¨ dst (7) dst (n + 1) ¨ dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 41 RR — Rotate Right RR dst Operation: C ¨ dst (0) dst (7) ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 The content s of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 42 RRC — Rotate Right Through Carry RRC dst Operation: dst (7) ¨ C C ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 43 SBC — Subtract With Carry SBC dst,src Operation: dst ¨ dst – src – c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 44 SCF — Set Carry Flag SCF Operation: C ¨ 1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 DF Example: The statement SCF sets the carry flag to logic one.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 45 SRA — Shift Right Arithmetic SRA dst Operation: dst (7) ¨ dst (7) C ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is perform ed on the destination operand.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 46 STOP — Stop Operation STOP Operation: The STOP instruction stops both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 47 SUB — Subtract SUB dst,src Operation: dst ¨ dst – src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 48 TCM — Test Complement Under Mask TCM dst,src Operation: (NOT dst) AND src Thi s instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 49 TM — Test Under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 50 XOR — Logical Exclusive OR XOR dst,src Operation: dst ¨ dst XOR src The source operand is logically exclusive- ORed with the destination operand and the result is stored in the destination.
S3C9228/P9228 CLOCK CIRCUITS 7- 1 7 CLOCK CIRCUITS OVERVIEW The S3C9228 microcontroller has two oscillator circuits: a main clock, and a sub clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits.
CLOCK CIRCUITS S3C9 228/P9228 7- 2 MAIN OSCILLATOR CIRCUITS X IN X OUT Figure 7-1. Crystal/Ceramic Oscillator X IN X OUT Figure 7-2. External Oscillator X IN X OUT R Figure 7-3. RC Oscillator SUB OSCILLATOR CIRCUITS XT IN XT OUT 32.768 kHz Figure 7-4.
S3C9228/P9228 CLOCK CIRCUITS 7- 3 CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted.
CLOCK CIRCUITS S3C9 228/P9228 7- 4 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in address D4H. It is read/write addressable and has the following funct.
S3C9228/P9228 CLOCK CIRCUITS 7- 5 OSCILLATOR CONTROL REGISTER (OSCCON) The oscillator control register, OSCCON, is located in address D3H. It is read/write addressable and has the following functions: — System clock selection — Main oscillator control — Sub oscillator control OSCCON.
CLOCK CIRCUITS S3C9 228/P9228 7- 6 SWITCHING THE CPU CLOCK Data loadings in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as the CPU clock, and also how this frequency is to be divided by setting CLKCON.
S3C9228/P9228 CLOCK CIRCUITS 7- 7 STOP CONTROL REGISTER (STPCON) The STOP control register, STPCON, is located in address E0H. It is read/write addressable and has the following functions: — Enable/Disable STOP instruction After a reset, the STOP instruction is disabled, because the value of STPCON is "other values".
CLOCK CIRCUITS S3C9 228/P9228 7- 8 NOTES.
S3C9228/P9228 RESET RESET and POWER-DOWN 8- 1 8 RESET RESET and POWER-DOWN SYSTEM RESET OVERVIEW During a power-on reset, the voltage at V DD goes to High level and the RESET pin is forced to Low level. The RESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock.
RESET RESET and POWER-DOWN S3C9228 /P9228 8- 2 POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP. In Stop mode, the operation of the CPU and main oscillator is halted. All peripherals which the main oscillator is selected as a clock source stop also because main oscillator stops.
S3C9228/P9228 RESET RESET and POWER-DOWN 8- 3 Using an Internal Interrupt to Release Stop Mode An internal interrupt, watch timer, can be used to release stop mode because the watch timer operates in stop mode if the clock source of watch timer is sub clock.
RESET RESET and POWER-DOWN S3C9228 /P9228 8- 4 HARDWARE RESET RESET VALUES Table 8-1 list the values for CPU and system registers, peripheral control registers, and peripheral data registers following a RESET operation in normal operating mode.
S3C9228/P9228 RESET RESET and POWER-DOWN 8- 5 Table 8-1. Register Values after RESET RESET (Continued) Register Name Mnemonic Address Bit Values after RESET RESET Dec Hex 76543210 System Mode Register.
RESET RESET and POWER-DOWN S3C9228 /P9228 8- 6 NOTES.
S3C9228/P9228 I/O P ORTS 9- 1 9 I/O PORTS OVERVIEW The S3C9228/P9228 microcontroller has seven bit-programmable I/O ports, P0-P6. Port 0 is 6-bit port, port 1, port 2, and port 6 are 4-bit ports, port 3 is 2-bit port, and port 4 and port 5 are 8-bit ports.
I/O PORTS S3C9228/P 9228 9- 2 PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all seven S3C9228 I/O port data registers. Data registers for ports 1, 2, 3, 4, 5, and 6 have the general format shown in Figure 9-1. Table 9-2.
S3C9228/P9228 I/O P ORTS 9- 3 PORT 0 Port 0 is an 6-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading the port 0 data register, P0 at location E4H in page 0.
I/O PORTS S3C9228/P 9228 9- 4 Port 0 Control Register (P0CON) EBH, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P0.3/BUZ (INT) P0CON bit-pair pin configuration settings: 00 01 10 11 N-channel open-drain output mode Alternative function (TAOUT, BUZ) P0.
S3C9228/P9228 I/O P ORTS 9- 5 Port 0 Interrupt Pending Bits (INTPND1.3-.0) D6H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB INTPND1 bit configuration settings: 0 1 P0.3 (INT) Interrupt is pending (when read) No interrupt pending (when read), clear pending bit (when write) P0.
I/O PORTS S3C9228/P 9228 9- 6 PORT 1 Port 1 is an 4-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location E5H in page 0.
S3C9228/P9228 I/O P ORTS 9- 7 Port 1 Interrupt Control Register (P1INT) F1H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Not used P1INT bit configuration settings: 0 1 P1.3 (INT) Enable interrupt Disable interrupt P1.2 (INT) P1.1 (INT) P1.0 (INT) Figure 9-8.
I/O PORTS S3C9228/P 9228 9- 8 Port 1 Interrupt Edge Selection Register (P1EDGE) F2H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P1EDGE bit configuration settings: 0 1 P1.3 (INT) Rising edge detection Falling edge detection P1.2 (INT) P1.1 (INT) P1.0 (INT) Not used Figure 9-10.
S3C9228/P9228 I/O P ORTS 9- 9 PORT 2 Port 2 is an 4-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location E6H in page 0.
I/O PORTS S3C9228/P 9228 9- 10 Port 2 Pull-up Control Register (P2PUR) F4H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P2PUR bit configuration settings: 0 1 Enable pull-up resistor Disable pull-up resistor Not used P2.
S3C9228/P9228 I/O P ORTS 9- 11 PORT 3 Port 3 is an 2-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location E7H in page 0.
I/O PORTS S3C9228/P 9228 9- 12 Port 3 Interrupt Control Register (P3INT) F7H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Not used P3INT bit configuration settings: 0 1 Enable interrupt Disable interrupt P3.1 (INTP) P3.0 (INTP) Figure 9-15. Port 3 Interrupt Control Register (P3INT) Port 3 Interrupt Pending Bits (INTPND2.
S3C9228/P9228 I/O P ORTS 9- 13 Port 3 Interrupt Edge Selection Register (P3EDGE) F8H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P3EDGE bit configuration settings: 0 1 Rising edge detection Falling edge detection P3.1 (INTP) P3.0 (INTP) Not used Figure 9-17.
I/O PORTS S3C9228/P 9228 9- 14 PORT 4 Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location E8H in page 0. P4.0-P4.7 can serve as inputs or as push-pull, open-drain outputs.
S3C9228/P9228 I/O P ORTS 9- 15 PORT 5 Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location E9H in page 0. P5.0-P5.7 can serve as inputs or as push-pull, open-drain outputs.
I/O PORTS S3C9228/P 9228 9- 16 PORT 6 Port 6 is an 4-bit I/O port with individually configurable pins. Port 6 pins are accessed directly by writing or reading the port 6 data register, P6 at location EAH in page 0. P6.0-P6.3 can serve as inputs or as push-pull, open-drain outputs.
S3C9228/P9228 ( Preliminary Spec ) BASIC TIMER 10- 1 10 BASIC TIMER OVERVIEW Basic timer (BT) can be used in two different ways: — As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. — To signal the end of the required oscillation stabilization interval after a reset or a stop mode release.
BASIC TIMER S3C9228 /P9228 ( Preliminary Spec ) 10- 2 BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function.
S3C9228/P9228 ( Preliminary Spec ) BASIC TIMER 10- 3 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than “1010B”.
BASIC TIMER S3C9228 /P9228 ( Preliminary Spec ) 10- 4 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows).
S3C9228/P9228 TIMER 1 11- 1 11 TIMER 1 ONE 16-BIT TIMER MODE (TIMER 1) The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. If TACON.7 is set to "1", timer 1 is used as a 16-bit timer. If TACON.7 is set to "0", timer 1 is used as two 8-bit timers.
TIMER 1 S3C9228/P922 8 11- 2 Timer 1 Control Register (TACON) You use the timer 1 control register, TACON, to — Enable the timer 1 operating (interval timer) — Select the timer 1 input clock frequ.
S3C9228/P9228 TIMER 1 11- 3 NOTE: When one 16-bit timer mode (TACON.7 <- "1": Timer 1) TACON.6-.4 M U X 1/8 1 /64 1 /256 1 /512 INTPND2.0 TAOUT T1INT 1/1 DIV R fxt T1CLK (X IN or XT IN ) fxx BTCON.0 TACON.2 TBCNT TACNT 16-Bit Comparator TBDATA Buffer TADATA Buffer TBDATA TADATA LSB MSB LSB MSB Match Signal Counter clear signal TACON.
TIMER 1 S3C9228/P922 8 11- 4 TWO 8-BIT TIMERS MODE (TIMER A and B) OVERVIEW The 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B have the interval timer mode by using the appropriate TACON and TBCON setting, respectively.
S3C9228/P9228 TIMER 1 11- 5 TACON and TBCON are located in page 0, at address BBH and BAH, and is read/write addressable using register addressing mode. A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer A interrupt.
TIMER 1 S3C9228/P922 8 11- 6 Timer B Control Register (TBCON) BAH, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Timer B match interrupt enable bit: 0 = Disable match interrupt 1 = Enable match interrupt Not us.
S3C9228/P9228 TIMER 1 11- 7 FUNCTION DESCRIPTION Interval Timer Function (Timer A and Timer B) The timer A and B module can generate an interrupt: the timer A match interrupt (TAINT) and the timer B match interrupt (TBINT). The timer A match interrupt pending condition (INTPND2.
TIMER 1 S3C9228/P922 8 11- 8 NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer A) TACON.6-.4 M U X 1/8 1 /64 1 /256 1 /512 INTPND2.0 TAOUT TAINT DIV R fxt T1CLK/ P0.1 (X IN or XT IN ) fxx BTCON.0 TACON.2 8-Bit Comparator TADATA Buffer TADATA Register LSB MSB LSB MSB Match Signal Counter Clear Signal TACON.
S3C9228/P9228 TIMER 1 11- 9 1/1 1/8 1 /64 1 /256 1 /512 NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer B) TBCON.6-.4 M U X INTPND2.1 TBINT DIV R fxt (X IN or XT IN ) fxx BTCON.0 TBCON.2 8-Bit Comparator TBDATA Buffer TBDATA Register LSB MSB LSB MSB Match Signal Counter Clear Signal TBCON.
TIMER 1 S3C9228/P922 8 11- 10 NOTES.
S3C9228/P9228 WATCH TIMER 12- 1 12 WATCH TIMER OVERVIEW Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1".
WATCH TIMER S3C922 8/P9228 12- 2 WATCH TIMER CONTROL REGISTER (WTCON) The watch timer control register, WTCON is used to select the input clock source, the watch timer interrupt time and Buzzer signal, to enable or disable the watch timer function. It is located in page 0 at address DAH, and is read/write addressable using register addressing mode.
S3C9228/P9228 WATCH TIMER 12- 3 WATCH TIMER CIRCUIT DIAGRAM WT INT Enable WTCON.1 WTCON.2 WTCON.3 WTCON.4 WTCON.5 WTCON.6 Enable/Disable Selector Circuit MUX INTPND2.3 WTINT WTCON.6 f W /2 15 f W /2 14 f W /2 13 f W /2 7 f W /64 (0.5 kHz) f W /32 (1 kHz) f W /16 (2 kHz) f W /8 (4 kHz) (1 Hz) f X = Main clock (where fx = 4.
WATCH TIMER S3C922 8/P9228 12- 4 NOTES.
S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 1 13 LCD CONTROLLER/DRIV ER OVERVIEW The S3C9228/P9228 microcontroller can directly drive an up-to- 128 -dot ( 16 segments x 8 commons) LCD panel.
LCD CONTROLLER/DRIVER S3C9228/P9228 13- 2 LCD CIRCUIT DIAGRAM SEG15/P5.3 COM4/SEG19/P5.7 COM7/SEG16/P5.4 160 16 Data BUS Port Latch LPOT Display RAM (Page1) Port Latch Port Latch Timing Controller MUX SEG Control or Selector COM Control or selector f LCD SEG0/P2.
S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 3 LCD RAM ADDRESS AREA RAM addresses of page 1 are used as LCD data memory. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off.
LCD CONTROLLER/DRIVER S3C9228/P9228 13- 4 LCD MODE CONTROL REGISTER (LMOD) A LMOD is located in page 0, at address FEH, and is read/write addressable using register addressing mode.
S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 5 LCD PORT CONTROL REGISTER The LCD port control register LPOT is used to control LCD signal pins or normal I/O pins. Following a RESET , a LPOT values are cleared to "0". LCD Port Control Register D8H, R/W .
LCD CONTROLLER/DRIVER S3C9228/P9228 13- 6 LCD VOLTAGE DIVIDING RESISTORS 1/5 Bias S3C9228/P9228 V DD R R R R R LMOD.4 V LC1 V LC2 V LC3 V LC4 V LC5 V SS 1/4 Bias S3C9228/P9228 V DD R R R R R LMOD.4 V LC1 V LC2 V LC3 V LC4 V LC5 V SS 1/3 Bias S3C9228/P9228 V DD R R R R R LMOD.
S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 7 1 Frame FR V DD V SS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM1 V LC2 (V LC3 ) V LC4 V SS V DD V LC1 SEG0 V LC2 (V LC3 ) V LC4 V SS V DD V LC1 COM2 V LC2 (.
LCD CONTROLLER/DRIVER S3C9228/P9228 13- 8 1 Frame V DD V SS 0 1 2 3 0 1 2 3 COM1 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) COM2 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) COM3 V SS V DD V LC1 ( V LC2 ).
S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 9 1 Frame V DD V SS 0 1 2 COM1 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) COM2 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) SEG0 V SS V DD V LC1 ( V LC2 ) V LC3 ( .
LCD CONTROLLER/DRIVER S3C9228/P9228 13- 10 NOTES.
S3C9228/P9228 A/D C ONVERTER 14- 1 14 10-BIT ANALOG-TO-DIGITAL CONVERTER OVERVIEW The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 10 -bit digital values.
A/D CONVERTER S3C9 228/P9228 14- 2 CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for conversion clock with an 4.
S3C9228/P9228 A/D C ONVERTER 14- 3 Conversion Data Register ADDATAH/ADDATAL D1H/D2H, Page 0, Read Only .9 .8 .7 .6 .5 .4 .3 .2 MSB LSB (ADDATAH) ------ .
A/D CONVERTER S3C9 228/P9228 14- 4 S3C9228 AD0-AD3 Analog Input Pin V DD 101 C (V SS ≤ ADC input ≤ V DD ) Figure 14-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy.
S3C9228/P9228 SERIAL I/O INTERFACE 1 5- 1 15 SERIAL I/O INTERFAC E OVERVIEW Serial I/O modules, SIO can interface with various types of external device that require serial data transfer.
SERIAL I/O INTERFACE S3C9228/P9228 15- 2 SIO CONTROL REGISTERS (SIOCON) The control register for serial I/O interface module, SIOCON, is located at E1H in page 0.
S3C9228/P9228 SERIAL I/O INTERFACE 1 5- 3 SIO PRE-SCALER REGISTER (SIOPS) The prescaler register for serial I/O interface module, SIOPS, are located at E3H in page 0.
SERIAL I/O INTERFACE S3C9228/P9228 15- 4 SERIAL I/O TIMING DIAGRAM (SIO) SO Transmit Complete SIO INT Set SIOCON.3 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SI SCK Figure 15-4 . Serial I/O Timing in Transmit/Receive Mode ( Tx at falling, SIOCON.
S3C9228/P9228 ELECT RICAL DATA 16- 1 16 ELECTRICAL DATA OVERVIEW In this chapter, S3C9228/P9228 electrical characteristics are presented in tables and graphs.
ELECTRICAL DATA S3C 9228/P9228 16- 2 Table 16-1. Absolute Maximum Ratings (T A = 25 ° C) Parameter Symbol Conditions Rating Unit Supply voltage V DD – – 0.3 to + 6.5 V Input voltage V IN Ports 0 –6 – 0.3 to V DD + 0.3 V Output voltage V O – – 0.
S3C9228/P9228 ELECT RICAL DATA 16- 3 Table 16-2. D.C. Electrical Characteristics (Continued) (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Input .
ELECTRICAL DATA S3C 9228/P9228 16- 4 Table 16-2. D.C. Electrical Characteristics (Concluded) (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Supply current (1) I DD1 Run mode: V DD = 5 V ± 10% 8.0 MHz – 6.
S3C9228/P9228 ELECT RICAL DATA 16- 5 Table 16-3. Data Retention Supply Voltage in Stop Mode (T A = – 25 ° C to + 85 ° C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage V DDDR – 2.0 – 5.5 V Data retention supply current I DDDR Stop mode, T A = 25 ° C V DDDR = 2.
ELECTRICAL DATA S3C 9228/P9228 16- 6 Execution of STOP Instrction RESET Occurs ~ ~ V DDDR ~ ~ Stop Mode Oscillation Stabilization TIme Normal Operating Mode Data Retention Mode t WAIT RESET V DD 0.2 V DD 0.8 V DD NOTE: t WAIT is the same as 16 × 1/BT clock.
S3C9228/P9228 ELECT RICAL DATA 16- 7 Table 16-5. A.C. Electrical Characteristics (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit SCK cycle time t K.
ELECTRICAL DATA S3C 9228/P9228 16- 8 Table 16-6. A/D Converter Electrical Characteristics (T A = – 25 ° C to + 85 ° C, V DD = 2.7 V to 5.5 V, V SS = 0 V) Parameter Symbol Conditions Min Typ Max Unit Resolution – 10 – bit Total accuracy VDD = 5.
S3C9228/P9228 ELECT RICAL DATA 16- 9 RESET t RSL 0.2 V DD Figure 16-4. Input Timing for RESET RESET t KH t KL 0.2V DD SCK t KCY 0.8V DD 0.8V DD 0.2V DD t SIK t KSI SI SO t KSO Output Data Figure 16-5.
ELECTRICAL DATA S3C 9228/P9228 16- 10 Table 16-7. Main Oscillation Characteristics (T A = – 25 ° C to + 85 ° C) Oscillator Clock Configuration Parameter Test Condition Min Typ Max Units Crystal X IN C1 X OUT Main oscillation frequency 2.7 V – 5.
S3C9228/P9228 ELECT RICAL DATA 16- 11 Table 16-9. Main Oscillation Stabilization Time (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit Crystal fx > 1 MHz – – 30 ms Ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage ranage.
ELECTRICAL DATA S3C 9228/P9228 16- 12 Table 16-10. Sub Oscillation Stabilization Time (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit Crystal – – – 10 s External clock XT IN input high and low width (t XH , t XL ) 5 – 15 µ s t XTH t XTL V DD -0.
S3C9228/P9228 ELECT RICAL DATA 16- 13 2 MHz 6.25 kHz (main)/8.2 kHz(sub) 1 2 6 Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) 1.0 MHz Instruction Clock 8 MHz 4 MHz fx (Main/Sub oscillation frequency) 400 kHz 2.7 5.
ELECTRICAL DATA S3C 9228/P9228 16- 14 NOTES.
S3C9228/P9228 MECHANICAL DATA 1 7- 1 17 MECHANICAL DATA OVERVIEW The S3C9228/P9228 microcontroller is currently available in a 42-pin SDIP and 44-pin QFP package. NOTE : Dimensions are in millimeters. 39.50 MAX 39.10 ± 0 .2 0.50 ± 0.1 1.78 (1.77) 0.
MECHANICAL DATA S3C9228/P9228 1 7- 2 44-QFP-1010B #44 NOTE : Dimensions are in millimeters. 10.00 ± 0.2 13.20 ± 0.3 10.00 ± 0.2 13.20 ± 0.3 #1 0.35 + 0.10 - 0.05 0.80 (1.00) 0.10 MAX 0.80 ± 0.20 0.05 MIN 2.05 ± 0.10 2.30 MAX 0.15 + 0.10 - 0.05 0-8 Figure 17-2.
S3C9228/P9228 S3P9228 OTP 18- 1 18 S3P9228 OTP OVERVIEW The S3P9228 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C9228 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format.
S3P9228 OTP S3C9228/P9228 18- 2 COM1/P6.2 COM0/P6.3 P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P1.0/AD0/INT P1.1/AD1/INT SDAT /P1.2/AD2/INT SCLK /P1.3/AD3/INT V DD /V DD V SS /V SS X OUT X IN V PP /TEST XT IN XT OUT RESET RESET / RESET P2.3 P2.
S3C9228/P9228 S3P9228 OTP 18- 3 Table 18-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P1.2 SDAT 3 (9) I/O Serial data pin. Output port when reading and input port when writing.
S3P9228 OTP S3C9228/P9228 18- 4 Table 18-4. D.C. Electrical Characteristics (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Supply current (1) I DD1 Run mode: V DD = 5 V ± 10% 8.0 MHz – 6.0 12.0 mA Crystal oscillator C1 = C2 = 22pF 4.
S3C9228/P9228 S3P9228 OTP 18- 5 2 MHz 6.25 kHz (main)/8.2 kHz(sub) 1 2 6 Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) 1.0 MHz Instruction Clock 8 MHz 4 MHz fx (Main/Sub oscillation frequency) 400 kHz 2.7 5.5 400 kHz (main)/32.
S3P9228 OTP S3C9228/P9228 18- 6 NOTES.
S3C9228/P9228 DEVEL OPMENT TOOLS 19- 1 19 DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy-to-use development support system in turn key form. The development support system is configured with a host system, debugging tools, and support software.
DEVELOPMENT TOOLS S3C9228/P9228 19- 2 BUS SMDS2+ RS-232C POD Probe Adapter PROM/OTP Writer Unit RAM Break/Display Unit Trace/Timer Unit SAM8 Base Unit Power Supply Unit IBM-PC AT or Compatible TB9228 Target Board EVA Chip Target Application System Figure 19-1.
S3C9228/P9228 DEVEL OPMENT TOOLS 19- 3 TB9228 TARGET BOARD The TB9228 target board is used for the S3C9228 microcontroller. It is supported by the SMDS2+ development system.
DEVELOPMENT TOOLS S3C9228/P9228 19- 4 Table 19-1. Power Selection Settings for TB9228 "To User_V CC " Settings Operating Mode Comments To User_V CC Off On Target System SMDS2/SMDS2+ TB9228 V CC V SS V CC The SMDS2/SMDS2+ supplies V CC to the target board (evaluation chip) and the target system.
S3C9228/P9228 DEVEL OPMENT TOOLS 19- 5 SMDS2+ Selection (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available.
DEVELOPMENT TOOLS S3C9228/P9228 19- 6 J101 42-SDIP J102 44-QFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 43 44 45 46 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 50 49 48 47 P6.2 P6.3 P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.
S3C9228/P9228 DEVEL OPMENT TOOLS 19- 7 Target Board Target System Target Cable for Connector Part Name: AP42SD Order Code: SM6538 J101 1 42 21 22 J101 1 42 21 22 50-Pin DIP Connector Figure 19-4.
DEVELOPMENT TOOLS S3C9228/P9228 19- 8 NOTES.
S3C9228/P9228 PRODUCT OVERVIEW 1- 1 1 PRODUCT OVERVIEW SAM8 8RC RI PRODUCT FAMILY Samsung's SAM88RCRI family of 8-bit single-chi p CMOS microcontrollers offer fast and efficient CPU, a wide range of integrated peripherals, and supports OTP device .
PRODUCT OVERVIEW S3C9228/P9228 1- 2 FEATURES CPU • SAM88RCRI CPU core Memory • 8192 × 8 bits program memory (ROM) • 264 × 8 bits data memory (RAM) (Including LCD data memory) Instruction Set .
S3C9228/P9228 PRODUCT OVERVIEW 1- 3 BLOCK DIAGRAM 8-Bit Timer/ CounterA Port I/O and Interrupt Control SAM88RCRI CPU RESET X IN XT IN I/O Port 0 8-Kbyte ROM 264-Byte Register File X OUT XT OUT 16-Bit Timer/ Counter1 8-Bit Timer/ CounterB TAOUT/ P0.0 T1CLK/ P0.
PRODUCT OVERVIEW S3C9228/P9228 1- 4 PIN ASSIGNMENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 S3C9228 (44-QFP) P1.0/AD0/INT P1.1/AD1/INT P1.2/AD2/INT P1.3/AD3/INT V DD V SS X OUT X IN TEST XT IN XT OUT RESET P2.3 P2.2/SI SEG0/P2.1/SO SEG1/P2.
S3C9228/P9228 PRODUCT OVERVIEW 1- 5 COM1/P6.2 COM0/P6.3 P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P1.0/AD0/INT P1.1/AD1/INT P1.2/AD2/INT P1.3/AD3/INT V DD V SS X OUT X IN TEST XT IN XT OUT RESET P2.3 P2.2/SI SEG0/P2.1/SO S3C9228 (42-SDIP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 COM2/P6.
PRODUCT OVERVIEW S3C9228/P9228 1- 6 PIN DESCRIPTIONS Table 1- 1 . Pin Descriptions Pin Names Pin Type Pin Description Circuit Number Pin Numbers Share Pins P0.0 P0.1 P0.2 P0.3 I/O 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups.
S3C9228/P9228 PRODUCT OVERVIEW 1- 7 Table 1- 1 . Pin Descriptions (Continued) Pin Names Pin Type Pin Description Circuit Number Pin Numbers Share Pins V DD , V SS – Power input pins for internal pow.
PRODUCT OVERVIEW S3C9228/P9228 1- 8 PIN CIRCUIT DIAGRAMS RESET V DD Pull-Up Resistor Noise Filter Figure 1-4. Pin Circuit Type B V DD Output Output Disable Data V SS Figure 1-5.
S3C9228/P9228 PRODUCT OVERVIEW 1- 9 V DD Pull-up Enable V DD I/O Pull-up Resistor Output Disable Data External Interrupt Input Open-Drain Figure 1-7. Pin Circuit Type E-4 V DD I/O Pull-up Resistor Circuit Type E To ADC Data ADEN ADSELECT Open-Drain EN Data Output Disable Pull-up Enable Figure 1-8.
PRODUCT OVERVIEW S3C9228/P9228 1- 10 Out SEG/COM V LC3 Output Disable V LC2 V LC1 V SS V LC4 V LC5 Figure 1-9. Pin Circuit Type H-23.
S3C9228/P9228 PRODUCT OVERVIEW 1- 11 V DD Pull-up Enable V DD I/O Pull-up Resistor Data Open-Drain EN Circuit Type H-23 LCD Out EN COM/SEG Output Disable Figure 1-10. Pin Circuit Type H-32 V DD Pull-up Enable V DD I/O Pull-up Resistor Data Open-Drain EN Circuit Type H-23 LCD Out EN COM/SEG Output Disable Figure 1-11.
PRODUCT OVERVIEW S3C9228/P9228 1- 12 V DD Pull-up Enable V DD I/O Pull-up Resistor Data Open-Drain EN Circuit Type H-23 LCD Out EN COM/SEG Output Disable Port Enable (LMOD.
S3C9228/P9228 ADDRESS SPACES 2- 1 2 ADDRESS SPACES OVERVIEW The S3C9228/P9228 microcontroller has three kinds of address space: — Program memory (ROM) — Internal register file — LCD display register file A 16 -bit address bus supports program memory operations.
ADDRESS SPACES S3C9228/P9228 2- 2 PROGRAM MEMORY (ROM) Program memory (ROM) stores program code or table data. The S3C9228 has 8K bytes of mask- programable program memory. The program memory address range is therefore 0H-1FFFH. The first 2 bytes of the ROM (0000H– 0001H) are an interrupt vector address.
S3C9228/P9228 ADDRESS SPACES 2- 3 REGISTER ARCHITECTURE The upper 72 bytes of the S3C9228/P9228 's internal register file are addressed as working registers, system cont r ol registe r s and periphe r al control registers. The lower 184 bytes of internal register file (00H– B7 H) is called the general purpose register space .
ADDRESS SPACES S3C9228/P9228 2- 4 COMMON WORKING REGISTER AREA (C0H–CFH) The SAM88RCR I register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time.
S3C9228/P9228 ADDRESS SPACES 2- 5 SYSTEM STACK S 3C9 -series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3C9228/P9228 architecture supports stack operations in the internal register file.
ADDRESS SPACES S3C9228/P9228 2- 6 + + PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file usi.
S3C9228/P9228 ADDRESSING MODES 3- 1 3 ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand.
ADDRESSING MODES S3C9228/P9228 3- 2 REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register (see Figure 3- 1).
S3C9228/P9228 ADDRESSING MODES 3- 3 INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand.
ADDRESSING MODES S3C9228/P9228 3- 4 INDIRECT REGISTER ADDRESSING MODE ( C ontinued ) dst OPCODE PAIR Points to Rigister Pair Example Instruction References Program Memory Sample Instructions: CALL @RR2 JP @RR2 Program Memory Register File Value used in Instruction OPERAND REGISTER Program Memory 16-Bit Address Points to Program Memory Figure 3- 4 .
S3C9228/P9228 ADDRESSING MODES 3- 5 INDIRECT REGISTER ADDRESSING MODE (C ontinued ) dst OPCODE OPERAND 4-Bit Working Register Address Point to the Woking Register (1 of 16) Sample Instruction: OR R6, @R2 Program Memory Register File src 4 LSBs Value used in Instruction OPERAND CFH C0H .
ADDRESSING MODES S3C9228/P9228 3- 6 INDIRECT REGISTER ADDRESSING MODE (C oncluded ) dst OPCODE 4-Bit Working Register Address Sample Instructions: LCD R5,@RR6 ; Program memory access LDE R3,@RR14 ; Ex.
S3C9228/P9228 ADDRESSING MODES 3- 7 INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3- 7). You can use Indexed addressing mode to access locations in the internal register file or in external memory.
ADDRESSING MODES S3C9228/P9228 3- 8 INDEXED ADDRESSING MODE (C ontinued ) Point to Working Register Pair (1 of 8) LSB Selects 16-Bit address added to offset dst OPCODE Program Memory XS (OFFSET) 4-Bit Working Register Address Sample Instructions: LDC R4, #04H[RR2] ; The values in the program address (RR2 + #04H) are loaded into register R4.
S3C9228/P9228 ADDRESSING MODES 3- 9 INDEXED ADDRESSING MODE (C oncluded ) Point to Working Register Pair (1 of 8) LSB Selects 16-Bit address added to offset Program Memory 4-Bit Working Register Address Sample Instructions: LDC R4, #1000H[RR2] ; The values in the program address (RR2 + #1000H) are loaded into register R4.
ADDRESSING MODES S3C9228/P9228 3- 10 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
S3C9228/P9228 ADDRESSING MODES 3- 11 DIRECT ADDRESS MODE (C ontinued ) OPCODE Program Memory Upper Address Byte Program Memory Address Used Lower Address Byte Sample Instructions: JP C,JOB1 ; Where JOB1 is a 16-bit immediate address CALL DISPLAY ; Where DISPLAY is a 16-bit immediate address Next OPCODE Figure 3- 11 .
ADDRESSING MODES S3C9228/P9228 3- 12 RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value.
S3C9228/P9228 CONTROL REGISTERS 4- 1 4 CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3C9228/P9228 control registers are presented in an easy-to-read format. These descriptions will help familiarize you with the mapped locations in the register file.
CONTROL REGISTERS S3C9228/P9228 4- 2 Table 4-1. Sys tem and Peripheral C ontrol Registers (Page 0) Register Name Mnemonic Address (Page 0) R/W Decimal Hex Port 0 Control Register P0CON 235 EBH R/W Por.
S3C9228/P9228 CONTROL REGISTERS 4- 3 Table 4- 1. Sys tem and Peripheral C ontrol Registers (Page 0) Register Name Mnemonic Address (Page 0) R/W Decimal Hex Locations D8H-B9H are not mapped.
CONTROL REGISTERS S3C9228/P9228 4- 4 FLAGS - System Flags Register .7 .6 .5 Bit Identifier RESET RESET Value Read/Write R = Read-only W = Write-only R/W = Read/write ' - ' = Not used Bit num.
S3C9228/P9228 CONTROL REGISTERS 4- 5 AD C ON — A/D Converter Co ntrol Register D 0 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––000000 Read/Write – – R/W R/W R R/W R/W R/W .7-.6 Not used for the S3C9228/P9228 .5- . 4 A/D Input Pin Selection Bits 0 0 AD0 (P1.
CONTROL REGISTERS S3C9228/P9228 4- 6 BTC ON — Basic Timer Co ntrol Register DCH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7- .4 Watchdog Timer En able Bits 1010 Disable watchdog function Any other value Enable watchdog function .
S3C9228/P9228 CONTROL REGISTERS 4- 7 CLKCON — System Clock Control Register D4H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .
CONTROL REGISTERS S3C9228/P9228 4- 8 FLAGS — System Flags Register D5H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value xxxx –––– Read/Write R/W R/W R/W R/W –––– .7 Carry Flag (C) 0 Operation does not generate a carry or borrow condition .
S3C9228/P9228 CONTROL REGISTERS 4- 9 INTPND1 — Interrupt Pending Register 1 D6 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 P1.3's Interrupt Pending Bit 0 No interrupt pending (when read), clear pending bit (when write) 1 Interrupt is pending (when read) .
CONTROL REGISTERS S3C9228/P9228 4- 10 INTPND2 — Interrupt Pending Register 2 D7 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––000000 Read/Write – – R/W R/W R/W R/W R/W R/W .
S3C9228/P9228 CONTROL REGISTERS 4- 11 LMOD — LCD Mode Control Register FE H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value –0000000 Read/Write – R/W R/W R/W R/W R/W R/W R/W .7 Not used for S3C9228/P9228 .6 COM Pins High Impedance Control Bit 0 Normal COMs signal output 1 COM pins are at high impedance .
CONTROL REGISTERS S3C9228/P9228 4- 12 LPOT — LCD Port Control Register D8 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value –0000000 Read/Write – R/W R/W R/W R/W R/W R/W R/W .7 Not used for S3C9228/P9228 .6-.4 SEG4-SEG19 and COM0-COM3 Selection Bit SEG4-7 SEG8-11 SEG12-15 SEG16-19/ COM7-COM4 COM0-3 P4.
S3C9228/P9228 CONTROL REGISTERS 4- 13 OSCCON — Oscillator Control Register D3 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––00–0 Read/Write –––– R/W R/W – R/W .7 -.4 Not used for S3C9228/P9228 .3 Main Oscillator Control Bit 0 Main oscillator RUN 1 Main oscillator STOP .
CONTROL REGISTERS S3C9228/P9228 4- 14 P0CON – Port 0 Control Register EBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P0.3/BUZ/INT Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Alternative function (BUZ output) .
S3C9228/P9228 CONTROL REGISTERS 4- 15 P0INT –Port 0 Interrupt Enable Register EDH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P0.3's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt .
CONTROL REGISTERS S3C9228/P9228 4- 16 P0PUR –Port 0 Pull-up Resistors Enable Register ECH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P0.3's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor .
S3C9228/P9228 CONTROL REGISTERS 4- 17 P0EDGE –Port 0 Interrupt Edge Selection Register EEH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P0.3's Interrupt Edge Setting Bit 0 Falling edge interrupt 1 Rising edge interrupt .
CONTROL REGISTERS S3C9228/P9228 4- 18 P1CON – Port 1 Control Register EFH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P1.3/AD3/INT Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Alternative function (ADC mode) .
S3C9228/P9228 CONTROL REGISTERS 4- 19 P1INT –Port 1 Interrupt Enable Register F1H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P1.3's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt .
CONTROL REGISTERS S3C9228/P9228 4- 20 P1PUR –Port 1 Pull-up Resistors Enable Register F0H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P1.3's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor .
S3C9228/P9228 CONTROL REGISTERS 4- 21 P1EDGE –Port 1 Interrupt Edge Selection Register F2H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P1.3's Interrupt Edge Setting Bit 0 Falling edge interrupt 1 Rising edge interrupt .
CONTROL REGISTERS S3C9228/P9228 4- 22 P2CON – Port 2 Control Register F3H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P2.3 Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Not available .
S3C9228/P9228 CONTROL REGISTERS 4- 23 P2PUR –Port 2 Pull-up Resistors Enable Register F4H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P2.3's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor .
CONTROL REGISTERS S3C9228/P9228 4- 24 P3CON – Port 3 Control Register F5H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .
S3C9228/P9228 CONTROL REGISTERS 4- 25 P3INT –Port 3 Interrupt Enable Register F7H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––––00 Read/Write –––––– R/W R/W .7-.2 Not used for S3C9228/P9228 .1 P3.1's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt .
CONTROL REGISTERS S3C9228/P9228 4- 26 P3PUR –Port 3 Pull-up Resistors Enable Register F6H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––––00 Read/Write –––––– R/W R/W .7-.2 Not used for S3C9228/P9228 .1 P3.1's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor .
S3C9228/P9228 CONTROL REGISTERS 4- 27 P3EDGE –Port 3 Interrupt Edge Selection Register F8H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––––00 Read/Write –––––– R/W R/W .7-.4 Not used for S3C9228/P9228 .1 P3.1's Interrupt State Setting Bit 0 Falling edge interrupt 1 Rising edge interrupt .
CONTROL REGISTERS S3C9228/P9228 4- 28 P4CONH – Port 4 Control Register High Byte F9H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P4.7/SEG11 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .
S3C9228/P9228 CONTROL REGISTERS 4- 29 P4CONL –Port 4 Control Register Low Byte FAH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7-.6 P4.3/SEG7 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .
CONTROL REGISTERS S3C9228/P9228 4- 30 P5CONH – Port 5 Control Register High Byte FBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 -.6 P5.7/SEG19/COM4 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .
S3C9228/P9228 CONTROL REGISTERS 4- 31 P5CONL – Port 5 Control Register Low Byte FCH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 -.6 P5.3/SEG15 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .
CONTROL REGISTERS S3C9228/P9228 4- 32 P6CON – Port 6 Control Register High Byte FDH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 -.6 P6.3/COM0 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode .
S3C9228/P9228 CONTROL REGISTERS 4- 33 SIOCON — SIO Control Register E1 H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 0000000– Read/Write R/W R/W R/W R/W R/W R/W R/W – .7 SIO Shift Clock Selection Bit 0 Internal clock ( P.S clock) 1 External clock (SCK) .
CONTROL REGISTERS S3C9228/P9228 4- 34 STPCON – Stop Control Register E0H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .
S3C9228/P9228 CONTROL REGISTERS 4- 35 SYM — System Mode Register DFH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value ––––0000 Read/Write –––– R/W R/W R/W R/W .
CONTROL REGISTERS S3C9228/P9228 4- 36 T A CON — Timer 1/A Control Register BBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 0 000000– Read/Write R/W R/W R/W R/W R/W R/W R/W – .7 Timer 1 Mode Selection Bit 0 Two 8-bit timers mode (Timer A/B) 1 One 16-bit timer mode (Timer 1) .
S3C9228/P9228 CONTROL REGISTERS 4- 37 T B CON — Timer B Control Register BA H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value –000000– Read/Write – R/W R/W R/W R/W R/W R/W – .7 Not used for S3C9228/P9228 .6-.4 Timer B Clock Selection Bits 000 fxx/512 001 fxx/256 010 fxx/64 011 fxx/8 100 fxx (system clock) 101 fxt (sub clock) .
CONTROL REGISTERS S3C9228/P9228 4- 38 WTCON — Watch Timer Control Register DA H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET RESET Value 0000000– Read/Write R/W R/W R/W R/W R/W R/W R/W – .7 Watch Timer Clock Selection Bit 0 Select main clock divided by 2 7 (fx/128) 1 Select sub clock ( fxt) .
S3C9228/P9228 INTERRUPT STRUCTURE 5- 1 5 INTERRUPT STRUCTURE OVERVIEW The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through a interrupt vector which is assigned in ROM address 0000H–0001H.
INTERRUPT STRUCTURE S3C9228/P9228 5- 2 INTERRUPT PENDING FUNCTION TYPES When the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (IRET) occurs.
S3C9228/P9228 INTERRUPT STRUCTURE 5- 3 INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request pending bit to "1". 2. The CPU generates an interrupt acknowledge signal.
INTERRUPT STRUCTURE S3C9228/P9228 5- 4 S3C9228/P9228 INTERRUPT STRUCTURE The S3C9228/P9228 microcontroller has fourteen peripheral interrupt sources: — Timer 1/A interr upt — Timer B interrupt —.
S3C9228/P9228 INTERRUPT STRUCTURE 5- 5 SYM.3 (EI, DI) P0INT.0 P0.0 External Interript P0INT.1 P0.1 External Interript P0.3 External Interript P0.2 External Interript P0INT.2 P0INT.3 INTPND1.0 INTPND1.1 INTPND1.2 INTPND1.3 P1.0 External Interript P1INT.
INTERRUPT STRUCTURE S3C9228/P9228 5- 6 Programming Tip — How to clear an interrupt pending bit As the following examples are shown, a load instruction should be used to clear an interrupt pending bit. Examples: 1. LD INTPND1, #11111011B ; Clear P0.2's interrupt pending bit • • • IRET 2.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 1 6 SAM8 8RC R I INSTRUCTION SET OVERVIEW The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8- bit arithmetic and logic operations. There are 41 instructions.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 2 Table 6- 1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst,src Load LDC dst,src Load program memory LDE ds.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 3 Table 6- 1 . Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions CALL dst Call procedure IRET Interrupt re.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 4 FLAGS REGISTER (FLAGS) The FLAGS register contains eight bits that describe the current status of CPU operations.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 5 INSTRUCTION SET NOTATION Table 6- 2 . Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign flag V Overflow flag 0 Cleared to logic zero 1 Set to logic one * Set or cleared according to operation – Value is unaffected x Value is undefined Table 6- 3 .
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 6 Table 6- 4 . Instruction Notation Conventions Notation Description Actual Operand Range cc Condition code See list of condition codes in Table 6- 6. r Working register only Rn (n = 0–15) rr Working register pair RRp (p = 0, 2, 4, .
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 7 Table 6- 5 . Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – 0123456 7 U 0 DEC R1 DEC IR1 ADD r1,r2 ADD r1,Ir2 ADD R2,R1 ADD IR2,R1 ADD R1,IM .
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 8 Table 6- 5 . Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – 8 9 A B C D E F U 0 LD r1,R2 LD r2,R1 JR cc,RA LD r1,IM JP cc,DA INC r1 .
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 9 CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc).
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 10 INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM88RCRI instruction set. Information is arranged in a consistent format for improved readability and for fast referencing.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 11 ADC — Add With Carry ADC dst,src Operation: dst ¨ dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 12 ADD — Add ADD dst,src Operation: dst ¨ dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 13 AND — Logical AND AND dst,src Operation: dst ¨ dst AND src The source operand is logically ANDed with the destination operand.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 14 CALL — Call Procedure CALL dst Operation: SP ¨ SP – 1 @SP ¨ PCL SP ¨ SP –1 @SP ¨ PCH PC ¨ dst The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 15 CCF — Complement Carry Flag CCF Operation: C ¨ NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 16 CLR — Clear CLR dst Operation: dst ¨ "0" The destination location is cleared to "0".
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 17 COM — Complement COM dst Operation: dst ¨ NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 18 CP — Compare CP dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 19 DEC — Decrement DEC dst Operation: dst ¨ dst – 1 The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 20 DI — Disable Interrupts DI Operation: SYM (2) ¨ 0 Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt processing.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 21 EI — Enable Interrupts EI Operation: SYM (2) ¨ 1 An EI instruction sets bit 2 of the system mode register, SYM.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 22 IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 23 INC — Increment INC dst Operation: dst ¨ dst + 1 The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 24 IRET — Interrupt Return IRET IRET Operation: FLAGS ¨ @SP SP ¨ SP + 1 PC ¨ @SP SP ¨ SP + 2 SYM(2) ¨ 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 25 JP — Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC ¨ dst The conditional JUMP instruction transfers program cont.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 26 JR — Jump Relative JR cc,dst Operation: If cc is true, PC ¨ PC + dst If the condition specified by the condition code (cc) is true, the relative addre.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 27 LD — Load LD dst,src Operation: dst ¨ src The contents of the source are loaded into the destination.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 28 LD — Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH .
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 29 LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst ¨ src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 30 LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 31 LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src Operation: dst ¨ src rr ¨ rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 32 LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src Operation: dst ¨ src rr ¨ rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 33 NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typic ally, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 34 OR — Logical OR OR dst,src Operation: dst ¨ dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 35 POP — Pop From Stack POP dst Operation: dst ¨ @SP SP ¨ SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 36 PUSH — Push To Stack PUSH src Operation: SP ¨ SP – 1 @SP ¨ src A PUSH instruction decrements the stack pointer value and loads the contents of the source ( src) into the location addressed by the decremented stack pointer.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 37 RCF — Reset Carry Flag RCF RCF Operation: C ¨ 0 The carry flag is cleared to logic zero, regardless of its previous value.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 38 RET — Return RET Operation: PC ¨ @SP SP ¨ SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 39 RL — Rotate Left RL dst Operation: C ¨ dst (7) dst (0) ¨ dst (7) dst (n + 1) ¨ dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value o f bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 40 RLC — Rotate Left Through Carry RLC dst Operation: dst (0) ¨ C C ¨ dst (7) dst (n + 1) ¨ dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 41 RR — Rotate Right RR dst Operation: C ¨ dst (0) dst (7) ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 The content s of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 42 RRC — Rotate Right Through Carry RRC dst Operation: dst (7) ¨ C C ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 43 SBC — Subtract With Carry SBC dst,src Operation: dst ¨ dst – src – c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 44 SCF — Set Carry Flag SCF Operation: C ¨ 1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 DF Example: The statement SCF sets the carry flag to logic one.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 45 SRA — Shift Right Arithmetic SRA dst Operation: dst (7) ¨ dst (7) C ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is perform ed on the destination operand.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 46 STOP — Stop Operation STOP Operation: The STOP instruction stops both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained.
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 47 SUB — Subtract SUB dst,src Operation: dst ¨ dst – src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 48 TCM — Test Complement Under Mask TCM dst,src Operation: (NOT dst) AND src Thi s instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).
S3C9228/P9228 S AM8 8RC RI INSTRUCTION SET 6 - 49 TM — Test Under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value.
SAM8 8 RI INSTRUCTION SET S3C9228/P9228 6 - 50 XOR — Logical Exclusive OR XOR dst,src Operation: dst ¨ dst XOR src The source operand is logically exclusive- ORed with the destination operand and the result is stored in the destination.
S3C9228/P9228 CLOCK CIRCUITS 7- 1 7 CLOCK CIRCUITS OVERVIEW The S3C9228 microcontroller has two oscillator circuits: a main clock, and a sub clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits.
CLOCK CIRCUITS S3C9 228/P9228 7- 2 MAIN OSCILLATOR CIRCUITS X IN X OUT Figure 7-1. Crystal/Ceramic Oscillator X IN X OUT Figure 7-2. External Oscillator X IN X OUT R Figure 7-3. RC Oscillator SUB OSCILLATOR CIRCUITS XT IN XT OUT 32.768 kHz Figure 7-4.
S3C9228/P9228 CLOCK CIRCUITS 7- 3 CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted.
CLOCK CIRCUITS S3C9 228/P9228 7- 4 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in address D4H. It is read/write addressable and has the following funct.
S3C9228/P9228 CLOCK CIRCUITS 7- 5 OSCILLATOR CONTROL REGISTER (OSCCON) The oscillator control register, OSCCON, is located in address D3H. It is read/write addressable and has the following functions: — System clock selection — Main oscillator control — Sub oscillator control OSCCON.
CLOCK CIRCUITS S3C9 228/P9228 7- 6 SWITCHING THE CPU CLOCK Data loadings in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as the CPU clock, and also how this frequency is to be divided by setting CLKCON.
S3C9228/P9228 CLOCK CIRCUITS 7- 7 STOP CONTROL REGISTER (STPCON) The STOP control register, STPCON, is located in address E0H. It is read/write addressable and has the following functions: — Enable/Disable STOP instruction After a reset, the STOP instruction is disabled, because the value of STPCON is "other values".
CLOCK CIRCUITS S3C9 228/P9228 7- 8 NOTES.
S3C9228/P9228 RESET RESET and POWER-DOWN 8- 1 8 RESET RESET and POWER-DOWN SYSTEM RESET OVERVIEW During a power-on reset, the voltage at V DD goes to High level and the RESET pin is forced to Low level. The RESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock.
RESET RESET and POWER-DOWN S3C9228 /P9228 8- 2 POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP. In Stop mode, the operation of the CPU and main oscillator is halted. All peripherals which the main oscillator is selected as a clock source stop also because main oscillator stops.
S3C9228/P9228 RESET RESET and POWER-DOWN 8- 3 Using an Internal Interrupt to Release Stop Mode An internal interrupt, watch timer, can be used to release stop mode because the watch timer operates in stop mode if the clock source of watch timer is sub clock.
RESET RESET and POWER-DOWN S3C9228 /P9228 8- 4 HARDWARE RESET RESET VALUES Table 8-1 list the values for CPU and system registers, peripheral control registers, and peripheral data registers following a RESET operation in normal operating mode.
S3C9228/P9228 RESET RESET and POWER-DOWN 8- 5 Table 8-1. Register Values after RESET RESET (Continued) Register Name Mnemonic Address Bit Values after RESET RESET Dec Hex 76543210 System Mode Register.
RESET RESET and POWER-DOWN S3C9228 /P9228 8- 6 NOTES.
S3C9228/P9228 I/O P ORTS 9- 1 9 I/O PORTS OVERVIEW The S3C9228/P9228 microcontroller has seven bit-programmable I/O ports, P0-P6. Port 0 is 6-bit port, port 1, port 2, and port 6 are 4-bit ports, port 3 is 2-bit port, and port 4 and port 5 are 8-bit ports.
I/O PORTS S3C9228/P 9228 9- 2 PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all seven S3C9228 I/O port data registers. Data registers for ports 1, 2, 3, 4, 5, and 6 have the general format shown in Figure 9-1. Table 9-2.
S3C9228/P9228 I/O P ORTS 9- 3 PORT 0 Port 0 is an 6-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading the port 0 data register, P0 at location E4H in page 0.
I/O PORTS S3C9228/P 9228 9- 4 Port 0 Control Register (P0CON) EBH, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P0.3/BUZ (INT) P0CON bit-pair pin configuration settings: 00 01 10 11 N-channel open-drain output mode Alternative function (TAOUT, BUZ) P0.
S3C9228/P9228 I/O P ORTS 9- 5 Port 0 Interrupt Pending Bits (INTPND1.3-.0) D6H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB INTPND1 bit configuration settings: 0 1 P0.3 (INT) Interrupt is pending (when read) No interrupt pending (when read), clear pending bit (when write) P0.
I/O PORTS S3C9228/P 9228 9- 6 PORT 1 Port 1 is an 4-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location E5H in page 0.
S3C9228/P9228 I/O P ORTS 9- 7 Port 1 Interrupt Control Register (P1INT) F1H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Not used P1INT bit configuration settings: 0 1 P1.3 (INT) Enable interrupt Disable interrupt P1.2 (INT) P1.1 (INT) P1.0 (INT) Figure 9-8.
I/O PORTS S3C9228/P 9228 9- 8 Port 1 Interrupt Edge Selection Register (P1EDGE) F2H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P1EDGE bit configuration settings: 0 1 P1.3 (INT) Rising edge detection Falling edge detection P1.2 (INT) P1.1 (INT) P1.0 (INT) Not used Figure 9-10.
S3C9228/P9228 I/O P ORTS 9- 9 PORT 2 Port 2 is an 4-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location E6H in page 0.
I/O PORTS S3C9228/P 9228 9- 10 Port 2 Pull-up Control Register (P2PUR) F4H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P2PUR bit configuration settings: 0 1 Enable pull-up resistor Disable pull-up resistor Not used P2.
S3C9228/P9228 I/O P ORTS 9- 11 PORT 3 Port 3 is an 2-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location E7H in page 0.
I/O PORTS S3C9228/P 9228 9- 12 Port 3 Interrupt Control Register (P3INT) F7H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Not used P3INT bit configuration settings: 0 1 Enable interrupt Disable interrupt P3.1 (INTP) P3.0 (INTP) Figure 9-15. Port 3 Interrupt Control Register (P3INT) Port 3 Interrupt Pending Bits (INTPND2.
S3C9228/P9228 I/O P ORTS 9- 13 Port 3 Interrupt Edge Selection Register (P3EDGE) F8H, Page 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P3EDGE bit configuration settings: 0 1 Rising edge detection Falling edge detection P3.1 (INTP) P3.0 (INTP) Not used Figure 9-17.
I/O PORTS S3C9228/P 9228 9- 14 PORT 4 Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location E8H in page 0. P4.0-P4.7 can serve as inputs or as push-pull, open-drain outputs.
S3C9228/P9228 I/O P ORTS 9- 15 PORT 5 Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location E9H in page 0. P5.0-P5.7 can serve as inputs or as push-pull, open-drain outputs.
I/O PORTS S3C9228/P 9228 9- 16 PORT 6 Port 6 is an 4-bit I/O port with individually configurable pins. Port 6 pins are accessed directly by writing or reading the port 6 data register, P6 at location EAH in page 0. P6.0-P6.3 can serve as inputs or as push-pull, open-drain outputs.
S3C9228/P9228 ( Preliminary Spec ) BASIC TIMER 10- 1 10 BASIC TIMER OVERVIEW Basic timer (BT) can be used in two different ways: — As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. — To signal the end of the required oscillation stabilization interval after a reset or a stop mode release.
BASIC TIMER S3C9228 /P9228 ( Preliminary Spec ) 10- 2 BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function.
S3C9228/P9228 ( Preliminary Spec ) BASIC TIMER 10- 3 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than “1010B”.
BASIC TIMER S3C9228 /P9228 ( Preliminary Spec ) 10- 4 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows).
S3C9228/P9228 TIMER 1 11- 1 11 TIMER 1 ONE 16-BIT TIMER MODE (TIMER 1) The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. If TACON.7 is set to "1", timer 1 is used as a 16-bit timer. If TACON.7 is set to "0", timer 1 is used as two 8-bit timers.
TIMER 1 S3C9228/P922 8 11- 2 Timer 1 Control Register (TACON) You use the timer 1 control register, TACON, to — Enable the timer 1 operating (interval timer) — Select the timer 1 input clock frequ.
S3C9228/P9228 TIMER 1 11- 3 NOTE: When one 16-bit timer mode (TACON.7 <- "1": Timer 1) TACON.6-.4 M U X 1/8 1 /64 1 /256 1 /512 INTPND2.0 TAOUT T1INT 1/1 DIV R fxt T1CLK (X IN or XT IN ) fxx BTCON.0 TACON.2 TBCNT TACNT 16-Bit Comparator TBDATA Buffer TADATA Buffer TBDATA TADATA LSB MSB LSB MSB Match Signal Counter clear signal TACON.
TIMER 1 S3C9228/P922 8 11- 4 TWO 8-BIT TIMERS MODE (TIMER A and B) OVERVIEW The 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B have the interval timer mode by using the appropriate TACON and TBCON setting, respectively.
S3C9228/P9228 TIMER 1 11- 5 TACON and TBCON are located in page 0, at address BBH and BAH, and is read/write addressable using register addressing mode. A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer A interrupt.
TIMER 1 S3C9228/P922 8 11- 6 Timer B Control Register (TBCON) BAH, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Timer B match interrupt enable bit: 0 = Disable match interrupt 1 = Enable match interrupt Not us.
S3C9228/P9228 TIMER 1 11- 7 FUNCTION DESCRIPTION Interval Timer Function (Timer A and Timer B) The timer A and B module can generate an interrupt: the timer A match interrupt (TAINT) and the timer B match interrupt (TBINT). The timer A match interrupt pending condition (INTPND2.
TIMER 1 S3C9228/P922 8 11- 8 NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer A) TACON.6-.4 M U X 1/8 1 /64 1 /256 1 /512 INTPND2.0 TAOUT TAINT DIV R fxt T1CLK/ P0.1 (X IN or XT IN ) fxx BTCON.0 TACON.2 8-Bit Comparator TADATA Buffer TADATA Register LSB MSB LSB MSB Match Signal Counter Clear Signal TACON.
S3C9228/P9228 TIMER 1 11- 9 1/1 1/8 1 /64 1 /256 1 /512 NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer B) TBCON.6-.4 M U X INTPND2.1 TBINT DIV R fxt (X IN or XT IN ) fxx BTCON.0 TBCON.2 8-Bit Comparator TBDATA Buffer TBDATA Register LSB MSB LSB MSB Match Signal Counter Clear Signal TBCON.
TIMER 1 S3C9228/P922 8 11- 10 NOTES.
S3C9228/P9228 WATCH TIMER 12- 1 12 WATCH TIMER OVERVIEW Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1".
WATCH TIMER S3C922 8/P9228 12- 2 WATCH TIMER CONTROL REGISTER (WTCON) The watch timer control register, WTCON is used to select the input clock source, the watch timer interrupt time and Buzzer signal, to enable or disable the watch timer function. It is located in page 0 at address DAH, and is read/write addressable using register addressing mode.
S3C9228/P9228 WATCH TIMER 12- 3 WATCH TIMER CIRCUIT DIAGRAM WT INT Enable WTCON.1 WTCON.2 WTCON.3 WTCON.4 WTCON.5 WTCON.6 Enable/Disable Selector Circuit MUX INTPND2.3 WTINT WTCON.6 f W /2 15 f W /2 14 f W /2 13 f W /2 7 f W /64 (0.5 kHz) f W /32 (1 kHz) f W /16 (2 kHz) f W /8 (4 kHz) (1 Hz) f X = Main clock (where fx = 4.
WATCH TIMER S3C922 8/P9228 12- 4 NOTES.
S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 1 13 LCD CONTROLLER/DRIV ER OVERVIEW The S3C9228/P9228 microcontroller can directly drive an up-to- 128 -dot ( 16 segments x 8 commons) LCD panel.
LCD CONTROLLER/DRIVER S3C9228/P9228 13- 2 LCD CIRCUIT DIAGRAM SEG15/P5.3 COM4/SEG19/P5.7 COM7/SEG16/P5.4 160 16 Data BUS Port Latch LPOT Display RAM (Page1) Port Latch Port Latch Timing Controller MUX SEG Control or Selector COM Control or selector f LCD SEG0/P2.
S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 3 LCD RAM ADDRESS AREA RAM addresses of page 1 are used as LCD data memory. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off.
LCD CONTROLLER/DRIVER S3C9228/P9228 13- 4 LCD MODE CONTROL REGISTER (LMOD) A LMOD is located in page 0, at address FEH, and is read/write addressable using register addressing mode.
S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 5 LCD PORT CONTROL REGISTER The LCD port control register LPOT is used to control LCD signal pins or normal I/O pins. Following a RESET , a LPOT values are cleared to "0". LCD Port Control Register D8H, R/W .
LCD CONTROLLER/DRIVER S3C9228/P9228 13- 6 LCD VOLTAGE DIVIDING RESISTORS 1/5 Bias S3C9228/P9228 V DD R R R R R LMOD.4 V LC1 V LC2 V LC3 V LC4 V LC5 V SS 1/4 Bias S3C9228/P9228 V DD R R R R R LMOD.4 V LC1 V LC2 V LC3 V LC4 V LC5 V SS 1/3 Bias S3C9228/P9228 V DD R R R R R LMOD.
S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 7 1 Frame FR V DD V SS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM1 V LC2 (V LC3 ) V LC4 V SS V DD V LC1 SEG0 V LC2 (V LC3 ) V LC4 V SS V DD V LC1 COM2 V LC2 (.
LCD CONTROLLER/DRIVER S3C9228/P9228 13- 8 1 Frame V DD V SS 0 1 2 3 0 1 2 3 COM1 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) COM2 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) COM3 V SS V DD V LC1 ( V LC2 ).
S3C9228/P9228 LCD CONTROLLER/DRIV ER 13- 9 1 Frame V DD V SS 0 1 2 COM1 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) COM2 V SS V DD V LC1 ( V LC2 ) V LC3 ( V LC4 ) SEG0 V SS V DD V LC1 ( V LC2 ) V LC3 ( .
LCD CONTROLLER/DRIVER S3C9228/P9228 13- 10 NOTES.
S3C9228/P9228 A/D C ONVERTER 14- 1 14 10-BIT ANALOG-TO-DIGITAL CONVERTER OVERVIEW The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 10 -bit digital values.
A/D CONVERTER S3C9 228/P9228 14- 2 CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for conversion clock with an 4.
S3C9228/P9228 A/D C ONVERTER 14- 3 Conversion Data Register ADDATAH/ADDATAL D1H/D2H, Page 0, Read Only .9 .8 .7 .6 .5 .4 .3 .2 MSB LSB (ADDATAH) ------ .
A/D CONVERTER S3C9 228/P9228 14- 4 S3C9228 AD0-AD3 Analog Input Pin V DD 101 C (V SS ≤ ADC input ≤ V DD ) Figure 14-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy.
S3C9228/P9228 SERIAL I/O INTERFACE 1 5- 1 15 SERIAL I/O INTERFAC E OVERVIEW Serial I/O modules, SIO can interface with various types of external device that require serial data transfer.
SERIAL I/O INTERFACE S3C9228/P9228 15- 2 SIO CONTROL REGISTERS (SIOCON) The control register for serial I/O interface module, SIOCON, is located at E1H in page 0.
S3C9228/P9228 SERIAL I/O INTERFACE 1 5- 3 SIO PRE-SCALER REGISTER (SIOPS) The prescaler register for serial I/O interface module, SIOPS, are located at E3H in page 0.
SERIAL I/O INTERFACE S3C9228/P9228 15- 4 SERIAL I/O TIMING DIAGRAM (SIO) SO Transmit Complete SIO INT Set SIOCON.3 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SI SCK Figure 15-4 . Serial I/O Timing in Transmit/Receive Mode ( Tx at falling, SIOCON.
S3C9228/P9228 ELECT RICAL DATA 16- 1 16 ELECTRICAL DATA OVERVIEW In this chapter, S3C9228/P9228 electrical characteristics are presented in tables and graphs.
ELECTRICAL DATA S3C 9228/P9228 16- 2 Table 16-1. Absolute Maximum Ratings (T A = 25 ° C) Parameter Symbol Conditions Rating Unit Supply voltage V DD – – 0.3 to + 6.5 V Input voltage V IN Ports 0 –6 – 0.3 to V DD + 0.3 V Output voltage V O – – 0.
S3C9228/P9228 ELECT RICAL DATA 16- 3 Table 16-2. D.C. Electrical Characteristics (Continued) (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Input .
ELECTRICAL DATA S3C 9228/P9228 16- 4 Table 16-2. D.C. Electrical Characteristics (Concluded) (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Supply current (1) I DD1 Run mode: V DD = 5 V ± 10% 8.0 MHz – 6.
S3C9228/P9228 ELECT RICAL DATA 16- 5 Table 16-3. Data Retention Supply Voltage in Stop Mode (T A = – 25 ° C to + 85 ° C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage V DDDR – 2.0 – 5.5 V Data retention supply current I DDDR Stop mode, T A = 25 ° C V DDDR = 2.
ELECTRICAL DATA S3C 9228/P9228 16- 6 Execution of STOP Instrction RESET Occurs ~ ~ V DDDR ~ ~ Stop Mode Oscillation Stabilization TIme Normal Operating Mode Data Retention Mode t WAIT RESET V DD 0.2 V DD 0.8 V DD NOTE: t WAIT is the same as 16 × 1/BT clock.
S3C9228/P9228 ELECT RICAL DATA 16- 7 Table 16-5. A.C. Electrical Characteristics (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit SCK cycle time t K.
ELECTRICAL DATA S3C 9228/P9228 16- 8 Table 16-6. A/D Converter Electrical Characteristics (T A = – 25 ° C to + 85 ° C, V DD = 2.7 V to 5.5 V, V SS = 0 V) Parameter Symbol Conditions Min Typ Max Unit Resolution – 10 – bit Total accuracy VDD = 5.
S3C9228/P9228 ELECT RICAL DATA 16- 9 RESET t RSL 0.2 V DD Figure 16-4. Input Timing for RESET RESET t KH t KL 0.2V DD SCK t KCY 0.8V DD 0.8V DD 0.2V DD t SIK t KSI SI SO t KSO Output Data Figure 16-5.
ELECTRICAL DATA S3C 9228/P9228 16- 10 Table 16-7. Main Oscillation Characteristics (T A = – 25 ° C to + 85 ° C) Oscillator Clock Configuration Parameter Test Condition Min Typ Max Units Crystal X IN C1 X OUT Main oscillation frequency 2.7 V – 5.
S3C9228/P9228 ELECT RICAL DATA 16- 11 Table 16-9. Main Oscillation Stabilization Time (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit Crystal fx > 1 MHz – – 30 ms Ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage ranage.
ELECTRICAL DATA S3C 9228/P9228 16- 12 Table 16-10. Sub Oscillation Stabilization Time (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit Crystal – – – 10 s External clock XT IN input high and low width (t XH , t XL ) 5 – 15 µ s t XTH t XTL V DD -0.
S3C9228/P9228 ELECT RICAL DATA 16- 13 2 MHz 6.25 kHz (main)/8.2 kHz(sub) 1 2 6 Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) 1.0 MHz Instruction Clock 8 MHz 4 MHz fx (Main/Sub oscillation frequency) 400 kHz 2.7 5.
ELECTRICAL DATA S3C 9228/P9228 16- 14 NOTES.
S3C9228/P9228 MECHANICAL DATA 1 7- 1 17 MECHANICAL DATA OVERVIEW The S3C9228/P9228 microcontroller is currently available in a 42-pin SDIP and 44-pin QFP package. NOTE : Dimensions are in millimeters. 39.50 MAX 39.10 ± 0 .2 0.50 ± 0.1 1.78 (1.77) 0.
MECHANICAL DATA S3C9228/P9228 1 7- 2 44-QFP-1010B #44 NOTE : Dimensions are in millimeters. 10.00 ± 0.2 13.20 ± 0.3 10.00 ± 0.2 13.20 ± 0.3 #1 0.35 + 0.10 - 0.05 0.80 (1.00) 0.10 MAX 0.80 ± 0.20 0.05 MIN 2.05 ± 0.10 2.30 MAX 0.15 + 0.10 - 0.05 0-8 Figure 17-2.
S3C9228/P9228 S3P9228 OTP 18- 1 18 S3P9228 OTP OVERVIEW The S3P9228 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C9228 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format.
S3P9228 OTP S3C9228/P9228 18- 2 COM1/P6.2 COM0/P6.3 P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P1.0/AD0/INT P1.1/AD1/INT SDAT /P1.2/AD2/INT SCLK /P1.3/AD3/INT V DD /V DD V SS /V SS X OUT X IN V PP /TEST XT IN XT OUT RESET RESET / RESET P2.3 P2.
S3C9228/P9228 S3P9228 OTP 18- 3 Table 18-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P1.2 SDAT 3 (9) I/O Serial data pin. Output port when reading and input port when writing.
S3P9228 OTP S3C9228/P9228 18- 4 Table 18-4. D.C. Electrical Characteristics (T A = – 25 ° C to + 85 ° C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Supply current (1) I DD1 Run mode: V DD = 5 V ± 10% 8.0 MHz – 6.0 12.0 mA Crystal oscillator C1 = C2 = 22pF 4.
S3C9228/P9228 S3P9228 OTP 18- 5 2 MHz 6.25 kHz (main)/8.2 kHz(sub) 1 2 6 Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) 1.0 MHz Instruction Clock 8 MHz 4 MHz fx (Main/Sub oscillation frequency) 400 kHz 2.7 5.5 400 kHz (main)/32.
S3P9228 OTP S3C9228/P9228 18- 6 NOTES.
S3C9228/P9228 DEVEL OPMENT TOOLS 19- 1 19 DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy-to-use development support system in turn key form. The development support system is configured with a host system, debugging tools, and support software.
DEVELOPMENT TOOLS S3C9228/P9228 19- 2 BUS SMDS2+ RS-232C POD Probe Adapter PROM/OTP Writer Unit RAM Break/Display Unit Trace/Timer Unit SAM8 Base Unit Power Supply Unit IBM-PC AT or Compatible TB9228 Target Board EVA Chip Target Application System Figure 19-1.
S3C9228/P9228 DEVEL OPMENT TOOLS 19- 3 TB9228 TARGET BOARD The TB9228 target board is used for the S3C9228 microcontroller. It is supported by the SMDS2+ development system.
DEVELOPMENT TOOLS S3C9228/P9228 19- 4 Table 19-1. Power Selection Settings for TB9228 "To User_V CC " Settings Operating Mode Comments To User_V CC Off On Target System SMDS2/SMDS2+ TB9228 V CC V SS V CC The SMDS2/SMDS2+ supplies V CC to the target board (evaluation chip) and the target system.
S3C9228/P9228 DEVEL OPMENT TOOLS 19- 5 SMDS2+ Selection (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available.
DEVELOPMENT TOOLS S3C9228/P9228 19- 6 J101 42-SDIP J102 44-QFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 43 44 45 46 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 50 49 48 47 P6.2 P6.3 P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.
S3C9228/P9228 DEVEL OPMENT TOOLS 19- 7 Target Board Target System Target Cable for Connector Part Name: AP42SD Order Code: SM6538 J101 1 42 21 22 J101 1 42 21 22 50-Pin DIP Connector Figure 19-4.
DEVELOPMENT TOOLS S3C9228/P9228 19- 8 NOTES.
デバイスSamsung S3C9228/P9228の購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
Samsung S3C9228/P9228をまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはSamsung S3C9228/P9228の技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Samsung S3C9228/P9228の取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Samsung S3C9228/P9228で得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Samsung S3C9228/P9228を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はSamsung S3C9228/P9228の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Samsung S3C9228/P9228に関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちSamsung S3C9228/P9228デバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
