SiemensメーカーERTEC200の使用説明書/サービス説明書
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Copyright © Siemens AG 2007. All rights reserved. Page 1 ERTEC 200 Manual Technical data subject to change Version 1.1.0 . RTEC 200 E nhanced R eal- T ime E thernet C ontroller E Manual.
Edition (04/2007) Disclaimer of Liabilit y We have checked the contents of this manual for agreement with the hard ware and software described. Since deviations c annot be precluded entirely, we cannot guarantee full agreement. However, the data in this manual are reviewed regularl y.
Preface Target Audience of this Manual This manual is intended for hard ware developers who want to use the ERTEC 200 for new prod ucts. Experi ence working with processors and designin g emb edded syst ems and kno wledge of Ethernet are required for this.
This manual will be updated a s requir ed. You can find t he current version of the m anual on the Internet at http://www.siemens.com/comdec . Guide To help you quickly find the information you need, .
Contents 1 Introduc tion ................................................................................................................... ......... 9 1.1 Applications of the ER TEC 200 ...............................................................
4.4.2 F-Timer Register Descrip tion ................................................................................................... ...... 44 4.5 Watchdog Ti mers ....................................................................................
11.1.3 ETM9 Regi sters ................................................................................................................. ............ 94 11.2 Trace Inte rface ............................................................................
List of Figures Figure 1: ERTEC 200 Block Diagr am .................................................................................................................... 10 Figure 2: ERTEC 200 Packa ge Descr iption ......................................
1 Introduction The ERTEC 200 is intended for the implem en tation of PROF INET devices with RT and IRT functional it y. With its integrated ARM946 process or and 2-port Ethernet s witch with integrate.
1.3 Structure of the ERTEC 200 The figure below sho ws the function groups with the common communication p aths. DMA- Cont rol ler AHB/APB Bridge GPI O Maste r Master P P o r t s 7 APB 50MHz / 32 Bit .
1.4 ERTEC 200 Package The ERTEC 200 is supplied in an FBGA package with 304 pins. The distanc e between the pins is 0.8 mm. T he package dimensions are 19 m m x 19 mm. Figure 2: ERTEC 200 Package Description Soldering instructions for the ERT EC 200 can be found in the foll owing documents: /10/ Soldering instructions for lead -based block.
1.5 Signal Function Description ERTEC 200 Pin Description The ERTEC 200 Ethernet communic ation block is available i n a 304-pin FBGA package. The signal names of the ERTEC 200 are described in this section. 1.5.1 GPIO 0 to 31 and Alternative Function s Various signals are multiple xe d on the same pin.
No. Signal Name Alternative Function 1 Alternative Function 2 Alternative Function 3 I/O (Reset) Pull- PIN No. Comment General Purpose I/O / I/O 23 GPIO22 SPI1_SFRMIN DBGACK B/I/O/(I) up F10 GPIO or SPI1 (I) or Debug (O) This GPIO is used as chip select when booting from Nand Flash or SPI ROM.
1.5.4 Clock and Reset No. Signal Name I/O (Reset) Pull- PIN No. Comment CLOCK / RESET GENERATION 42 CLKP_A I (I) B14 Quartz connection 43 CLKP_B O D14 Quartz connection 44 F_CLK I (I) B13 F_CLK for F-c ounter 45 REF_CLK Dependent on PIN CONFIG[1] A15 Tristate or reference clock output, 25 MHz 46 RESET_N I (I) up B7 PowerOn reset 1.
No. Signal Name Alternative Reset Functio n I/O (Reset) Pull- PIN No. Comment EMIF (External Memory Interface) 66 A13 O (O) G2 Address bit 13 SDRAM: Address 11 67 A14 O (O) G1 Address bit 14 SDRAM: Address 12 68 A15 BOOT1 B (I) dn H2 Address bit 15 ERTEC 200 boot mode (ext.
No. Signal Name Alternative Reset Functio n I/O (Reset) Pull- PIN No. Comment EMIF (External Memory Interface) 109 WR_N O (O) A4 Write strobe 110 RD_N O (O) B5 Read strobe 111 CS_PER0_N O (O) D5 Chip .
No. Function 1 LBU Config (6,5,2)=xx0b Function 2 PHY Debug and GPIO[44:32] Config (6,5,2)=011b Function 3 ETM Trace and GPIO[44:32] Config (6,5,2)=101b Function 4 Reserved [6,5,2]=111b IO (Reset See Config [6,5,2]) Pull - PIN No.
No. Function 1 LBU Config (6,5,2)=xx0b Function 2 PHY Debug and GPIO[44:32] Config (6,5,2)=011b Function 3 ETM Trace and GPIO[44:32] Config (6,5,2)=101b Function 4 Reserved [6,5,2]=111b IO (Reset See Config [6,5,2]) Pull - PIN No.
No. Signal Name I/O Pull- PIN No. Comment PHY1 and PHY2 196 P1SDxN I F19 Port1 FX dif ferential SD input 197 P1SDxP I G19 Port1 FX differential SD input 198 P1TDxN O C22 Port1 FX differential transmit.
Signal description: IO = Signal direction from perspective of the application I: Input O: Output B: Bidirectional P: Power supply Pull- = Internal pull-up/pull-down resistor connected to the signa l p.
2 ARM946E-S Processor The ARM946E-S processor is impleme nted in the ERTEC 200. This description is based on / 1 / and / 2 /. 2.1 Structure of ARM946E-S An ARM946E-S processor system is used.
2.2 Description of ARM946E-S The ARM946E-S processor system is a member of the AR M9 Thumb famil y. It has a processor core with Harvard architecture. Compared to the standard ARM9 famil y, th e ARM946E-S has an enhanc ed V5TE architecture perm itting faster switching between ARM and T humb code segments and an enhanced multi plier stru cture.
2.6 Memory Protection Unit (MPU) The memory protection unit enabl es the user to partition s pecific memory areas (I-cache, D-cache, or DT CM) into various regions and to assign different attrib utes to them. A maximum of 8 regions of variable size can be set.
2.9.1 Prioritization of Interrupts It is possible to set the priorities of the IRQ and FIQ interrupts. Priorities 0 to 15 can be assigned to IRQ interrupts while priorities 0 to 7 can be assigned to FIQ interrupts. T he hig hest priority is 0 for both interru pt levels.
The CPU accepts an IRQ-/FIQ request by reading the IRVEC/F IVEQ register. This register contains the binar y-co ded vector number of the highest priority interrupt request at th e moment. Each of the two interrupt vector registers can be referenced using t wo different addresses.
2.9.9 IRQ Interrupts as FIQ Interrupt Sources Interrupts from the IRQ interrupt can be placed on FIQ6 and FIQ7 können. The interrupts of the FIQ interrupt c ontroller are used for debug ging, monitoring address area acc ess, and for the watchdog. FIQ interrupts no.
PRIOREG 1 0x0074 4 bytes R/W 0x0000000F .... ... ... .... ... ... .... PRIOREG15 0x00AC 4 bytes R/W 0x0000000F Priority register 15 Table 4: Overview of Interrupt Control Register 2.
FIQACK R Addr.: 0x5000_0018 Default: 0xFFFF_FFFF Description Fast interrupt vector register with F IQ acknowledge Confirmation of fast interrupt request by reading the ass ociated interrupt vector Bit No. Name Description 2 – 0 FIVEC Binary code of FIQ number 31 – 3 Vector ID Valid FIQ vector: always ‘1’.
FIQIRR R Addr.: 0x5000_0050 Default: 0x0000_0020 Description FIQ request register Indication of the fast interrupt request detected with a positive edge Bit No. Name Description 7 – 0 FIQIRR Inputs 0 to 7 of the FIQ interru pt controller '0' = No request '1' = Request is occurred FIQ_MASKREG R/W Addr.
SWIRREG R/W Addr.: 0x5000_006C Default: 0x0000_0000 Description Soft ware interrupt register Specification of interrupt requests Bit No. Name Description 15 – 0 SWIRREG Interrupt input 0 to 15 0 =No interrupt request 1=Set interrupt request PRIOREG 0 R/W Addr.
2.10 ARM946E-S Register The ARM946E-S uses CP15 registers for s ystem control. Consequently, the follo wing settings are possible: • Configure cache t ype and cache memory area • Configure tightly.
3 Bus System of the ERTEC 200 Internally, the ERTEC 200 has t wo buses. High-performance communication bus (multilay er AHB bus) I/O bus (A PB bus) The following function blocks are connec ted.
4 I/O on APB bus The ERTEC 200 block has multiple I/O function blocks. They are connected to the 32-bi t APB I/O bus. The ARM946E-S, DMA controller and LBU interface can acces s the I/O.
The following download modes are supp orted: BOOT(3) BOOT(2) BOOT (1) BOOT(0) BOOTING O F 0 0 0 0 External ROM with 8-bit data width 0 0 0 1 External ROM with 16-bit data width 0 0 1 0 External ROM wi.
4.2 General Purpose I/O (GPIO) Up to 45 General Purpose Inputs/Outputs are availab le i n the ERT EC 200. These are divide d into t wo groups: • GPIO[31:0] 32 bits on the APB I/O bus • GPIO[44:32].
4.2.1 Address Assignment of GPIO Regist ers The GPIO registers are 32 bits in width. T he registers ca n be read or written to with 8-bit, 16-bit, or 32-bit accesses.
17:16 GPIO8_PORT_MODE Port GPIO[8]; 19:18 GPIO9_PORT_MODE Port GPIO[9]; 21:20 GPIO10_PORT_MODE Port GPIO[10]; 23:22 GPIO11_PORT_MODE Port GPIO[11]; 25:24 GPIO12_PORT_MODE Port GPIO[12]; 27:26 GPIO13_PORT_MODE Port GPIO[13]; 29:28 GPIO14_PORT_MODE Port GPIO[14]; 31:30 GPIO15_PORT_MODE Port GPIO[15]; GPIO_PORT_MODE_H W/R Addr.
GPIO2_ IN R Addr.: 0x4000_2528 Default: Port assignment Description Input register f o r General Purpose IO [44:32] Bit No. Name Description 31..13 Reserved Reserved 12..0 GPIO2_IN[44:32] 0: GPIO i nputx = 0, 1: GPIO input x = 1 4.3 Timer 0/1/2 Three independent timers are integrate d in t he ERTEC 200.
4.3.1.1 Timer 0/1 Interrupts The timer 0/1 interrupt is active (High) starting from t he point at which the timer value is counted down to 0. The timer interrupt is deactivated (Lo w) when the reload value is automatically reloaded or t he "LOAD“ bit is set by the user.
4.3.3 Address Assignment of Timer Registe rs The timer registers are 32 bits in width. For read/ write acce ss of the timer registers to be meaningful, a 32-bit access is required. However, a byte-by- byte write op eration is not inte rcepted b y the hardware.
CTRL_STAT1 R/W Addr.: 0x4000_2004 Default: 0x0000_0000 Description Control/status register 1. Configuration and c ontrol bits for Timer No. 1. Bit No. Name Description 0 Run/xStop *) Stop/start of timer: 0: Timer is stopped 1: Timer is running Note: If this bit = 0, the timer interrupt is inactive (0) and the status bit (Bit 5) is reset (0).
RELD_PREDIV R/W Addr.: 0x4000_2014 Default: 0x0000_0000 Description Reload re gister for the two prescalers Bit No. Name Description 7:0 Prediv [7:0] Relo ad value of prescaler 0 15:8 Prediv [15:8] Reload va lue of prescaler 1 31-16 Reserved Not relevant (read=0) TIM0 R Addr.
4.4 F-Timer Function An F-timer is integrated in the ERTEC 200 in add ition to the sy stem timers. This timer works independently of the system clock and can be used for fail-safe applicati ons, for example. T he F-timer is triggered via the alternative “F _CLK” functi on at the external “BYP_CLK” inpu t.
4.4.1 Address Assignment of F-Timer Regis ters The F-timer registers are 32 bits in width . The registers can be written to in 32-bit width only . F-Counter (Base Address 0x4000_2700) Register Name Of.
4.5 Watchdog Timers Two watchdog timers are integrated in the E RTEC 200. The wa tchdog tim ers are inte nd ed for stand-alone monitoring of processes. The working clock of 50 MHz is derived fr om the PLL the sam e as the processor clock. 4.5.1 Watchdog Timer 0 Watchdog timer 0 is a 32-bit down-counter to which the WDOUT 0_N outpu t is assigned.
4.5.6 Watchdog Registers The watchdog registers are 32 bits in width. For read/writ e access of the watchdog regis t ers to be mea ningful, a 32-bit access is required. However, a byte-by-byte w rit e operation is not intercept ed by the hardware. To prevent the watchdog registers from being written to inad vertently, e.
RELD0_LOW R/W Addr.: 0x4000_2104 Default: 0x0000_FFFF Description Reload re gister 0_Low. Reload value for bits 15:0 of watchdog counter 0. Bit No. Name Description 15-0 Reload0 [15:0] Reload valu e for bits 15:0 of watchdog counter 0. 31-16 Key bits Ke y bits for writing to this register (read=0).
4.6 UART Interf ace A UART interface is implemented in t he ERT E C 200. T he inputs and outputs of t he UART interface are available as an alternative function at GPIO po rt [12:8]. For this purpose, the I/O must be a ssigned to the relevant inputs and outputs and the alternative function must be assigned (see GPIO register description).
The baud rate generation is d erived from the internal 50 MHz APB clock. The resulting deviatio ns from the standard baud rates used are so small that a secure data transmissio n is achieved.
4.6.2 UART Register Description UARTDR R/W Addr.: 0x4000_2300 Default: 0x-- Description UART data registers Bit No. Name Description 7 – 0 ------- WRITE: - If FIFO is enabled, the written data are entered in t he FIFO. - If FIFO is disabled, the written data ar e entered in the Transmit holdi ng register (the first word in the Transmit FIFO).
UARTLCR_H R/W Addr.: 0x4000_2308 Default: 0x00 Description UART line cont rol register high byte bit rate and control reg ister bits 22 to 16 Bit No. Name Description 0 BRK Send break = 1 A LOW level is sent continuously at the Transmit output. 1 PEN Parity enable = 1 Parity check and gener ation are enabled.
UARTCR R/W Addr.: 0x4000_2314 Default: 0x00 Description UART control registers Bit No. Name Description 0 UART EN UART Enable = 1 UART sending/receiv in g of data is enabled 1 SIREN SIR enable = 1 IrDA SIR Endec is ena bled.
UARTIIR/UARTICR R/W Addr.: 0x4000_231C Default: 0x00 Description UART interrupt i dentificatio n register (read) UART interrupt clear register (write) Bit No. Name Description 0 MIS (Read) Modem Interru pt Status This bit is set if UARTMSINTR is active.
4.7 Synchronous Interface SPI An SPI interface is implemented in the ERTEC 200. T he inpu ts and outputs of the SPI inte rface are avai labl e as an alternative function at GPIO po rt [23:16].
For the synchronous clock out put of the SPI interface, the following frequencies ar e calculated acc ording to the assigned SPI registers: 50 MHz SCLKOUT = ----------------------------- CPSDRV * (1+S.
4.7.2 SPI Register Description SSPCR0 R/W Addr.: 0x4000_2200 Default: 0x0000 Description Control register 0. Configur ation frame format and baud rate for SPI.
15-7 ------- Reserved Read: Value is undefined Write: Should always be written with zero SSPDR R/W Addr.: 0x4000_2208 Default: 0x---- Description SPI data register Bit No.
SSPIIR/SSPICR R/W Addr.: 0x40 00_2214 Default: 0x0000 Description SPI interrupt i dentification register (read) SPI interrupt clear register (write) Bit No.
UART_CLK 0x0070 4 bytes R/W 0x00000000 UART clock selection 50MHz/6MHz Table 16: Over view of System Control Re gisters 4.8.2 System Control Register Description ID_REG R Addr.: 0x4000_2600 Default: 0x4027_0100 Description Identificati on of ERTEC 200.
PLL_STAT_REG R/W Addr.: 0x4000_2614 Default: 0x0007_0005 Description Status register for PLL of ERTEC 200 a nd i nterrupt control for FIQ3 Bit No. Name Description 31.
QVZ_AHB_M R Addr.: 0x4000_2630 Default: 0x0000_0000 Description Master identifie r of an incorrect addressing on the multila yer AHB Bit No. Name Description 31:4 Reserved Reserved 3 QVZ_AHB_DMA DMA 2 QVZ_AHB_IRT IRT 1 QVZ_AHB_LBU LBU 0 QVZ_AHB_ARM946 ARM946 QVZ_APB_ADR R Addr.
ARM9_CTRL R/W Addr.: 0x4000_2650 Default: 0x0000_1939 Description Check of ARM 9 inp uts that ar e not accessible from exter nal pins. This register can only be w ritten to if th e Write enable bit is set in the ARM9_WE register. T his register can only be changed for debuggin g purposes! Bit No.
12:10 P2_PHY_MODE 000: 10BASE-T HD, Auto-Neg disabled 001: 10BASE-T FD, Auto-Neg disable d 010: 100BASE-TX/FX HD, Auto-Neg dis abled 011: 100BASE-TX/FX FD, Auto-Neg disabl ed 100: 100BASE-TX HD annou .
5 General Hardw are Functions 5.1 Clock Generation and Clock Supply The clock system of the ERTEC 200 basically consists of f our clock systems that are decoup led through asynchr onous transfers.
5.1.2 JTAG Clock Supply The clock supply for the JTAG interface is im plem ented using the JT AG_CLK pin. The frequency range i s between 0 and 10 MHz. The boundar y s can and the ICE macro cell of the ARM946E -S are enabled via the JT AG interface. 5.
f/MHz t/µs t LOCK = 645 µs 35 Power- up PLL a c t i v e R e s e t 300 Figure 11: Pow er-Up Phase of the PLL The lock status of the PLL is monitored by the hard ware. Loss of the input cl ock and PLL not locked status is signale d with interrupt FIQ3.
5.3 Address Sp Monitoring mechan egal accesses, and timeout. The followi • AHB bus • APB bus • EMIF 5.3.1 AHB Bus Mo Separate address space mo DMA, LBU).
Config [6] Config [5] Config [4] Config [3] Config [2] Config [1] Meaning - - - - - 1 REF_CLK tristate - - - - - 0 REF_CLK output (25 MHz) - 1 - - 0 - LBU = On, LBU-CFG: LBU_WR_N has read/write contro.
6 External Memor y Interface (EMIF) In order to access an external memory area, an E xternal M emory I nter F ace is incorp orated in the ERTEC 200. The interface contains one SDRAM memor y controller and one SR AM memory control eac h for asynchronous memor y and I/O.
6.1 Address Assignment of EMIF Registers The EMIF registers are 32 bits in width . These registers can only be written to with double words. EMIF (Base Address 0x7000_0 000) Register Name Offset Addre.
SDRAM Bank Config W/R Addr.: 0x7000_0008 Default: 0x0000_20A0 Description SDRAM bank config re gister Bit No. Name Description 31..14 Reserved Reserved 13* CL CAS latency 0: SDRAM is activated with CAS latency = 2 1: SDRAM is activated with CAS latency = 3 12.
Async Bank 0 Config W/R Addr.: 0x7000_0010 Default: 0x3FFF_FFF2 Async Bank 1 Config W/R Addr.: 0x7000_0014 Default: 0x3FFF_FFF2 Async Bank 2 Config W/R Addr.
Extended Config W/R Addr.: 0x7000_0020 Default: 0x0303_0000 Description Setting of addit ional functionalities Bit No. Name Description 31 Reserved Reserved 30 T EST_1 Test Mode 1 0: 200 µs delay aft.
7 Local Bus Unit (LBU). The ERTEC 200 can also be operate d from an external host pr ocessor. The LBU bus i nte rfaces are ava ilable for this purpose: The bus system is selected using the CONFIG[2] input pin.
The four segments are addressed vi a the t wo LBU_SEG[1:0] inputs. LBU_SEG[1 : 0] Addressed Segment 00 LBU_PAGE0 01 LBU_PAGE1 10 LBU_PAGE2 11 LBU_PAGE3 Copyright © Siemens AG 2007. All rights reserved. 75 ERTEC 200 Manual Technical data subject to change Version 1.
7.1 Page Range Setting The page size of each page is set in the PAGEx_RANGE_H IGH and PAGEx_RANGE_LOW range registers (x = 0 to 3). Together, the two page range registers yield a 32-bit addres s register. The size of the page varies bet ween 256 bytes and 2 MBytes.
7.3 LBU Address Mapping The following table illustrates an e xampl e of the ERTEC 200 Address Ma pping from the Perspective of an External H os t Processor: Seg(1:0) AD(19: 0) SEGMENT Distribution SEG.
7.4 Page Control Setting The user can use the page control reg ister to set the type of access to the relevant page. Certain areas of the ERTEC 200 must be implemented with a 32-bit data access in ord er to ensure data consistency. For other areas, an 8-bit or 16- bit data access is permitted.
7.5.1 LBU Read from ERTEC 200 w ith separa te Read/Write line (LB U_RDY_N activ e lo w) LBU_CS_R_N/ LBU_CS_M_N LBU_RD_N LBU_A(2 0:0)A/ LBU_SEG (1:0)/ LBU_BE (1:0 )_N LBU_RDY_N LBU_D(15:0) t CSRS t ARS.
7.5.2 LBU Write to ERTEC 200 with separa t e Read/ Write line (LBU_RDY_N active lo w) LBU_CS_R_N/ LBU_CD_M_N LBU_WR_N LBU_A(20:0)/ LBU_SEG(1:0) LBU_BE(1:0)_N LBU_RDY_N LBU_D(15:0) t CSW S t AW S t WR .
7.5.3 LBU Read from ERTEC 200 w ith common Read/Write line (LBU_ RDY_ N active low) LBU_CS_R _N/ LBU_CS _M_N LBU_W R LBU_A(20:0) / LBU_SEG (1:0)/ LBU_BE (1:0 )_N LBU_RD Y LBU_D(15: 0) t WC S t ACS t C.
7.5.4 LBU Write to ERTEC 200 with common Read/ Write line (LBU_RDY_N active low) LBU_CS_R_ N/ LBU_CS _M_N LBU_W R_N LBU_A(2 0:0)/ LBU_SEG (1:0)/ LBU_BE(1:0)_N LBU_RD Y LBU_D(15: 0) t WC S t ACS t CRE .
7.7 Address Assignment of LBU Registers The LBU registers are 16 bits in width . These registers can only be written to with words. The LBU pagi ng configuration registers are addressed via the "LBU _CS_R_N” input.
LBU_P0_RG_H W/R Addr.: LBU_CS_R_ N+0x02 Default: 0x0000_0001 (64k ) LBU_P1_RG_H W/R Addr.: LBU_CS_R_ N+0x1 2 Default: 0x0000_0010 (1M) LBU_P2_RG_H W/R Addr.: LBU_CS_R_ N+0x2 2 Default: 0x0000_0020 (2M) LBU_P3_RG_H W/R Addr.: LBU_CS_R_ N+0x3 2 Default: 0x0000_0000 (2 k) Description High word of LBU Pagex_Range_register Bit No.
8 DMA-Controller The ERTEC 200 has a 1-channel DMA co ntroller. T his enables da ta to be transferred without placi ng an additional load on the ARM946E-S.
8.1 DMA Register Address Assignment The DMA registers are 32 bits in width . The registers can be written to with 32-bit accesses only. Only the ARM946E- S processor can access the registers.
(DMAC0ConfReg) Channel Config (*) W/R Addr.: 0x8000_000C Default: 0x0000_0000 Description Control Bits. 31 START/ABORT Write: 0: Stop Transfer 1: Start Transfer Read: 0: Transfer completed or stopped 1: Transfer not yet complete 30 Reserved Reserv ed 29 INTR_ENABLE (****) 1: Enable interrupt 28.
9 Multiport Ethernet PHY A 2-fold multiport PHY (Physical Layer T ransceiver) that supports the following transfer modes is integrated in th e ERTEC 200: • 10BASE-T • 100BASE-TX • 100BASE-FX These transfer modes are availab le separat ely for eac h port and can be set differently.
• P1/2_PHYADDRESS 4..0 Port1 = 00000b; Port2 = 00001b • P1/2_PHYMODE 2..0 see PHY_CONFIG in the SYSTEM-CONT ROL register area • P1/2_MIIMODE 1..0 MII-Interface (permanently set) • P1/2_SMIISOU.
Power-State is approximately 15 mW per PHY. The Lo w-Power-Mode is exited again with Link-Pulses or Packets on the MII interface. The digital modes are reinitiali zed, but the configur ation is not saved again.
10 Memory Description This section presents a detailed descriptio n of t he memory areas of all integrated function groups. 10.1 Memory Partitioning of the ERTEC 200 The table below lists the AHB masters alon g with th eir options for accessing various memory areas.
10.2 Detailed Memory Description The table below prese nts a detailed de scription of the mem ory segments. Mirrored segments should not be used for addressing to ensure compat ible memory expansion at a later date.
Segment Contents Größe A dressbereich Beschreibung 5 ARM-ICU 256 MB 5000_0000- 5FFF_FFFF ARM – Interrupt-Controller 128 Byte physical Note2 6 Not used 256 MB 600 0_0000- 6FFF_FFFF 7 EMIF-Register .
11 Test and Debugging 11.1 ETM9 Embedded Trace Macrocell An ETM9 module is integrated in the ARM9 46E-S of t he ERT EC 200 to enable the instruction code and data to be traced. The ARM946E-S supplies the ET M module with the sign als needed to carr y out the trace functions.
11.2 Trace Interface The trace interface is paramet erize d, enabled, and disabled b y means of a connecte d de bugger (e.g. by Lauterbach) on the JTAG interface.
12 Miscellaneous 12.1 Acronyms/Glossary: AHB AM B A A dvanc ed H igh Performance B us (Multimaster, Bursts) AMB A A dvanced M icrocontroller B us A rchitecture APB AMB A A dvanced P eriph eral B us (S.
12.2 References: /1/ Technical Reference Manual ARM946E-S REV1 16 February 2001 (DDI 0201A_946ES.PDF ); /2/ Technical Reference Manu al ARM946E-S 16 December 1999 (DDI_ 0165 A_9E-S_TRM. PDF); /3/ AHB PCI Bridge Revision2.5 08 July 2002 (amba2pci_r e v2.
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