Texas InstrumentsメーカーTMS320C2XXの使用説明書/サービス説明書
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TMS320C2xx User ’ s Guide Literature Number: SPRU127B Manufacturing Part Number: D412008-9761 revision A January 1997 Printed on Recycled Paper.
IMPORT ANT NOTICE T exas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify , before placing orders, that the information being relied on is current.
How to Use This Manual iii Preface Read This First About This Manual This user ’s guide describes the architecture, hardware, assembly language instructions, and general operation of the TMS320C2xx digital signal processors (DSPs). This manual can also be used as a reference guide for developing hardware and/or software applications.
How to Use This Manual iv For this information: Look here: Addressing modes (for addressing data memory) Chapter 6, Addressing Modes Assembly language instructions Chapter 7, Assembly Language Instruc.
Notational Conventions/Information About Cautions v Read This First Notational Conventions This document uses the following conventions: Program listings and program examples are shown in a special typeface .
Related Documentation From T exas Instruments vi Related Documentation From T exas Instruments This subsection describes related TI documents that can be ordered by calling the T exas Instruments Literature Response Center at (800) 477–8924. When ordering, please identify the document by its title and literature number .
Related Documentation From T exas Instruments vii Read This First TMS320C2xx Simulator Getting Started (literature number SPRU137) describes how to install the TMS320C2xx simulator and the C source debugger for the ’C2xx. The installation for MS-DOS , PC-DOS , SunOS , Solaris , and HP-UX systems is covered.
Related Articles viii Related Articles “A Greener World Through DSP Controllers”, Panos Papamichalis, DSP & Multimedia T echnology , September 1994. “A Single-Chip Multiprocessor DSP for Image Processing—TMS320C80”, Dr . Ing. Dung T u, Industrie Elektronik , Germany , March 1995.
Related Articles ix Read This First “Fixed or Floating? A Pointed Question in DSPs”, Jim Larimer and Daniel Chen, EDN , August 3, 1995. “Function-Focused Chipsets: Up the DSP Integration Core”, Panos Papamichalis, DSP & Multimedia T echnology , March/April 1995.
T rademarks x Trademarks TI, 320 Hotline On-line, XDS510, XDS510PP , XDS510WS, and XDS51 1 are trademarks of T exas Instruments Incorporated. HP-UX is a trademark of Hewlett-Packard Company . Intel is a trademark of Intel Corporation. MS-DOS and Windows are registered trademarks of Microsoft Corporation.
If Y ou Need Assistance xi Read This First If Y ou Need Assistance. . . World-W ide Web Sites TI Online http://www .ti.com Semiconductor Product Information Center (PIC) http://www .ti.com/sc/docs/pic/home.htm DSP Solutions http://www .ti.com/dsps 320 Hotline On-line http://www .
Contents xiii Contents 1 Introduction 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summarizes the features of the TMS320 family of products and presents typical applications.
Contents xiv 3 Central Processing Unit 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the TMS320C2xx CPU. Includes information about the central arithmetic logic unit, the accumulator , the shifters, the multiplier , and the auxiliary register arithmetic unit.
Contents xv Contents 5 Program Control 5-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the TMS320C2xx hardware and software features used in controlling program flow , including program-address generation logic and interrupts.
Contents xvi 6.3 Indirect Addressing Mode 6-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Current Auxiliary Register 6-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents xvii Contents 9 Synchronous Serial Port 9-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the operation and control of the TMS320C2xx on-chip synchronous serial port.
Contents xviii 10.3 Controlling and Resetting the Port 10-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Asynchronous Serial Port Control Register (ASPCR) 10-7 . . . . . . . . . . . . . . . . . . . . 10.
Contents xix Contents D Submitting ROM Codes to TI D-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Explains the process for submitting custom program code to TI for designing masks for the on-chip ROM on a TMS320 DSP .
Figures xx Figures 1–1 TMS320 Family 1-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Overall Block Diagram of the ’C2xx 2-2 . . . . . . . . . . . . . . . . . .
Figures xxi Contents 5–5 INT2/INT3 Request Flow Chart 5-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6 Maskable Interrupt Operation Flow Chart 5-20 . . . . . . . . . . . . . . . . . . . . . .
Figures xxii 1 1–2 ’C209 Interrupt Flag Register (IFR) — Data-Memory Address 0006h 1 1-12 . . . . . . . . . . . . . . . 1 1–3 ’C209 Interrupt Mask Register (IMR) — Data-Memory Address 0004h 1 1-13 . . . . . . . . . . . . . 1 1–4 ’C209 T imer Control Register (TCR) — I/O Address FFFCh 1 1-15 .
T ables xxiii Contents T ables 1–1 T ypical Applications for TMS320 DSPs 1-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 ’C2xx Generation Summary 1-5 . . . . . . . . . . . . . . . . . . . . . . . . .
T ables xxiv 9–1 SSP Interface Pins 9-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2 Run and Emulation Modes 9-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Examples xxv Contents Examples 4–1 An Interrupt Service Routine Supporting INT1 and HOLD 4-28 . . . . . . . . . . . . . . . . . . . . . . . . . 6–1 RPT Instruction Using Short-Immediate Addressing 6-2 . . . . . . . . . . . . . . . . . . . . . . . .
Notes, Cautions, and Warnings xxvi Cautions Obtain the Proper T iming Information 4-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Do Not Write to T est/Emulation Addresses 4-8 . . . . . . . . .
1-1 Introduction Introduction The TMS320C2xx (’C2xx) is one of several fixed-point generations of DSPs in the TMS320 family . The ’C2xx is source-code compatible with the TMS320C2x. Much of the code written for the ’C2x can be reassembled to run on a ’C2xx device.
TMS320 Family 1-2 1.1 TMS320 Family The TMS320 family consists of fixed-point, floating-point, and multiprocessor digital signal processors (DSPs). TMS320 DSPs have an architecture de- signed specifically for real-time signal processing.
TMS320 Family 1-3 Introduction Figure 1–1. TMS320 Family Performance.
TMS320 Family 1-4 1.1.2 T ypical Applications for the TMS320 Family T able 1–1 lists some typical applications for the TMS320 family of DSPs. The TMS320 DSPs offer adaptable approaches to traditional signal-processing problems such as filtering and vocoding.
TMS320C2xx Generation 1-5 Introduction 1.2 TMS320C2xx Generation T exas Instruments uses static CMOS integrated-circuit technology to fabricate the TMS320C2xx DSPs.
Key Features of the TMS320C2xx 1-6 1.3 Key Features of the TMS320C2xx Key features on the various ’C2xx devices are: Speed: 50-, 35-, or 25-ns execution time of a single-cycle instruction 20, 28.
Key Features of the TMS320C2xx 1-7 Introduction Instruction set: Single-instruction repeat operation Single-cycle multiply/accumulate instructions Memory block move instructions for better program/dat.
2-1 Architectural Overview Architectural Overview This chapter provides an overview of the architectural structure and compo- nents of the ’C2xx. The ’C2xx DSPs use an advanced, modified Harvard archi- tecture that maximizes processing power by maintaining separate bus struc- tures for program memory and data memory .
2-2 Figure 2–1. Overall Block Diagram of the ’C2xx Program control PRDB PRDB DRDB DRDB DWEB DRAB DW AB PA B DWEB Stack 8 × 16 MUX MST ACK PA R NP AR MUX PC ROM/flash SARAM DARAM B0 DARAM B1, B2 S.
’C2xx Bus Structure 2-3 Architectural Overview 2.1 ’C2xx Bus Structure Figure 2–2 shows a block diagram of the ’C2xx bus structure. The ’C2xx inter- nal architecture is built around six 16-bit buses: P AB. The program address bus provides addresses for both reads from and writes to program memory .
’C2xx Bus Structure 2-4 Figure 2–2. Bus Structure Block Diagram B0 DARAM ROM/ flash SARAM B1, B2 DARAM Memory mapped registers PA B DRAB DW AB PRDB DRDB DWEB Control bus External signals Memory co.
Central Processing Unit 2-5 Architectural Overview 2.2 Central Processing Unit The CPU is the same on all the ’C2xx devices. The ’C2xx CPU contains: A 32-bit central arithmetic logic unit (CALU) A.
Central Processing Unit 2-6 2.2.3 Multiplier The on-chip multiplier performs 16-bit × 16-bit 2s-complement multiplication with a 32-bit result. In conjunction with the multiplier , the ’C2xx uses the 16-bit temporary register (TREG) and the 32-bit product register (PREG).
Memory and I/O Spaces 2-7 Architectural Overview 2.3 Memory and I/O Spaces The ’C2xx memory is organized into four individually selectable spaces: pro- gram, local data, global data, and I/O.
Memory and I/O Spaces 2-8 CPU reads data on the third cycle and writes data on the fourth cycle. However , DARAM allows the CPU to write and read in one cycle; the CPU writes to DARAM on the master phase of the cycle and reads from DARAM on the slave phase.
Memory and I/O Spaces 2-9 Architectural Overview 2.3.4 Flash Memory Some of the ’C2xx devices feature on-chip blocks of flash memory , which is electronically erasable and programmable, and non-volatile. Each block of flash memory will have a set of control registers that allow for erasing, pro- gramming, and testing of that block.
Program Control 2-10 2.4 Program Control Several features provide program control: The program controller of the CPU decodes instructions, manages the pipeline, stores the status of operations, and decodes conditional opera- tions.
On-Chip Peripherals 2-1 1 Architectural Overview 2.5 On-Chip Peripherals All the ’C2xx devices have the same CPU, but different on-chip peripherals are connected to their CPUs.
On-Chip Peripherals 2-12 2.5.5 General-Purpose I/O Pins The ’C2xx has pins that provide general-purpose input or output signals. All ’C2xx devices have a general-purpose input pin, BIO , and a general-purpose output pin, XF .
Scanning-Logic Circuitry 2-13 Architectural Overview 2.6 Scanning-Logic Circuitry The ’C2xx has JT AG scanning-logic circuitry that is compatible with IEEE Standard 1 149.
3-1 Central Processing Unit This chapter describes the main components of the central processing unit (CPU). First, this chapter describes three fundamental sections of the CPU (see Figure 3–1): Inp.
3-2 Figure 3–1. Block Diagram of the Input Scaling, Central Arithmetic Logic, and Multiplication Sections of the CPU 32 Input shifter (32 bits) 16 32 Output shifter (32 bits) 32 C Accumulator CALU 3.
Input Scaling Section 3-3 Central Processing Unit 3.1 Input Scaling Section A 32-bit input data-scaling shifter (input shifter) aligns a 16-bit value coming from memory to the 32-bit CALU. This data alignment is necessary for data- scaling arithmetic as well as aligning masks for logical operations.
Input Scaling Section 3-4 Shift count . The shifter can left-shift a 16-bit value by 0 to 16 bits. The size of the shift (or the shift count) is obtained from one of two sources: A constant embedded in the instruction word.
Multiplication Section 3-5 Central Processing Unit 3.2 Multiplication Section The ’C2xx uses a 16-bit × 16-bit hardware multiplier that can produce a signed or unsigned 32-bit product in a single machine cycle.
Multiplication Section 3-6 Inputs . The multiplier accepts two 16-bit inputs: One input is always from the 16-bit temporary register (TREG). The TREG is loaded before the multiplication with a data-value from the data read bus (DRDB). The other input is one of the following: A data-memory value from the data read bus (DRDB).
Multiplication Section 3-7 Central Processing Unit T able 3–1. Product Shift Modes for the Product-Scaling Shifter PM Shift Comments 00 no shift Product sent to CALU or data write bus (DWEB) with no.
Central Arithmetic Logic Section 3-8 3.3 Central Arithmetic Logic Section Figure 3–6 shows the main components of the central arithmetic logic section, which are: The central arithmetic logic unit (CALU), which implements a wide range of arithmetic and logic functions.
Central Arithmetic Logic Section 3-9 Central Processing Unit 3.3.1 Central Arithmetic Logic Unit (CALU) The central arithmetic logic unit (CALU), implements a wide range of arithme- tic and logic functions, most of which execute in a single clock cycle.
Central Arithmetic Logic Section 3-10 Status bits . Four status bits are associated with the accumulator: Carry bit (C). C (bit 9 of status register ST1) is affected during: Additions to and subtractions from the accumulator: C = 0 When the result of a subtraction generates a borrow .
Central Arithmetic Logic Section 3-1 1 Central Processing Unit 3.3.3 Output Data-Scaling Shifter The output data-scaling shifter (output shifter) has a 32-bit input connected to the 32-bit output of the accumulator and a 16-bit output connected to the data bus.
Auxiliary Register Arithmetic Unit (ARAU) 3-12 3.4 Auxiliary Register Arithmetic Unit (ARAU) The CPU also contains the auxiliary register arithmetic unit (ARAU), an arith- metic unit independent of the central arithmetic logic unit (CALU).
Auxiliary Register Arithmetic Unit (ARAU) 3-13 Central Processing Unit The eight auxiliary registers (AR7–AR0) provide flexible and powerful indirect addressing. Any location in the 64K data memory space can be accessed us- ing a 16-bit address contained in an auxiliary register .
Auxiliary Register Arithmetic Unit (ARAU) 3-14 execute phase of the pipeline. For information on the operation of the pipeline, see Section 5.2 on page 5-7. In addition to using the auxiliary registers to reference data-memory address- es, you can use them for other purposes.
Status Registers ST0 and ST1 3-15 Central Processing Unit 3.5 Status Registers ST0 and ST1 The ’C2xx has two status registers, ST0 and ST1, which contain status and control bits. These registers can be stored into and loaded from data memory , thus allowing the status of the machine to be saved and restored for subrou- tines.
Status Registers ST0 and ST1 3-16 T able 3–2. Bit Fields of Status Registers ST0 and ST1 Name Description ARB Auxiliary register pointer buffer . Whenever the auxiliary register pointer (ARP) is loaded, the pre- vious ARP value is copied to the ARB, except during an LST (load status register) instruction.
Status Registers ST0 and ST1 3-17 Central Processing Unit T able 3–2. Bit Fields of Status Registers ST0 and ST1 (Continued) Name Description OVM Overflow mode bit. OVM determines how overflows in the CALU are handled. The SETC and CLRC instructions set and clear this bit, respectively .
4-1 Memory and I/O Spaces Memory and I/O Spaces This chapter describes the ’C2xx memory configuration options and the ad- dress maps of the individual ’C2xx devices. It also illustrates typical ways of interfacing the ’C2xx with external memory and external input/output (I/O) devices.
Overview of the Memory and I/O Spaces 4-2 4.1 Overview of the Memory and I/O Spaces The ’C2xx address map is organized into four individually selectable spaces: Program memory (64K words) contains the instructions to be executed, as well as data used during program execution.
Overview of the Memory and I/O Spaces 4-3 Memory and I/O Spaces 4.1.1 Pins for Interfacing to External Memory and I/O Spaces The pins for interfacing to external memory and I/O space, described in T able 4–1, are of four main types: External buses. Sixteen signals (A15–A0) are available for passing an address from the ’C2xx to another device.
Overview of the Memory and I/O Spaces 4-4 T able 4–1. Pins for Interfacing With External Memory and I/O Spaces (Continued) Description Pin(s) Read/write signals R/W Read/write pin. This pin indicates the direction of transfer between the ’C2xx and external program, data, or I/O space.
Program Memory 4-5 Memory and I/O Spaces 4.2 Program Memory Program-memory space holds the code for applications; it can also hold table information and constant operands. The program-memory space addresses up to 64K 16-bit words. Every ’C2xx device contains a DARAM block B0 that can be configured as program memory or data memory .
Program Memory 4-6 Figure 4–1. Interface With External Program Memory A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A1 1 A12 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D1 1 D12 D13 D14 D15 PS RD WE A0 A1 A2 A3 A4 A5 A6 .
Local Data Memory 4-7 Memory and I/O Spaces 4.3 Local Data Memory The local data-memory space addresses up to 64K 16-bit words. Every ’C2xx device has three on-chip DARAM blocks: B0, B1, and B2. Block B0 has 256 words that are configurable as either data locations or program locations.
Local Data Memory 4-8 4.3.1 Data Page 0 Address Map T able 4–2 shows the address map of data page 0 (addresses 0000h–007Fh). Note the following: Three memory-mapped registers can be accessed with .
Local Data Memory 4-9 Memory and I/O Spaces 4.3.2 Interfacing With External Local Data Memory While the ’C2xx is accessing the on-chip local data-memory blocks, the exter- nal memory signals DS and STRB are in high impedance.
Local Data Memory 4-10 Figure 4–3. Interface With External Local Data Memory A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A1 1 A12 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D1 1 D12 D13 D14 D15 DS RD WE A0 A1 A2 A3 A4.
Global Data Memory 4-1 1 Memory and I/O Spaces 4.4 Global Data Memory Addresses in the upper 32K words (8000h–FFFFh) of local data memory can be used for global data memory . The global memory allocation register (GREG) determines the size of the global data-memory space, which is be- tween 256 and 32K words.
Global Data Memory 4-12 As an example of configuring global memory , suppose you want to designate 8K addresses as global addresses. Y ou would write the 8-bit value 1 1 100000 2 to the eight LSBs of the GREG (see Figure 4–4). This would designate ad- dresses E000h–FFFFh of data memory as global data addresses (see Figure 4–5).
Global Data Memory 4-13 Memory and I/O Spaces toggled between local memory and global memory . For example, in the system of Figure 4–6, when GREG = XXXXXXXX00000000 2 (no global memory), the local data RAM is fully accessible; when GREG = XXXXXXXX10000000 2 (all global memory), the local data RAM is not accessible.
Boot Loader 4-14 4.5 Boot Loader This section applies to ’C2xx devices that have an on-chip boot loader . The boot loader is used for booting software from an 8-bit external ROM to a 16-bit external RAM at reset (see Figure 4–7). The source for your program is an ex- ternal ROM located in external global data memory .
Boot Loader 4-15 Memory and I/O Spaces 4.5.2 Connecting the EPROM to the Processor T o map the EPROM into the global data space at address 8000h, make the following connections between the processor and the EPROM (refer to Figure 4–8): Connect the address lines of the processor and the EPROM (see lines A14–A0 in the figure).
Boot Loader 4-16 4.5.3 Programming the EPROM T exas Instruments fixed-point development tools provide the utilities to gener- ate the boot ROM code. (For an introduction to the procedure for generating boot loader code, see Appendix C, Program Examples .
Boot Loader 4-17 Memory and I/O Spaces Figure 4–9 shows how to store a 16-bit program into the 8-bit EPROM. A sub- script h (for example, on Word1 h ) indicates the high-byte and a subscript l (for example, on Word1 l ) indicates the low byte. Figure 4–9.
Boot Loader 4-18 4.5.5 Boot Loader Execution Once the EPROM has been programmed and installed, and the boot loader has been enabled, the processor automatically boots the program from EPROM at startup. If you need to reboot the processor during operation, bring the RS pin low to cause a hardware reset.
Boot Loader 4-19 Memory and I/O Spaces Figure 4–10. Program Code T ransferred From 8-Bit EPROM to 16-Bit RAM 8-Bit EPROM 16-Bit RAM Address 7 0 Address 15 8 7 0 8000h Destination h = 00h 0000h Word1 h W ord1 l 8001h Destination l = 00h • Word2 h W ord2 l 8002h Length N h •• .
Boot Loader 4-20 Figure 4–1 1. Interrupt V ectors T ransferred First During Boot Load 8000h 8-bit EPROM in global data memory 16-bit RAM in program memory 0000h 003Fh 8001h Destination h (00) Destin.
Boot Loader 4-21 Memory and I/O Spaces 4.5.6 Boot Loader Program ********************************************************************************* * TMS320C2xx Boot Loader Program * * * * This code se.
Boot Loader 4-22 * * Transfer code * LOOP LACC *+,8 ; Load ACC with high byte of code shifted by 8 bits SACL HBYTE ; Store high byte LACL *+,AR0 ; Load ACC with low byte of code AND #0FFH ; Mask off u.
I/O Space 4-23 Memory and I/O Spaces 4.6 I/O Space The ’C2xx supports an I/O address range of 64K 16-bit words. Figure 4–12 shows the ’C2xx I/O address map.
I/O Space 4-24 The map has three main sections of addresses: Addresses 0000h–FEFFh allow access to off-chip peripherals typically used in DSP applications, such as digital-to-analog and analog-to-digital converters. Addresses FF00h–FF0Fh are mapped to on-chip I/O space.
I/O Space 4-25 Memory and I/O Spaces 4.6.1 Accessing I/O Space All I/O words (external I/O ports and on-chip I/O registers) are accessed with the IN and OUT instructions. Accesses to external parallel I/O ports are multi- plexed over the same address and data buses for program and data-memory accesses.
I/O Space 4-26 Figure 4–13. I/O Port Interface Circuitry A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7 IS WE 1 2 3 6 4 5 18 16 14 12 9 7 5 3 3 4 7 8 13 14 17 18 11 1 5 V A B C G1 G2A G2B Y0 Y1 Y2 Y3 Y4 Y5 Y6 .
Direct Memory Access Using the HOLD Operation 4-27 Memory and I/O Spaces 4.7 Direct Memory Access Using the HOLD Operation The ’C2xx HOLD operation allows direct-memory access to external program, data, and I/O spaces. The process is controlled by two signals: HOLD.
Direct Memory Access Using the HOLD Operation 4-28 Example 4–1. An Interrupt Service Routine Supporting INT1 and HOLD .mmregs ;Include c2xx memory–mapped registers. ICR .set 0FFECh ;Define interrupt control register in I/O space. ICRSHDW .set 060h ;Define ICRSHDW in scratch pad location.
Direct Memory Access Using the HOLD Operation 4-29 Memory and I/O Spaces Here are three valid methods for exiting the IDLE state, thus deasserting HOLDA and restoring the buses to normal operation: Cause a rising edge on the HOLD/INT1 pin when MODE = 0.
Direct Memory Access Using the HOLD Operation 4-30 Figure 4–15. Reset Deasserted Before HOLD Deasserted RS HOLD HOLDA Direct Memory Access Using the HOLD Operation.
Device-Specific Information 4-31 Memory and I/O Spaces 4.8 Device-Specific Information For ’C2xx devices other than the ’C209, this section mentions the presence or absence of the boot loader and HOLD features, shows address maps, and explains the contents and configuration of the program-memory and data- memory maps.
Device-Specific Information 4-32 Figure 4–16. ’C203 Address Map FFFFh ’C203 Program ’C203 Data FFFFh 0800h 0400h 03FFh 0300h 02FFh 0200h 01FFh 0080h 007Fh 0060h 005Fh 0000h External DARAM B1 .
Device-Specific Information 4-33 Memory and I/O Spaces DARAM blocks B1 and B2 are fixed, but DARAM block B0 may be mapped to program space or data space, depending on the value of the CNF bit (bit 12 of status register ST1): CNF = 0. B0 is mapped to data space and is accessible at data addresses 0200h–02FFh.
Device-Specific Information 4-34 T able 4–6. ’C203 Data-Memory Configuration Options CNF DARAM B0 (hex) DARAM B1 (hex) DARAM B2 (hex) External (hex) Reserved (hex) 0 0200–02FF 0300–03FF 0060–007F 0800–FFFF 0000–005F 0080–01FF 0400–07FF 1 – 0300–03FF 0060–007F 0800–FFFF 0000–005F 0080–02FF 0400–07FF 4.
Device-Specific Information 4-35 Memory and I/O Spaces Figure 4–17. ’C204 Address Map FFFFh ’C204 Program ’C204 Data FFFFh 0800h 0400h 03FFh 0300h 02FFh 0200h 01FFh 0080h 007Fh 0060h 005Fh 000.
Device-Specific Information 4-36 Y ou select or deselect the ROM by changing the level on the MP/MC pin at re- set: MP/MC = 0 at reset. The device is configured as a microcomputer . The on-chip ROM is enabled and is accessible at addresses 0000h–0FFFh.
Device-Specific Information 4-37 Memory and I/O Spaces T able 4–7. ’C204 Program-Memory Configuration Options MP/MC CNF ROM (hex) DARAM B0 (hex) External (hex) Reserved (hex) 0 0 0000–0FFF – 1.
5-1 Program Control This chapter discusses the processes and features involved in controlling the flow of a program on the ’C2xx. Program control involves controlling the order in which one or more blocks of instructions are executed.
Program-Address Generation 5-2 5.1 Program-Address Generation Program flow requires the processor to generate the next program address (sequential or nonsequential) while executing the current instruction. Pro- gram-address generation is illustrated in Figure 5–1 and summarized in T able 5–1.
Program-Address Generation 5-3 Program Control T able 5–1. Program-Address Generation Summary Operation Program-Address Source Sequential operation PC (contains program address +1) Dummy cycle P AR .
Program-Address Generation 5-4 The ’C2xx can load the PC in a number of ways, to accommodate sequential and nonsequential program flow . T able 5–2 shows what is loaded to the PC according to the code operation performed.
Program-Address Generation 5-5 Program Control PSHD and POPD. These instructions allow you to build a stack in data memory for the nesting of subroutines or interrupts beyond eight levels. The PSHD instruction pushes a data-memory value onto the top of the stack.
Program-Address Generation 5-6 Figure 5–3. A Pop Operation Before Instruction After Instruction Accumulator Accumulator or memory 82h or memory 45h location location 45h 16h 16h 7h Stack 7h Stack 33h 33h 42h 42h 56h 56h 37h 37h 61h 61h 61h 5.
Pipeline Operation 5-7 Program Control 5.2 Pipeline Operation Instruction pipelining consists of a sequence of bus operations that occur dur- ing the execution of an instruction. The ’C2xx pipeline has four independent stages: instruction-fetch, instruction-decode, operand-fetch, and instruction- execute.
Branches, Calls, and Returns 5-8 5.3 Branches, Calls, and Returns Branches, calls, and returns break the sequential flow of instructions by trans- ferring control to another location in program memory . A branch only transfers control to the new location.
Branches, Calls, and Returns 5-9 Program Control By the time the unconditional call instruction reaches the execute phase of the pipeline, the next two instruction words have already been fetched.
Conditional Branches, Calls, and Returns 5-10 5.4 Conditional Branches, Calls, and Returns The ’C2xx provides branch, call, and return instructions that will execute only if one or more conditions are met. Y ou specify the conditions as operands of the conditional instruction.
Conditional Branches, Calls, and Returns 5-1 1 Program Control Group 2. Y ou can select up to three conditions. Each of these conditions must be from a different category (A, B, or C); you cannot have two condi- tions from the same category . For example, you can test TC, C, and BIO at the same time, but you cannot test C and NC at the same time.
Conditional Branches, Calls, and Returns 5-12 The conditional branch instructions are BCND (branch conditionally) and BANZ (branch if currently selected auxiliary register is not equal to 0). The BANZ instruction is useful for implementing loops. 5.4.
Conditional Branches, Calls, and Returns 5-13 Program Control RETC, like RET , is a single-word instruction. However , because of the poten- tial PC discontinuity , it operates with the same ef fective execution time as the conditional branch (BCND) and the conditional call (CC).
Repeating a Single Instruction 5-14 5.5 Repeating a Single Instruction The ’C2xx repeat (RPT) instruction allows the execution of a single instruction N + 1 times, where N is specified as an operand of the RPT instruction. When RPT is executed, the repeat counter (RPTC) is loaded with N.
Interrupts 5-15 5.6 Interrupts Interrupts are hardware- or software-driven signals that cause the ’C2xx to suspend its current program sequence and execute a subroutine. T ypically , in- terrupts are generated by hardware devices that need to give data to or take data from the ’C2xx (for example, A/D and D/A converters and other proces- sors).
Interrupts 5-16 3) Execute the interrupt service routine. Once the interrupt is acknowl- edged, the ’C2xx branches to its corresponding subroutine called an inter- rupt service routine (ISR). The ’C2xx follows the branch instruction you place at a predetermined address (the vector location) and executes the ISR you have written.
Interrupts 5-17 Program Control T able 5–5. ’C2xx Interrupt Locations and Priorities (Continued) K † V ector Location Name Priority Function 10 14h INT10 – User-defined software interrupt 11 1.
Interrupts 5-18 5.6.3 Maskable Interrupts When a maskable interrupt is successfully requested by a hardware device or by an external pin, the corresponding flag or flags are activated. These flags are activated whether or not the interrupt is later acknowledged by the proces- sor .
Interrupts 5-19 Program Control After an interrupt request is received by the CPU, the CPU must decide wheth- er to acknowledge the request. Maskable hardware interrupts are acknowl- edged only after certain conditions are met: Priority is highest.
Interrupts 5-20 Figure 5–6 summarizes how maskable interrupts are handled by the CPU. Figure 5–6. Maskable Interrupt Operation Flow Chart Interrupt request sent to CPU Corresponding IFR flag bit s.
Interrupts 5-21 Program Control 1 to the corresponding IFR bit. All pending interrupts can be cleared by writing the current contents of the IFR back into the IFR. Acknowledgement of a hardware request also clears the corresponding IFR bit. A device reset clears all IFR bits.
Interrupts 5-22 Bit 3 RINT — Receive interrupt flag. Bit 3 is tied to the receive interrupt for the synchro- nous serial port. T o avoid double interrupts, write a 1 to this bit in the interrupt service routine. RINT = 0 Interrupt RINT is not pending.
Interrupts 5-23 Program Control For ’C2xx devices other than the ’C209, Figure 5–8 shows the IMR. Descrip- tions of the bits follow the figure. For a description of the ’C209 IMR, see sub- section 1 1.3.1, ’C209 Interrupt Registers , on page 1 1-1 1.
Interrupts 5-24 Bit 0 HOLD/INT1 — HOLD/Interrupt 1 mask. This bit masks or unmasks interrupts re- quested at the HOLD /INT1 pin. HOLD/INT1 = 0 HOLD /INT1 is masked.
Interrupts 5-25 Program Control to mask INT3 (prevent the setting of flags FINT3 and INT2/INT3) write a 0 to MINT3. If INT2/INT3 is not set, the CPU has not received and will not acknowl- edge the interrupt request. When INT2/INT3 is set, one or both of the interrupts is pending.
Interrupts 5-26 Figure 5–9 shows the ICR, and bit descriptions follow the figure. Figure 5–9. ’C2xx Interrupt Control Register (ICR) — I/O-Space Address FFECh 15 5 4 3 2 1 0 Reserved MODE FINT.
Interrupts 5-27 Program Control Bit 0 MINT2 — Interrupt 2 mask. This bit masks the external interrupt INT2 or , in conjunc- tion with the INT2/INT3 bit of the IMR, unmasks INT2 . MINT2 = 0 INT2 is masked. Neither FINT2 nor bit 1 of the IFR (INT2/INT3) is set by a request on the INT2 pin.
Interrupts 5-28 Note: The INTR instruction does not affect IFR flags. When you use the INTR instruction to initiate an interrupt that has an associated flag bit in the IFR, the instruction neither sets nor clears the flag bit. No software write operation can set the IFR flag bits; only the appropriate hardware requests can.
Interrupts 5-29 Program Control Figure 5–10. Nonmaskable Interrupt Operation Flow Chart Interrupt request sent to CPU Interrupt acknowledged TRAP instruction? Ye s No INTM bit set to 1 PC saved on stack Interrupt service routine run Return instruction restores PC Program continues 5.
Interrupts 5-30 Managing ISRs within ISRs The ’C2xx hardware stack allows you to have ISRs within ISRs. When consid- ering nesting ISRs like this, keep the following in mind: If you want the ISR be .
Interrupts 5-31 Program Control For an external, maskable hardware interrupt, a minimum latency of eight cycles is required to synchronize the interrupt externally , recognize the inter- rupt, and branch to the interrupt vector location. On the ninth cycle, the inter- rupt vector is fetched.
Interrupts 5-32 before the return, the new return address would be added to the hardware stack, even if the stack were already full. T o allow the CPU to complete the return, interrupts are also blocked after a RET instruction until at least one instruction at the return address is executed.
Reset Operation 5-33 Program Control 5.7 Reset Operation Reset (RS ) is a nonmaskable external interrupt that can be used at any time to put the ’C2xx into a known state. Reset is the highest priority interrupt; no other interrupt takes precedence over reset.
Reset Operation 5-34 Peripherals: The timer count is set to its maximum value (FFFFh), the timer divide- down value is set to 0, and the timer starts counting down. The synchronous serial port is reset: The port emulation mode is set to immediate stop.
Reset Operation 5-35 Program Control T able 5–6. Reset V alues of On-Chip Registers Mapped to Data Space Name Data-Memory Address Reset V alue Description IMR 0004h 0000h Interrupt mask register GREG 0005h 0000h Interrupt control register IFR 0006h 0000h Synchronous data transmit and receive register T able 5–7.
Power-Down Mode 5-36 5.8 Power-Down Mode The ’C2xx has a power-down mode that allows the ’C2xx core to enter a dor- mant state and use less power than during normal operation.
Power-Down Mode 5-37 Program Control 5.8.2 T ermination of Power-Down During a HOLD Operation One of the necessary steps in the HOLD operation is the execution of an IDLE instruction (see Section 4.7, Direct Memory Access Using The HOLD Opera- tion , on page 4-27) .
6-1 Addressing Modes Addressing Modes This chapter explains the three basic memory addressing modes used by the ’C2xx instruction set. The three modes are: Immediate addressing mode Direct addressin.
Immediate Addressing Mode 6-2 6.1 Immediate Addressing Mode In immediate addressing, the instruction word contains a constant to be ma- nipulated by the instruction. The ’C2xx supports two types of immediate ad- dressing: Short-immediate addressing.
Immediate Addressing Mode 6-3 Addressing Modes Figure 6–2. T wo Words Loaded Consecutively to the Instruction Register in Example 6–2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 0 1 1 1 1 1 1 1 0 1 .
Direct Addressing Mode 6-4 6.2 Direct Addressing Mode In the direct addressing mode, data memory is addressed in blocks of 128 words called data pages. The entire 64K of data memory consists of 512 data pages labeled 0 through 51 1, as shown in Figure 6–3.
Direct Addressing Mode 6-5 Addressing Modes Figure 6–4. Instruction Register (IR) Contents in Direct Addressing Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 LSBs 0 8 MSBs 8 MSBs Bits 15 through 8 indicate the instruction type (for example, ADD) and also contain any information regarding a shift of the data value to be accessed by the instruction.
Direct Addressing Mode 6-6 6.2.1 Using Direct Addressing Mode When you use direct addressing mode, the processor uses the DP to find the data page and uses the seven LSBs of the instruction register to find a particu- lar address on that page. Always do the following: 1) Set the data page.
Direct Addressing Mode 6-7 Addressing Modes Example 6–3. Using Direct Addressing with ADD (Shift of 0 to 15) LDP #4 ;Set data page to 4 (addresses 0200h–027Fh). ADD 9h,5 ;The contents of data address 0209h are ;left–shifted 5 bits and added to the ;contents of the accumulator.
Direct Addressing Mode 6-8 In Example 6–5, the ADDC instruction references a data memory address that is generated as shown following the program code. Note that if an instruction does not perform shifts, like the ADDC instruction does not, all eight MSBs of the instruction contain the opcode for the instruction type.
Indirect Addressing Mode 6-9 Addressing Modes 6.3 Indirect Addressing Mode Eight auxiliary registers (AR0–AR7) provide flexible and powerful indirect ad- dressing. Any location in the 64K data memory space can be accessed using a 16-bit address contained in an auxiliary register .
Indirect Addressing Mode 6-10 ister as the data memory address and then increments or decrements the content of the current auxiliary register by the index amount. Increment or decrement by an index amount using reverse carry . The value in AR0 is the index amount.
Indirect Addressing Mode 6-1 1 Addressing Modes T able 6–1. Indirect Addressing Operands (Continued) Option Operand Example Increment by index amount, adding with reverse carry *BR0+ L T *BR0+ loads.
Indirect Addressing Mode 6-12 Example 6–6. Selecting a New Current Auxiliary Register MAR *,AR1 ;Load the ARP with 1 to make AR1 the ;current auxiliary register.
Indirect Addressing Mode 6-13 Addressing Modes T able 6–2. Effects of the ARU Code on the Current Auxiliary Register ARU Code 6 5 4 Arithmetic Operation Performed on Current AR 0 0 0 No operation on.
Indirect Addressing Mode 6-14 T able 6–3. Field Bits and Notation for Indirect Addressing Instruction Opcode Bits 15 – 8 7 6 5 4 3 2 1 0 Operand(s) Operation ← 8 MSBs → 10000 ← NAR → * No .
Indirect Addressing Mode 6-15 Addressing Modes 6.3.5 Examples of Indirect Addressing In Example 6–7, when the ADD instruction is fetched from program memory , the instruction register is loaded with the value shown.
Indirect Addressing Mode 6-16 Example 6–9. Decrement by 1 ADD *–,8 ;Operates as in Example 6–7, but in ;addition, the current auxiliary register ;is decremented by one. Example 6–10. Increment by Index Amount ADD *0+,8 ;Operates as in Example 6–7, but in ;addition, the content of register AR0 ;is added to the current auxiliary ;register.
Indirect Addressing Mode 6-17 Addressing Modes 6.3.6 Modifying Auxiliary Register Content The LAR, ADRK, SBRK, and MAR instructions are specialized instructions for changing the content of an auxiliary register (AR): The LAR instruction loads an AR. The ADRK instruction adds an immediate value to an AR; SBRK subtracts an immediate value.
7-1 Assembly Language Instructions Assembly Language Instructions The ’C2xx instruction set supports numerically intensive signal-processing op- erations as well as general-purpose applications such as multiprocessing and high-speed control.
Instruction Set Summary 7-2 7.1 Instruction Set Summary This section provides a summary of the instruction set in six tables (T able 7–1 to T able 7–6) according to the following functional headin.
Instruction Set Summary 7-3 Assembly Language Instructions IAAA AAAA (One I followed by seven As) The I at the left represents a bit that reflects whether direct addressing (I = 0) or indirect ad- dressing (I = 1) is being used. When direct addressing is used, the seven As are the seven least significant bits (LSBs) of a data memory address.
Instruction Set Summary 7-4 ZL VC ZL VC T wo 4-bit fields — each representing the following conditions: ACC = 0 Z ACC < 0 L Overflow V Carry C A conditional instruction contains two of these 4-bit fields. The 4-LSB field of the instruction is a mask field.
Instruction Set Summary 7-5 Assembly Language Instructions T able 7–1. Accumulator , Arithmetic, and Logic Instructions (Continued) Mnemonic Opcode Cycles Words Description AND AND ACC with data val.
Instruction Set Summary 7-6 T able 7–1. Accumulator , Arithmetic, and Logic Instructions (Continued) Mnemonic Opcode Cycles Words Description SUB Subtract from ACC with shift of 0 to 15, direct or i.
Instruction Set Summary 7-7 Assembly Language Instructions T able 7–2. Auxiliary Register Instructions Mnemonic Description Words Cycles Opcode ADRK Add constant to current AR, short immediate 1 1 0.
Instruction Set Summary 7-8 T able 7–3. TREG, PREG, and Multiply Instructions (Continued) Mnemonic Opcode Cycles Words Description MAC Multiply and accumulate, direct or indirect 2 3 1010 0010 IAAA .
Instruction Set Summary 7-9 Assembly Language Instructions T able 7–4. Branch Instructions (Continued) M n e mo n ic Opcode Cycles Words Description CALL Call subroutine, indirect 2 4 01 1 1 1010 1A.
Instruction Set Summary 7-10 T able 7–5. Control Instructions (Continued) Mnemonic Opcode Cycles Words Description POPD Pop top of stack to data memory , direct or indirect 1 1 1000 1010 IAAA AAAA P.
Instruction Set Summary 7-1 1 Assembly Language Instructions T able 7–6. I/O and Memory Instructions (Continued) Mnemonic Opcode Cycles Words Description TBLR T able read, direct or indirect 1 3 101.
How T o Use the Instruction Descriptions 7-12 7.2 How T o Use the Instruction Descriptions Section 7.3 contains detailed information on the instruction set. The descrip- tion for each instruction presents the following categories of information: Syntax Operands Opcode Execution Status Bits Description Words Cycles Examples 7.
How T o Use the Instruction Descriptions 7-13 Assembly Language Instructions [, x] Operand x is optional. Example: For the syntax: ADD dma , [, shift ] you must supply dma , as in the instruction: ADD.
How T o Use the Instruction Descriptions 7-14 7.2.2 Operands Operands can be constants, or assembly-time expressions referring to memory , I/O ports, register addresses, pointers, shift counts, and a variety of other constants.
How T o Use the Instruction Descriptions 7-15 Assembly Language Instructions The field called dma contains the value dma , which is defined in the operands category .
How T o Use the Instruction Descriptions 7-16 7.2.7 Words The words category specifies the number of memory words (one or two) re- quired to store the instruction. When the number of words depends on the ad- dressing mode used for an instruction, the words category specifies which ad- dressing modes require one word and which require two words.
How T o Use the Instruction Descriptions 7-17 Assembly Language Instructions If an instruction requires memory operand(s), the rows in the table indicate the location(s) of the operand(s), as defined here: DARAM The operand is in internal dual-access RAM.
How T o Use the Instruction Descriptions 7-18 The instruction-cycle timings are based on the following assumptions: At least the next four instructions are fetched from the same memory sec- tion (internal or external) that was used to fetch the current instruction (ex- cept in the case of PC discontinuity instructions, such as B, CALL, etc.
How T o Use the Instruction Descriptions 7-19 Assembly Language Instructions The instruction also specifies that AR0 will be the next auxiliary register; therefore, after the instruction ARP = 0. Because no carry is generated during the addition, the carry bit (C) be- comes 0.
Instruction Descriptions 7-20 7.3 Instruction Descriptions This section contains detailed information on the instruction set for the ’C2xx (For a summary of the instruction set, see Section 7.
Absolute V alue of Accumulator ABS 7-21 Assembly Language Instructions Syntax ABS Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then .
ABS Absolute V alue of Accumulator 7-22 Example 1 ABS Before Instruction After Instruction ACC X 1234h ACC 0 1234h CC Example 2 ABS Before Instruction After Instruction ACC X 0FFFFFFFFh ACC 0 1h CC Ex.
Add to Accumulator ADD 7-23 Assembly Language Instructions Syntax ADD dma [, shift ] Direct addressing ADD dma , 16 Direct with left shift of 16 ADD ind [, shift [, AR n ] ] Indirect addressing ADD in.
ADD Add to Accumulator 7-24 Execution Increment PC, then ... Event Addressing mode (ACC) + ( (data-memory address) 2 s hift ) → ACC Direct or indirect (ACC) + ( (data-memory address) 2 16 ) → ACC .
Add to Accumulator ADD 7-25 Assembly Language Instructions Cycles for a Single ADD Instruction (Using Direct and Indirect Addressing) Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1.
ADD Add to Accumulator 7-26 Example 3 ADD #1h ;Add short immediate Before Instruction After Instruction ACC X 2h ACC 0 03h CC Example 4 ADD #1111h,1 ;Add long immediate with shift of 1 Before Instruct.
Add to Accumulator With Carry ADDC 7-27 Assembly Language Instructions Syntax ADDC dma Direct addressing ADDC ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alu.
ADDC Add to Accumulator With Carry 7-28 Cycles for a Repeat (RPT) Execution of an ADDC Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1 † n+p External n+nd n+nd .
Add to Accumulator With Sign Extension Suppressed ADDS 7-29 Assembly Language Instructions Syntax ADDS dma Direct addressing ADDS ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-mem.
ADDS Add to Accumulator With Sign Extension Suppressed 7-30 Cycles for a Repeat (RPT) Execution of an ADDS Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1 † n+p.
Add to Accumulator With Shift Specified by TREG ADDT 7-31 Assembly Language Instructions Syntax ADDT dma Direct addressing ADDT ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memor.
ADDT Add to Accumulator With Shift Specified by TREG 7-32 Cycles for a Repeat (RPT) Execution of an ADDT Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1 † n+p E.
Add Short-Immediate V alue to Auxiliary Register ADRK 7-33 Assembly Language Instructions Syntax ADRK # k Short immediate addressing Operands k: 8-bit short immediate value ADRK # k 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 0 1111000 k Execution Increment PC, then .
AND AND With Accumulator 7-34 Syntax AND dma Direct addressing AND ind [, AR n ] Indirect addressing AND # lk [, shift ] Long immediate addressing AND # lk , 16 Long immediate with left shift of 16 Op.
AND With Accumulator AND 7-35 Assembly Language Instructions Status Bits None This instruction is not affected by SXM. Description If direct or indirect addressing is used, the low word of the accumulator is ANDed with a data-memory value, and the result is placed in the low word posi- tion in the accumulator .
AND AND With Accumulator 7-36 Example 1 AND 16 ;(DP = 4: addresses 0200h–027Fh) Before Instruction After Instruction Data Memory Data Memory 0210h 00FFh 0210h 00FFh ACC 12345678h ACC 00000078h Examp.
Add PREG to Accumulator AP AC 7-37 Assembly Language Instructions Syntax AP AC Operands None AP AC 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 1 011111000000100 Execution Increment PC, then ... (ACC) + shifted (PREG) → ACC Status Bits Affected by Affects PM and OVM C and OV This instruction is not affected by SXM.
AP AC Add PREG to Accumulator 7-38 Example APAC ;(PM = 01) Before Instruction After Instruction PREG 40h PREG 40h ACC X 20h ACC 0 A0h CC.
Branch Unconditionally B 7-39 Assembly Language Instructions Syntax B pma [, ind [, AR n ] ] Indirect addressing Operands pma: 16-bit program-memory address n: V alue from 0 to 7 designating the next .
BACC Branch to Location Specified by Accumulator 7-40 Syntax BACC Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 1 0 0 0 1 1 1 1 1 0 1 Execution ACC(15:0) → PC Status Bits None Description Control is passed to the 16-bit address residing in the lower half of the accumu- lator .
Branch on Auxiliary Register Not Zero BANZ 7-41 Assembly Language Instructions Syntax BANZ pma [, ind [, AR n ] ] Indirect addressing Operands pma: 16-bit program-memory address n: V alue from 0 to 7 .
BANZ Branch on Auxiliary Register Not Zero 7-42 Example 1 BANZ PGM0 ;(PGM0 labels program address 0) Before Instruction After Instruction ARP 0 ARP 0 AR0 5h AR0 4h Because the content of AR0 is not zero, the program branches to program ad- dress 0 is loaded into the program counter (PC), and the program continues executing from that location.
Branch Conditionally BCND 7-43 Assembly Language Instructions Syntax BCND pma , cond 1 [, cond 2] [,...] Operands pma: 16-bit program-memory address cond Condition EQ ACC = 0 NEQ ACC ≠ 0 L T ACC <.
BCND Branch Conditionally 7-44 Example BCND PGM191,LEQ,C If the accumulator contents are less than or equal to zero and the carry bit is set, program address 191 is loaded into the program counter , and the program continues to execute from that location.
T est Bit BIT 7-45 Assembly Language Instructions Syntax BIT dma , bit code Direct addressing BIT ind , bit code [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address bit code:.
BIT T est Bit 7-46 Cycles for a Single BIT Instruction Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2 † 1+p External 1+d 1+d 1+d 2+d+p † If the operand and the code are in.
T est Bit Specified by TREG BITT 7-47 Assembly Language Instructions Syntax BITT dma Direct addressing BITT ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue .
BITT T est Bit Specified by TREG 7-48 Cycles for a Single BITT Instruction Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2 † 1+p External 1+d 1+d 1+d 2+d+p † If the operand.
Block Move From Data Memory to Data Memory BLDD 7-49 Assembly Language Instructions Syntax General syntax: BLDD source, destination BLDD # lk , dma Direct with long immediate source BLDD # lk , ind [,.
BLDD Block Move From Data Memory to Data Memory 7-50 Execution Increment PC, then ... (PC) → MST ACK lk → PC (source) → destination For indirect, modify (current AR) and (ARP) as specified (PC) .
Block Move From Data Memory to Data Memory BLDD 7-51 Assembly Language Instructions Cycles Cycles for a Single BLDD Instruction Operand ROM DARAM SARAM External Source: DARAM Destination: DARAM 3 3 3 .
BLDD Block Move From Data Memory to Data Memory 7-52 Cycles for a Repeat (RPT) Execution of a BLDD Instruction Operand ROM DARAM SARAM External Source: DARAM Destination: DARAM n+2 n+2 n+2 n+2+2p Sour.
Block Move From Data Memory to Data Memory BLDD 7-53 Assembly Language Instructions Example 1 BLDD #300h,20h ;(DP = 6) Before Instruction After Instruction Data Memory Data Memory 300h 0h 300h 0h 320h.
BLPD Block Move From Program Memory to Data Memory 7-54 Syntax General syntax: BLPD source , destination BLPD # pma , dma Direct with long immediate source BLPD # pma , ind [, AR n ] Indirect with lon.
Block Move From Program Memory to Data Memory BLPD 7-55 Assembly Language Instructions Description A word in program memory pointed to by the source is copied to data-memory space pointed to by destination . The first word of the source space is pointed to by a long-immediate value.
BLPD Block Move From Program Memory to Data Memory 7-56 Cycles Cycles for a Single BLPD Instruction Operand ROM DARAM SARAM External Source: DARAM/ROM Destination: DARAM 3 3 3 3+2p code Source: SARAM .
Block Move From Program Memory to Data Memory BLPD 7-57 Assembly Language Instructions Cycles for a Repeat (RPT) Execution of a BLPD Instruction (Continued) Operand External SARAM DARAM ROM Source: SA.
CALA Call Subroutine at Location Specified by Accumulator 7-58 Syntax CALA Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 1 1 0 0 0 1 1 1 1 1 0 1 Execution PC + 1 → TOS ACC(15:0) → PC Status Bits None Description The current program counter (PC) is incremented and pushed onto the top of the stack (TOS).
Call Unconditionally CALL 7-59 Assembly Language Instructions Syntax CALL pma [, ind [, AR n ] ] Indirect addressing Operands pma: 16-bit program-memory address n: V alue from 0 to 7 designating the n.
CC Call Conditionally 7-60 Syntax CC pma , cond Ă 1 [, cond Ă 2] [,...] Operands pma: 16-bit program-memory address cond Condition EQ ACC = 0 NEQ ACC ≠ 0 L T ACC < 0 LEQ ACC ≤ 0 GT ACC > 0.
Call Conditionally CC 7-61 Assembly Language Instructions Example CC PGM191,LEQ,C If the accumulator contents are less than or equal to zero and the carry bit is set, 0BFh (191) is loaded into the program counter , and the program continues to execute from that location.
CLRC Clear Control Bit 7-62 Syntax CLRC control bit Operands control bit: Select one of the following control bits: C Carry bit of status register ST1 CNF RAM configuration control bit of status regis.
Clear Control Bit CLRC 7-63 Assembly Language Instructions Words 1 Cycles for a Single CLRC Instruction ROM DARAM SARAM External 1 1 1 1+p Cycles for a Repeat (RPT) Execution of a CLRC Instruction ROM.
CMPL Complement Accumulator 7-64 Syntax CMPL Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then ... (ACC) → ACC Status Bits None Description The contents of the accumulator are replaced with its logical inversion (1s complement).
Compare Auxiliary Register With AR0 CMPR 7-65 Assembly Language Instructions Syntax CMPR CM Operands CM: V alue from 0 to 3 Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CM 1 0 0 0 1 0 1 1 1 1 1 1 0 1 Execution Increment PC, then ... Compare (current AR) to (AR0) and place the result in the TC bit of status register ST1.
DMOV Data Move in Data Memory 7-66 Syntax DMOV dma Direct addressing DMOV ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue from 0 to 7 designating the next a.
Data Move in Data Memory DMOV 7-67 Assembly Language Instructions Cycles for a Single DMOV Instruction Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 3 † 1+p External ‡ 2+2d.
IDLE Idle Until Interrupt 7-68 Syntax IDLE Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 0 0 0 1 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then wait for unmasked or nonmaskable hardware interrupt.
Input Data From Port IN 7-69 Assembly Language Instructions Syntax IN dma , PA Direct addressing IN ind , PA [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue fro.
IN Input Data From Port 7-70 Cycles for a Single IN Instruction Program Operand ROM DARAM SARAM External Destination: DARAM 2+io src 2+io src 2+io src 3+io src +2p code Destination: SARAM 2+io src 2+i.
Software Interrupt INTR 7-71 Assembly Language Instructions Syntax INTR K Operands K: V alue from 0 to 31 that indicates the interrupt vector location to branch to Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 .
LACC Load Accumulator With Shift 7-72 Syntax LACC dma [, shift ] Direct addressing LACC dma, 16 Direct with left shift of 16 LACC ind [, shift [, AR n ] ] Indirect addressing LACC ind , 16 [, AR n ] I.
Load Accumulator With Shift LACC 7-73 Assembly Language Instructions Execution Increment PC, then ... Event Addressing mode (data-memory address) × 2 shift → ACC Direct or indirect (data-memory add.
LACC Load Accumulator With Shift 7-74 Example 1 LACC 6,4 ;(DP = 8: addresses 0400h–047Fh, ;SXM = 0) Before Instruction After Instruction Data Memory Data Memory 406h 01h 406h 01h ACC X 012345678h AC.
Load Low Accumulator and Clear High Accumulator LACL 7-75 Assembly Language Instructions Syntax LACL dma Direct addressing LACL ind [, AR n ] Indirect addressing LACL # k Short immediate Operands dma:.
LACL Load Low Accumulator and Clear High Accumulator 7-76 Cycles for a Single LACL Instruction (Using Direct and Indirect Addressing) Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1.
Load Low Accumulator and Clear High Accumulator LACL 7-77 Assembly Language Instructions Example 3 LACL #10h Before Instruction After Instruction ACC X 7FFFFFFFh ACC X 010h CC.
LACT Load Accumulator With Shift Specified by TREG 7-78 Syntax LACT dma Direct addressing LACT ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue from 0 to 7 d.
Load Accumulator With Shift Specified by TREG LACT 7-79 Assembly Language Instructions Cycles for a Single LACT Instruction Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2 † .
LAR Load Auxiliary Register 7-80 Syntax LAR AR x , dma Direct addressing LAR AR x , ind [, AR n ] Indirect addressing LAR AR x , # k Short immediate addressing LAR AR x , # lk Long immediate addressin.
Load Auxiliary Register LAR 7-81 Assembly Language Instructions Description The contents of the specified data-memory address or an 8-bit or 16-bit con- stant are loaded into the specified auxiliary register (ARx). The specified con- stant is acted upon like an unsigned integer , regardless of the value of SXM.
LAR Load Auxiliary Register 7-82 Example 1 LAR AR0,16 ;(DP = 6: addresses 0300h–037Fh) Before Instruction After Instruction Data Memory Data Memory 310h 18h 310h 18h AR0 6h AR0 18h Example 2 LAR AR4.
Load Data Page Pointer LDP 7-83 Assembly Language Instructions Syntax LDP dma Direct addressing LDP ind [, AR n ] Indirect addressing LDP # k Short immediate addressing Operands dma: 7 LSBs of the dat.
LDP Load Data Page Pointer 7-84 Cycles for a Single LDP Instruction (Using Direct and Indirect Addressing) Program Operand ROM DARAM SARAM External DARAM 2 2 2 2+p code SARAM 2 2 2, 3 † 2+p code Ext.
Load Product Register High Word LPH 7-85 Assembly Language Instructions Syntax LPH dma Direct addressing LPH ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue.
LPH Load Product Register High Word 7-86 Cycles for a Repeat (RPT) Execution of an LPH Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1 † n+p External n+nd n+nd .
Load Status Register LST 7-87 Assembly Language Instructions Syntax LST # m , dma Direct addressing LST # m , ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alu.
LST Load Status Register 7-88 Figure 7–4. LST #1 Operation 1 5 1 4 1 3 1 21 1 1 0 9 8765 43210 ST0 ARP OV OVM 1 INTM DP ↑ ↑ ↑ 1 5 1 4 1 3 1 21 1 1 0 9 8765 43210 Data ↓ ↓ ↓ ↓ ↓ ↓ .
Load Status Register LST 7-89 Assembly Language Instructions Cycles for a Repeat (RPT) Execution of an LST Instruction Program Operand ROM DARAM SARAM External DARAM 2n 2n 2n 2n+p code SARAM 2n 2n 2n,.
LST Load Status Register 7-90 Example 4 LST #1,00h ;(DP = 6) ;Note that the ARB is loaded with ;the new ARP value. Before Instruction After Instruction Data Memory Data Memory 300h E1BCh 300h E1BCh ST.
Load TREG LT 7-91 Assembly Language Instructions Syntax L T dma Direct addressing LT ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue from 0 to 7 designating.
LT Load TREG 7-92 Cycles for a Repeat (RPT) Execution of an L T Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1 † n+p External n+nd n+nd n+nd n+1+p+nd † If th.
Load TREG and Accumulate Previous Product LTA 7-93 Assembly Language Instructions Syntax L T A dma Direct addressing LTA ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory addre.
LTA Load TREG and Accumulate Previous Product 7-94 Cycles for a Repeat (RPT) Execution of an L T A Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1 † n+p Externa.
Load TREG, Accumulate Previous Product, and Move Data LT D 7-95 Assembly Language Instructions Syntax L TD dma Direct addressing LT D ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data.
LT D Load TREG, Accumulate Previous Product, and Move Data 7-96 Words 1 Cycles for a Single L TD Instruction Program Operand ROM DARAM SARAM External ‡ DARAM 1 1 1 1+p SARAM 1 1 1, 3 † 1+p Externa.
Load TREG, Accumulate Previous Product, and Move Data LT D 7-97 Assembly Language Instructions Example 2 LTD *,AR3 ;(PM = 0) Before Instruction After Instruction ARP 1 ARP 3 AR1 3FEh AR1 3FEh Data Mem.
LT P Load TREG and Store PREG in Accumulator 7-98 Syntax L TP dma Direct addressing LT P ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue from 0 to 7 designa.
Load TREG and Store PREG in Accumulator LT P 7-99 Assembly Language Instructions Cycles for a Repeat (RPT) Execution of an L TP Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SAR.
LT S Load TREG and Subtract Previous Product 7-100 Syntax L TS dma Direct addressing LT S ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue from 0 to 7 design.
Load TREG and Subtract Previous Product LT S 7-101 Assembly Language Instructions Cycles for a Repeat (RPT) Execution of an L TS Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SA.
MAC Multiply and Accumulate 7-102 Syntax MAC pma , dma Direct addressing MAC pma , ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address pma: 16-bit program-memory address .
Multiply and Accumulate MAC 7-103 Assembly Language Instructions Description The MAC instruction: Adds the previous product, shifted as defined by the PM status bits, to the accumulator . The carry bit is set (C = 1) if the result of the addition gener- ates a carry and is cleared (C = 0) if it does not generate a carry .
MAC Multiply and Accumulate 7-104 Cycles Cycles for a Single MAC Instruction Operand ROM DARAM SARAM External Operand 1: DARAM/ ROM Operand 2: DARAM 3 3 3 3+2p code Operand 1: SARAM Operand 2: DARAM 3.
Multiply and Accumulate MAC 7-105 Assembly Language Instructions Cycles for a Repeat (RPT) Execution of an MAC Instruction (Continued) Operand External SARAM DARAM ROM Operand 1: DARAM/ ROM Operand 2:.
MACD Multiply and Accumulate With Data Move 7-106 Syntax MACD pma , dma Direct addressing MACD pma , ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address pma: 16-bit progr.
Multiply and Accumulate With Data Move MACD 7-107 Assembly Language Instructions Status Bits Affected by Affects PM and OVM C and OV Description The MACD instruction: Adds the previous product, shifted as defined by the PM status bits, to the accumulator .
MACD Multiply and Accumulate With Data Move 7-108 Cycles for a Single MACD Instruction (Continued) Operand External SARAM DARAM ROM Operand 1: External Operand 2: DARAM 3+p op1 3+p op1 3+p op1 3+p op1.
Multiply and Accumulate With Data Move MACD 7-109 Assembly Language Instructions Cycles for a Repeat (RPT) Execution of an MACD Instruction (Continued) Operand External SARAM DARAM ROM Operand 1: SARA.
MACD Multiply and Accumulate With Data Move 7-1 10 Example 2 MACD 0FF00h,*,AR6 ;(PM = 0, CNF = 1) Before Instruction After Instruction ARP 5 ARP 6 AR5 308h AR5 308h Data Memory Data Memory 308h 23h 30.
Modify Auxiliary Register MAR 7-1 1 1 Assembly Language Instructions Syntax MAR dma Direct addressing MAR ind [, AR n ] Indirect addressing Operands n: V alue from 0 to 7 designating the next auxiliar.
MAR Modify Auxiliary Register 7-1 12 Words 1 Cycles for a Single MAR Instruction ROM DARAM SARAM External 1 1 1 1+p Cycles for a Repeat (RPT) Execution of an MAR Instruction ROM DARAM SARAM External n n n n+p Example 1 MAR *,AR1 ;Load the ARP with 1.
Multiply MPY 7-1 13 Assembly Language Instructions Syntax MPY dma Direct addressing MPY ind [, AR n ] Indirect addressing MPY # k Short immediate addressing Operands dma: 7 LSBs of the data-memory add.
MPY Multiply 7-1 14 Cycles for a Single MPY Instruction (Using Direct and Indirect Addressing) Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2 † 1+p External 1+d 1+d 1+d 2+d+.
Multiply MPY 7-1 15 Assembly Language Instructions Example 2 MPY *,AR2 Before Instruction After Instruction ARP 1 ARP 2 AR1 40Dh AR1 40Dh Data Memory Data Memory 40Dh 7h 40Dh 7h TREG 6h TREG 6h PREG 3.
MPY A Multiply and Accumulate Previous Product 7-1 16 Syntax MPY A dma Direct addressing MPY A ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue from 0 to 7 d.
Multiply and Accumulate Previous Product MPY A 7-1 17 Assembly Language Instructions Cycles for a Repeat (RPT) Execution of an MPY A Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+.
MPYS Multiply and Subtract Previous Product 7-1 18 Syntax MPYS dma Direct addressing MPYS ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue from 0 to 7 design.
Multiply and Subtract Previous Product MPYS 7-1 19 Assembly Language Instructions Cycles for a Repeat (RPT) Execution of an MPYS Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SA.
MPYU Multiply Unsigned 7-120 Syntax MPYU dma Direct addressing MPYU ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue from 0 to 7 designating the next auxilia.
Multiply Unsigned MPYU 7-121 Assembly Language Instructions Cycles for a Single MPYU Instruction Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2 † 1+p External 1+d 1+d 1+d 2+.
NEG Negate Accumulator 7-122 Syntax NEG Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 0 0 0 0 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then ... (ACC) × –1 → ACC Status Bits Affected by Affects OVM C and OV Description The content of the accumulator is replaced with its arithmetic complement (2s complement).
Negate Accumulator NEG 7-123 Assembly Language Instructions Example 3 NEG ;(OVM = 1) Before Instruction After Instruction ACC X 080000000h ACC 0 7FFFFFFFh CC X1 OV OV.
NMI Nonmaskable Interrupt 7-124 Syntax NMI Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 0 0 1 0 1 0 0 1 1 1 1 1 0 1 Execution (PC) + 1 → stack 24h → PC 1 → INTM Status Bits Affects INTM This instruction is not affected by INTM.
No Operation NOP 7-125 Assembly Language Instructions Syntax NOP Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 Execution Increment PC Status Bits None Description No operation is performed. The NOP instruction affects only the PC.
NORM Normalize Contents of Accumulator 7-126 Syntax NORM ind Indirect addressing Operands ind: Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– NORM ind 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 1 01000001 ARU N NAR Note: ARU, N, and NAR are defined in Section 6.
Normalize Contents of Accumulator NORM 7-127 Assembly Language Instructions Notes: For the NORM instruction, the auxiliary register operations are executed dur- ing the fourth phase of the pipeline, the execution phase. For other instruc- tions, the auxiliary register operations take place in the second phase of the pipeline, in the decode phase.
NORM Normalize Contents of Accumulator 7-128 Example 3 15-Bit Normalization: MAR *,AR1 ;Use AR1 to store the exponent. LAR AR1,#0Fh ;Initialize exponent counter. RPT #14 ;15-bit normalization specified (yielding ;a 4-bit exponent and 16-bit mantissa).
OR With Accumulator OR 7-129 Assembly Language Instructions Syntax OR dma Direct addressing OR ind [, AR n ] Indirect addressing OR # lk [, shift ] Long immediate addressing OR # lk, 16 Long immediate.
OR OR With Accumulator 7-130 Status Bits None This instruction is not affected by SXM. Description An OR operation is performed on the contents of the accumulator and the con- tents of the addressed data-memory location or a long-immediate value. The long-immediate value may be shifted before the OR operation.
OR With Accumulator OR 7-131 Assembly Language Instructions Example 1 OR DAT8 ;(DP = 8) Before Instruction After Instruction Data Memory Data Memory 408h 0F000h 408h 0F000h ACC X 100002h ACC X 10F002h.
OUT Output Data to Port 7-132 Syntax OUT dma , PA Direct addressing OUT ind , PA [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address P A: 16-bit I/O address n: V alue from 0 .
Output Data to Port OUT 7-133 Assembly Language Instructions Cycles Cycles for a Single OUT Instruction Program Operand ROM DARAM SARAM External Source: DARAM 3+io dst 3+io dst 3+io dst 5+io dst +2p c.
PA C Load Accumulator With Product Register 7-134 Syntax P AC Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then ... shifted (PREG) → ACC Status Bits Affected by PM Description The content of PREG, shifted as specified by the PM status bits, is loaded into the accumulator .
Pop T op of Stack to Low Accumulator POP 7-135 Assembly Language Instructions Syntax POP Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 0 0 1 1 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then .
POP Pop T op of Stack to Low Accumulator 7-136 Example POP Before Instruction After Instruction ACC X 82h ACC X 45h CC Stack 45h Stack 16h 16h 7h 7h 33h 33h 42h 42h 56h 56h 37h 37h 61h 61h 61h.
Pop T op of Stack to Data Memory POPD 7-137 Assembly Language Instructions Syntax POPD dma Direct addressing POPD ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V.
POPD Pop T op of Stack to Data Memory 7-138 Cycles for a Repeat (RPT) Execution of a POPD Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+2 † n+p External 2n+nd 2.
Push Data-Memory V alue Onto Stack PSHD 7-139 Assembly Language Instructions Syntax PSHD dma Direct addressing PSHD ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n:.
PSHD Push Data-Memory V alue Onto Stack 7-140 Cycles for a Repeat (RPT) Execution of a PSHD Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1 † n+p External n+nd .
Push Low Accumulator Onto Stack PUSH 7-141 Assembly Language Instructions Syntax PUSH Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 1 1 1 1 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then... Push all stack locations down one level ACC(15:0) → TOS Status Bits None Description The stack values move down one level.
RET Return From Subroutine 7-142 Syntax RET Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 Execution (TOS) → PC Pop stack one level. Status Bits None Description The contents of the top stack register are copied into the program counter .
Return Conditionally RETC 7-143 Assembly Language Instructions Syntax RETC cond 1 [, cond 2] [ ,... ] Operands cond Condition EQ ACC = 0 NEQ ACC ≠ 0 L T ACC < 0 LEQ ACC ≤ 0 GT ACC > 0 GEQ AC.
ROL Rotate Accumulator Left 7-144 Syntax ROL Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then ... C → ACC(0) (ACC(31)) → C (ACC(30:0)) → ACC(31:1) Status Bits Affects C This instruction is not affected by SXM.
Rotate Accumulator Right ROR 7-145 Assembly Language Instructions Syntax ROR Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then ... C → ACC(31) (ACC(0)) → C (ACC(31:1)) → ACC(30:0) Status Bits Affects C This instruction is not affected by SXM.
RPT Repeat Next Instruction 7-146 Syntax RPT dma Direct addressing RPT ind [, AR n ] Indirect addressing RPT # k Short immediate Operands dma: 7 LSBs of the data-memory address n: V alue from 0 to 7 d.
Repeat Next Instruction RPT 7-147 Assembly Language Instructions Cycles for a Single RPT Instruction (Using Direct and Indirect Addressing) Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SAR.
SACH Store High Accumulator With Shift 7-148 Syntax SACH dma [, shift2 ] Direct addressing SACH ind [, shift2 [, AR n ] ] Indirect addressing Operands dma: 7 LSBs of the data-memory address shift2: Le.
Store High Accumulator With Shift SACH 7-149 Assembly Language Instructions Cycles for a Repeat (RPT) Execution of an SACH Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n .
SACL Store Low Accumulator With Shift 7-150 Syntax SACL dma [, shift2 ] Direct addressing SACL ind [, shift2 [, AR n ] ] Indirect addressing Operands dma: 7 LSBs of the data-memory address shift2: Lef.
Store Low Accumulator With Shift SACL 7-151 Assembly Language Instructions Cycles for a Repeat (RPT) Execution of an SACL Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+2 † n+p External 2n+nd 2n+nd 2n+nd 2n+2+nd+p † If the operand and the code are in the same SARAM block.
SAR Store Auxiliary Register 7-152 Syntax SAR AR x , dma Direct addressing SAR AR x, ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address x: V alue from 0 to 7 designating.
Store Auxiliary Register SAR 7-153 Assembly Language Instructions Cycles for a Repeat (RPT) Execution of an SAR Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+2 .
SBRK Subtract Short-Immediate V alue From Auxiliary Register 7-154 Syntax SBRK # k Short immediate addressing Operands k: 8-bit positive short immediate value SBRK # k 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 0 1111100 k Execution Increment PC, then ... (current AR) – k → current AR Note that k is an 8-bit positive constant.
Set Control Bit SETC 7-155 Assembly Language Instructions Syntax SETC control bit Operands control bit: Select one of the following control bits: C Carry bit of status register ST1 CNF RAM configurati.
SETC Set Control Bit 7-156 Words 1 Cycles for a Single SETC Instruction ROM DARAM SARAM External 1 1 1 1+p Cycles for a Repeat (RPT) Execution of an SETC Instruction ROM DARAM SARAM External n n n n+p.
Shift Accumulator Left SFL 7-157 Assembly Language Instructions Syntax SFL Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 0 1 0 0 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then ... (ACC(31)) → C (ACC(30:0)) → ACC(31:1) 0 → ACC(0) Status Bits Affects C This instruction is not affected by SXM.
SFR Shift Accumulator Right 7-158 Syntax SFR Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 0 1 0 0 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then .
Shift Accumulator Right SFR 7-159 Assembly Language Instructions Example 1 SFR ;(SXM = 0: no sign extension) Before Instruction After Instruction ACC X B0001234h ACC 0 5800091Ah CC Example 2 SFR ;(SXM.
SP AC Subtract PREG From Accumulator 7-160 Syntax SP AC Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 1 0 0 0 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then ... (ACC) – shifted (PREG) → ACC Status Bits Affected by Affects PM and OVM C and OV This instruction is not affected by SXM.
Store High PREG SPH 7-161 Assembly Language Instructions Syntax SPH dma Direct addressing SPH ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue from 0 to 7 de.
SPH Store High PREG 7-162 Cycles for a Repeat (RPT) Execution of an SPH Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+2 † n+p External 2n+nd 2n+nd 2n+nd 2n+2+nd.
Store Low PREG SPL 7-163 Assembly Language Instructions Syntax SPL dma Direct addressing SPL ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue from 0 to 7 des.
SPL Store Low PREG 7-164 Cycles for a Repeat (RPT) Execution of an SPL Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+2 † n+p External 2n+nd 2n+nd 2n+nd 2n+2+nd+.
Store Long-Immediate V alue to Data Memory SPLK 7-165 Assembly Language Instructions Syntax SPLK # lk , dma Direct addressing SPLK # lk , ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the .
SPLK Store Long-Immediate V alue to Data Memory 7-166 Example 2 SPLK #1111h,*+,AR4 Before Instruction After Instruction ARP 0 ARP 4 AR0 300h AR0 301h Data Memory Data Memory 300h 07h 300h 1111 h.
Set PREG Output Shift Mode SPM 7-167 Assembly Language Instructions Syntax SPM constant Operands constant: V alue from 0 to 3 that determines the product shift mode Opcode constant 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Execution Increment PC, then .
SQRA Square V alue and Accumulate Previous Product 7-168 Syntax SQRA dma Direct addressing SQRA ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue from 0 to 7 .
Square V alue and Accumulate Previous Product SQRA 7-169 Assembly Language Instructions Cycles for a Repeat (RPT) Execution of an SQRA Instruction Program Operand ROM DARAM SARAM External DARAM n n n .
SQRS Square V alue and Subtract Previous Product 7-170 Syntax SQRS dma Direct addressing SQRS ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue from 0 to 7 de.
Square V alue and Subtract Previous Product SQRS 7-171 Assembly Language Instructions Cycles for a Repeat (RPT) Execution of an SQRS Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+.
SST Store Status Register 7-172 Syntax SST # m , dma Direct addressing SST # m , ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue from 0 to 7 designating the.
Store Status Register SST 7-173 Assembly Language Instructions Status registers ST0 and ST1 are defined in Section 3.5, Status Registers ST0 and ST1 , on page 3-15.
SUB Subtract From Accumulator 7-174 Syntax SUB dma [, shift ] Direct addressing SUB dma , 16 Direct with left shift of 16 SUB ind [, shift [, AR n ] ] Indirect addressing SUB ind , 16 [, AR n ] Indire.
Subtract From Accumulator SUB 7-175 Assembly Language Instructions Execution Increment PC, then ... Event Addressing mode (ACC) – ((data-memory address) 2 shift ) → ACC Direct or indirect (ACC) .
SUB Subtract From Accumulator 7-176 Cycles for a Single SUB Instruction (Using Direct and Indirect Addressing) Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2 † 1+p External 1+d 1+d 1+d 2+d+p † If the operand and the code are in the same SARAM block.
Subtract From Accumulator SUB 7-177 Assembly Language Instructions Before Instruction After Instruction ARP 7 ARP 0 AR7 301h AR7 300h Data Memory Data Memory 301h 04h 301h 04h ACC X 09h ACC 1 01h CC E.
SUBB Subtract From Accumulator With Borrow 7-178 Syntax SUBB dma Direct addressing SUBB ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue from 0 to 7 designat.
Subtract From Accumulator With Borrow SUBB 7-179 Assembly Language Instructions Cycles for a Repeat (RPT) Execution of an SUBB Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARA.
SUBC Conditional Subtract 7-180 Syntax SUBC dma Direct addressing SUBC ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue from 0 to 7 designating the next auxi.
Conditional Subtract SUBC 7-181 Assembly Language Instructions SUBC af fects OV but is not affected by OVM; therefore, the accumulator does not saturate upon positive or negative overflows when executing this instruc- tion.
SUBS Subtract From Accumulator With Sign Extension Suppressed 7-182 Syntax SUBS dma Direct addressing SUBS ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue f.
Subtract From Accumulator With Sign Extension Suppressed SUBS 7-183 Assembly Language Instructions Cycles for a Repeat (RPT) Execution of an SUBS Instruction Program Operand ROM DARAM SARAM External D.
SUBT Subtract From Accumulator With Shift Specified by TREG 7-184 Syntax SUBT dma Direct addressing SUBT ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue fro.
Subtract From Accumulator With Shift Specified by TREG SUBT 7-185 Assembly Language Instructions Cycles for a Single SUBT Instruction Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2 † 1+p External 1+d 1+d 1+d 2+d+p † If the operand and the code are in the same SARAM block.
TBLR T able Read 7-186 Syntax TBLR dma Direct addressing TBLR ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue from 0 to 7 designating the next auxiliary reg.
T able Read TBLR 7-187 Assembly Language Instructions Cycles Cycles for a Single TBLR Instruction Program Operand ROM DARAM SARAM External Source: DARAM/ROM Destination: DARAM 3 3 3 3+p code Source: S.
TBLR T able Read 7-188 Cycles for a Repeat (RPT) Execution of a TBLR Instruction (Continued) Program Operand ROM DARAM SARAM External Source: DARAM/ROM Destination: SARAM n+2 n+2 n+2 n+4 † n+2+p cod.
T able Write TBL W 7-189 Assembly Language Instructions Syntax TBL W dma Direct addressing TBL W ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V alue from 0 to 7.
TBL W T able Write 7-190 Cycles Cycles for a Single TBL W Instruction Program Operand ROM DARAM SARAM External Source: DARAM/ROM Destination: DARAM 3 3 3 3+p code Source: SARAM Destination: DARAM 3 3 .
T able Write TBL W 7-191 Assembly Language Instructions Cycles for a Repeat (RPT) Execution of a TBL W Instruction (Continued) Program Operand ROM DARAM SARAM External Source: DARAM/ROM Destination: S.
TRAP Software Interrupt 7-192 Syntax TRAP Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 0 0 1 0 1 0 0 1 1 1 1 1 0 1 Execution (PC) + 1 → stack 22h → PC Status Bits Not affected by INTM; does not affect INTM.
Exclusive OR With Accumulator XOR 7-193 Assembly Language Instructions Syntax XOR dma Direct addressing XOR ind [, AR n ] Indirect addressing XOR # lk , [, shift ] Long immediate addressing XOR # lk, .
XOR Exclusive OR With Accumulator 7-194 Status Bits None Description With direct or indirect addressing, the low half of the accumulator value is exclusive ORed with the content of the addressed data memory location, and the result replaces the low half of the accumulator value; the upper half of the accumulator value is unaffected.
Exclusive OR With Accumulator XOR 7-195 Assembly Language Instructions Example 1 XOR DAT127 ;(DP = 511: addresses FF80h–FFFFh) Before Instruction After Instruction Data Memory Data Memory 0FFFFh 0F0.
ZALR Zero Low Accumulator and Load High Accumulator With Rounding 7-196 Syntax ZALR dma Direct addressing ZALR ind [, AR n ] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: V al.
Zero Low Accumulator and Load High Accumulator With Rounding ZALR 7-197 Assembly Language Instructions Cycles for a Repeat (RPT) Execution of a ZALR Instruction Program Operand ROM DARAM SARAM Externa.
8-1 On-Chip Peripherals On-Chip Peripherals This chapter discusses on-chip peripherals connected to the ’C2xx CPU and their control registers. The on-chip peripherals are controlled through memory-mapped registers. The operations of the timer and the serial ports are synchronized to the processor through interrupts and interrupt polling.
Control of On-Chip Peripherals 8-2 8.1 Control of On-Chip Peripherals The on-chip peripherals are controlled by accessing control registers that are mapped to on-chip I/O space. Data is also transferred to and from the peripher- als through these registers.
Control of On-Chip Peripherals 8-3 On-Chip Peripherals T able 8–1. Peripheral Register Locations and Reset Conditions (Continued) Register Name I/O Address Register Name Effects at Reset Reset V alue Other ’C2xx ’C209 IOSR – FFF6h 18xxh I/O status register .
Clock Generator 8-4 8.2 Clock Generator The high pulse of the master clock output signal (CLKOUT1) signifies the logic phase of the device (the phase when values are changed), while the low pulse signifies the latch phase (the phase when values are latched).
Clock Generator 8-5 On-Chip Peripherals External Oscillator . CLKIN is the output of an external oscillator , which is connected to the CLKIN/X2 pin. The X1 pin must be left unconnected.
Clock Generator 8-6 T able 8–2. ’C2xx Input Clock Modes Clock Mode CLKOUT1 Rate DIV2 DIV1 External CLKIN Source? Internal Oscillator Internal PLL ÷ 2 CLKOUT1 = CLKIN ÷ 2 0 0 No Enabled Disabled .
CLKOUT1-Pin Control (CLK) Register 8-7 On-Chip Peripherals 8.3 CLKOUT1-Pin Control (CLK) Register Y ou can use bit 0 of the CLK register to turn of f the pin for the master clock out- put signal (CLKOUT1). The CLK register is located at address FFE8h in I/O space and has the organization shown in Figure 8–3.
Timer 8-8 8.4 Timer The ’C2xx features an on-chip timer with a 4-bit prescaler . This timer is a down counter that can be stopped, restarted, reset, or disabled by specific status bits. Y ou can use the timer to generate periodic CPU interrupts. Figure 8–4 shows a functional block diagram of the timer .
Timer 8-9 On-Chip Peripherals The TINT request automatically sets the TINT flag bit in the interrupt flag regis- ter (IFR). Y ou can mask or unmask the request with the interrupt mask register (IMR). If you are not using the timer , mask TINT so that it does not cause an unexpected interrupt.
Timer 8-10 sor v are the TIM and PRD, respectively . Both are16-bit registers mapped to I/O space. The 4-bit TDDR (timer divide-down register) and the 4-bit PSC (prescaler counter) are contained in the timer control register (TCR) described in subsec- tion 8.
Timer 8-1 1 On-Chip Peripherals Figure 8–5. ’C2xx Timer Control Register (TCR) — I/O-Space Address FFF8h 15 12 11 10 96 5 4 30 Reserved FREE SOFT PSC TRB TSS TDDR 0 R/W–0 R/W–0 R/W–0 R/W–0 W–0 R/W–0 Note: 0 = Always read as zeros; R = Read access; W = Write access; value following dash (–) is value after reset.
Timer 8-12 Bit 4 TSS — Timer stop status bit. TSS stops or starts the timer . At reset, TSS is cleared to 0 and the timer immediately starts. TSS = 0 Starts or restarts the timer . TSS = 1 Stops the timer . Bits 3–0 TDDR — T imer divide-down register .
Timer 8-13 On-Chip Peripherals 8.4.4 Setting the T imer Interrupt Rate When the divide-down value (TDDR) is 0, you can program the timer to gener- ate an interrupt (TINT) every 2 to 65 536 cycles by programming the period register (PRD) from 0 to 65 535 (FFFFh).
Wait-State Generator 8-14 8.5 W ait-State Generator W ait states are necessary when you want to interface the ’C2xx with slower external logic and memory . By adding wait states, you lengthen the time the CPU waits for external memory or an external I/O port to respond when the CPU reads from or writes to that memory or port.
Wait-State Generator 8-15 On-Chip Peripherals state generator , see subsection 1 1.4.3 on page 1 1-16. T o avoid bus conflicts, all writes to external addresses take at least two cycles.
Wait-State Generator 8-16 T able 8–4 shows how to set the number of wait states you want for each type of off-chip memory . For example, if you write 1s to bits 0 through 5, the device will generate seven wait states for off-chip lower program memory and seven wait states for off-chip upper program memory .
General-Purpose I/O Pins 8-17 On-Chip Peripherals 8.6 General-Purpose I/O Pins The ’C2xx provides pins that can be used to supply input signals from an exter- nal device or output signals to an external device. These pins are not bound to specific uses; rather , they can provide input or output signals for a great vari- ety purposes.
General-Purpose I/O Pins 8-18 Figure 8–7. BIO Timing Diagram Example BIO CLKOUT1 1 CLKOUT1 cycle 8.6.2 Output Pin XF The XF pin is the external flag output pin. If you connect XF to an input pin of another processor , you can use XF as a signal to other processor .
9-1 Synchronous Serial Port Synchronous Serial Port The ’C2xx devices have a synchronous serial port that provides direct communication with serial devices such as codecs (coder/decoders) and serial A/D converters. The serial port may also be used for intercommunication between processors in multiprocessing applications.
Overview of the Synchronous Serial Port 9-2 9.1 Overview of the Synchronous Serial Port Both receive and transmit operations of the synchronous serial port have a four-word-deep first-in, first-out (FIFO) buffer .
Components and Basic Operation 9-3 Synchronous Serial Port 9.2 Components and Basic Operation The synchronous serial port has several hard-wired parts, including two FIFO buffers and six signal pins. Figure 9–1 shows how the components of the syn- chronous serial port are interconnected.
Components and Basic Operation 9-4 Data signal. The data signal carries the actual data that is transferred in the transmit/receive operation. The data signal transmit pin (DX) of one device should be connected to the data signal receive (DR) pin on another device.
Components and Basic Operation 9-5 Synchronous Serial Port Figure 9–2. 2-Way Serial Port T ransfer With External Frame Sync and External Clock TMS320C203 TLC320AD55C Analog signal A/D D/A Analog sig.
Components and Basic Operation 9-6 9.2.3 Interrupts The synchronous serial port (SSP) has two hardware interrupts that let the pro- cessor know when the FIFO buffers need to be serviced: T ransmit interrupts (XINT s) cause a branch to address 000Ah in program space whenever the transmit-interrupt trigger condition is met.
Components and Basic Operation 9-7 Synchronous Serial Port Receiving a word through the serial port typically is done as follows: 1) Data from the DR pin is shifted, bit-by-bit (MSB first), into the receive shift register (RSR). 2) When the RSR is full, the RSR copies the data to the receive FIFO buffer .
Controlling and Resetting the Port 9-8 9.3 Controlling and Resetting the Port The synchronous serial port control register (SSPCR) controls the operation of the synchronous serial port.
Controlling and Resetting the Port 9-9 Synchronous Serial Port T able 9–2. Run and Emulation Modes FREE SOFT Run/Emulation Mode 0 0 Immediate stop 0 1 Stop after completion of word 1 0 Free run 1 1 Free run Note: If an option besides immediate stop is chosen for the receiver , an overflow error is possible.
Controlling and Resetting the Port 9-10 Bits 9–8 FR1, FR0 — FIFO receive-interrupt bits. The values you write to FR0 and FR1 set an interrupt trigger condition based on the contents of the receive FIFO buffer .
Controlling and Resetting the Port 9-1 1 Synchronous Serial Port Bit 3 TXM — T ransmit mode. This bit determines the source device for the frame synchronization (frame sync) pulse for transmissions. It configures the transmit frame sync pin (FSX) as an output or as in input.
Controlling and Resetting the Port 9-12 Bit 0 DLB — Digital loopback mode. The DLB bit can be used to put the serial port in digital loopback mode. DLB = 0 Digital loopback mode is disabled. The DR, FSR, and CLKR signals are connected to their respective device pins.
Controlling and Resetting the Port 9-13 Synchronous Serial Port A transmit frame sync pulse marks the start of a data transmission. The syn- chronous serial port can transmit using the internal frame sync source or using an external source: T o use internal frame sync pulses , set the TXM bit in the SSPCR to 1.
Controlling and Resetting the Port 9-14 1) Create interrupt service routines for XINT s and RINT s and include a branch to each service routine at the appropriate interrupt vector address: The RINT vector is fetched from address 0008h. The XINT vector is fetched from address 000Ah.
Managing the Contents of the FIFO Buffers 9-15 Synchronous Serial Port 9.4 Managing the Contents of the FIFO Buffers The SDTR is a read/write register (at I/O address FFF0h) that is used to send data to the transmit FIFO buffer and to extract data from the receive FIFO buffer .
T ransmitter Operation 9-16 9.5 T ransmitter Operation T ransmitter operation is different in continuous and burst modes. Other differ- ences also depend on whether an internal or an external frame sync is used.
T ransmitter Operation 9-17 Synchronous Serial Port If the SDTR is loaded with a new word while the transmit FIFO buffer is full, the new word will be lost; the FIFO buffer will not accept any more than four words. The burst mode can be discontinued (changed to continuous mode) only by a serial-port or device reset.
T ransmitter Operation 9-18 9.5.2 Burst Mode T ransmission With External Frame Sync (FSM = 1, TXM = 0) Use burst mode transmission with external frame sync to transfer short pack- ets at rates lower than maximum packet frequency while using an external frame sync generator .
T ransmitter Operation 9-19 Synchronous Serial Port Figure 9–5. Burst Mode T ransmission With External Frame Sync FSX CLKX DX XINT A15 MSB A14 A13 A12 A1 1 A10 .
T ransmitter Operation 9-20 9.5.3 Continuous Mode T ransmission With Internal Frame Sync (FSM = 0, TXM = 1) Use continuous mode transmission with internal frame sync to transfer long packets at maximum packet frequency while using an internal frame sync gen- erator .
T ransmitter Operation 9-21 Synchronous Serial Port If the SDTR is loaded with a new word while the transmit FIFO buffer is full, the new word will be lost; the FIFO buffer will not accept any more than four words. Continuous mode can be discontinued (changed to burst mode) only by a seri- al-port or device reset.
T ransmitter Operation 9-22 9.5.4 Continuous Mode T ransmission with External Frame Sync (FSM=0, TXM=0) Use continuous mode transmission with external frame sync to transfer long packets at maximum packet frequency while using an external frame sync generator .
T ransmitter Operation 9-23 Synchronous Serial Port The continuous mode can be discontinued (changed to burst mode) only by a serial-port or device reset. Changing the FSM bit during transmit or halt will not necessarily cause a switch to burst mode. Figure 9–7.
Receiver Operation 9-24 9.6 Receiver Operation Receiver operation is different in continuous and burst modes. The receiver does not generate frame sync pulses; it always takes the frame sync pulse as an input. In selecting the proper receive mode, note that the mode for the receiver must match the mode for the transmitter .
Receiver Operation 9-25 Synchronous Serial Port If a frame sync pulse occurs during reception, reception is restarted, and the bits that were shifted into the RSR before the pulse are lost. Figure 9–8. Burst Mode Reception CLKR FSR DR RINT A15 MSB A14 A13 A12 A1 1 A10 .
Receiver Operation 9-26 3) The remaining bits in the word are then shifted into the RSR, one by one at the falling edge of each consecutive clock cycle. 4) After all bits have been received, if the FIFO buffer is not full, the contents of the RSR are copied to the receive FIFO buffer .
T roubleshooting 9-27 Synchronous Serial Port 9.7 T roubleshooting The synchronous serial port uses three bits for troubleshooting and testing. In addition to using these three bits, you must be able to identify special error conditions that may occur in actual transfers.
T roubleshooting 9-28 T able 9–6. Run and Emulation Modes FREE SOFT Run/Emulation Mode 0 0 Immediate stop 0 1 Stop after completion of word 1 0 Free run 1 1 Free run Note: If an option besides immediate stop is chosen for the receiver , an overflow error is possible.
T roubleshooting 9-29 Synchronous Serial Port 9.7.2 Burst Mode Error Conditions The following are descriptions of errors that can occur in burst mode: Underflow . Underflow is caused if an external FSX occurs, and there are no new words in the transmit FIFO buffer .
T roubleshooting 9-30 Overflow . Overflow occurs when the RSR has new data to pass to the receive FIFO buffer but the FIFO buf fer is full. Overflow errors are fatal to a reception. For as long as the FIFO buffer is full, any incoming words will be lost.
10-1 Asynchronous Serial Port Asynchronous Serial Port The ’C2xx has an asynchronous serial port that can be used to transfer data to and from other devices.
Overview of the Asynchronous Serial Port 10-2 10.1 Overview of the Asynchronous Serial Port The on-chip asynchronous serial port (ASP) provides easy serial data commu- nication between host CPUs and the ’C2xx or between two ’C2xx devices.
Components and Basic Operation 10-3 Asynchronous Serial Port 10.2 Components and Basic Operation Figure 10–1 shows the main components of the asynchronous serial port.
Components and Basic Operation 10-4 T able 10–1. Asynchronous Serial Port Interface Pins Pin Name Description TX Asynchronous serial port data transmit pin. T ransmits serial data from the asynchronous serial port transmit shift register (AXSR). RX Asynchronous serial port data receive pin.
Components and Basic Operation 10-5 Asynchronous Serial Port I/O status register (IOSR). Bits in the IOSR indicate detection of the in- coming baud rate, various error conditions, the status of data transfers, detection of a break on the RX pin, the status of pins IO3–IO0, and detec- tion of changes on pins IO3–IO0.
Components and Basic Operation 10-6 10.2.5 Basic Operation Figure 10–2 shows a typical serial link between a ’C2xx device and any host CPU. In this mode of communication, any 8-bit character can be transmitted or received serially by way of the transmit data pin (TX) or the receive data pin (RX), respectively .
Controlling and Resetting the Port 10-7 Asynchronous Serial Port 10.3 Controlling and Resetting the Port The asynchronous serial port is programmed through three on-chip registers mapped to I/O space: the asynchronous serial port control register (ASPCR), the I/O status register (IOSR), and the baud-rate divisor register (BRD).
Controlling and Resetting the Port 10-8 Bits 12–10 Reserved. Always read as 0s. Bit 9 DIM — Delta interrupt mask. DIM selects whether or not delta interrupts are asserted on the TXRXINT interrupt line. A delta interrupt is generated by a change on one of the general-purpose I/O pins (IO3, IO2, IO1, or IO0).
Controlling and Resetting the Port 10-9 Asynchronous Serial Port Bit 3 CIO3 — Configuration bit for IO3. CIO3 configures I/O pin 3 (IO3) as an input or as an output. CIO3 = 0 IO3 is configured as an input. This is the default value at re- set. CIO3 = 1 IO3 is configured as an output.
Controlling and Resetting the Port 10-10 10.3.2 I/O Status Register (IOSR) The IOSR returns the status of the asynchronous serial port and of I/O pins IO0–IO3. The IOSR is a 16-bit, on-chip register mapped to address FFF6h in I/O space. Figure 10–4 shows the fields in the IOSR, and bit descriptions fol- low the figure.
Controlling and Resetting the Port 10-1 1 Asynchronous Serial Port Bit 1 1 THRE — T ransmit register (ADTR) empty indicator . THRE is set to 1 when the contents of the transmit register (ADTR) are transferred to the transmit shift register (AXSR). THRE is reset to 0 by the loading of the trans- mit register with a new character .
Controlling and Resetting the Port 10-12 Bit 7 DIO3 — Change detect bit for IO3. DIO3 indicates whether a change has occurred on the IO3 pin. A change can be detected only when IO3 is config- ured as an input by the CIO3 bit of the ASPCR (CIO3 = 0) and the serial port is enabled by the URST bit of the ASPCR (URST = 1).
Controlling and Resetting the Port 10-13 Asynchronous Serial Port Bit 3 IO3 — Status bit for IO3. When the IO3 pin is configured as an input (by the CIO3 bit of the ASPCR), this bit reflects the current level on the IO3 pin. IO3 = 0 The IO3 signal is low .
Controlling and Resetting the Port 10-14 T able 10–2. Common Baud Rates and the Corresponding BRD V alues BRD V alue in Hexadecimal Baud Rate CLKOUT1 = 20 MHz (50 ns) CLKOUT1 = 28.57 MHz (35 ns) CLKOUT1 = 40 MHz (25 ns) 1200 041 1 05CC 0823 2400 0208 02E6 041 1 4800 0104 0173 0208 9600 0082 00B9 0104 19200 0041 005C 0082 10.
Controlling and Resetting the Port 10-15 Asynchronous Serial Port 10.3.5 Using I/O Pins IO3, IO2, IO1, and IO0 Pins IO3, IO2, IO1, and IO0 can be individually configured as inputs or outputs and can be used as handshake control for the asynchronous serial port or as general-purpose I/O pins.
Controlling and Resetting the Port 10-16 When pins IO0–IO3 are configured as inputs When pins IO0–IO3 are configured as inputs, the eight LSBs of the IOSR allow you to monitor these four pins.
Controlling and Resetting the Port 10-17 Asynchronous Serial Port 10.3.6 Using Interrupts The asynchronous serial port interrupt (TXRXINT) can be generated by three types of interrupts: T ransmit interrupts. A transmit interrupt is generated when the ADTR empties during transmission.
Controlling and Resetting the Port 10-18 TXRXINT leads the CPU to interrupt vector location 000Ch in program memory . The branch at that location should lead to an interrupt service routine that identifies the cause of the interrupt and then acts accordingly .
T ransmitter Operation 10-19 Asynchronous Serial Port 10.4 T ransmitter Operation The transmitter consists of an 8-bit transmit register (ADTR) and an 8-bit trans- mit shift register (AXSR). Data to be transmitted is written to the ADTR, and then the port transfers the data to the AXSR.
Receiver Operation 10-20 10.5 Receiver Operation The receiver includes two internal 8-bit registers: the receive register (ADTR) and receive shift register (ARSR). The data received at the RX pin should have the serial form shown in Figure 10–7 (the number of stop bits required de- pends on the value of the STB bit in the ASPCR).
1 1-1 TMS320C209 All ’C2xx devices use the same central processing unit (CPU), bus structure, and instruction set, but the ’C209 has some notable differences.
’C209 V ersus Other ’C2xx Devices 1 1-2 1 1.1 ’C209 V ersus Other ’C2xx Devices This section explains the differences between the ’C209 and other ’C2xx de- vices and concludes with a table to help you find the other information in this manual that applies to the ’C209.
’C209 V ersus Other ’C2xx Devices 1 1-3 TMS320C209 Memory and I/O Spaces: The I/O addresses of the peripheral registers are different on the ’C209. The ’C209 does not support the ’C2xx HOLD operation. Interrupts: The ’C209 has four maskable interrupt lines, none of them shared.
’C209 V ersus Other ’C2xx Devices 1 1-4 For information about: Look here: Interrupts Main description Chapter 5, Program Control V ector locations T able 1 1–4 (page 1 1-10) Flag and mask registers Subsection 1 1.3.1 (page 1 1-1 1) Interrupt acknowledge pin Subsection 1 1.
’C209 Memory and I/O Spaces 1 1-5 TMS320C209 1 1.2 ’C209 Memory and I/O Spaces The ’C209 does not have an on-chip boot loader and does not support the ’C2xx HOLD operation.
’C209 Memory and I/O Spaces 1 1-6 Figure 1 1–1. ’C209 Address Maps ’C209 Program ’C209 Data FFFFh 2000h 1FFFh 1000h 0FFFh 0800h 0400h 03FFh 0300h 02FFh 0200h 01FFh 0080h 007Fh 0060h 005Fh 00.
’C209 Memory and I/O Spaces 1 1-7 TMS320C209 Do Not Write to Reserved Addresses T o avoid unpredictable operation of the processor , do not write to any addresses labeled Reserved.
’C209 Memory and I/O Spaces 1 1-8 (4K) are mapped to external data memory . Thus, a total of 8K additional addresses (4K program and 4K data) are available for external memory .
’C209 Memory and I/O Spaces 1 1-9 TMS320C209 T able 1 1–2. ’C209 Data-Memory Configuration Options RAMEN CNF DARAM B0 (hex) DARAM B1 (hex) DARAM B2 (hex) SARAM (hex) External (hex) Reserved (hex.
’C209 Interrupts 1 1-10 1 1.3 ’C209 Interrupts T able 1 1–4 lists the interrupts available on the ’C209 and shows their vector locations. In addition, it shows the priority of each of the hardware interrupts. Note that a device reset can be initiated in either of two ways: by driving the RS pin low or by driving the RS pin high.
’C209 Interrupts 1 1-1 1 TMS320C209 T able 1 1–4. ’C209 Interrupt Locations and Priorities (Continued) K † V ector Location Name Priority Function 15 1Eh INT15 – User-defined software interr.
’C209 Interrupts 1 1-12 Figure 1 1–2. ’C209 Interrupt Flag Register (IFR) — Data-Memory Address 0006h 15 4 3 2 1 0 Reserved TINT INT3 INT2 INT1 0 R/W1C–0 R/W1C–0 R/W1C–0 R/W1C–0 Note: 0 = Always read as zeros; R = Read access; W1C = Write 1 to this bit to clear it to 0; value following dash (–) is value after reset.
’C209 Interrupts 1 1-13 TMS320C209 Figure 1 1–3. ’C209 Interrupt Mask Register (IMR) — Data-Memory Address 0004h 15 4 3 2 1 0 Reserved TINT INT3 INT2 INT1 0 R/W–0 R/W–0 R/W–0 R/W–0 Note: Note: 0 = Always read as zeros; R = Read access; W = Write access; value following dash (–) is value after reset.
’C209 On-Chip Peripherals 1 1-14 1 1.4 ’C209 On-Chip Peripherals The ’C209 has these on-chip peripherals: Clock generator . The clock generator is fundamentally the same on all ’C2xx devices, including the ’C209. However , the ’C209 is limited to the two clock modes described in subsection 1 1.
’C209 On-Chip Peripherals 1 1-15 TMS320C209 T able 1 1–5. ’C209 Input Clock Modes Clock Mode CLKOUT1 Rate CLKMOD Oscillator PLL ÷ 2 CLKOUT1 = CLKIN ÷ 2 0 Enabled Disabled × 2 CLKOUT1 = CLKIN × 2 1 Disabled Enabled Remember the following points when configuring the clock mode: The modes cannot be configured dynamically .
’C209 On-Chip Peripherals 1 1-16 Bit 4 TSS — Timer stop status bit. TSS is a 1-bit flag that stops or starts the timer . T o stop the timer , set TSS to 1. T o start or restart the timer , set TSS to 0. At reset, TSS is cleared to 0 and the timer immediately starts.
’C209 On-Chip Peripherals 1 1-17 TMS320C209 Figure 1 1–5. ’C209 Wait-State Generator Control Register (WSGR) — I/O Address FFFFh 15–4 3 2 1 0 Reserved A VIS ISWS DSWS PSWS 0 W–1 W–1 W–1 W–1 Note: 0 = Always read as zeros; W = Write access; value following dash (–) is value after reset.
A-1 Appendix A Register Summary For the status and control registers of the ’C2xx devices, this appendix summarizes: Their addresses Their reset values The functions of their bits T opic Page A.1 Addresses and Reset V alues A-2 . . . . . . . . . . .
Addresses and Reset V alues A-2 A.1 Addresses and Reset V alues The following tables list the ’C2xx registers, the addresses at which they can be accessed, and their reset values. Note that the registers mapped to internal I/O space on the ’C209 are at addresses different from those of other ’C2xx devices.
Addresses and Reset V alues A-3 Register Summary T able A–3. Addresses and Reset V alues of On-Chip Registers Mapped to I/O Space (Continued) I/O Address Name Description Reset V alue Other ’C2xx .
Register Descriptions A-4 A.2 Register Descriptions The following figures summarize the content of the ’C2xx status and control registers that are divided into fields. (The other registers contain no control bits; they simply hold a single 16-bit value.
Register Descriptions A-5 Register Summary Status Register ST0 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 X X X 0 X 1 † 1 X X X X X X X X X ARP OV OVM INTM DP All unmasked interrupts enabled All unmasked interrupts disabled 0 1 Auxiliary register pointer Selects the current page (0, 1, 2, .
Register Descriptions A-6 ’C2xx Interrupt Flag Register (IFR) — Except ’C209 — Data-Memory Address 0006h 15 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Reserved † TXRXINT XINT RINT TINT INT2/INT3 HOLD/INT1 .
Register Descriptions A-7 Register Summary Interrupt Mask Register (IMR) — Except ’C209 — Data-Memory Address 0004h 15 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Reserved † TXRXINT XINT RINT TINT INT2/INT3 H.
Register Descriptions A-8 Interrupt Control Register (ICR) — I/O Address FFECh 15 5 4 3 2 1 0 0 0 0 0 0 0 Reserved † MODE FINT3 FINT2 MINT3 MINT2 INT3 request will not reach CPU. INT3 request will reach CPU. 0 1 Double-edge mode. HOLD/INT1 pin both negative- and positive-edge sensitive Single-edge mode.
Register Descriptions A-9 Register Summary Timer Control Register (TCR) — Except ’C209 — I/O Address FFF8h 15 12 11 10 96 5 4 30 0 000000 Reserved † FREE SOFT PSC TRB TSS TDDR Start or restart timer . Stop timer . 0 0 1 1 Stop after the next decrement of the TIM (hard stop).
Register Descriptions A-10 Wait-State Generator Control Register (WSGR) — Except ’C209— I/O Address FFFCh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Reserved † ISWS DSWS P.
Register Descriptions A-1 1 Register Summary CLK Register — I/O Address FFE8h 15 1 0 0 0 Reserved † CLKOUT1 0 1 CLKOUT1 signal available at CLKOUT1 pin CLKOUT1 signal not available at CLKOUT1 pin R/W CLKOUT1 pin control † These reserved bits are always read as 0s.
Register Descriptions A-12 Synchronous Serial Port Control Register (SSPCR) — I/O Address FFF1h 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 FREE SOFT TCOMP RFNE FT1 FT0 FR1 FR0 0 1 0 1 Immediate stop Stop after completion of word Free run Free run 0 0 1 1 0 1 T ransmit buffer empty .
Register Descriptions A-13 Register Summary Asynchronous Serial Port Control Register (ASPCR) — I/O Address FFF5h 15 14 13 12 11 10 9 8 0 0 0 0 0 0 FREE SOFT URST Reserved † DIM TIM Immediate stop Process stops after character completion.
Register Descriptions A-14 I/O Status Register (IOSR) — I/O Address FFF6h 15 14 13 12 11 10 9 8 0 0 0 1 1 0 0 0 Reserved † ADC ‡ BI ‡ TEMT THRE ‡ FE ‡ OE ‡ DR ‡ R R/W1C R/W1C 0 1 Normal operation. CAD bit of ASPCR is 1 and A or a is received in ADTR.
B-1 Appendix A TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison This appendix contains a table that compares the TMS320C1x, TMS320C2x, TMS320C2xx, and TMS320C5x instructions alphabetically . Each table entry shows the syntax for the instruction, indicates which devices support the instruction, and describes the operation of the instruction.
Using the Instruction Set Comparison T able B-2 B.1 Using the Instruction Set Comparison T able T o help you read the comparison table, this section provides an example of a table entry and a list of acronyms.
Using the Instruction Set Comparison T able B-3 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison B.1.2 Symbols and Acronyms Used in the T able The following table lists the instruction set symbols and acronyms used throughout this chapter: T able B–1.
Using the Instruction Set Comparison T able B-4 Based on the device, this is how the indirect addressing operand {ind} is interpreted: {ind} ’C1x : { * | *+ | *– } ’C2x : { * | *+ | *– | *0+| .
Enhanced Instructions B-5 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison B.2 Enhanced Instructions An enhanced instruction is a single mnemonic that performs the functions of several similar instructions.
Instruction Set Comparison T able B-6 B.3 Instruction Set Comparison T able Syntax 1x 2x 2xx 5x Description ABS √ √ √ √ Absolute V alue of Accumulator If the contents of the accumulator are less than zero, replace the contents with the 2s complement of the contents.
Instruction Set Comparison T able B-7 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison Syntax Description 5x 2xx 2x 1x ADDK # k √ √ √ Add to Accumulator Short Immediate TMS320C1x devices: Add an 8-bit immediate value to the accumulator .
Instruction Set Comparison T able B-8 Syntax Description 5x 2xx 2x 1x AND dma AND { ind } [ , next ARP ] AND # lk [ , shift ] √ √ √ √ √ √ √ √ √ √ AND With Accumulator TMS320C1x and TMS320C2x devices: AND the con- tents of the addressed data-memory location with the 16 LSBs of the accumulator .
Instruction Set Comparison T able B-9 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison Syntax Description 5x 2xx 2x 1x B [ D ] pma [ , { ind } [ , next ARP ]] √ Branch Unconditionally With Optional Delay Modify the current auxiliary register and ARP as speci- fied and pass control to the designated program- memory address.
Instruction Set Comparison T able B-10 Syntax Description 5x 2xx 2x 1x BBNZ pma [ , { ind } [ , next ARP ]] √ √ √ Branch on Bit ≠ Zero If the TC bit = 1, branch to the specified program- memory address. TMS320C2x devices: Modify the current AR and ARP as specified.
Instruction Set Comparison T able B-1 1 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison Syntax Description 5x 2xx 2x 1x BGEZ pma BGEZ pma [ , { ind } [ , next ARP ]] √ √ √ √ √ Branch if Accumulator ≥ Zero If the contents of the accumulator ≥ 0, branch to the specified program-memory address.
Instruction Set Comparison T able B-12 Syntax Description 5x 2xx 2x 1x BLDD # lk, dma BLDD # lk, { ind } [ , next ARP ] BLDD dma, # lk BLDD { ind } , # lk [ , next ARP ] BLDD BMAR, dma BLDD BMAR, { in.
Instruction Set Comparison T able B-13 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison Syntax Description 5x 2xx 2x 1x BLKD dma1, dma2 BLKD dma1, { ind } [ , next ARP ] √ √ √ √ √ √ Block Move From Data Memory to Data Memory Move a block of words from one location in data mem- ory to another location in data memory .
Instruction Set Comparison T able B-14 Syntax Description 5x 2xx 2x 1x BNC pma [ , { ind } [ , next ARP ]] √ √ √ Branch on No Carry If the C bit = 0, branch to the specified program- memory address. TMS320C2x devices: Modify the current AR and ARP as specified.
Instruction Set Comparison T able B-15 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison Syntax Description 5x 2xx 2x 1x BZ pma BZ pma [ , { ind } [ , next ARP ]] √ √ √ √ Branch if Accumulator = Zero If the contents of the accumulator = 0, branch to the specified program-memory address.
Instruction Set Comparison T able B-16 Syntax Description 5x 2xx 2x 1x CC pma, cond 1 [ , cond 2 ] [, ...] √ Call Conditionally If the specified conditions are met, control is passed to the pma. Not all combinations of conditions are mean- ingful. CC [ D ] pma , cond 1 [ , cond 2 ] [, .
Instruction Set Comparison T able B-17 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison Syntax Description 5x 2xx 2x 1x CNFP √ √ √ Configure Block as Program Memory Configure on-chip RAM block B0 as program memory . Block B0 is mapped into program-memory locations 65280h–65535h.
Instruction Set Comparison T able B-18 Syntax Description 5x 2xx 2x 1x EINT √ √ √ √ Enable Interrupts Enable all interrupts; clear the INTM to 0. Maskable interrupts are enabled immediately after the EINT instruction executes. EXAR √ Exchange ACCB With ACC Exchange the contents of the ACC with the contents of the ACCB.
Instruction Set Comparison T able B-19 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison Syntax Description 5x 2xx 2x 1x INTR K √ √ Soft Interrupt T ransfer program control to the program-memory ad- dress specified by K (an integer from 0 to 31). This in- struction allows you to use your software to execute any interrupt service routine.
Instruction Set Comparison T able B-20 Syntax Description 5x 2xx 2x 1x LACT dma LACT { ind } [ , next ARP ] √ √ √ √ √ √ Load Accumulator With Shift Specified by T Register Left shift the contents of the addressed data-memory location by the value specified in the 4 LSBs of the T register; load the result into the accumulator .
Instruction Set Comparison T able B-21 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison Syntax Description 5x 2xx 2x 1x LDP dma LDP { ind } [ , next ARP ] LDP # k √ √ √ √ √ √ √ √ √ √ Load Data-Memory Page Pointer TMS320C1x devices: Load the LSB of the contents of the addressed data-memory location into the DP regis- ter .
Instruction Set Comparison T able B-22 Syntax Description 5x 2xx 2x 1x LST # n, dma LST # n, { ind } [ , next ARP ] √ √ √ √ √ √ Load Status Register n Load the contents of the addressed data-memory lo- cation into ST n .
Instruction Set Comparison T able B-23 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison Syntax Description 5x 2xx 2x 1x MAC pma, dma MAC pma, { ind } [ , next ARP ] √ √ √ √ √ √ Multiply a.
Instruction Set Comparison T able B-24 Syntax Description 5x 2xx 2x 1x MPY A dma MPY A { ind } [ , next ARP ] √ √ √ √ √ √ Multiply and Accumulate Previous Product Multiply the contents of the T register (TMS320C2x/ 2xx) or TREG0 (TMS320C5x) by the contents of the addressed data-memory location; place the result in the P register .
Instruction Set Comparison T able B-25 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison Syntax Description 5x 2xx 2x 1x OR dma OR { ind } [ , next ARP ] OR # lk [ , shift ] √ √ √ √ √ √ .
Instruction Set Comparison T able B-26 Syntax Description 5x 2xx 2x 1x POPD dma POPD { ind } [ , next ARP ] √ √ √ √ √ √ Pop T op of Stack to Data Memory T ransfer the value on the top of the stack into the ad- dressed data-memory location and then pop the stack one level.
Instruction Set Comparison T able B-27 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison Syntax Description 5x 2xx 2x 1x RETE √ Enable Interrupts and Return From Interrupt Copy the contents of the top of the stack into the PC and pop the stack one level.
Instruction Set Comparison T able B-28 Syntax Description 5x 2xx 2x 1x RPT dma RPT { ind } [ , next ARP ] RPT # k RPT # lk √ √ √ √ √ √ √ √ √ √ Repeat Next Instruction TMS320C2x devices: Load the 8 LSBs of the ad- dressed value into the RPTC; the instruction following RPT is executed the number of times indicated by RPTC + 1.
Instruction Set Comparison T able B-29 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison Syntax Description 5x 2xx 2x 1x SACH dma [ , shift ] SACH { ind } [ , shift [ , next ARP ]] √ √ √ √ √ √ √ √ Store High Accumulator With Shift Copy the contents of the accumulator into a shifter .
Instruction Set Comparison T able B-30 Syntax Description 5x 2xx 2x 1x SBBB √ Subtract ACCB From Accumulator With Borrow Subtract the contents of the ACCB and the logical in- version of the carry bit from the accumulator . The result is stored in the accumulator; the accumulator buffer is not affected.
Instruction Set Comparison T able B-31 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison Syntax Description 5x 2xx 2x 1x SHM √ √ Set Hold Mode Set the HM status bit to 1.
Instruction Set Comparison T able B-32 Syntax Description 5x 2xx 2x 1x SQRA dma SQRA { ind } [ , next ARP ] √ √ √ √ √ √ Square and Accumulate Previous Product Add the contents of the P register (shifted as specified by the PM status bits) to the accumulator .
Instruction Set Comparison T able B-33 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison Syntax Description 5x 2xx 2x 1x SUB dma [ , shift ] SUB { ind } [ , shift [ , next ARP ]] SUB # k SUB # lk [ , .
Instruction Set Comparison T able B-34 Syntax Description 5x 2xx 2x 1x SUBT dma SUBT { ind } [ , next ARP ] √ √ √ √ √ √ Subtract From Accumulator With Shift Specified by T Register Left sh.
Instruction Set Comparison T able B-35 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison Syntax Description 5x 2xx 2x 1x XOR dma XOR { ind } [ , next ARP ] XOR # lk [ , shift ] √ √ √ √ √ √.
Instruction Set Comparison T able B-36 Syntax Description 5x 2xx 2x 1x ZALR dma ZALR { ind } [ , next ARP ] √ √ √ √ √ √ Zero Low Accumulator , Load High Accumulator With Rounding Load the contents of the addressed data-memory location into the 16 MSBs of the accumulator .
C-1 Appendix A Program Examples This appendix provides: A brief introduction to the process for generating executable program files. Sample programs for implementing simple routines and using interrupts, I/O pins, the timer , and the serial ports. This appendix is not intended to teach you how to use the software develop- ment tools.
About These Program Examples C-2 C.1 About These Program Examples Figure C–1 illustrates the basic process for creating assembly language files and then generating executable files from them: 1) Use the ’C2xx assembler to create: A command file ( c203.
About These Program Examples C-3 Program Examples The program examples in Section C.2 and Section C.3 consist of code for shared files and task-specific files. T able C–1 describes the shared programs. Shared files contain code that is used by multiple task-specific files.
About These Program Examples C-4 T able C–2. T ask-Specific Programs in This Appendix (Continued) Program Functional Description See ... uart.asm Causes the asynchronous serial port to transmit a test message continuously at 1200 baud. Baud rate is 1200 at 50-ns cycle time.
Shared Program Code C-5 Program Examples C.2 Shared Program Code Example C–1. Generic Command File (c203.cmd) /* Title: c203.cmd */ /* Generic command file for linking TMS320C2xx assembler files */ /* input files: *.obj files */ /* output files: *.out file */ /* Map files: *.
Shared Program Code C-6 Example C–2. Header File With I/O Register Declarations (init.h) * File: init.h * * Include file with I/O register declarations * .mmregs ; Include reserved words .bss dmem,10 ; Undefined variables space .def ini_d, start,codtx ; Directive for symbol address ; generation in the current module ; –optional ini_d: .
Shared Program Code C-7 Program Examples Example C–3. Header File With Interrupt V ector Declarations (vector .h) * File: vector.h * * File defines Interrupt vector labels * .
T ask-Specific Program Code C-8 C.3 T ask-Specific Program Code Example C–4. Implementing Simple Delay Loops (delay .asm) * File: delay.asm * * Function: Delay loop. XF and I/O 3 pins toggle after each delay * .title ”Delay routine” ; Title .copy ”init.
T ask-Specific Program Code C-9 Program Examples Example C–5. T esting and Using the Timer (timer.asm) * File: timer.asm * * Function: Timer test code * * PRD=0x00ff,TDDR=f @ 50ns, gives an interrupt interval=205us * * PRD=0xffff,TDDR=0 @ 50ns, gives an interrupt interval=3.
T ask-Specific Program Code C-10 Example C–6. T esting and Using Interrupt INT1 (intr1.asm) * File: intr1.asm * * Function: Interrupt test code * * For each INT1 interrupt XF,I/O pins IO3 and IO2 will toggle and * * transmit char ’c’ through UART * .
T ask-Specific Program Code C-1 1 Program Examples Example C–7. Implementing a HOLD Operation (hold.asm) * File: hold.asm * * Function: HOLD test code * * Check for HOLDA toggle for HOLD requests in MODE 0 * * Check for XF toggle on HOLD/INT1 requests in MODE 1 * .
T ask-Specific Program Code C-12 Example C–8. T esting and Using Interrupts INT2 and INT3 (intr23.asm) * File: intr23.asm * * Function: Interrupt test code * * Interrupt on INT2 or INT3 will toggle IO3 and IO2 bits * * and icr value copied in the Buffer @300 * .
T ask-Specific Program Code C-13 Program Examples Example C–9. Asynchronous Serial Port T ransmission (uart.asm) * File: uart.asm * * Function: UART Test Code * * Continuously sends ’’C203 UART is fine’ at 1200 baud. * .title ” UART Test” ; Title .
T ask-Specific Program Code C-14 Example C–9. Asynchronous Serial Port T ransmission (uart.asm) (Continued) lar ar1,#rxbuf lar ar0, #20 ; load buffer size mar *,ar1 ; load data pointer clrc intm wai.
T ask-Specific Program Code C-15 Program Examples Example C–10. Loopback to V erify T ransmissions of Asynchronous Serial Port (echo.asm) (Continued) * UART initialization * splk #0ffffh,ifr ; clear.
T ask-Specific Program Code C-16 Example C–1 1. T esting and Using Automatic Baud-Rate Detection on Asynchronous Serial Port (autobaud.asm) * File: autobaud.asm * * Function: UART,auto baud test * * Locks to incoming baud rate if the first character * * is ”A” or ”a” & continuously echoes data received * * through the port.
T ask-Specific Program Code C-17 Program Examples Example C–1 1. T esting and Using Automatic Baud-Rate Detection on Asynchronous Serial Port (autobaud.
T ask-Specific Program Code C-18 Example C–12. T esting and Using Asynchronous Serial Port Delta Interrupts (bitio.asm) * File: bitio.asm * * Function: Delta interrupt test code * * Accepts delta interrupt on IO pins 3 and 2 * * If bit level changes on bit 7, send character ’c’ * * through UART & toggle xf pin.
T ask-Specific Program Code C-19 Program Examples Example C–12. T esting and Using Asynchronous Serial Port Delta Interrupts(bitio.asm) (Continued) uart: setc xf ; toggle xf bit in 68h,iosr ; Bit i/.
T ask-Specific Program Code C-20 Example C–13. Synchronous Serial Port Continuous Mode T ransmission (ssp.asm) * File: ssp.asm * * Function: Continuous transmit in CONTINUOUS mode * * Internal shift clock and frame sync * * Transmit FIFO level is set to 4 * .
T ask-Specific Program Code C-21 Program Examples Example C–14. Using Synchronous Serial Port With Codec Device (ad55.asm) * File: ad55.asm * * Function: Burst mode simple loop back on AD55 CODEC * * CODEC master clock 10 MHz * * Simple I/O at 9.6-kHz sampling * .
T ask-Specific Program Code C-22 Example C–14. Using Synchronous Serial Port With Codec Device (ad55.asm) (Continued) codtx: splk #0010h, ifr ; clear tx intr flag clrc intm ret codrx: setc xf ; togg.
Introduction to Generating Boot Loader Code C-23 Program Examples C.4 Introduction to Generating Boot Loader Code The ’C2xx on-chip boot loader boots software from an 8-bit external EPROM to a 16-bit external RAM at reset.
Introduction to Generating Boot Loader Code C-24 Example C–15. Linker Command File MEMORY { PAGE 0: /* PM – Program memory */ EX1_PM :ORIGIN=0H , LENGTH=0FEFFH /* External program RAM */ B0_PM :OR.
D-1 Appendix A Submitting ROM Codes to TI The size of a printed circuit board is a consideration in many DSP applications. T o make full use of the board space, T exas Instruments offers this ROM code option that reduces the chip count and provides a single-chip solution.
D-2 Figure D–1. TMS320 ROM Code Submittal Flow Chart Customer TMS320 Design Customer submits: — TMS320 New Code Release Form — Print Evaluation and Acceptance Form (PEAF) — Purchase order for .
D-3 Submitting ROM Codes to TI The TMS320 ROM code may be submitted in one of the following forms: 5-1/4-in floppy: COFF format from macro-assembler/linker (preferred) Modem (BBS): COFF format from ma.
E-1 Appendix A Design Considerations for Using XDS510 Emulato r This appendix assists you in meeting the design requirements of the T exas Instruments XDS510 emulator with respect to IEEE-1 149.1 designs and discusses the XDS510 cable (manufacturing part number 2617698-0001).
Designing Y our T arget System’ s Emulator Connector (14-Pin Header) E-2 E.1 Designing Y our T arget System’ s Emulator Connector (14-Pin Header) JT AG target devices support emulation through a dedicated emulation port.
Designing Y our T arget System’ s Emulator Connector (14-Pin Header) E-3 Design Considerations for Using XDS510 Emulato r T able E–1. 14-Pin Header Signal Descriptions Signal Description Emulator † State T arget † State EMU0 Emulation pin 0 I I/O EMU1 Emulation pin 1 I I/O GND Ground PD(V CC ) Presence detect.
Bus Protocol E-4 E.2 Bus Protocol The IEEE 1 149.1 specification covers the requirements for the test access port (T AP) bus slave devices and provides certain rules, summarized as follows: The TMS and TDI inputs are sampled on the rising edge of the TCK signal of the device.
Emulator Cable Pod E-5 Design Considerations for Using XDS510 Emulato r E.3 Emulator Cable Pod Figure E–2 shows a portion of the emulator cable pod. The functional features of the pod are: TDO and TCK_RET can be parallel-terminated inside the pod if required by the application.
Emulator Cable Pod Signal Timing E-6 E.4 Emulator Cable Pod Signal Timing Figure E–3 shows the signal timings for the emulator cable pod. T able E–2 defines the timing parameters illustrated in the figure.
Emulation Timing Calculations E-7 Design Considerations for Using XDS510 Emulato r E.5 Emulation Timing Calculations Example E–1 and Example E–2 help you calculate emulation timings in your system. For actual target timing parameters, see the appropriate data sheet for the device you are emulating.
Emulation Timing Calculations E-8 Example E–1. Key T iming for a Single-Processor System Without Buffers t pd TCK_RET-TMS TDI t d TMSmax t su TTMS t TCKfactor ( 20 ns 10 ns ) 0.4 75 ns, or 13.3 MHz t pd TCK_RET–TDO t d TTDO t su TDOmin t TCKfactor ( 15 ns 3n s ) 0.
Emulation Timing Calculations E-9 Design Considerations for Using XDS510 Emulato r In a multiprocessor application, it is necessary to ensure that the EMU0 and EMU1 lines can go from a logic low level to a logic high level in less than 10 µ s, this parameter is called rise time, t r .
Connections Between the Emulator and the T arget System E-10 E.6 Connections Between the Emulator and the T arget System It is extremely important to provide high-quality signals between the emulator and the JT AG target system.
Connections Between the Emulator and the T arget System E-1 1 Design Considerations for Using XDS510 Emulato r Figure E–5. Emulator Connections With Signal Buffering V CC Emulator header V CC GND 12.
Connections Between the Emulator and the T arget System E-12 E.6.2 Using a T arget-System Clock Figure E–6 shows an application with the system test clock generated in the target system. In this application, the emulator ’ s TCK signal is left uncon- nected.
Connections Between the Emulator and the T arget System E-13 Design Considerations for Using XDS510 Emulato r E.6.3 Configuring Multiple Processors Figure E–7 shows a typical daisy-chained multiprocessor configuration that meets the minimum requirements of the IEEE 1 149.
Physical Dimensions for the 14-Pin Emulator Connector E-14 E.7 Physical Dimensions for the 14-Pin Emulator Connector The JT AG emulator target cable consists of a 3-foot section of jacketed cable that connects to the emulator , an active cable pod, and a short section of jack- eted cable that connects to the target system.
Physical Dimensions for the 14-Pin Emulator Connector E-15 Design Considerations for Using XDS510 Emulato r Figure E–9. 14-Pin Connector Dimensions 0.100 inch, nominal (pin spacing) Key , pin 6 0.100 inch, nominal (pin spacing) 0.87 inch, nominal 0.
Emulation Design Considerations E-16 E.8 Emulation Design Considerations This section describes the use and application of the scan path linker (SPL), which can simultaneously add all four secondary JT AG scan paths to the main scan path. It also describes the use of the emulation pins and the configuration of multiple processors.
Emulation Design Considerations E-17 Design Considerations for Using XDS510 Emulato r Figure E–10. Connecting a Secondary JT AG Scan Path to a Scan Path Linker TDI TCK TDO TRST TMS TDO TRST TCK TMS TDI DTDI0 DTMS0 DTDO0 DTCK TDO TRST TCK TMS TDI SPL JT AG 0 JT AG N DTDI1 DTMS1 DTDO1 DTDI2 DTMS2 DTDO2 DTDI3 DTMS3 DTDO3 .
Emulation Design Considerations E-18 E.8.2 Emulation Timing Calculations for a Scan Path Linker (SPL) Example E–3 and Example E–4 help you to calculate the key emulation tim- ings in the SPL secondary scan path of your system. For actual target timing parameters, see the appropriate device data sheet for your target device.
Emulation Design Considerations E-19 Design Considerations for Using XDS510 Emulato r Of the following two cases, the worst-case path delay is calculated to deter- mine the maximum system test clock frequency .
Emulation Design Considerations E-20 E.8.3 Using Emulation Pins The EMU0/1 pins of TI devices are bidirectional, 3-state output pins. When in an inactive state, these pins are at high impedance. When the pins are active, they provide one of two types of output: Signal Event.
Emulation Design Considerations E-21 Design Considerations for Using XDS510 Emulato r Figure E–1 1. EMU0/1 Configuration to Meet Timing Requirements of Less Than 25 ns Open- collector drivers EMU0/1-IN Backplane T arget board m TCK XCNT_ENABLE T o emulator EMU0 PA L Pullup resistor Open- collector drivers T arget board 1 EMU0/1 EMU0/1-OUT .
Emulation Design Considerations E-22 The bused EMU0/1 signals go into a programmable logic array device PA L whose function is to generate a low pulse on the EMU0/1-IN signal when a low level is detected on the EMU0/1-OUT signal.
Emulation Design Considerations E-23 Design Considerations for Using XDS510 Emulato r Figure E–13. EMU0/1 Configuration With Additional AND Gate to Meet T iming Requirements of Greater Than 25 ns Op.
Emulation Design Considerations E-24 Y ou do not need to have devices on one target board stop devices on another target board using the EMU0/1 signals (see the circuit in Figure E–14). In this configuration, the global-stop capability is lost. It is important not to overload EMU0/1 with more than 16 devices.
Emulation Design Considerations E-25 Design Considerations for Using XDS510 Emulato r Figure E–15. TBC Emulation Connections for n JT AG Scan Paths JT AG0 JT AGN TDI EMU1 TMS TDO EMU0 TRST TCK TDO T.
F-1 Appendix A Glossary A A0–A15: Collectively , the external address bus; the 16 pins are used in par- allel to address external data memory , program memory , or I/O space. ACC: See accumulator . ACCH: Accumulator high word. The upper 16 bits of the accumulator .
F-2 analog-to-digital (A/D) converter: A circuit that translates an analog signal to a digital signal. AR: See auxiliary register . AR0–AR7: Auxiliary registers 0 through 7. See auxiliary register . ARAU: See auxiliary register arithmetic unit (ARAU).
F-3 Glossary B B0: An on-chip block of dual-access RAM that can be configured as either data memory or program memory , depending on the value of the CNF bit in status register ST1. B1: An on-chip block of dual-access RAM available for data memory . B2: An on-chip block of dual-access RAM available for data memory .
F-4 CALU: See central arithmetic logic unit (CALU). carry bit: Bit 9 of status register ST1; used by the CALU for extended arithmetic operations and accumulator shifts and rotates.
F-5 Glossary clock mode (clock generator): One of the modes which sets the internal CPU clock frequency to a fraction or multiple of the frequency of the input clock signal CLKIN. The ’C209 has two clock modes ( ÷ 2 and × 2); other ’C2xx devices have four clock modes ( ÷ 2, × 1, × 2, and × 4).
F-6 current data page: The data page indicated by the content of the data page pointer (DP). See also data page ; DP . D D0–D15: Collectively , the external data bus; the 16 pins are used in parallel to transfer data between the ’C2xx and external data memory , program memory , or I/O space.
F-7 Glossary decode phase: The phase of the pipeline in which the instruction is de- coded. See also pipeline ; instruction-fetch phase ; operand-fetch phase; instruction-execute phase .
F-8 DRAB: See data-read address bus (DRAB). DRDB: See data read bus (DRDB). DS: Data memory select pin . The ’C2xx asserts DS to indicate an access to external data memory (local or global).
F-9 Glossary FR0/FR1: FIFO receive-interrupt bits . Bits 8 and 9 of the synchronous serial port control register (SSPCR); together they set an interrupt trigger condition based on the number of words in the receive FIFO buffer .
F-10 G general-purpose input/output pins: Pins that can be used to accept input signals and/or send output signals but are not linked to specific uses. These pins are the input pin BIO , the output pin XF , and the input/output pins IO0, IO1, IO2, and IO3.
F-1 1 Glossary IC: (Used in earlier documentation.) See interrupt control register (ICR). ICR: See interrupt control register (ICR) . IFR: See interrupt flag register (IFR) .
F-12 INT1–INT3: Three external pins used to generate general-purpose hard- ware interrupts. internal interrupt: A hardware interrupt caused by an on-chip peripheral. interrupt: A signal sent to the CPU that (when not masked or disabled) forces the CPU into a subroutine called an interrupt service routine (ISR).
F-13 Glossary IO0–IO3 bits: Bits 0–3 of the IOSR. When pins IO0–IO3 are configured as inputs, these bits reflect the current logic levels on the pins. For example, the IO0 bit reflects the level on the IO0 pin. See also CIO0–CIO3 bits ; DIO0–DIO3 bits .
F-14 LSB : Least significant bit. The lowest order bit in a word. When used in plural form (LSBs), refers to a specified number of low-order bits, beginning with the lowest order bit and counting to the left. For example, the four LSBs of a 16-bit value are bits 0 through 3.
F-15 Glossary MST ACK: See micro stack . multiplier: A part of the CPU that performs 16-bit × 16-bit multiplication and generates a 32-bit product. The multiplier operates using either signed or unsigned 2s-complement arithmetic. N next AR: See next auxiliary register .
F-16 OV bit: Overflow flag bit. Bit 12 of status register ST0; indicates whether the result of an arithmetic operation has exceeded the capacity of the accu- mulator . overflow (in a register): A condition in which the result of an arithmetic op- eration exceeds the capacity of the register used to hold that result.
F-17 Glossary pipeline : A method of executing instructions in an assembly line fashion. The ’C2xx pipeline has four independent phases. During a given CPU cycle, four different instructions can be active, each at a dif ferent stage of completion.
F-18 program control logic: Logic circuitry that decodes instructions, manages the pipeline, stores status of operations, and decodes conditional opera- tions. program counter (PC): A register that indicates the location of the next instruction to be executed.
F-19 Glossary receive interrupt (asynchronous serial port): An interrupt (TXRXINT) caused during reception by any one of these events: the ADTR holds a new character; overrun occurs; a framing error occurs; a break has been detected on the RX pin; a character A or a has been detected in the ADTR by the automatic baud-rate detection logic.
F-20 RPTC: See repeat counter (RPTC). RRST : Receive reset bit . Bit 4 of the synchronous serial port control register (SSPCR); resets the receiver portion of the synchronous serial port. RS : Reset pin . When driven low , causes a reset on any ’C2xx device, includ- ing the ’C209.
F-21 Glossary single-access RAM: See SARAM . slave phase: See latch phase . SOFT bit (asynchronous serial port): Bit 14 in the asynchronous serial port control register (ASPCR); a special emulation bi.
F-22 status registers ST0 and ST1: T wo 16-bit registers that contain bits for de- termining processor modes, addressing pointer values, and indicating various processor conditions and arithmetic logic results.
F-23 Glossary TIM bit: T ransmit interrupt mask bit . Bit 8 of the asynchronous serial port control register (ASPCR); enables or disables transmit interrupts of the asynchronous serial port.
F-24 transmit mode (TXM) bit: Bit 3 of the synchronous serial port control regis- ter (SSPCR); determines whether the source signal for frame synchro- nization is external or internal. transmit pin (asynchronous serial port): See TX pin . transmit pin (synchronous serial port): See DX pin .
F-25 Glossary URST : Reset asynchronous serial port bit . Bit 13 of the asynchronous serial port control register (ASPCR); resets the asynchronous port. V vector: See interrupt vector . vector location: See interrupt vector location . W wait state : A CLKOUT1 cycle during which the CPU waits when reading from or writing to slower external memory .
F-26 Z zero fill: Fill the unused low or high order bits in a register with zeros. Glossary.
Index Index-1 Index * operand 6-10 *+ operand 6-10 *– operand 6-10 *0+ operand 6-10 *0– operand 6-10 *BR0+ operand 6-1 1 *BR0– operand 6-1 1 14-pin connector , dimensions E-15 14-pin header head.
Index Index-2 accumulator instructions (continued) store high byte of accumulator to data memory (SACH) 7-148 store low byte of accumulator to data memory (SACL) 7-150 subtract conditionally from accu.
Index Index-3 asynchronous serial port (continued) baud-rate detection logic detecting A or a character (ADC bit) 10-10 enabling/disabling (CAD bit) 10-8 block diagram 10-3 components 10-3 configurati.
Index Index-4 B B instruction 7-39 BACC instruction 7-40 BANZ instruction 7-41 baud-rate detection procedure 10-14 divisor register (BRD) 10-13 generator 10-4 BCND instruction 7-43 BI bit 10-10 BIO pi.
Index Index-5 bus request pin (BR ) definition 4-3 shown in figure 4-13, 4-15 buses block diagram 2-4 data read bus (DRDB) 2-3 data write bus (DWEB) 2-3 data-read address bus (DRAB) 2-3 data-write add.
Index Index-6 CMPR instruction 7-65 CNF (DARAM configuration bit) 3-16 code compatibility 1-6 codec, definition F-5 conditional instructions 5-10 to 5-13 conditional branch 5-1 1 to 5-13 conditional c.
Index Index-7 data memory select pin (DS ) definition 4-3 shown in figure 4-10, 4-13 data page 0 4-8 caution about test/emulation addresses 4-8 data page pointer (DP) caution about initializing DP 6-5.
Index Index-8 emulator cable pod E-5 connection to target system, JT AG mechanical dimensions E-14 to E-25 designing the JT AG cable E-1 emulation pins E-20 pod interface E-5 pod timings E-6 signal bu.
Index Index-9 H hardware interrupts definition 5-15 nonmaskable external 5-27 priorities 5-16 types 5-15 hardware reset 5-33 header 14-pin E-2 dimensions, 14-pin E-2 HOLD (HOLD operation request pin) .
Index Index-10 IMR (interrupt mask register) 5-22 to 5-38 bits ’C203/C204 5-23 ’C209 1 1-13 in interrupt acknowledgement process 5-19 quick reference A-7 IN instruction 7-69 IN0 bit 9-10 indirect .
Index Index-1 1 INT1 interrupt ’C203/C204 flag bit (HOLD/INT1) 5-22 mask bit (HOLD/INT1) 5-24 priority 5-16 vector location 5-16 ’C209 flag bit 1 1-12 mask bit 1 1-13 priority 1 1-10 vector locati.
Index Index-12 interrupt (continued) phases of operation 5-15 priorities ’C203/C204 5-16 ’C209 1 1-10 in interrupt acknowledgement process 5-19 registers interrupt control register (ICR) 5-24 inte.
Index Index-13 L LACC instruction 7-72 LACL instruction 7-75 LACT instruction 7-78 LAR instruction 7-80 latch phase of CPU cycle F-13 latency , interrupt 5-30 to 5-36 after execution of RET 5-32 durin.
Index Index-14 memory (continued) introduction 4-2 local data memory description 4-7 to 4-10 pages of (diagram) 4-7 on-chip memory , advantages 4-2 organization 4-2 overview 2-7 pins for external inte.
Index Index-15 next program address register (NP AR) definition F-15 shown in figure 5-2 NMI hardware interrupt description 5-27 priority ’C203/C204 5-17 ’C209 1 1-1 1 vector location ’C203/C204.
Index Index-16 OUT instruction 7-132 output modes external count E-20 signal event E-20 output shifter 3-1 1 OV (overflow flag bit) 3-16 overflow in accumulator detecting (OV bit) 3-16 enabling/disabl.
Index Index-17 PREG instructions (continued) load high bits of PREG (LPH) 7-85 set PREG output shift mode (SPM) 7-167 store high word of PREG to data memory (SPH) 7-161 store low word of PREG to data .
Index Index-18 program memory (continued) configuration RAM (dual-access) ’C203 4-33 ’C204 4-36 ’C209 1 1-8 RAM (single-access) 1 1-7 ROM ’C204 4-36 ’C209 1 1-7 description 4-5 external inte.
Index Index-19 registers (continued) mapped to data page 0 4-8 mapped to I/O space ’C203/C204 4-24 ’C209 1 1-9 accessing 4-25 quick reference A-1 to A-14 status registers ST0 and ST1 3-15 timer co.
Index Index-20 S SACH instruction 7-148 SACL instruction 7-150 SAR instruction 7-152 SARAM (single-access RAM) configuration 1 1-7 definition F-20 description 2-8 SBRK instruction 7-154 scaling shifte.
Index Index-21 status registers ST0 and ST1 addresses and reset values A-2 bits 3-15 clear control bit (CLRC instruction) 7-62 introduction 3-15 load (LST instruction) 7-87 load data page pointer (LDP.
Index Index-22 synchronous serial port (continued) troubleshooting bits for testing the port 9-27 error conditions burst mode 9-29 continuous mode 9-29 underflow in transmitter burst mode 9-29 continu.
Index Index-23 timer control register (TCR) 8-10 to 8-12 ’C209 1 1-15 quick reference A-9 timer counter register (TIM) 8-12, F-23 to F-26 timer period register (PRD) 8-12, F-23 to F-26 timing calcul.
Index Index-24 TSS bit ’C203/C204 8-12 ’C209 1 1-16 TX pin 10-4 TXM bit 9-1 1 TXRXINT bit in interrupt flag register (IFR) 5-21 in interrupt mask register (IMR) 5-23 TXRXINT interrupt flag bit 5-2.
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