Texas InstrumentsメーカーTMS320F28015の使用説明書/サービス説明書
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TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 Digital Signal Processors Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com Contents 1 F280x, F2801x, C280x DSPs ...................................
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 4.4 Enhanced CAP Modules (eCAP1/2/3/4) .................................
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 6.13 ROM Timing (C280x only) ...........................................
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 List of Figures 2-1 TMS320F2809, TMS320F2808 100-Pin PZ LQFP (Top View) .
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 6-9 Warm Reset .........................................................
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 List of Tables 2-1 Hardware Features (100-MHz Devices) .................
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 6-9 XCLKIN Timing Requirements - PLL Enabled ...........................
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 Digital Signal Proces.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 2 Introduction The TM.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 Table 2-2. Hardware Features (60-MHz Devices) FEATURE TYPE (1) F2802-60 F2801-60 F28016 F28015 Instruction cycle (at 60 MHz) – 16.
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 5.
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 5.
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 5.
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 5.
4 C B A D E 2 1 3 K F G H J 5 7 6 9 8 10 Bottom V iew TRST TCK TDI TDO TMS EMU0 EMU1 V DD3VFL TEST1 TEST2 XCLKOUT XCLKIN X1 X2 XRS GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO9 GPIO8 GPIO10 GP.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 2.2 Signal Descriptions Table 2-3 describes the signals on the 280x devices.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com Signal Descriptions (continued) PIN NO. GGM/ NAME DESCRIPTION (1) PZ ZGM PIN # BALL # Internal/External Oscillator Input.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 Signal Descriptions (continued) PIN NO. GGM/ NAME DESCRIPTION (1) PZ ZGM PIN # BALL # V DD 10 E2 V DD 42 G6 V DD 59 F10 CPU and Logic Digital Power Pins (1.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 Signal Descriptions (continued) PIN NO.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
INT[12:1] Real- Time JT AG (TDI, TDO, TRST , TCK, TMS, EMU0, EMU1) C28x CPU (100 MHz) NMI , INT13 Memory Bus INT14 SYSCLKOUT RS CLKIN 12-Bit ADC ADCSOCA/B SOCA/B 16 Channels 12 6 32 XCLK OUT XRS XCLKI.
0x00 0000 Block Start Address Data Space Prog Space M0 V ector − RAM (32 x 32) (Enabled if VMAP = 0) M1 SARAM (1K y 16) 0x00 0400 Peripheral Frame 0 0x00 0800 0x00 0D00 Peripheral Frame 1 (protected.
0x00 0000 Block Start Address Data Space Prog Space M0 SARAM (1K y 16) M1 SARAM (1K y 16) 0x00 0400 Peripheral Frame 0 0x00 0800 0x00 0D00 Peripheral Frame 1 (protected) 0x00 6000 Peripheral Frame 2 (.
0x00 0000 Block Start Address Data Space 0x00 0400 0x00 0800 0x00 0D00 0x00 6000 0x00 7000 0x00 8000 0x00 9000 0x00 A000 0x3D 7800 0x3D 7C00 0x3F 7FF8 0x3F 8000 0x3F 9000 0x3F A000 0x3F F000 0x3F FFC0.
0x00 0000 Block Start Address 0x00 0400 0x00 0800 0x00 0D00 0x00 6000 0x00 7000 0x00 8000 0x00 9000 0x3D 7800 0x3F 0000 0x3F 7FF8 0x3F 8000 0x3F 9000 0x3F F000 0x3F FFC0 OTP (F2802 Only) (A) (1K y 16,.
0x00 0000 Block Start Address 0x00 0400 0x00 0800 0x00 0D00 0x00 6000 0x00 7000 0x00 8000 0x00 9000 0x3D 7800 0x3F 4000 0x3F 7FF8 0x3F 8000 0x3F 9000 0x3F F000 0x3F FFC0 OTP (F2801/F2801x Only) (A) (1.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 Table 3-1.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 The wait-states for the various spaces in the memory map area are listed in Table 3-6 .
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 3.2 Brief Descriptions 3.2.1 C28x CPU The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 3.2.4 Real-Time JTAG and Analysis The 280x implements the standard IEEE 1149.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 3.2.8 L0, L1, H0 SARAMs The F2809 and F2808 each contain an additional 16K x 16 of single-access RAM, divided into 3 blocks (L0-4K, L1-4K, H0-8K).
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 3.2.10 Security The 280x devices support high levels of security to protect the user firmware from being reverse engineered.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 3.2.11 Peripheral Interrupt Expansion (PIE) Block The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 3.2.17 Peripheral Frames 0, 1, 2 (PFn) The 280x segregate peripherals into three sections.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com eQEP: The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed measurement using capture unit and high-speed measurement using a 32-bit unit timer.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 Table 3-8.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
XINT2 C28 CPU CPUTIMER2 (ReservedforDSP/BIOS) CPUTIMER0 W atchdog Peripherals (SPI,SCI,I2C,eCAN,ePWM,eCAP ,eQEP ,ADC) TINT0 InterruptControl XNMICR(15:0) XINT.
INT12 MUX INT1 1 INT2 INT1 CPU (Enable) (Flag) INTx INTx.8 PIEIERx(8:1) PIEIFRx(8:1) MUX INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 From Peripherals or External Interrupts (Enable) (Flag) IER(12.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 Table 3-13.
PLL X1 X2 Power Modes Control W atchdog Block 28x CPU Peripheral Bus Low-Speed Peripherals SCI-A/B, SPI-A/B/C/D Peripheral Registers High-Speed Prescaler Low-Speed Prescaler Clock Enables GPIO MUX Sys.
X1 XCLKIN (3.3-V clock input) On chip oscillator X2 xor PLLSTS[OSCOFF] OSCCLK PLL VCOCLK 4-bit PLL Select (PLLCR) OSCCLK or VCOCLK CLKIN OSCCLK 0 PLLSTS[PLLOFF] n n ≠ 0 /2 PLLSTS[CLKINDIV] TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.
External Clock Signal (T oggling 0 −V D DIO ) XCLKIN X2 NC X1 External Clock Signal (T oggling 0 −V D D ) XCLKIN X2 NC X1 C L1 X2 X1 Crystal C L2 XCLKIN TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 3.6.1.2 PLL-Based Clock Module The 280x devices have an on-chip, PLL-based clock module.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 3.6.1.3 Loss of Input Clock In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still issue a limp-mode clock.
/512 OSCCLK WDCR (WDPS(2:0)) WDCLK WDCNTR(7:0) WDKEY(7:0) Good Key 101 WDCR (WDCHK(2:0)) Bad WDCHK Key WDCR (WDDIS) Clear Counter SCSR (WDENINT) W atchdog Prescaler Generate Output Pulse (512 OSCCLKs).
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 3.7 Low-Power Modes Block The low-power modes on the 280x are similar to the 240x devices.
Borrow Reset T imer Reload SYSCLKOUT TCR.4 (T imer Start Status) TINT 16-Bit T imer Divide-Down TDDRH:TDDR 32-Bit T imer Period PRDH:PRD 32-Bit Counter TIMH:TIM 16-Bit Prescale Counter PSCH:PSC Borrow TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.
INT1 to INT12 INT14 C28x TINT2 TINT0 PIE CPU- TIMER0 CPU- TIMER2 (Reservedfor DSP/BIOS) INT13 TINT1 CPU- TIMER1 XINT13 TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
PIE TZ1 to TZ6 Peripheral Bus ePWM1 module ePWM2 module ePWMx module EPWM1SYNCI EPWM2SYNCI EPWM2SYNCO EPWMxSYNCI EPWMxSYNCO ADC GPIO MUX EPWM1SYNCI EPWM1SYNCO ADCSOCx0 EPWMxA EPWMxB EPWM2A EPWM2B EPWM1A EPWM1B EPWM1INT EPWM1SOC EPWM2INT EPWM2SOC EPWMxINT EPWMxSOC to eCAP1 module (sync in) TZ1 to TZ6 TZ1 to TZ6 .
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
CTR = PRD TBPRD Shadow (16) TBPRD Active (16) Counter Up/Down (16-Bit) TBCNT Active (16) TBCTL[PHSEN] TBCTL[SWFSYNC] (Software-Forced Sync) EPWMxSYNCI CTR = ZERO CTR_Dir CTR = CMPB Disabled Sync In/Ou.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
TSCTR (counter−32 bit) RST CAP1 (APRD active) LD CAP2 (ACMP active) LD CAP3 (APRD shadow) LD CAP4 (ACMP shadow) LD Continuous / Oneshot Capture Control LD1 LD2 LD3 LD4 32 32 PRD [0−31] CMP [0−31.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
QWDTMR QWDPRD 16 QWDOG UTIME QUPRD QUTMR 32 UT OUT WDT OUT Quadrature capture unit (QCAP) QCPRDLA T QCTMRLA T 16 QFLG QEPSTS QEPCTL Registers used by multiple units QCLK QDIR QI QS PHE PCSOUT Quadratu.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
Digital Value + 0, Digital Value + 40 96 Input A nalog Voltage * ADCLO 3 when input ≤ 0 V when 0 V < input < 3 V when input ≥ 3 V Digital Value + 4095, TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.
Result Registers EPWMSOCB S/W GPIO/XINT2 _ADCSOC EPWMSOCA S/W Sequencer 2 Sequencer 1 SOC SOC ADC Control Registers 70B7h 70B0h 70AFh 70A8h Result Reg 15 Result Reg 8 Result Reg 7 Result Reg 1 Result .
ADCINA[7:0] ADCINB[7:0] ADCLO ADCREFIN ADC External Current Bias Resistor ADCRESEXT ADCREFP V DD 1A18 V DD 2A18 V SS1AG ND V SS2AG ND V DD AIO V SSAIO V DD A2 V SSA2 ADC Reference Positive Output ADCR.
ADCINA[7:0] ADCINB[7:0] ADCLO ADCREFIN ADC External Current Bias Resistor ADCRESEXT ADCREFP V DD 1A18 V DD 2A18 V SS1AG ND V SS2AG ND V DD AIO V SSAIO V DD A2 V SSA2 ADC Reference Positive Output ADCR.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 4.6.2 ADC Registers The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-5 .
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 4.7 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) The CAN module has the following features: • Fully compliant with CAN protocol, version 2.
Mailbox RAM (512 Bytes) 32-Message Mailbox of 4 × 32-Bit W ords Memory Management Unit CPU Interface, Receive Control Unit, T imer Management Unit eCAN Memory (512 Bytes) Registers and Message Object.
Mailbox Enable − CANME Mailbox Direction − CANMD T ransmission Request Set − CANTRS T ransmission Request Reset − CANTRR T ransmission Acknowledge − CANT A Abort Acknowledge − CANAA Receiv.
Mailbox Enable − CANME Mailbox Direction − CANMD T ransmission Request Set − CANTRS T ransmission Request Reset − CANTRR T ransmission Acknowledge − CANT A Abort Acknowledge − CANAA Receiv.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com The CAN registers listed in Table 4-7 are used by the CPU to configure and control the CAN controller and the message objects.
Baud rate = LSPCLK 16 LSPCLK (BRR ) 1) * 8 when BRR ≠ 0 Baud rate = when BRR = 0 Max bit rate + 100 MHz 16 + 6.25 10 6 b ń s Max bit rate + 60 M Hz 16 + 3.75 10 6 b ń s TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
TX FIFO _0 LSPCLK WUT Frame Format and Mode Even/Odd Enable Parity SCI RX Interrupt select logic BRKDT RXRDY SCIRXST .6 SCICTL1.3 8 SCICTL2.1 RX/BK INT ENA SCIRXD SCIRXST .1 TXENA SCI TX Interrupt select logic TX EMPTY TXRDY SCICTL2.0 TX INT ENA SCITXD RXENA SCIRXD RXW AKE SCICTL1.
Baud rate = LSPCLK 4 LSPCLK (SPIB RR ) 1) when SPIBRR = 3 to 127 Baud rate = when SPIBRR = 0,1, 2 TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 The SPI port operation is configured and controlled by the registers listed in Table 4-10 through Table 4-13 .
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
S SPICTL.0 SPI INT FLAG SPI INT E N A SPISTS.6 S Clock Polarity T alk LSPCLK 4 5 6 1 2 3 0 0 1 2 3 SPI Bit Rate State Control SPIRXBUF Buffer Register Clock Phase Receiver Overrun Flag SPICTL.4 Overrun INT ENA SPICCR.3 − 0 SPIBRR.6 − 0 SPICCR.6 SPICTL.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 4.10 Inter-Integrated Circuit (I2C) The 280x device contains one I2C Serial Port.
SYSRS Data[16] SYSCLKOUT Data[16] Addr[16] Control I2CINT1A I2CINT2A C28X CPU GPIO MUX I 2 C−A System Control Block I2CAENCLK PIE Block SDAA SCLA Peripheral Bus TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.
GPxDA T (read) Input Qualification GPxMUX1/2 High Impedance Output Control GPIOx pin XRS 0 = Input, 1 = Output Low Power Modes Block GPxDIR (latch) Peripheral 2 Input Peripheral 3 Input Peripheral 1 O.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 The 280x supports 34 GPIO pins.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
GPyCTRL Reg SYNC SYSCLKOUT Qualification Input Signal Qualified By 3 or 6 Samples GPIOx T ime between samples GPxQSEL Number of Samples TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
PREFIX TMS 320 F 28015 PZ TMX = Experimental Device TMP = Prototype Device TMS = Qualified Device DEVICE F AMIL Y 320 = TMS320 E DSP Family TECHNOLOGY P ACKAGE TYPE PZ = 100-Pin Low-Profile Quad Flatpack (LQFP) GGM = 100-Ball Ball Grid Array (BGA) ZGM = 100-Ball Lead-Free BGA F = Flash EEPROM (1.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 SPRU790 TMS320x280x, .
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com Application Reports and Software Key Links Include: 1. C2000 Get Started - www.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 methods described in this report can improve the absolute accuracy of the ADC to levels better than 0.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 6 Electrical Specifications This section provides the absolute maximum ratings and the recommended operating conditions for the TMS320F280x DSPs.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 6.2 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Device supply voltage, I/O, V DDIO 3.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 6.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 Table 6-3.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 6.4.1 Reducing Current Consumption 280x devices have a richer peripheral mix compared to the 281x family.
0.0 50.0 100.0 150.0 200.0 250.0 10 20 30 40 50 60 70 80 90 100 SYSCLKOUT (MHz) Current (mA) IDD IDDA18 IDDIO IDD3VFL 3.3-V current 1.8-V current 0.0 100.
Curr e nt V s SYSCLKO UT 0 20 40 60 80 10 0 12 0 14 0 16 0 18 0 20 0 10 2 0 3 0 40 5 0 6 0 70 8 0 9 0 10 SY SCLK OU T (MHz) C urre nt (mA) I DD I D D A 18 1. 8v curr ent I DD IO I DD 3VF L 3 .3v c urr ent D evice Po w er Vs S Y S C L K OUT 0.0 10 0 . 0 20 0 .
EMU0 EMU1 TRST TMS TDI TDO T CK VDDIO DSP EMU0 EMU1 TRST TMS TDI TDO T CK T CK_RET 13 14 2 1 3 7 11 9 6inchesorless PD GND GND GND GND GND 5 4 6 8 10 12 JT AGHeader VDDIO TMS320F2809, TMS3.
T ransmission Line 4.0 pF 1.85 pF Z0 = 50 Ω (Α ) T ester Pin Electronics Data Sheet T iming Reference Point Output Under T est 42 Ω 3.5 nH Device Pin (B) TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 6.6.3 Device Clock Table This section provides the timing requirements and switching characteristics for the various clock options available on the 280x DSPs.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 6.
C4 C3 XCLKOUT (B) XCLKIN (A) C5 C9 C10 C1 C8 C6 TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen.
t w(RSL 1) t h(b oo t-mod e) (B ) V DD IO , V DD3 VFL V DD A2 , V D DA IO (3.3 V) XCLKIN X1/X2 XRS Boot-Mode Pins V DD , V DD 1A18 , V DD 2A18 (1.8 V) XCLKOUT I/O Pins (C) User-Code Dependent User-Cod.
t h(b oo t-mod e) (A ) t w(RSL 2) XCLKIN X1/X2 XRS Boot-Mode Pins XCLKOUT I/O Pins Address/Data/ Control (Internal) Boot-ROM Execution Starts User-Code Execution Starts User-Code Dependent User-Code E.
OSCCLK SYSCLKOUT W rite to PLLCR OSCCLK * 2 (Current CPU Frequency) OSCCLK/2 (CPU Frequency While PLL is Stabilizing With the Desired Frequency . This Period (PLL Lock-up T ime, t p ) is 131 072 OSCCLK Cycles Long.
GPIO Signal 1 Sampling Window Output From Qualifier 1 1 111111111 0000000 000 SYSCLKOUT QUALPRD = 1 (SYSCLKOUT/2) (SYSCLKOUT cycle * 2 * QUALPRD) * 5 (C) ) (A) GPxQSELn = 1,0 (6 samples) Sampling Peri.
GPIOxn XCLKOUT t w(GPI) TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 6.
W AKE INT (A) XCLKOUT Address/Data (internal) t d(W AKE− I DLE) t w(W AKE− INT) TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
t w(W AKE-INT) t d(W AKE-ST BY) t d(IDL E− XCOL ) W ake−up Signal X1/X2 or X1 or XCLKIN XCLKOUT ST ANDBY Normal Execution ST ANDBY Flushing Pipeline (A) (B) (C) (D) (E) (F) Device Status TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.
t d(IDL E− XCOL ) X1/X2 or XCLKIN XCLKOUT HAL T HAL T W ake-up Latency Flushing Pipeline t d(W AKE− HAL T) (A) (B) (C) (D) Device Status (E) (G) (F) PLL Lock-up T ime Normal Execution t w(W AKE-GP.
PWM (B) TZ XCLKOUT (A) t w(TZ ) t d(T Z-PW M)H Z TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 6.10 Enhanced Control Peripherals 6.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com Table 6-25 shows the high-resolution PWM switching characteristics. Table 6-25.
ADCSOCAO or ADCSOCBO t w(AD CSOC AL ) XNMI , XINT1, XINT2 t w(INT) Interrupt V ector t d(INT ) Address bus (internal) TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 Table 6-30.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 Table 6-34.
9 4 SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Master In Data Must Be V alid Master Out Data Is V alid 8 5 3 2 1 SPISTE (A) TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 Table 6-35.
Data V alid 1 1 SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Master In Data Must Be V alid Master Out Data Is V alid 1 7 6 10 3 2 SPISTE (A) TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
20 15 SPISIMO SPISOMI SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPISIMO Data Must Be V alid SPISOMI Data Is V alid 19 16 14 13 12 SPISTE (A) TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.
Data V alid 22 SPISIMO SPISOMI SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPISIMO Data Must Be V alid SPISOMI Data Is V alid 21 12 18 17 14 13 SPISTE (A) TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 6.
ADC Power Up Delay ADC Ready for Conversions PWDNBG PWDNREF PWDNADC Request for ADC Conversion t d(B GR) t d(PW D) TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
ac R s ADCIN0 C p 10 pF R on 1 k Ω 1.64 pF C h Switch T ypical V alues of the Input Circuit Components: Switch Resistance (R on ): 1 k Ω Sampling Capacitor (C h ): 1.
Analog Input on Channel Ax or Bx ADC Clock Sample and Hold SH Pulse SMODE Bit t dsch x_n t dsch x_n+1 Sample n Sample n+1 Sample n+2 t SH ADC Event T rigger from ePWM or Other Sources t d(SH ) TMS320F.
Analog Input on Channel Ax Analog Input on Channel Bx ADC Clock Sample and Hold SH Pulse t SH t dsch A0_n t dsch B0_n t dsch B0_n +1 Sample n Sample n+1 Sample n+2 t dsch A0_n +1 t d(SH ) ADC Event T .
N + ( SINAD * 1.76 ) 6.02 TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.
+ ƪ ǒ t a(fp) t c(SCO) Ǔ * 1 ƫ (round up to the next highest integer) or 0, whichever is larger (round up to the next highest integer) or 1, whichever is larger + ƪ ǒ t a(fr ) t c(SCO) Ǔ * 1 ƫ.
+ ƪ ǒ t a(r p) t c(SCO) Ǔ * 1 ƫ (round up to the next highest integer) or 0, whichever is larger + ƪ ǒ t a(r r) t c(SCO) Ǔ * 1 ƫ (round up to the next highest integer) or 1, whichever is large.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 7 Migrating From F280x Devices to C280x Devices 7.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 8 Revision History This data sheet revision history highlights the technical changes made to the SPRS230K device-specific data sheet to make it an SPRS230L revision.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 9 Mechanical Data Table 9-1 through Table 9-6 show the thermal data.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com Table 9-6. F2809 Thermal Model 100-pin PZ Results AIR FLOW PARAMETER 0 lfm 150 lfm 250 lfm 500 lfm θ JA [°C/W] High k PCB 44.
PACKAGE OPTION ADDENDUM www.ti.com 5-Nov-2010 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Te.
PACKAGE OPTION ADDENDUM www.ti.com 5-Nov-2010 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requir.
PACKAGE OPTION ADDENDUM www.ti.com 5-Nov-2010 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requir.
PACKAGE OPTION ADDENDUM www.ti.com 5-Nov-2010 Addendum-Page 4 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requir.
MECHANICAL DA T A MPBG028B FEBRUAR Y 1997 – REVISED MA Y 2002 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GGM (S–PBGA–N100) PLASTIC BALL GRID ARRA Y 0,08 0,10 1,40 MAX 0,85 0,55 0,45 0,45 0.
.
MECHANICAL DA T A MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PZ (S-PQFP-G100) PLASTIC QUAD FLA TP ACK 4040149 /B 1 1/96 50 26 0,13 NOM Gage Pl.
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Texas Instruments TMS320F28015をまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはTexas Instruments TMS320F28015の技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Texas Instruments TMS320F28015の取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Texas Instruments TMS320F28015で得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Texas Instruments TMS320F28015を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はTexas Instruments TMS320F28015の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
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