VXIメーカー320222-01の使用説明書/サービス説明書
ページ先へ移動 of 209
VXI-MXI User Manual October 1993 Edition Part Number 320222-01 © Copyright 1989, 1993 National Instruments Corporation. All Rights Reserved..
National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin, TX 78730-5039 (512) 794-0100 (800) 433-3488 (toll-free U.S. and Canada) Technical support fax: (512) 794-5678 Branch Offic.
Limited Warranty The National Instruments MXIbus boards and accessories are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation.
FCC/DOC Radio Frequency Interference Compliance This equipment generates and uses radio frequency energy and, if not installed and used in strict accordance with the instructions in this manual, may cause interference to radio and television reception.
© National Instruments Corporation v VXI-MXI User Manual Contents About This Manual ............................................................................................................... xi Organization of This Manual .......................
Contents VXI-MXI User Manual vi © National Instruments Corporation Chapter 4 Register Descriptions ......................................................................................................... 4-1 Register Maps ...........................
Contents © National Instruments Corporation vii VXI-MXI User Manual Chapter 6 Theory of Operation .......................................................................................................... 6-1 VMEbus Address and Address Modifier Transceivers .
Contents VXI-MXI User Manual viii © National Instruments Corporation Figures Figure 1-1. VXI-MXI Interface Module ............................................................................. 1-2 Figure 1-2. VXI-MXI Interface Module with INTX Option .
Contents © National Instruments Corporation ix VXI-MXI User Manual Figure 6-1. Master to Slave VMEbus/MXIbus Transfers ................................................... 6-7 Figure 6-2. Deadlock Situation ............................................
© National Instruments Corporation xi VXI-MXI User Manual About This Manual The VXI-MXI User Manual describes the functional, physical, and electrical aspects of the VXI-MXI and contains information concerning its operation and programming.
About This Manual VXI-MXI User Manual xii © National Instruments Corporation How to Use This Manual If you will be installing your VXI-MXI into a system with a VXIbus Resource Manager, you only need to read Chapters 1 through 3 of this manual.
© National Instruments Corporation 1-1 VXI-MXI User Manual Chapter 1 General Information This chapter describes the VXI-MXI features, lists the contents of your VXI-MXI kit, and explains how to unpack the VXI-MXI kit. The VXI-MXI interface is a C-size extended class mainframe extender for the VXIbus (VMEbus Extensions for Instrumentation).
General Information Chapter 1 VXI-MXI User Manual 1-2 © National Instruments Corporation Figure 1-1. VXI -MXI Interface Module.
Chapter 1 General Information © National Instruments Corporation 1-3 VXI-MXI User Manual Figure 1-2. VXI -MXI Interface Module with INTX Option.
General Information Chapter 1 VXI-MXI User Manual 1-4 © National Instruments Corporation Overview The VXI-MXI is an extended class Register-Based VXIbus device with optional Slot 0 capability so that it can reside in any slot in a C-size or D-size VXIbus chassis.
Chapter 1 General Information © National Instruments Corporation 1-5 VXI-MXI User Manual – Data transfer bus arbiter (PRI ARBITER) – Interrupt acknowledge daisy-chain driver – Pushbutton system.
General Information Chapter 1 VXI-MXI User Manual 1-6 © National Instruments Corporation What Your Kit Should Contain Your VXI-MXI kit should contain the following components: Component Part Number S.
Chapter 1 General Information © National Instruments Corporation 1-7 VXI-MXI User Manual The following optional equipment is also available and may be necessary if your VXI-MXI includes the INTX daughter card.
© National Instruments Corporation 2-1 VXI-MXI User Manual Chapter 2 General Description This chapter contains the physical and electrical specifications for the VXI-MXI and describes the characteristics of key interface board components.
General Description Chapter 2 VXI-MXI User Manual 2-2 © National Instruments Corporation Table 2-1. VXI -MXI VMEbus Signals (Continued) Driver Device Receiver Device Bus Signals Part Number Part Number IACKIN* – LS540 IACKOUT* GAL20V8 – IRQ[7-1]* AS760, LS145 LS540 All MXIbus transceivers meet the requirements of the MXIbus specification.
Chapter 2 General Description © National Instruments Corporation 2-3 VXI-MXI User Manual The VXI-MXI does not support the following VMEbus modules: • Serial Clock Driver • Power Monitor Table 2-3 indicates the VXI-MXI VMEbus compliance levels. Table 2-3.
General Description Chapter 2 VXI-MXI User Manual 2-4 © National Instruments Corporation Table 2-3. VXI -MXI VMEbus Compliance Levels (Continued) Compliance Notation Description Bus Master Compliance.
Chapter 2 General Description © National Instruments Corporation 2-5 VXI-MXI User Manual VXI-MXI Functional Description In simplest terms, the VXI -MXI can be thought of as a bus translator that converts VXIbus signals into appropriate MXIbus signals.
General Description Chapter 2 VXI-MXI User Manual 2-6 © National Instruments Corporation SYSFAIL* SYSRESET* ACFAIL* VMEbus IRQ7-1 IRQ* Interrupt Circuitry SYSFAIL, ACFAIL, SYSRESET Logic Daughter Car.
Chapter 2 General Description © National Instruments Corporation 2-7 VXI-MXI User Manual • Interrupt Circuitry This circuitry generates and receives interrupt requests on the VMEbus, the MXIbus, and on boards plugged into the daughter card connectors.
General Description Chapter 2 VXI-MXI User Manual 2-8 © National Instruments Corporation The following information applies only to VXI-MXI kits that include the INTX daughter card option. Figure 2-2 is a block diagram of the circuitry of the INTX daughter card.
Chapter 2 General Description © National Instruments Corporation 2-9 VXI-MXI User Manual • Interrupt Control The interrupt control logic maps the VMEbus interrupt lines to and from the corresponding INTX interrupt lines.
© National Instruments Corporation 3-1 VXI-MXI User Manual Chapter 3 Configuration and Installation This chapter describes the configuration and installation of the VXI-MXI. Configuring the VXI-MXI Before installing the VXI-MXI in the VXIbus mainframe, configure the VXI-MXI to suit the needs for your VXIbus system.
Configuration and Installation Chapter 3 VXI-MXI User Manual 3-2 © National Instruments Corporation Figure 3-1 shows the locations and factory default settings of the VXI -MXI configuration jumpers and switches for a VXI-MXI without the INTX option. Figure 3-1.
Chapter 3 Configuration and Installation © National Instruments Corporation 3-3 VXI-MXI User Manual Figure 3-2 shows the locations and factory default settings of the VXI -MXI configuration jumpers and switches for a VXI-MXI with the INTX option. Figure 3-2.
Configuration and Installation Chapter 3 VXI-MXI User Manual 3-4 © National Instruments Corporation The Metal Enclosure The VXI-MXI is housed in a metal enclosure to improve EMC performance and to provide easy handling.
Chapter 3 Configuration and Installation © National Instruments Corporation 3-5 VXI-MXI User Manual When the VXI -MXI is installed in Slot 0, it becomes the VMEbus System Controller, meaning that it has VMEbus Data Transfer Bus Arbiter capability (PRI ARBITER) and that it drives the 16 MHz VMEbus system clock.
Configuration and Installation Chapter 3 VXI-MXI User Manual 3-6 © National Instruments Corporation VXIbus Logical Address Each device in a VXIbus/MXIbus system is assigned a unique number between 0 and 254. This 8-bit number, called the logical address , defines the base address for the configuration registers located on the device.
Chapter 3 Configuration and Installation © National Instruments Corporation 3-7 VXI-MXI User Manual Shown at Default setting of Logical Address 1 LOGICAL ADDRESS SWITCH Push this side down for logic 0 Push this side down for logic 1 OFF ON 1 2 3 4 5 6 7 8 OFF 1 2 3 4 5 6 7 8 a.
Configuration and Installation Chapter 3 VXI-MXI User Manual 3-8 © National Instruments Corporation a. Level 3 Requester (default) • • • • • • • • • • • • • • • • VMEbus Request Level • • • • • • • • b.
Chapter 3 Configuration and Installation © National Instruments Corporation 3-9 VXI-MXI User Manual configuration allows VXIbus transfers to have short bus timeout values and MXIbus transfers to have much longer timeout values.
Configuration and Installation Chapter 3 VXI-MXI User Manual 3-10 © National Instruments Corporation VMEbus Timeout Chain Position The VME BTO Chain Position jumper block indicates the location of the VXI -MXI interface in relation to other VXI-MXIs installed in the mainframe.
Chapter 3 Configuration and Installation © National Instruments Corporation 3-11 VXI-MXI User Manual If the system contains more than one VXI-MXI, select which card will supply the VMEbus timeout, and set the jumper block according to the VXI-MXI's position in relation to the adjacent VXI-MXIs.
Configuration and Installation Chapter 3 VXI-MXI User Manual 3-12 © National Instruments Corporation For the VXI -MXIs that do not supply the VMEbus timeout, set the VME BTO Chain Position jumper block to reflect each VXI-MXI's position in relation to the adjacent VXI-MXIs.
Chapter 3 Configuration and Installation © National Instruments Corporation 3-13 VXI-MXI User Manual Interlocked Arbitration Mode Interlocked arbitration mode is an optional mode of operation in which the system performs as one large VXIbus mainframe with only one master of the entire system (VXIbus and MXIbus) at any given moment.
Configuration and Installation Chapter 3 VXI-MXI User Manual 3-14 © National Instruments Corporation Select interlocked arbitration mode by changing the default setting of the slide switch from Normal to Interlocked Bus Cycles as shown in Figure 3-11.
Chapter 3 Configuration and Installation © National Instruments Corporation 3-15 VXI-MXI User Manual MXIbus System Controller Enabled Disabled S4 a. Not MXIbus System Controller (Default Setting) MXIbus System Controller Enabled Disabled S4 b. MXIbus System Controller Figure 3-12.
Configuration and Installation Chapter 3 VXI-MXI User Manual 3-16 © National Instruments Corporation MXIbus System Controller Timeout The MXIbus System Controller is also responsible for the MXIbus system timeout. The timeout period begins when a MXIbus data strobe (DS) is received.
Chapter 3 Configuration and Installation © National Instruments Corporation 3-17 VXI-MXI User Manual MXIbus Fairness Option The MXIbus fairness feature ensures that all requesting devices will be granted use of the MXIbus. This feature prevents a high priority MXIbus device from consuming all of the MXIbus bandwidth.
Configuration and Installation Chapter 3 VXI-MXI User Manual 3-18 © National Instruments Corporation CLK10 Source The VXIbus specification requires that Slot 0 devices supply a clock signal, CLK10, on a differential ECL output.
Chapter 3 Configuration and Installation © National Instruments Corporation 3-19 VXI-MXI User Manual • • • • • • Drive CLK10 from onboard 10MHz, Slot 0 Drive CLK10 from SMB CLK10, Slot 0 Receive CLK10, Non-Slot 0 CLK10 Source Select a.
Configuration and Installation Chapter 3 VXI-MXI User Manual 3-20 © National Instruments Corporation EXT CLK SMB Input/Output If you want to have synchronized CLK10 signals in multiple VXIbus mainframes, you can connect the CLK10 signals of the two mainframes together using the EXT CLK SMB connectors on the front panel of the VXI-MXI.
Chapter 3 Configuration and Installation © National Instruments Corporation 3-21 VXI-MXI User Manual Drive CLK10 from INTX CLK10, Slot 0 (W9 and W10 must be removed) W2 W3 Do Not Drive CLK10 from INTX CLK10 INTX CLK10 Routing W1 Receive CLK10 from INTX Drive CLK10 out INTX a.
Configuration and Installation Chapter 3 VXI-MXI User Manual 3-22 © National Instruments Corporation The VXI-MXI must be installed in Slot 0 if you want to route the INTX CLK10 signal to the VXIbus CLK10 signal.
Chapter 3 Configuration and Installation © National Instruments Corporation 3-23 VXI-MXI User Manual Reset Signal Select The VXI-MXI generates a 200 ms active low pulse both on power-up and when you press the pushbutton system reset switch on the front panel.
Configuration and Installation Chapter 3 VXI-MXI User Manual 3-24 © National Instruments Corporation MXIbus Termination The MXIbus is a matched impedance bus and requires termination networks at the first and last device in the MXIbus daisy-chain.
Chapter 3 Configuration and Installation © National Instruments Corporation 3-25 VXI-MXI User Manual networks are not used, you should leave these internal terminators in place.
Configuration and Installation Chapter 3 VXI-MXI User Manual 3-26 © National Instruments Corporation If the daughter card will be the first or last device in the INTX chain (irrespective of the VXI-MXI's position in the MXIbus chain), you should leave these terminators in place.
Chapter 3 Configuration and Installation © National Instruments Corporation 3-27 VXI-MXI User Manual • If interlocked mode is used, the VXI -MXIs must be the highest priority VMEbus requesters in their mainframe. However, one, and only one , mainframe in the MXIbus link can have a higher priority VMEbus requester than its VXI-MXIs.
Configuration and Installation Chapter 3 VXI-MXI User Manual 3-28 © National Instruments Corporation Connecting the MXIbus Cable MXIbus devices are daisy-chained together with MXIbus cables. Dual-ended cables are polarized and require proper connection to function properly.
Chapter 3 Configuration and Installation © National Instruments Corporation 3-29 VXI-MXI User Manual If your MXIbus cable has a single connector on one end and a dual-ended connector on the other end.
Configuration and Installation Chapter 3 VXI-MXI User Manual 3-30 © National Instruments Corporation In a properly configured MXIbus system, the first and last devices in the daisy-chain each have only one cable connected to their device connector.
Chapter 3 Configuration and Installation © National Instruments Corporation 3-31 VXI-MXI User Manual Keep in mind that a system can contain only one device acting as the VXIbus Resource Manager (RM). It is important that the RM be run only after all other devices in the system have been powered on.
© National Instruments Corporation 4-1 VXI-MXI User Manual Chapter 4 Register Descriptions This chapter contains detailed information on the use of the VXI-MXI registers, which are used to configure and control the module's operation.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-2 © National Instruments Corporation Table 4-1. VXI -MXI Register Map Register Name Offset from Base Type Size Address (Hex) VXIbus ID Register 0.
Chapter 4 Register Descriptions © National Instruments Corporation 4-3 VXI-MXI User Manual 3E 3C 3A 38 36 34 32 30 2E 2C 2A 28 26 24 22 20 1E 1C 1A 18 16 14 12 10 0E 0C 0A 08 06 04 02 00 Interrupt Ac.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-4 © National Instruments Corporation VXIbus Configuration Registers These registers are defined by the VXIbus specification for all VXIbus devices.
Chapter 4 Register Descriptions © National Instruments Corporation 4-5 VXI-MXI User Manual 11-0r MANID Manufacturer ID Bits This number uniquely identifies the manufacturer of the VXIbus device. These bits are configured in hardware as hex FF6, the VXIbus manufacturer ID number assigned to National Instruments.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-6 © National Instruments Corporation Device Type Register VXIbus Address: Base Address + 2 (hex) Attributes: Read Only R 15 14 13 12 11 10 9 0 0 .
Chapter 4 Register Descriptions © National Instruments Corporation 4-7 VXI-MXI User Manual VXIbus Status/Control Register VXIbus Address: Base Address + 4 (hex) Attributes: Read/Write R 15 14 13 12 1.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-8 © National Instruments Corporation 7-4r VERSION VXI-MXI Version Number Bits These bits specify the revision version number of the VXI-MXI according the table below.
Chapter 4 Register Descriptions © National Instruments Corporation 4-9 VXI-MXI User Manual VXIbus Extender Registers These registers are defined for VXIbus extender devices.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-10 © National Instruments Corporation Logical Address Window Register VXIbus Address: Base Address + A (hex) Attributes: Read/Write This register defines the range of logical addresses that are mapped into and out of the VXI-MXI through the MXIbus.
Chapter 4 Register Descriptions © National Instruments Corporation 4-11 VXI-MXI User Manual LAEN LADIR Window Applies to 0 X Disabled 10 VXI cycles to MXI cycles 1 MXI cycles to VXI cycles 12-11r/w 1 Reserved Bits These bits are reserved and read back as ones.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-12 © National Instruments Corporation The Logical Address Window Register has the following format when the CMODE bit is set: R/W 7 6543 2 1 LALO.
Chapter 4 Register Descriptions © National Instruments Corporation 4-13 VXI-MXI User Manual To accommodate 8-bit devices that write to this register, the window is not enabled until the lower byte of the register is written. Therefore, 8-bit devices should write the upper byte first, then the lower byte.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-14 © National Instruments Corporation A16 Window Map Register VXIbus Address: Base Address + C (hex) Attributes: Read/Write This register defines the range of addresses in the lower 48 KB of A16 space that is mapped into and out of the VXI -MXI through the MXIbus.
Chapter 4 Register Descriptions © National Instruments Corporation 4-15 VXI-MXI User Manual A16EN A16DIR Window Applies to 0 X Disabled 10 VXI cycles to MXI cycles 1 MXI cycles to VXI cycles 12-11r/w 1 Reserved Bits These bits are reserved and read back as ones.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-16 © National Instruments Corporation The A16 Window Map Register has the following format when the CMODE bit is set: R/W 7 6543 2 1 A16LOW7 A16L.
Chapter 4 Register Descriptions © National Instruments Corporation 4-17 VXI-MXI User Manual To accommodate 8-bit devices that write to this register, the window is not enabled until the lower byte of the register is written. Therefore, 8-bit devices should write the upper byte first, then the lower byte.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-18 © National Instruments Corporation A24 Window Map Register VXIbus Address: Base Address + E (hex) Attributes: Read/Write This register defines the range of addresses in A24 space that are mapped into and out of the VXI-MXI through the MXIbus.
Chapter 4 Register Descriptions © National Instruments Corporation 4-19 VXI-MXI User Manual A24EN A24DIR Window Applies to 0 X Disabled 10 VXI cycles to MXI cycles 1 MXI cycles to VXI cycles 12-11r/w 1 Reserved Bits These bits are reserved and read back as ones.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-20 © National Instruments Corporation The A24 Window Map Register has the following format when the CMODE bit is set: R/W 7 6543 2 1 A24LOW7 A24L.
Chapter 4 Register Descriptions © National Instruments Corporation 4-21 VXI-MXI User Manual To accommodate 8-bit devices that write to this register, the window is not enabled until the lower byte of the register is written. Therefore, 8-bit devices should write the upper byte first, then the lower byte.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-22 © National Instruments Corporation A32 Window Map Register VXIbus Address: Base Address + 10 (hex) Attributes: Read/Write This register defines the range of addresses in A32 space that are mapped into and out of the VXI-MXI through the MXIbus.
Chapter 4 Register Descriptions © National Instruments Corporation 4-23 VXI-MXI User Manual A32EN A32DIR Window Applies to 0 X Disabled 10 VXI cycles to MXI cycles 1 MXI cycles to VXI cycles 12-11r/w 1 Reserved Bits These bits are reserved and read back as ones.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-24 © National Instruments Corporation The A32 Window Map Register has the following format when the CMODE bit is set: R/W 7 6543 2 1 A32LOW7 A32L.
Chapter 4 Register Descriptions © National Instruments Corporation 4-25 VXI-MXI User Manual To accommodate 8-bit devices that write to this register, the window is not enabled until the lower byte of the register is written. Therefore, 8-bit devices should write the upper byte first, then the lower byte.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-26 © National Instruments Corporation INTX Interrupt Configuration Register (on VXI-MXIs with INTX only) VXIbus Address: Base Address + 12 (hex) .
Chapter 4 Register Descriptions © National Instruments Corporation 4-27 VXI-MXI User Manual INTX Trigger Configuration Register (on VXI-MXIs with INTX only) VXIbus Address: Base Address + 14 (hex) At.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-28 © National Instruments Corporation INTX Utility Configuration Register (on VXI-MXIs with INTX only) VXIbus Address: Base Address + 18 (hex) At.
Chapter 4 Register Descriptions © National Instruments Corporation 4-29 VXI-MXI User Manual 5r/w ACFAILIN Extended ACFAIL Inward Bit Setting this bit enables the INTX ACFAIL line to be mapped into the VMEbus ACFAIL line. Clearing this bit disables the mapping of the INTX ACFAIL line onto the VMEbus ACFAIL line.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-30 © National Instruments Corporation Subclass Register VXIbus Address: Base Address + 1E (hex) Attributes: Read only R 15 14 13 12 11 10 9 1 1 111 1 10 8 SUBCLASS 76 543 21 0 1 1 111 11 0 These bits define the subclass of a VXIbus extended device.
Chapter 4 Register Descriptions © National Instruments Corporation 4-31 VXI-MXI User Manual MXIbus Defined Registers MXIbus Status/Control Register VXIbus Address: Base Address + 20 (hex) Attributes:.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-32 © National Instruments Corporation MXI Address Modifiers RMWMODE Bit Routing Block X MXIbus block to VMEbus block Non-Block 0 MXIbus RMW cycle.
Chapter 4 Register Descriptions © National Instruments Corporation 4-33 VXI-MXI User Manual 11r MXSCTO MXIbus System Controller Timeout Status Bit If this VXI-MXI is the MXIbus System Controller, this bit is set if the VXI-MXI sent a MXIbus BERR on the last MXIbus transfer in response to a MXIbus System Controller Timeout.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-34 © National Instruments Corporation 8r FAIR VXI-MXI Fairness Status Bit When this bit is set, the VXI-MXI is configured as a fair MXIbus requester. If this bit is cleared, the VXI -MXI is configured as an unfair MXIbus requester.
Chapter 4 Register Descriptions © National Instruments Corporation 4-35 VXI-MXI User Manual 4r MXACFAILINT MXIbus ACFAIL Status Bit When this bit is set, the VXIbus ACFAIL line is active and is being driven across the MXIbus IRQ line. When this bit is cleared, the ACFAIL signal is not driving the MXIbus IRQ line.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-36 © National Instruments Corporation MXIbus Lock Register VXIbus Address: Base Address + 22 (hex) Attributes: Read/Write R 15 14 13 12 11 10 9 1.
Chapter 4 Register Descriptions © National Instruments Corporation 4-37 VXI-MXI User Manual MXIbus IRQ Configuration Register VXIbus Address: Base Address + 24 (hex) Attributes: Read/Write R/W 15 14 .
Register Descriptions Chapter 4 VXI-MXI User Manual 4-38 © National Instruments Corporation MIRQ x EN MIRQ x DIR Routing 0 X Disabled 10 VME IRQ X drives MXI IRQ 1 MXI IRQ drives VME IRQ X.
Chapter 4 Register Descriptions © National Instruments Corporation 4-39 VXI-MXI User Manual Drive Triggers/Read LA Register VXIbus Address: Base Address + 26 (hex) Attributes: Read/Write R/W 15 14 13.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-40 © National Instruments Corporation 1w DRVECL1 Drive ECL Trigger Line 1 Bit Setting this bit asserts the VXIbus ECL Trigger Line 1 after synchronizing the signal with the 10 MHz clock.
Chapter 4 Register Descriptions © National Instruments Corporation 4-41 VXI-MXI User Manual Trigger Mode Selection Register VXIbus Address: Base Address + 28 (hex) Attributes: Read/Write R 15 14 13 1.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-42 © National Instruments Corporation When in Sync, Semi-Sync, or Async Source Mode, write a zero to the PULSE bit in the Drive Triggers Register to generate a pulse on the trigger line selected by the OTS[3-0] bits.
Chapter 4 Register Descriptions © National Instruments Corporation 4-43 VXI-MXI User Manual 8w ETOEN External Trigger Output Enable Bit Setting this bit enables the OMS[2-0] modes to drive the selected trigger line to the TRIG OUT SMB connection.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-44 © National Instruments Corporation 3w ETRIG Enable Trigger Lines Bit When this bit is set, the protocols selected by the OMS[2-0] bits are enabled to drive the trigger line specified by the OTS[3-0] bits.
Chapter 4 Register Descriptions © National Instruments Corporation 4-45 VXI-MXI User Manual Interrupt Status/Control Register VXIbus Address: Base Address + 2A (hex) Attributes: Read/Write R 15 14 13.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-46 © National Instruments Corporation 12r ACFAILINT VXIbus ACFAIL Interrupt Status Bit If this bit is set, an interrupt is currently driven on the VMEbus interrupt line selected by the LINT[3-1] bits because the VXIbus ACFAIL line became set.
Chapter 4 Register Descriptions © National Instruments Corporation 4-47 VXI-MXI User Manual 8r ACFAIL VXIbus ACFAIL Status Bit This bit reflects the status of the VXIbus ACFAIL line.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-48 © National Instruments Corporation Status/ID Register VXIbus Address: Base Address + 2C (hex) Attributes: Read/Write R/W 15 14 13 12 11 10 9 S.
Chapter 4 Register Descriptions © National Instruments Corporation 4-49 VXI-MXI User Manual MXIbus Trigger Configuration Register VXIbus Address: Base Address + 2E (hex) Attributes: Read/Write R/W 15.
Register Descriptions Chapter 4 VXI-MXI User Manual 4-50 © National Instruments Corporation Trigger Synchronous Acknowledge Register VXIbus Address: Base Address + 34 (hex) Attributes: Write Only W 1.
Chapter 4 Register Descriptions © National Instruments Corporation 4-51 VXI-MXI User Manual IRQ Acknowledge Registers VXIbus Address: Base Address + 32 (hex) for IRQ1* Base Address + 34 (hex) for IRQ.
© National Instruments Corporation 5-1 VXI-MXI User Manual Chapter 5 Programming Considerations This chapter explains important considerations for programming and configuring a VXIbus/ MXIbus system using VXI -MXIs. Note: Detailed descriptions of all register bits can be found in Chapter 4, Register Descriptions .
Programming Considerations Chapter 5 VXI-MXI User Manual 5-2 © National Instruments Corporation PC with Multiframe Resource Manager Level 1 Level 2 MXIbus Device MXIbus Device VXIbus Mainframe VXI-MXI VXI-MXI VXIbus Mainframe VXI-MXI VXIbus Mainframe VXI-MXI MXIbus Interface Root Figure 5-1.
Chapter 5 Programming Considerations © National Instruments Corporation 5-3 VXI-MXI User Manual The recommended way to set up your system is to fill up Level 1 MXIbus links before adding additional levels. System performance decreases as the number of levels in the system increases because each level requires additional signal conversion.
Programming Considerations Chapter 5 VXI-MXI User Manual 5-4 © National Instruments Corporation Base7 Size = 1 Size = 2 Size = 3 Size = 4 Size = 5 Size = 6 Size = 7 Base6 Base5 Base4 Base3 Base2 Base1 Base0 Figure 5-3.
Chapter 5 Programming Considerations © National Instruments Corporation 5-5 VXI-MXI User Manual High/Low Configuration Format Each address mapping window on a MXIbus interface has High and Low address parameters associated with it when the CMODE bit in the MXIbus Control Register is set.
Programming Considerations Chapter 5 VXI-MXI User Manual 5-6 © National Instruments Corporation 3. Next, fill in the blanks for the number of logical addresses required by the first-level MXIbus devices.
Chapter 5 Programming Considerations © National Instruments Corporation 5-7 VXI-MXI User Manual 8. Determine the range of addresses that will be occupied by the root device and each first- level device and MXIbus link.
Programming Considerations Chapter 5 VXI-MXI User Manual 5-8 © National Instruments Corporation VXIbus Mainframe #1 VXI-MXI VXI-MXI VXIbus Mainframe #2 VXI-MXI MXIbus Device A MXIbus Device B VXIbus .
Chapter 5 Programming Considerations © National Instruments Corporation 5-9 VXI-MXI User Manual Into VXIbus Mainframe #3 FF-F0 EF-E0 DF-D0 CF-C0 BF-B0 AF-A0 9F-90 8F-80 7F-70 6F-60 5F-50 3F-30 4F-40 .
Programming Considerations Chapter 5 VXI-MXI User Manual 5-10 © National Instruments Corporation Resource Manager Mainframe: VXIbus Mainframe #1 Total number of logical addresses required by this dev.
Chapter 5 Programming Considerations © National Instruments Corporation 5-11 VXI-MXI User Manual MXIbus Link: MXIbus #1 Device: MXIbus Device A Number of logical addresses required by device: 3 Range.
Programming Considerations Chapter 5 VXI-MXI User Manual 5-12 © National Instruments Corporation MXIbus Link: MXIbus #2 Device: VXIbus Mainframe #6 Number of logical addresses required by device: 7 R.
Chapter 5 Programming Considerations © National Instruments Corporation 5-13 VXI-MXI User Manual Worksheets for Planning Your VXIbus/MXIbus Logical Address Map Use the worksheets on the following pages for analyzing your own VXIbus/MXIbus system. Follow the procedures used to fill out the worksheets for the sample VXIbus/MXIbus system.
Programming Considerations Chapter 5 VXI-MXI User Manual 5-14 © National Instruments Corporation Resource Manager Mainframe: Total number of logical addresses required by this device: Range = Round t.
Chapter 5 Programming Considerations © National Instruments Corporation 5-15 VXI-MXI User Manual MXIbus Link: Device: Number of logical addresses required by device: Range = Round total number up to .
Programming Considerations Chapter 5 VXI-MXI User Manual 5-16 © National Instruments Corporation MXIbus Link: Device: Number of logical addresses required by device: Range = Round total number up to .
Chapter 5 Programming Considerations © National Instruments Corporation 5-17 VXI-MXI User Manual MXIbus Link: Device: Number of logical addresses required by device: Range = Round total number up to .
Programming Considerations Chapter 5 VXI-MXI User Manual 5-18 © National Instruments Corporation Alternative Worksheets for Planning Your VXIbus/MXIbus Logical Address Map For most VXIbus/MXIbus systems, you may find the following worksheet helpful when setting up a system using the High/Low format for window configuration.
Chapter 5 Programming Considerations © National Instruments Corporation 5-19 VXI-MXI User Manual Device Device LA's Lower LA's Total LA's Range IN Range OUT Device Device LA's Low.
Chapter 5 Programming Considerations © National Instruments Corporation 5-21 VXI-MXI User Manual Planning a VXIbus/MXIbus System A16 Address Map The VXIbus specification does not define a method for dynamically determining the amount of A16 space each device requires.
Programming Considerations Chapter 5 VXI-MXI User Manual 5-22 © National Instruments Corporation BFFF-B000 AFFF-A000 9FFF-9000 8FFF-8000 7FFF-7000 6FFF-6000 5FFF-5000 4FFF-4000 3FFF-3000 2FFF-2000 1FFF-1000 0FFF-0000 F0 E0 C0 B0 A0 D0 90 80 50 40 00 60 70 30 20 10 Size = 2 Size = 3 Size = 4 Size = 5 Size = 6 Size = 7 Size = 1 Size = 0 Figure 5-12.
Chapter 5 Programming Considerations © National Instruments Corporation 5-23 VXI-MXI User Manual 4. Figure 5-17 is the worksheet for MXIbus #3, which includes VXIbus Mainframes #4 and #5. Mainframe #4 needs 2 KB and Mainframe #5 needs 1 KB of A16 space.
Programming Considerations Chapter 5 VXI-MXI User Manual 5-24 © National Instruments Corporation 5000 through 5FFF to MXIbus #3. For the VXI-MXI connected to MXIbus #3, we set Base = 5000, Size = 4 because 4 KB = 256 * 2 8-4 , and the direction toward MXIbus #3, or Out .
Chapter 5 Programming Considerations © National Instruments Corporation 5-25 VXI-MXI User Manual Table 5-4. Example VXIbus/MXIbus System Required A16 Space Amount of A16 Device Space Required VXIbus .
Programming Considerations Chapter 5 VXI-MXI User Manual 5-26 © National Instruments Corporation Resource Manager Mainframe: Amount of A16 space required for this mainframe: Round up to next address .
Chapter 5 Programming Considerations © National Instruments Corporation 5-27 VXI-MXI User Manual MXIbus Link: Device: Amount of A16 space required by this device: A16 space requirement for each secon.
Programming Considerations Chapter 5 VXI-MXI User Manual 5-28 © National Instruments Corporation MXIbus Link: Device: Amount of A16 space required by this device: A16 space requirement for each secon.
Chapter 5 Programming Considerations © National Instruments Corporation 5-29 VXI-MXI User Manual Worksheets for Planning Your VXIbus/MXIbus A16 Address Map Use the worksheets on the following pages for planning an A16 address map for your VXIbus/ MXIbus system.
Programming Considerations Chapter 5 VXI-MXI User Manual 5-30 © National Instruments Corporation Resource Manager Mainframe: Amount of A16 space required for this mainframe: Round up to next address .
Chapter 5 Programming Considerations © National Instruments Corporation 5-31 VXI-MXI User Manual MXIbus Link: Device: Amount of A16 space required by this device: A16 space requirement for each secon.
Programming Considerations Chapter 5 VXI-MXI User Manual 5-32 © National Instruments Corporation MXIbus Link: Device: Amount of A16 space required by this device: A16 space requirement for each secon.
Chapter 5 Programming Considerations © National Instruments Corporation 5-33 VXI-MXI User Manual MXIbus Link: Device: Amount of A16 space required by this device: A16 space requirement for each secon.
Programming Considerations Chapter 5 VXI-MXI User Manual 5-34 © National Instruments Corporation MXIbus Link: Device: Amount of A16 space required by this device: A16 space requirement for each secon.
Chapter 5 Programming Considerations © National Instruments Corporation 5-35 VXI-MXI User Manual Multiframe RM Operation On power-up, all MXIbus devices are isolated from each other because all address mapping windows are disabled.
Programming Considerations Chapter 5 VXI-MXI User Manual 5-36 © National Instruments Corporation b. Repeats Step 2 recursively. c. Sets the VXI-MXI inward logical address mapping window to cover the range up to (but not including) the VXI-MXI with the next highest logical address that was found in the logical address space.
Chapter 5 Programming Considerations © National Instruments Corporation 5-37 VXI-MXI User Manual The RM performs the following steps: 1. Scans logical addresses (0 to FF) and identifies all devices in VXIbus Mainframe #1.
Programming Considerations Chapter 5 VXI-MXI User Manual 5-38 © National Instruments Corporation 9. Enables the logical address window of the VXI-MXI in VXIbus Mainframe #2 for the entire inward mapping range of 0 to FF. Scans all logical addresses, skipping all previously encountered devices and defined ranges.
Chapter 5 Programming Considerations © National Instruments Corporation 5-39 VXI-MXI User Manual System Administration and Initiation System self-test administration, hierarchy configuration, and initiation of normal operation are handled as defined in the VXIbus specification.
© National Instruments Corporation 6-1 VXI-MXI User Manual Chapter 6 Theory of Operation A brief description of the VXI-MXI is given in Chapter 2 along with a functional block diagram (see Figure 2-1). The major elements of the VXI-MXI are discussed in more detail in this chapter.
Theory of Operation Chapter 6 VXI-MXI User Manual 6-2 © National Instruments Corporation VMEbus Control Signals Transceivers The VMEbus control signals transceivers control the sending and receiving .
Chapter 6 Theory of Operation © National Instruments Corporation 6-3 VXI-MXI User Manual The Synchronous protocol is a single trigger line broadcast that does not require an acknowledge from its acceptors. The source must assert the trigger for a minimum of 30 ns and allow at least 50 ns between assertions.
Theory of Operation Chapter 6 VXI-MXI User Manual 6-4 © National Instruments Corporation The two trigger interrupt conditions are Trigger Synchronous and Trigger Asynchronous. A synchronous trigger interrupt occurs when the input trigger signal changes from low to high.
Chapter 6 Theory of Operation © National Instruments Corporation 6-5 VXI-MXI User Manual Multiple MXIbus devices can interrupt on the same interrupt line; therefore, a MXIbus interrupt acknowledge daisy-chain is required. The MXIbus GIN and GOUT signals are normally used for the arbitration bus grant in/bus grant out daisy-chain.
Theory of Operation Chapter 6 VXI-MXI User Manual 6-6 © National Instruments Corporation The VMEbus interrupt lines can be individually driven by writing to the Interrupt Status/Control Register.
Chapter 6 Theory of Operation © National Instruments Corporation 6-7 VXI-MXI User Manual complete when the responding device sends DTACK* and the VXI -MXI releases the data strobe and address strobe. The VXI -MXI interface supports 8-bit, 16-bit, and 32-bit reads and writes across the MXIbus.
Theory of Operation Chapter 6 VXI-MXI User Manual 6-8 © National Instruments Corporation Table 6-3. Transfer Responses for VMEbus Address Modifiers AM5 AM4 AM3 AM2 AM1 AM0 Transfer Type HHHHHH A24 su.
Chapter 6 Theory of Operation © National Instruments Corporation 6-9 VXI-MXI User Manual Table 6-4. VMEbus/MXIbus Transfer Size Comparison VMEbus MXIbus Byte Locations DS1* DS0* A01 LWORD* Size AD01 .
Theory of Operation Chapter 6 VXI-MXI User Manual 6-10 © National Instruments Corporation VXI-MXI VXI-MXI VXIbus Mainframe #1 VXIbus Mainframe #2 MXIbus VMEbus VMEbus Slave Slave Master Master Slave Slave Figure 6-2.
Chapter 6 Theory of Operation © National Instruments Corporation 6-11 VXI-MXI User Manual Table 6-3. When a transfer involving an address in one of the inward windows is detected, the VXI-MXI begins arbitrating for the VMEbus. When the VXI -MXI wins the VMEbus, the MXIbus transfer is converted into a VMEbus transfer.
Theory of Operation Chapter 6 VXI-MXI User Manual 6-12 © National Instruments Corporation MXIbus specifies trapezoidal bus transceivers to reduce noise and crosstalk in the MXIbus transmission system. These transceivers have open collector drivers that generate precise trapezoidal waveforms with typical rise and fall times of 9 ns.
Chapter 6 Theory of Operation © National Instruments Corporation 6-13 VXI-MXI User Manual All MXIbus masters must have bus request logic for requesting the MXIbus, and the MXIbus System Controller must have bus arbiter logic to grant the bus to requesting masters.
Theory of Operation Chapter 6 VXI-MXI User Manual 6-14 © National Instruments Corporation For example, if the VXI -MXI owns the VMEbus and it receives a VMEbus bus request from another VXIbus device, the VXI-MXI continues holding the VMEbus and arbitrates for the MXIbus.
© National Instruments Corporation A-1 VXI-MXI User Manual Appendix A Specifications Capability Codes VMEbus Capability Code Description MA32, MA24, MA16 Master Mode A32, A24, and A16 addressing SA32.
Specifications Appendix A VXI-MXI User Manual A-2 © National Instruments Corporation MXIbus Capability Code Description MA32, MA24, MA16 Master Mode A32, A24, and A16 addressing SA32, SA24, SA16 Slav.
Appendix A Specifications © National Instruments Corporation A-3 VXI-MXI User Manual Safety Not applicable Shock and Vibration Not applicable Physical Board size Fully shielded VXI C-size board (9.
© National Instruments Corporation B-1 VXI-MXI User Manual Appendix B Mnemonics Key This appendix contains an alphabetical listing of mnemonics used in this manual to describe signals and terminology specific to MXIbus, VMEbus, VXIbus, and register bits.
Mnemonics Key Appendix B VXI-MXI User Manual B-2 © National Instruments Corporation Mnemonic Type Definition A A01 VBS VME Address Line 1 A16BASE[7-0] B A16 Window Base Address A16DIR B A16 Window Di.
Appendix B Mnemonics Key © National Instruments Corporation B-3 VXI-MXI User Manual Mnemonic Type Definition BTO VBS/MBS Bus Timeout BUSY* MBS Bus Busy C CLK10 VXS VXIbus 10-MHz System Clock CMODE B .
Mnemonics Key Appendix B VXI-MXI User Manual B-4 © National Instruments Corporation Mnemonic Type Definition I I[15-0] B Interrupt Acknowledge Status/ID IACK* VME VMEbus Interrupt Acknowledge IACKIN*.
Appendix B Mnemonics Key © National Instruments Corporation B-5 VXI-MXI User Manual Mnemonic Type Definition O OMS[2-0] B Output Trigger Mode Select OTS[3-0] B Output Trigger Select OUTEN B MODID Out.
Mnemonics Key Appendix B VXI-MXI User Manual B-6 © National Instruments Corporation Mnemonic Type Definition T TERMPWR MXI Terminator Power TRIGDIR[7-0] B Trigger Direction TRIGEN[7-0] B Trigger Enab.
© National Instruments Corporation C-1 VXI-MXI User Manual Appendix C VXI-MXI Component Placement This appendix contains instructions on opening the VXI-MXI module, and removing and reinstalling the optional INTX daughter card. This appendix also contains parts locator diagrams of the VXI-MXI and the INTX daughter card.
VXI-MXI Component Placement Appendix C VXI-MXI User Manual C-2 © National Instruments Corporation Figure C-1. VXI -MXI Parts Locator Diagram.
Appendix C VXI-MXI Component Placement © National Instruments Corporation C-3 VXI-MXI User Manual Removing the INTX Daughter Card from the VXI-MXI Under normal circumstances you will not need to remove the INTX card from the VXI-MXI module.
VXI-MXI Component Placement Appendix C VXI-MXI User Manual C-4 © National Instruments Corporation Figure C-3 is a parts locator diagram of the front side of the INTX daughter card, showing the location of the various components.
© National Instruments Corporation D- 1 VXI-MXI User Manual Appendix D Connector Descriptions This appendix describes the connector pin assignments for the MXIbus connector and the INTX connector. MXIbus Connector The MXIbus signals are assigned to the device connector as shown in Figure D-1 and Table D-1.
Connector Descriptions Appendix D VXI-MXI User Manual D- 2 © National Instruments Corporation The MXIbus defines 49 active signals, 12 ground lines, and 1 line for terminator power. Table D-2 describes the signals on the MXIbus connector and groups them in five categories.
Appendix D Connector Descriptions © National Instruments Corporation D- 3 VXI-MXI User Manual INTX Connector The INTX connector is used only on VXI-MXIs with the INTX daughter card option. The INTX signals are assigned to the device connector as shown in Figure D-2 and Table D-3.
Connector Descriptions Appendix D VXI-MXI User Manual D- 4 © National Instruments Corporation Table D-4. INTX Signal Groupings Category Description Signal Name Lines Type § Interrupts INTX Interrupt IRQ7-1* 7 O.C. Triggers INTX Trigger TRIG7-0 +,- 16 Diff Utility Lines INTX SYSRESET SYSRESET* 1 O.
© National Instruments Corporation E-1 VXI-MXI User Manual Appendix E Configuring a Two-Frame System This appendix describes how to configure a system containing two mainframes linked by VXI-MXI modules. Configuring VXI-MXIs for a Two-Frame System The factory configuration of the VXI-MXI is suitable for the most common system configurations.
Configuring a Two-Frame System Appendix E VXI-MXI User Manual E-2 © National Instruments Corporation Figure E-2 shows the necessary settings of the VXI -MXI configuration jumpers and switches for a VXI-MXI without the INTX option installed in Frame A.
Appendix E Configuring a Two-Frame System © National Instruments Corporation E-3 VXI-MXI User Manual Figure E-3 shows the necessary settings of the VXI -MXI configuration jumpers and switches for a VXI-MXI without the INTX option installed in Frame B.
Configuring a Two-Frame System Appendix E VXI-MXI User Manual E-4 © National Instruments Corporation Figure E-4 shows the necessary settings of the VXI -MXI configuration jumpers and switches for a VXI-MXI with the INTX option installed in Frame A. Figure E-4.
Appendix E Configuring a Two-Frame System © National Instruments Corporation E-5 VXI-MXI User Manual Figure E-5 shows the necessary settings of the VXI -MXI configuration jumpers and switches for a VXI-MXI with the INTX option installed in Frame B. Figure E-5.
Configuring a Two-Frame System Appendix E VXI-MXI User Manual E-6 © National Instruments Corporation Configuration Requirements for Two-Frame System This section contains miscellaneous information you need to consider as you configure a two-frame system.
© National Instruments Corporation F-1 VXI-MXI User Manual Appendix F Customer Communication For your convenience, this appendix contains forms to help you gather the information necessary to help us solve technical problems you might have as well as a form you can use to comment on the product documentation.
Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware, and use the completed copy of this form as a reference for your current configuration.
VXI-MXI Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item. Complete a new copy of this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration.
Other Products • Other MXIbus Devices in System Manufacturer Model Function Slot Logical Address • Other VXIbus Devices Manufacturer Model Function Slot Logical Address • Address Space(s) and Si.
Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: VXI-MXI User Manual Edition Date: October 1993 Part Number: 320222-01 Please comment on the completeness, clarity, and organization of the manual.
© National Instruments Corporation Glossary-1 VXI-MXI User Manual Glossary ___________________________________________________ Prefix Meaning Value n- nano- 10 -9 µ- micro- 10 -6 m- milli- 10 -3 K- .
Glossary VXI-MXI User Manual Glossary-2 © National Instruments Corporation Address Modifier One of six signals in the VMEbus specification used by VMEbus masters to indicate the address space and mode (supervisory/nonprivileged, data/ program/block) in which a data transfer is to take place.
Glossary © National Instruments Corporation Glossary-3 VXI-MXI User Manual Block-mode An uninterrupted transfer of data elements in which the master sources Transfer only the first address at the beginning of the cycle.
Glossary VXI-MXI User Manual Glossary-4 © National Instruments Corporation Configuration A set of registers through which the system can identify a module device Registers requirements.
Glossary © National Instruments Corporation Glossary-5 VXI-MXI User Manual Dynamically A device that has its logical address assigned by the Resource Manager. A Configured Device VXI device initially responds at Logical Address 255 when its MODID line is asserted.
Glossary VXI-MXI User Manual Glossary-6 © National Instruments Corporation I IACK Interrupt Acknowledge IC Integrated Circuit IEEE Institute of Electrical and Electronics Engineers IEEE 1014 The VME specification. in. inches I/O input/output; the techniques, media, and devices used to achieve communication between entities.
Glossary © National Instruments Corporation Glossary-7 VXI-MXI User Manual M MB megabytes of memory m meters Mainframe Extender A device such as the VXI-MXI that interfaces a VXIbus mainframe to an interconnect bus. It routes bus transactions from the VXIbus to the interconnect bus or vice versa.
Glossary VXI-MXI User Manual Glossary-8 © National Instruments Corporation N Nonprivileged One of the defined types of VMEbus data transfers; indicated by certain Access address modifier codes. Each of the defined VMEbus address spaces has a defined nonprivileged access mode.
Glossary © National Instruments Corporation Glossary-9 VXI-MXI User Manual Resource Manager A Message-Based Commander located at Logical Address 0, which provides configuration management services such as address map configuration, Commander and Servant mappings, and self-test and diagnostic management.
Glossary VXI-MXI User Manual Glossary-10 © National Instruments Corporation SMB Sub-miniature BNC; a miniature connector for coaxial cable connections.
Glossary © National Instruments Corporation Glossary-11 VXI-MXI User Manual TERMPWR Termination Power; 3.4 VDC for the MXIbus. Trigger Either TTL or ECL lines used for intermodule communication.
© National Instruments Corporation Index-1 VXI-MXI User Manual Index A A16 Window Map Register, 4-14 to 4-17 bit descriptions, 4-14 to 4-15, 4-16 definition, 2-7 description, 4-14 example, 4-15 forma.
Index VXI-MXI User Manual Index-2 © National Instruments Corporation A32EN, 4-22, 4-23 A32HIGH[7-0], 4-24 A32LOW[7-0], 4-24 A32SIZE[2-0], 4-23 ACCDIR, 4-7 ACFAIL, 4-47 ACFAILIE, 4-47 ACFAILIN, 4-29 A.
Index © National Instruments Corporation Index-3 VXI-MXI User Manual BTO. See VME BTO chain position; VME BTO circuitry. bus master compliance levels, 2-4 bus slave compliance levels, 2-3 C cable con.
Index VXI-MXI User Manual Index-4 © National Instruments Corporation environmental specifications, A-2 to A-3 equipment, optional, 1-6 to 1-7 ETOEN bit, 4-43 ETRG[7-0]DIR bit, 4-27 ETRG[7-0]EN bit, 4.
Index © National Instruments Corporation Index-5 VXI-MXI User Manual J jumpers and switches CLK10 source signal options, 3-19 EXT CLK SMB input/output, 3-20 factory default settings VXI-MXI with INTX.
Index VXI-MXI User Manual Index-6 © National Instruments Corporation connector description, D-1 to D-2 definition, 1-4 limit for daisy-chained devices, 3-29 mapping, 1-4 signal assignments, D-1 signa.
Index © National Instruments Corporation Index-7 VXI-MXI User Manual R RDY bit, 4-8 registers description format, 4-1 hard reset, 4-1 MXIbus defined registers Drive Triggers/Read LA Register, 4-39 to.
Index VXI-MXI User Manual Index-8 © National Instruments Corporation SUBCLASS bit, 4-30 Subclass Register, 4-30 switches. See jumpers and switches. Synchronous protocol, 6-3 SYSFAIL bit, 4-46 SYSFAIL.
Index © National Instruments Corporation Index-9 VXI-MXI User Manual signals list of signals, 2-1 to 2-2 signals supplied by VXI-MXI, 1-4 to 1-5 VMEbus Data Transfer Bus Arbiter (PRI ARBITER), 3-5 VMEbus Data Transfer Bus (DTB), 3-7 VMEbus System Controller, 3-5 VMEbus timeout.
デバイスVXI 320222-01の購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
VXI 320222-01をまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはVXI 320222-01の技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。VXI 320222-01の取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。VXI 320222-01で得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
VXI 320222-01を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はVXI 320222-01の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、VXI 320222-01に関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちVXI 320222-01デバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
