CypressメーカーCY14B104Kの使用説明書/サービス説明書
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PRELIMINARY CY14B104K, CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real T ime Clock Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-07103 Rev .
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 2 of 31 Pinout s Figure 1. Pi n Diagram - 44-P In and 54 -Pin TSOP II T able 1. Pin Definitions Pin Name I/O T ype Description A 0 – A 18 Input Address Inputs Used to Select one of the 524,288 bytes of the nvSRAM for x8 Configuration .
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 3 of 31 Device Operation The CY14B104K/CY14B104M nvSRAM is made u p of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile Qua ntumT rap cell.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 4 of 31 power-on-recall, the MPU must be active or the WE held inactive until the MPU comes out of reset.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 5 of 31 Preventing AutoStore The AutoS tore function is disabled by initiati ng an AutoS tore disable sequence. A sequence of read ope rations is performed in a manner si milar to the Software STORE initiation.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 6 of 31 Dat a Protection The CY14B104K/CY14B104M prot ects data from corruption during low voltage conditio ns by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected w hen V CC is less than V SWITCH .
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 7 of 31 must be set to ‘1’. This turns off the oscillator circuit, extending the battery life. If the OSCEN bit goes from disabled to ena bled, it takes approximately one second (two seconds maximum) for the oscillator to start.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 8 of 31 New time out values are written b y setting the watchd og write bit to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out value bits D5-D0 are enabled to modify the time out value .
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 9 of 31 Figure 4. RTC Rec ommended Component Co nfiguration Figure 5. Interrupt Block Diagram Recommended V alues Y 1 = 32.768 KHz (6 pF) C 1 = 21 pF C 2 = 21 pF X 1 X 2 Y1 C2 C1 Note: The recommende d values for C1 and C2 incl ude board trace capacit ance.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 10 of 31 T able 4. RTC Register Map [8] Register BCD Format Data [9] Function/Range CY14B104K CY14B104M D7 D6 D5 D4 D3 D2 D1 D0 0x7.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 1 1 of 31 T able 5. Register Map Detail Register Description CY14B104K CY14B104M 0x7FFFF 0x3FFFF Time Keeping - Y ears D7 D6 D5 D4 D3 D2 D1 D0 10s Y ea rs Y ears Contains the lower two BCD digits of the year .
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 12 of 31 Register Description CY14B104K CY14B104M 0x7FFF8 0x3FFF8 Calibration/Control D7 D6 D5 D4 D3 D2 D1 D0 OSCEN 0 Calibration Sign Calibration OSCEN Oscillato r Enable. When set to 1, the oscillator is stopped.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 13 of 31 Register Description CY14B104K CY14B104M 0x7FFF4 0x3FFF4 Alarm - Hours D7 D6 D5 D4 D3 D2 D1 D0 M 10s Alarm Hours Alarm Hours Contains the alarm value for the hours and the mask bi t to select or deselect the hours value.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 14 of 31 Maximum Ratin gs Exceeding maximum ratings may impair the useful life of the device. These user guid elines are not tested. S torage T emperature ................ ..........
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 15 of 31 AC T est Conditions Input Pulse Levels ..................... ........... .............. ...... 0V to 3V Input Rise and Fall T imes (10% - 90%) ..... ................. .. < 3 ns Input and Output T iming Reference Levels .
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 16 of 31 T able 6. RTC Characteristics Parameters Description T est Conditions Min Ty p Max Units I BAK [15] RTC Backup Current Room T emperature (25 o C) 300 nA Hot T emperature (85 o C) 450 nA V RTC ba t RTC Battery Pin V oltage 1.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 17 of 31 AC Switching Characteristics Parameters Description 20 ns 25 ns 45 ns Unit Cypress Parameters Alt Parameters Min Max Min M.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 18 of 31 Switching W aveforms Figure 8. SRAM Read Cycle 2: CE Controlled [3 , 16, 20] Figure 9.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 19 of 31 Switching W aveforms Figure 10. SRAM Write Cycle 2: CE Con trolled [3, 19, 20, 21] Figure 1 1 .
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 20 of 31 AutoStore/Power Up RECALL Parameters Descrip tion 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t HRECALL [23] Power Up R.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 21 of 31 Sof tware Controlled ST ORE and RECALL Cycle In the following table, the software controlled STORE and RECALL cycle p arameters are listed.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 22 of 31 Hardware STORE Cycle Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t DHSB HSB T o Output Active Time when write latch not set 20 25 25 ns t PHSB Hardware STORE Pulse Wid th 15 15 15 ns Switching W aveforms Figure 15.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 23 of 31 T ruth T able For SRAM Operations HSB should remain HIGH for SRAM Operations.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 24 of 31 Part Numbering Nomenclature Option: T - T ape & Reel Blank - S td. S peed: 20 - 20 ns 25 - 25 ns Data Bus: K - x8 + RT C M - x16 + RTC Density: 104 - 4 Mb V oltage: B - 3.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 25 of 31 Ordering Information Spee d (ns) Ordering Code Pac kage Diagram Package T ype Operating Range 20 CY14B104K-ZS20XCT 51-8508.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 26 of 31 Package Diagrams Figure 17. 44-Pin TSOP II (51-85087) MAX MIN. DIMENSION IN MM (INCH) 11.938 (0.470) PLANE SEATING PIN 1 I.D. 44 1 18.517 (0.729) 0.800 BSC 0° -5° 0.400(0.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 27 of 31 Figure 18. 54-Pin TSOP II (51-85160) Package Diagrams (continued) 51-85160 ** [+] Feedback.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 28 of 31 Document History Page Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock Document Number: 001-07103 Rev . ECN No. Submi ssion Date Orig.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 29 of 31 *F 1890926 See ECN vsutmp8/AE- SA Added Footnote 1, 2 and 3. Updated Logic Block d iagram Updated Pin definition T able Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8 ) package.
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev . *K Page 30 of 31 *I 2519319 06/20/08 GVCH/PYRS Added 20 ns access speed in “Features” Added I CC1 for tRC=20 ns for b oth industrial an.
Document #: 001-07103 Rev . *K Revised January 29, 2009 Page 31 of 31 AutoS tore and Qu antumT rap are re gistered tradem arks of Cypress Semico nductor Corpora tion. All product s and compa ny names mentio ned in this document are th e trademarks of their resp ective holders.
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Cypress CY14B104Kを既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はCypress CY14B104Kの不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Cypress CY14B104Kに関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちCypress CY14B104Kデバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
