CypressメーカーCY14B108Kの使用説明書/サービス説明書
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PRELIMINARY CY14B108K, CY14B108M 8 Mbit (1024K x 8/512K x 16) nvSRAM with Real T ime Clock Cypress Semiconducto r Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-47378 Rev .
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 2 of 29 Pinout s Figure 1. Pin Di a gr am : 44 -PI n and 54-Pin TSOP II T able 1. Pin Definitions Pin Name I/O T ype Description A 0 – A 19 Input Address Inputs Used to Select one of the 1,048,576 by tes of the nvSRAM for x8 Configuration .
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 3 of 29 Device Operation The CY14B108K/CY14B108M nvSRAM is made u p of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile Qua ntumT rap cell.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 4 of 29 power-on-recall, the MPU must be active or the WE held inactive until the MPU come s out of reset.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 5 of 29 Preventing AutoStore The AutoS tore function is disab led by initiati ng an AutoS tore disable sequence. A sequence of read ope rations is performed in a manner si milar to th e Software STORE initiation.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 6 of 29 Dat a Protection The CY14B108K/CY14B108M prot ects data from corruption during low voltage conditio ns b y inhibi ti ng all external ly initiated STORE and write operations. The low voltage condition is detected w hen V CC is less than V SWITCH .
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 7 of 29 Real Time Clock Operation nvTime Operation The CY14B108K/CY14B108 M offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. RTC registers use the last 16 address locations of the SRAM.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 8 of 29 calibration registers and the OSCEN bit are not affected by the ‘oscillator failed’ con dition. The value of OSCF must be reset to ‘0’ when the time reg isters are writ ten for t he first ti me.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 9 of 29 Figure 3. W atchdog Timer Block Diagram . Power Monitor The CY14B108K provides a power manage ment scheme with power fail interrupt capability . It also controls the internal switch to backup power for the clock and protects the memory from low V CC access.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 10 of 29 Figure 4. RTC Recommended Component Configuration Figure 5. Interrupt Block Diagram Recommended V alues Y 1 = 32.768 KHz (6 pF) C 1 = 21 pF C 2 = 21 pF Note: The recommende d values for C1 and C2 include board trace cap acitance .
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 1 1 of 29 T able 4. RTC Register Map [7] Register BCD Format Data [8] Function/Range CY14B108K CY14B108M D7 D6 D5 D4 D3 D2 D1 D0 0x.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 12 of 29 T able 5. Register Map Detail Register Description CY14B108K CY14B108M 0xFFFFF 0x7FFFF Time Keeping - Y ears D7 D6 D5 D4 D3 D2 D1 D0 10s Y ears Y ears Contains the lower two BCD di gits of the year .
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 13 of 29 Register Description CY14B108K CY14B108M 0xFFFF8 0x 7FFF8 Calibration/Con trol D7 D6 D5 D4 D3 D2 D1 D0 OSCEN 0 Calibrat ion Sign Calibration OSCEN O scillator Enable. When set to 1, the oscillator is stopped.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 14 of 29 Register Description CY14B108K CY14B108M 0xFFFF4 0x 7FFF4 Alarm - Hours D7 D6 D5 D4 D3 D2 D1 D0 M 10s Alarm Hours Alarm Hours Contains the alarm value for the hours and the mask bi t to select or deselect the hours value.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 15 of 29 Maximum Ratin gs Exceeding maximum ratings may impair the useful life of the device. These user g uidelines are not tested. S t orage T emperature ............. ... .. ... .
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 16 of 29 AC T est Conditions Input Pulse Levels ....................... ............ ........... ...... 0V to 3V Input Rise and Fall T imes (10% - 90%) ........ ................ < 3 ns Input and Output T iming Reference Levels .
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 17 of 29 T able 6. RTC Characteristics Parameters Description T est Conditions Min Ty p Max Units I BAK [14] RTC Backup Current Room T e mperature (25 o C) 300 nA Hot T emperature (85 o C) 4 50 nA V RTC ba t RTC Battery Pin V oltage 1.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 18 of 29 AC Switching Characteristics Parameters Descriptio n 20 ns 25 ns 45 ns Unit Cypress Parameters Alt Parameter s Min Max Min.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 19 of 29 Switching W aveforms Figure 8. SRAM Read Cycle 2: CE Controlled [3, 15, 1 9] Figure 9.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 20 of 29 Switching W aveforms Figure 10. SRAM Write Cycle 2: CE Controll ed [3, 18, 19, 2 0] Figure 1 1 .
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 21 of 29 AutoStore/Power Up RECALL Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t HRECALL [22] Power Up RE.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 22 of 29 Sof tware Controlled ST ORE and RECALL Cycle In the following table, the software controlled STORE and RECALL cycle parameters are listed.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 23 of 29 Hardware STORE Cycle Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t DHSB HSB T o Outp ut Active Time when write latch not set 20 25 25 ns t PHSB Hardware STORE Pulse Wid th 15 15 15 ns Switching W aveforms Figure 15.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 24 of 29 T ruth T able For SRAM Operations HSB should remain HIGH for SRAM Operations.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 25 of 29 Part Numbering Nomenclature Option: T - T ap e & Reel Blank - S t d. S peed: 20 - 20 ns 25 - 25 ns Data Bus: K - x8 + RT C M - x16 + RTC Density: 108 - 8 Mb V oltage: B - 3.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 26 of 29 Ordering Information Spee d (ns) Ordering Code Pac kage Diagram Package T yp e Operating Range 20 CY14B108K-ZS20XCT 51-850.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 27 of 29 Package Diagrams Figure 17. 44-Pin TSOP II (51-85087) MAX MIN. DIMENSION IN MM (INCH) 11.938 (0.470) PLANE SEATING PIN 1 I.D. 44 1 18.517 (0.729) 0.800 BSC 0° -5° 0.400(0.
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 28 of 29 Figure 18. 54-Pin TSOP II (51-85160) Package Diagrams (continued) 51-85160 ** [+] Feedback.
Document #: 001-47378 Rev . ** Revised April 01, 2009 Page 29 of 29 AutoS tore and QuantumT rap are re gistered trad emarks of Cypress Semi conductor Corpo ration. All prod ucts and com pany names menti o ned in this documen t are the trad emark s of th eir resp ectiv e holders.
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Cypress CY14B108Kをまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはCypress CY14B108Kの技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Cypress CY14B108Kの取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Cypress CY14B108Kで得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Cypress CY14B108Kを既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はCypress CY14B108Kの不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Cypress CY14B108Kに関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちCypress CY14B108Kデバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。