CypressメーカーCY7C1318JV18の使用説明書/サービス説明書
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18-Mbit DDR-II SRAM 2-W ord Burst Architecture CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-15271 Rev .
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 2 of 26 Logic Block Diagram (CY7C1316JV18) Logic Block Diagram (CY7C1916JV18) Wri te Reg Wri te Reg CLK A (19:0) Gen. K K Control Logic Address Register Read Add.
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 3 of 26 Logic Block Diagram (CY7C1318JV18) Logic Block Diagram (CY7C1320JV18) Wri te Reg Wri te Reg CLK A (19:0) Gen. K K Control Logic Address Register Read Add.
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 4 of 26 Pin Configuration The pin configuration for CY7C1316JV18, CY7C1318 JV18, and CY7C1320JV18 follow .
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 5 of 26 CY7C1318JV18 (1 M x 18) 123456789 1 0 1 1 A CQ NC/72M A R/W BWS 1 K NC/14 4M LD A NC/36M CQ B NC .
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 6 of 26 Pin Definitions Pin Name IO Pin Descripti on DQ [x:0] Input Output- Synchronous Data Input Output Signals . Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 7 of 26 CQ Output Clock CQ is Referenced with Respect to C . This is a free running clock and is synchronized to the input cl ock for output data (C) of the DDR-II.
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 8 of 26 Functional Overview The CY7C1316JV18, CY7C191 6JV18, CY7C1318JV18, and CY7C1320JV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of one and half cycles when DOFF pin is tied HIGH.
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 9 of 26 driver impedance. The value of RQ must be 5x the value of th e intended line impedance d riven by the SRAM. The allo wable range of RQ to guarantee impe dance matching with a to lerance of ±15% is between 175 Ω an d 350 Ω , with V DD Q =1 .
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 10 of 26 T ruth T able The truth table for the CY7C1316JV18, CY7C1 916JV1 8, CY7C1318JV18, and CY7C1320JV18 follow s.
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 1 1 of 26 Write Cycle Descriptions The write cycle description tabl e for CY7C1916JV18 follows. [2, 8] BWS 0 K K Comments L L–H – During the Data portion of a write sequence, the single byte (D [8:0] ) is written int o the de vi ce .
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 12 of 26 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 149.
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 13 of 26 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister .
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 14 of 26 T AP Controller St ate Diag ram The state diagram for the T AP controller follows.
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 15 of 26 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1, 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 16 of 26 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Ma.
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 17 of 26 Identification R egi ster Definitions Instruction Field Va l u e Description CY7C1316JV18 CY7C1916JV18 CY7C1 318JV18 CY7C1320JV18 Revision Numb er (31:29) 001 001 001 001 V ersion number .
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 18 of 26 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84.
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 19 of 26 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be power ed up and initialized in a predefined manner to prevent unde fined operations. During power up, when th e DOFF is tied H IGH, the DLL is locked a fter 1024 cycles of st able clock.
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 20 of 26 Maximum Ratings Exceeding maximum ratings may shorte n the battery life of the device. User guidelines are not te ste d. S torage T emperature ....
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 21 of 26 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 22 of 26 Switching Characteristics Over the Operating Range [19] Cypress Parameter Consor tium Parameter Description 300 MHz Unit Min Max t POWER V DD (T ypical) to the first Access [20] 1– m s t CYC t KHKH K Clock and C Clock Cycle Time 3.
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 23 of 26 Switching W aveforms Figure 3. Read/Write/Deselect Sequence [2 4, 25, 26 ] READ READ READ NOP NO.
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 24 of 26 Ordering Information Not all of the speed, package and temperature ranges are ava ilable. Please contact your local sales representative or visit www .
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev . *B Page 25 of 26 Package Diagram Figure 4. 165-ball FBGA (13 x 15 x 1.40 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø 0 . 2 5MCAB Ø0.
Document Number: 001-15271 Rev . *B Revised March 10, 2008 Page 26 of 26 QDR RAMs an d Quad Data Rate RAMs comp rise a new family of product s develope d by Cypress, IDT , NEC, Renesas, and Samsung. All pr oduct and co mpany nam es mentioned i n this documen t are the tr ad emarks of their respe ctive hold ers.
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Cypress CY7C1318JV18を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はCypress CY7C1318JV18の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Cypress CY7C1318JV18に関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちCypress CY7C1318JV18デバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
