CypressメーカーCY7C1320CV18の使用説明書/サービス説明書
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18-Mbit DDR-II SRAM 2-W ord Burst Architecture CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-07160 Rev .
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 2 of 29 Logic Block Diagram (CY7C1316CV18) Logic Block Diagram (CY7C1916CV18) Wri te Reg Wri te Reg CLK A (19:0) Gen. K K Control Logic Address Register Read Add.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 3 of 29 Logic Block Diagram (CY7C1318CV18) Logic Block Diagram (CY7C1320CV18) Wri te Reg Write Reg CLK A (19:0) Gen. K K Control Logic Address Register Read Add.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 4 of 29 Pin Configuration The pin configuration for CY7C1316CV18, CY7C191 6CV18, CY7C1318CV18, and CY7C1320CV18 follo w .
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 5 of 29 CY7C1318CV18 (1M x 18) 123456789 10 11 A CQ NC/72M A R/W BWS 1 K NC/14 4M LD A NC/36M CQ B NC DQ9.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 6 of 29 Pin Definitions Pin Name IO Pin Descripti on DQ [x:0] Input Output- Synchronous Dat a Input Output S ignals . Inputs are sampled on the rising edge of K and K clocks during valid write operations.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 7 of 29 CQ Output Clock CQ Referenced with Respect to C . This is a free running clock and is synchronized to the input clock for output data (C) of the DDR-II.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 8 of 29 Functional Overview The CY7C1316CV18, CY7C1916CV18, CY7C1 318CV18, and CY7C1320CV18 are synchronous pi pelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of one and half cycles when DOFF pin is tied HIGH.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 9 of 29 driver impedance. The value of RQ must be 5x the value of th e intended line impedance d riven by the SRAM. The allo wable range of RQ to guarantee impe dance matching with a to lerance of ±15% is between 175 Ω an d 350 Ω , with V DD Q =1 .
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 10 of 29 T ruth T able The truth table for the CY7C1316CV18, CY7C1916 CV18, CY7C13 18CV18, and CY7C1320CV18 fo llows.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 1 1 of 29 Write Cycle Descriptions The write cycle description t able for CY7C1 916CV18 follows. [2, 8] BWS 0 K K Comments L L–H – During the data portion of a write sequence, th e single byte (D [8:0] ) is written into the device.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 12 of 29 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 149.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 13 of 29 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister .
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 14 of 29 T AP Controller St ate Diag ram The state diagram for the T AP controller follows.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 15 of 29 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1, 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 16 of 29 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Ma.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 17 of 29 Identification R egi ster Definitions Instruction Field Va l u e Description CY7C1316CV18 CY7C1916CV18 CY7 C1318CV18 CY7C1320CV18 Revision Numb er (31:29) 000 000 000 000 V ersion numbe r .
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 18 of 29 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bum p ID 0 6R 28 10G 56 6A 8.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 19 of 29 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be power ed up and initialized in a predefined manner to prevent unde fined operations. Power Up Sequence ■ Apply power and drive DO FF either HIGH or LOW (all other inputs can be HIGH or LOW).
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 20 of 29 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature .
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 21 of 29 I SB1 Automatic Power Down Current Max V DD , Both Ports Deselected, V IN ≥ V IH or V IN ≤ V.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 22 of 29 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 23 of 29 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consor tium Parame.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 24 of 29 Output T imes t CO t CHQV C/C Clock Rise (or K/K in single clock mode) to Data V alid – 0.45 – 0.45 – 0.45 – 0.50 ns t DOH t CHQX Data Output Hold af ter Output C/C Clock Rise (Active to Active) –0.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 25 of 29 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 7, 28, 29 ] READ READ READ NOP NO.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 26 of 29 Ordering Information Not all of the speed, package and temperature ranges are ava ilable. Please contact your local sales representative or visit www .
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 27 of 29 200 CY7C1316CV18-200BZC 51-85180 165-Ball Fine Pi tch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1916CV18-200BZC CY7C1318CV18-200BZC CY7C1320CV18-200BZC CY7C1316CV18-200BZXC 5 1-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev . *E Page 28 of 29 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø 0 . 2 5MCAB Ø0.
Document Number: 001-07160 Rev . *E Revised June 18, 2008 Page 29 of 29 QDR RAMs an d Quad Data Rate RAMs comp rise a new family of product s develope d by Cypress, IDT , NEC, Renesas, and Samsung. All pr oduct and co mpany nam es mentioned i n this documen t are the tr ad emarks of their respe ctive hold ers.
デバイスCypress CY7C1320CV18の購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
Cypress CY7C1320CV18をまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはCypress CY7C1320CV18の技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Cypress CY7C1320CV18の取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Cypress CY7C1320CV18で得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Cypress CY7C1320CV18を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はCypress CY7C1320CV18の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Cypress CY7C1320CV18に関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちCypress CY7C1320CV18デバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
