CypressメーカーCY7C1354Cの使用説明書/サービス説明書
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9-Mbit (256K x 36/512K x 18) Pi p elined SRAM with NoBL™ Architecture CY7C1354C CY7C1356C Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05538 Rev .
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 2 of 28 A0, A1, A C MODE BW a BW b WE CE1 CE2 CE3 OE READ LOGIC DQs DQP a DQP b D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E .
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 3 of 28 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQa DQa V DDQ V SS DQa DQ.
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 4 of 28 Pin Configurations (continued) 234 5 6 7 1 A B C D E F G H J K L M N P R T U DQ a V DDQ NC/576 M NC/1G DQ c DQ d DQ c DQ d AA A A NC/18M .
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 5 of 28 Pin Configurations (continued) 23 4 567 1 A B C D E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c .
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 6 of 28 Pin Definitions Pin Name I/O T ype Pin Description A0, A1 A Input- Synchronous Address Inp ut s used to select on e of the addre ss locations . Sampled at the rising edge of the CLK. BW a ,BW b , BW c ,BW d , Input- Synchronous Byte Write Select Inpu t s, active LOW .
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 7 of 28 Functional Overview The CY7C1354C and C Y7C1356C are synchronous-pipeli ned Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transi tions. All synchronous input s pass through input registers co ntrolled by the rising ed ge of the clock.
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 8 of 28 Because the CY7C1354C and CY7C1356C are common I/O devices, data should not be driv en into the device while the outputs are active.
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 9 of 28 NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-S tate WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-S tate IGNORE CLO.
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 10 of 28 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1354C/CY7C1356C incorpora tes a serial boundary scan test access port (T AP) in th e BGA package only . The TQFP package does not offer this functionality .
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 1 1 of 28 TDI and TDO ba lls as show n in the T ap Co ntroller Bl ock Diagram. Upon power-up, the instruction register is loaded with the IDCODE in struction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in th e pre v i o us section.
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 12 of 28 PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection o f another boundary scan test operation.
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 13 of 28 3.3V T AP AC T est Conditions Input pulse levels .................. .............. .............. .. V SS to 3.3V Input rise and fall times ......... ........ ........... ... ........... .
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 14 of 28 Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (1 19-b all BGA .
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 15 of 28 Boundary Scan Exit Order (256K × 36) Bit # 1 19-ball ID 165-ball ID 1K 4 B 6 2H 4 B 7 3M 4 A 7 4F 4 B 8 5B 4 A 8 6G 4 A 9 7C 3 B 1 0 8B.
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 16 of 28 Boundary Scan Exit Order (512K × 18) Bit # 1 1 9-ball ID 165-ball ID 1K 4 B 6 2H 4 B 7 3M 4 A 7 4F 4 B 8 5B 4 A 8 6G 4 A 9 7C 3 B 1 0 8.
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 17 of 28 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T emperature with Power Applied .
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 18 of 28 Cap acit ance [16] Parameter Des criptio n T est Conditions 100 TQ FP Max. 1 19 BGA Max.
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 19 of 28 Switching Characteristics Over the Operating Range [18, 19] Parameter Description –250 –200 –166 Unit Min. Max. Min. Max. Min. Max. t Power [17] V CC (typical) to the First Access Read or Write 1 1 1 ms Clock t CYC Clock Cycle T ime 4.
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 20 of 28 Switching W aveforms Read/Write T iming [23, 24, 25] Notes: 23. For this waveform ZZ is tied low . 24. When CE is LOW, CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW . When CE is H IGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH.
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 21 of 28 NOP ,ST ALL and DESELECT Cycles [23, 24, 26] Note: 26. The IGNORE CLOCK EDGE or ST ALL cycle (Clock 3) illustrated CEN being used to create a pause. A wr ite is not perform ed during this cycle.
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 22 of 28 27. Device must be deselected when entering ZZ mode. See cycle descr ipt ion table for all possible signal co nditions to deselect the device. 28. I/Os are in High-Z when exiting ZZ sleep mode.
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 23 of 28 Ordering Information Not all of the spe ed, package and temperature ran ges are available. Please contact your local sales r epresentative or visit www .cypress.com for actual pro duct s offered.
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 24 of 28 250 CY7C1354C-250AXC 51-8 5050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1356C-250AXC CY7C1354C-250BGC 51-851 15 1 19-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1356C-250BGC CY7C1354C-250BGXC 51-851 15 1 19-ball Ball Grid Array (14 x 22 x 2.
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 25 of 28 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3.
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 26 of 28 Package Diagrams (continued) 1.27 20.32 2 16 5 4 37 L E A B D C H G F K J U P N M T R 12.00 19.50 30° TYP. 2.40 MAX. A1 CORNER 0.70 REF. U T R P N M L K J H G F E D C A B 21 43 65 7 Ø1.
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 27 of 28 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce.
CY7C1354C CY7C1356C Document #: 38-05538 Rev . *G Page 28 of 28 Document History Page Document Title: CY7C1354C/CY7C1356C 9-Mbit (256K x 36/5 12K x 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05538 REV .
デバイスCypress CY7C1354Cの購入後に(又は購入する前であっても)重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります:
Cypress CY7C1354Cをまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはCypress CY7C1354Cの技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Cypress CY7C1354Cの取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Cypress CY7C1354Cで得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Cypress CY7C1354Cを既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はCypress CY7C1354Cの不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Cypress CY7C1354Cに関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちCypress CY7C1354Cデバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。