CypressメーカーCY7C1387Dの使用説明書/サービス説明書
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18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document Number: 38-0 5545 Rev .
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 2 of 30 Logic Block Diagram – CY7C1386D/CY7C138 6F [3] (512K x 36) Logic Block Diagram – CY7C1387D/CY7C138 7F [3] .
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 3 of 30 Pin Configurations A A A A A 1 A 0 NC/72M NC/36M V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 4 of 30 Pin Configurations (continued) 234 5 67 1 A B C D E F G H J K L M N P R T U V DDQ NC/288M NC/144M DQP C DQ C D.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 5 of 30 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C138 6D (512K x 36) 234 567 1 A B C D E.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 6 of 30 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address inputs used to select one of the add ress locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 [2] are sampled active .
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 7 of 30 Functional Overview All synchronous inpu ts pass through input registers controlled by the rising edge of th e clock. All data outputs pass through output registers controlled by th e rising edge of the clock.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 8 of 30 The write signals (GW , BWE , and BW X ) and ADV inputs are ignored during this first cycl e. ADSP triggered write accesses require two cl ock cycles to complete.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 9 of 30 T ruth T able [4, 5, 6, 7, 8] Operation Add. Used CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cyc.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 10 of 30 T ruth T able for Read/Write [6, 9] Function (CY7C1386D/CY7C13 86F) GW BWE BW D BW C BW B BW A R e a d H HXXX.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 1 1 of 30 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1386D/CY 7C1387D/CY7C1386F/CY7C1387F incorporates a serial bound ary scan test access port (T AP). This part is fully compliant with 1 149.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 12 of 30 When the T AP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to allow for fault isolation of the board-le vel serial test data p ath.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 13 of 30 the T AP controller , it wi ll direct ly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will en able the output buffers to drive the output bus.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 14 of 30 3.3V T AP AC T est Conditions Input pulse levels ................... .............. ........... .....V SS to 3.3V Input rise and fall times ........... ........
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 15 of 30 Identification Register Definitions Instruction Field CY7C13 86D/CY7C1386F (512K × 36) CY7C1387D/CY7C1387F (.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 16 of 30 1 19-Ball BGA Boundary Scan Order [14, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 H4 23 F6.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 17 of 30 165-Ball BGA Boundary Scan Order [14, 16] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1N 6 3 1 D 1 0 6 1 G 1 2N.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 18 of 30 Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. For user guideline s, not tested. S torage T emperature ................
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 19 of 30 Cap acit ance [19] Parameter Description T est Co nditions 10 0 TQFP Max. 1 19 BGA Max 165 FBGA Max Unit C IN Input Capacit ance T A = 25 ° C, f = 1 MHz, V DD = 3.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 20 of 30 Switching Characteristics Over the Operating Range [20, 21] Parameter Description –250 –20 0 –167 Unit Min M ax Min Max Min Max t POWER V DD (T ypical) to the First Access [22] 11 1 m s Clock t CYC Clock Cycle Ti me 4.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 21 of 30 Switching W aveforms Read Cycle Timing [26] t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 22 of 30 Write Cycle T iming [26, 27] Switching W aveforms (conti nued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH O.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 23 of 30 Read/Write Cycle Timing [26, 28, 29] Switching W aveforms (conti nued) t CYC t CL CLK ADSP t ADH t ADS ADDRES.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 24 of 30 ZZ Mode T iming [30, 31] Switching W aveforms (conti nued) t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Notes 30.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 25 of 30 Ordering Information Not all of the spe ed, package, and temperature range s are availa b le. Please contact your local sales representative or visit www .cypress.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 26 of 30 250 CY7C1386D-250AXC 51-850 50 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial CY7C1387D-250AXC CY7C1386F-250BGC 51-8 51 15 1 19-ball Ball Grid Array (14 x 22 x 2.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 27 of 30 Package Diagrams Figure 1. 100-Pin Thin Plastic Q uad Flat p a ck (14 x 20 x 1.4 mm) (51-85050) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 28 of 30 Figure 2. 1 19-Ball BGA (1 4 x 22 x 2.4 mm) (51-85 1 15) Package Diagrams (continued) 51-851 15-*B [+] Feedba.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 29 of 30 © Cypress Semicond uctor Corporation , 2006-2007. The inf ormation cont ained herein i s subject to change witho ut notice.
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev . *E Page 30 of 30 Document History Page Document Title: CY7C1386D/CY7C1387D/CY7 C1386F/CY7C1387F, 18-Mbit (512 K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM Document Number: 38-05545 REV .
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Cypress CY7C1387Dをまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはCypress CY7C1387Dの技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Cypress CY7C1387Dの取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Cypress CY7C1387Dで得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Cypress CY7C1387Dを既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はCypress CY7C1387Dの不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Cypress CY7C1387Dに関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちCypress CY7C1387Dデバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
