CypressメーカーCY7C1415JV18の使用説明書/サービス説明書
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36-Mbit QDR™-II SRAM 4-W ord Burst Architecture CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-12557 Rev .
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 2 of 28 Logic Block Diagra m (CY7C141 1JV18) Logic Block Diagram (CY7C1426JV18) 1M x 8 Array CLK A (19:0) Gen. K K Control Logic Address Register D [7:0] Read Add.
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 3 of 28 Logic Block Diagram (CY7C1413JV18) Logic Block Diagram (CY7C1415JV18) CLK A (18:0) Gen. K K Control Logic Address Register D [17:0] Read Add. Decode Read Data Reg.
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 4 of 28 Pin Configuration The pin configuration for CY7C141 1JV18, CY7C1413JV18, and CY7C1415JV18 follows.
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 5 of 28 CY7C1413JV18 (2 M x 18) 123456789 10 11 A CQ NC/144M A WPS BWS 1 K NC/288M RPS A NC/72M CQ B NC .
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 6 of 28 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals . Sampled on the rising edge of K and K clocks when valid write operations are active.
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 7 of 28 CQ Echo Clock CQ is Referenced With Respect to C . This is a free running clock and is synchroni zed to the input clock for output data (C) of the QDR-II.
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 8 of 28 Functional Overview The CY7C141 1JV18, CY7C14 26JV18, CY7C1413JV18, and CY7C1415JV18 are synchronous pipe lined burst SRAMs with a read port and a write port.
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 9 of 28 includes forwarding data from a write cycle that was initiated on the previous K clock rise. Read accesses and w rite access must be scheduled such that one transaction is initiated on an y clock cycle.
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 10 of 28 T ruth T able The truth table for CY7C141 1JV18, CY7C1426 JV1 8, CY7C1413JV18, and CY7C1415JV18 follow s.
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 1 1 of 28 Write Cycle Descriptions The write cycle description tabl e for CY7C1426JV18 follows. [2, 10] BWS 0 K K L L–H – During the data portion of a write sequence, the single b yte (D [8:0] ) is written into the device.
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 12 of 28 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 149.
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 13 of 28 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister .
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 14 of 28 T AP Controller St ate Diag ram The state diagram for the T AP controller follows.
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 15 of 28 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [12, 13, 14] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 16 of 28 T AP AC Switching Characteristics Over the Operating Range [15, 16] Parameter Description Min M.
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 17 of 28 Identification R egi ster Definitions Instruction Field Va l u e Description CY7C141 1JV18 CY7C1426JV18 CY7C1413JV18 CY7C1415JV18 Revision Numb er (31:29) 000 000 000 000 V ersio n number .
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 18 of 28 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 8.
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 19 of 28 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent unde fined operations. Power Up Sequence ■ Apply power and drive DO FF either HIGH or LOW (all other inputs can be HIGH or LOW).
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 20 of 28 Maximum Ratings Exceeding maximum ratin gs may impair the useful life of the device. These user guidelines are not teste d. S torage T emperature .
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 21 of 28 I SB1 Automatic Power Down Current Max V DD , Both Ports Deselected, V IN ≥ V IH or V IN ≤ .
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 22 of 28 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 23 of 28 Switching Characteristics Over the Operating Range [22] Cypress Parameter Consortium Parameter .
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 24 of 28 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 7, 28, 29 ] K 1 2 34 5 6 7 RPS W.
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 25 of 28 Ordering Information Not all of the speed, package, and temper ature ranges are available. Please cont act your local sale s representative or visit www .
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 26 of 28 200 CY7C141 1 JV18-200BZC 51-85195 165-Ball Fine Pi tch Ball Grid Array (15 x 17 x 1.4 mm) Commercial CY7C1426JV18-200BZC CY7C1413JV18-200BZC CY7C1415JV18-200BZC CY7C141 1JV18-200BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.
CY7C141 1JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev . *C Page 27 of 28 Package Diagram Figure 6. 165 - B a ll FBGA (15 x 17 x 1.
Document Number: 001-12557 Rev . *C Revised June 25, 2008 Page 28 of 28 QDR RAMs an d Quad Data Rate RAMs comp rise a new family of product s develope d by Cypress, IDT , NEC, Renesas, and Samsung. A ll pr oduct an d company n ames mentio ned in this do cument are the tr ad emarks of their resp e ctive hold ers.
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Cypress CY7C1415JV18をまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはCypress CY7C1415JV18の技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Cypress CY7C1415JV18の取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Cypress CY7C1415JV18で得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Cypress CY7C1415JV18を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はCypress CY7C1415JV18の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Cypress CY7C1415JV18に関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちCypress CY7C1415JV18デバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
